Darlington transistor array device detection method

Abstract

The embodiment of the invention provides a Darlington transistor array detection method, which comprises the following steps of: testing every two pins of a device by using a transistor tester to obtain an I-V curve between every two pins; for the two pins with the abnormal I-V curve, when a preset voltage is applied, a first abnormal bright spot is obtained through infrared thermal imaging detection, the polarity of a power supply is turned over, the voltage is applied, and a second abnormal bright spot is obtained through infrared thermal imaging detection; and according to the first abnormal bright spot and the second abnormal bright spot, positioning an abnormal failure part. According to the invention, based on the detected abnormal bright spots, a circuit schematic diagram, circuit characteristics, internal structure characteristics and the like are combined, and a failure part can be accurately positioned.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a Darlington transistor array device detection method. Background Art

[0002] The Darlington Transistor Array is a composite transistor consisting of two or more transistors connected in series. It plays an important role in a variety of electronic application scenarios such as power amplifiers, switching circuits, sensor interfaces, etc. The Darlington transistor array includes an input terminal, an output terminal, a common terminal, multiple resistors, diodes, triodes, etc. The failure of any single transistor will cause the Darlington transistor array to fail. Traditional methods can detect whether a device has failed, but cannot accurately locate the failure site, especially for devices that do not provide technical support such as process layouts. It is particularly difficult to locate the failure site. Summary of the invention

[0003] In view of this, an object of an embodiment of the present application is to provide a Darlington transistor array device detection method to solve the problem of locating the failed part of the device.

[0004] Based on the above purpose, the embodiment of the present application provides a Darlington transistor array detection method, including:

[0005] Use a transistor tester to test the pins of the device in pairs to obtain the IV curve between the pins;

[0006] For the two pins with abnormal IV curves, when a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection;

[0007] According to the first abnormal bright spot and the second abnormal bright spot, the failure site where the abnormality occurs is located.

[0008] From the above, it can be seen that the Darlington transistor array device detection method provided in the embodiment of the present application uses a transistor tester to test the two pins of the device to obtain the IV curve between the two pins; for the two pins with abnormal IV curves, when a predetermined voltage is applied, infrared thermal imaging is used to detect the first abnormal bright spot, the power polarity is reversed and the voltage is applied, and the second abnormal bright spot is obtained by infrared thermal imaging detection; based on the first abnormal bright spot and the second abnormal bright spot, the abnormal failure site is located. Based on the detected abnormal bright spot, combined with the circuit schematic, circuit characteristics and internal structure characteristics, the present application can accurately locate the failure site, and adopts a variety of detection methods, combined with the failure site and the detection results, the cause of the failure can be analyzed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A schematic diagram of a method flow of an embodiment of the present application;

[0011] Figure 2 A typical circuit diagram of a Darlington transistor according to an embodiment of the present application;

[0012] Figure 3 A typical functional block diagram of a Darlington transistor array according to an embodiment of the present application;

[0013] Figure 4 A schematic diagram of the correspondence between the IV curve and the circuit functional blocks of an embodiment of the present application;

[0014] Figure 5A , 5B They are respectively schematic diagrams of the appearance of two devices in the embodiments of the present application;

[0015] Fig. 6A , 6B They are schematic diagrams of X-ray detection morphology of two devices in the embodiments of the present application;

[0016] Figure 7 Schematic diagram of IV curves of two devices according to an embodiment of the present application;

[0017] Figure 8 This is a schematic diagram of the internal chip morphology of the device F1 according to an embodiment of the present application;

[0018] Fig. 9 for Figure 8 A partial enlarged schematic diagram of

[0019] Fig.10 This is a schematic diagram of the internal chip morphology of the device F2 according to an embodiment of the present application;

[0020] Fig.11 This is a partial schematic diagram of the internal chip of the device F1 according to an embodiment of the present application under an electron microscope;

[0021] Fig.12 This is a schematic diagram of energy spectrum analysis of the device F1 according to an embodiment of the present application;

[0022] Fig.13A , 13B This is a schematic diagram of infrared thermal imaging of the device F1 according to an embodiment of the present application;

[0023] Fig.14 A schematic diagram showing the location of an abnormal bright spot of the device F1 according to an embodiment of the present application;

[0024] Fig.15 for Fig.14 A partial enlarged schematic diagram of

[0025] Fig.16A , 16B 16C and 16D are schematic diagrams of the locations of abnormal bright spots of the device F2 according to the embodiment of the present application;

[0026] Fig.17 A schematic diagram of the location of an abnormal bright spot of the device F2 according to an embodiment of the present application;

[0027] Fig.18A , 18B This is a schematic diagram of an EMMI image of a device F1 according to an embodiment of the present application;

[0028] Fig.19 A circuit diagram corresponding to the damage position of the device F1 according to an embodiment of the present application;

[0029] Fig. 20 This is a schematic diagram of the internal chip of the device F1 after peeling of the layers according to the embodiment of the present application;

[0030] Fig.21A , 21B for Fig. 20 A partial enlarged schematic diagram of

[0031] Fig. 22 This is a schematic diagram of the internal chip of the device F2 after peeling of the layers according to the embodiment of the present application;

[0032] Fig.23A , 23B , 23C, 23D Fig. 22 A partial enlarged schematic diagram of . DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0034] like Figure 2 As shown, the Darlington transistor includes an input terminal, an output terminal, a ground terminal, a common terminal, a compound transistor composed of two transistors, multiple diodes and multiple resistors, etc. A typical Darlington transistor array is usually a monolithic integrated circuit device with eight Darlington transistor structures integrated together. Accurately locating the failure location and circuit functional blocks of the Darlington transistor array can effectively determine the cause of device failure and provide reliable solutions.

[0035] In view of this, the present application provides a Darlington transistor array device detection method, which uses multiple detection means to detect the device, and accurately locates the failure part and circuit functional block by combining the circuit schematic, circuit characteristics and internal structure characteristics for the detected abnormal bright spots.

[0036] The technical solution of the present application is further described in detail below through specific embodiments.

[0037] like Figure 1 As shown, the embodiment of the present application provides a Darlington transistor array device detection method, comprising:

[0038] S101: Use a transistor tester to test two pins of the device to obtain an IV curve between two pins;

[0039] In this embodiment, a transistor tester is used to test the pins of the Darlington transistor array device in pairs to obtain an IV curve between the pins in pairs. Figure 3 As shown, pins 1-7 of the Darlington transistor array device are input terminals, pin 8 is the ground terminal, pin 9 is the common terminal, and pins 10-16 are output terminals. A transistor tester is used to test the input terminal (pins 1-7) and the ground terminal (pin 8), the input terminal and the output terminal (pins 10-16), the output terminal and the common terminal (pin 9), and the output terminal and the ground terminal of the device, respectively, to obtain the corresponding IV curve between the two pins, and to determine the abnormal IV curve by comparing the normal IV curve, and preliminarily judge the range of the abnormal failure position.

[0040] like Figure 2 , 4 As shown, a diode and a second-stage transistor are included between the output terminal and the ground terminal. When the ground terminal is connected to the positive electrode and the output terminal is connected to the negative electrode, the diode is forward-conducted, and the transistor emitter to collector is cut off, and the normal IV curve shows a diode characteristic; when the ground terminal is connected to the negative electrode and the output terminal is connected to the positive electrode, the transistor collector to emitter is cut off, the diode is reversely cut off, and the normal IV curve shows an open circuit characteristic.

[0041] A clamping diode is included between the output terminal and the common terminal. When used, the common terminal will be suspended or connected to the next stage according to the load conditions. When the output terminal is connected to the positive electrode and the common terminal is connected to the negative electrode, the clamping diode is forward-conducted, and the normal IV curve shows a diode characteristic; when the output terminal is connected to the negative electrode and the common terminal is connected to the positive electrode, the clamping diode is reverse-cutoff, and the normal IV curve shows an open-circuit characteristic.

[0042] The input terminal and the ground terminal include a resistor, a diode and two transistors. When the input terminal is connected to the positive electrode and the ground terminal is connected to the negative electrode, the conduction path is from the input terminal through a parallel structure of a 2.7 kilo-ohm resistor, two transistors and a 10.2 kilo-ohm resistor (a 7.2 kilo-ohm resistor and a 3 kilo-ohm resistor are connected in series) to the ground terminal. The normal IV curve is a two-stage resistive curve. The resistance of the two transistors is 12.9 kilo-ohms before conduction and 2.7 kilo-ohms after conduction. The inflection point is the base-emitter PN junction voltage drop of the two transistors; when the input terminal is connected to the negative electrode and the ground terminal is connected to the positive electrode, the conduction path is from the ground terminal through a parallel structure of a diode and a 12.9 kilo-ohm resistor (a 2.7 kilo-ohm resistor, a 7.2 kilo-ohm resistor and a 3 kilo-ohm resistor are connected in series) to the input terminal. The normal IV curve is a resistive characteristic first and a diode characteristic later. Before the diode is forward-conducted, the curve is a resistive characteristic with a resistance of 12.9 kilo-ohms. After the diode is forward-conducted, the curve is a diode characteristic with an inflection point being the diode junction voltage drop.

[0043] The input and output terminals include resistors and the base and collector of the first-stage transistor. When the input terminal is connected to the positive electrode and the output terminal is connected to the negative electrode, the conduction path is from the input terminal through the 2.7 kilo-ohm resistor and the base-collector of the first-stage transistor to the output terminal. The normal IV curve is an approximate diode characteristic. The PN junction between the base and the emitter of the first-stage transistor is open-circuit before forward conduction, and is resistive after conduction, with a resistance of 2.7 kilo-ohms. When the input terminal is connected to the negative electrode and the output terminal is connected to the positive electrode, the PN junction between the collector and the base of the first-stage transistor is reversely cut off, and the normal IV curve shows an open-circuit characteristic.

[0044] S102: for the two pins with abnormal IV curves, when a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection;

[0045] S103: Locate the failure location where the abnormality occurs based on the first abnormal bright spot and the second abnormal bright spot.

[0046] In this embodiment, after obtaining the IV curve between the two pins, the abnormal IV curve and the corresponding two abnormal pins are determined, and infrared thermal imaging detection is performed on the two pins. During the detection process, one of the pins is connected to the positive pole and the other pin is connected to the negative pole. A predetermined voltage is applied to the two pins, and the first abnormal bright spot is obtained by infrared detection. After that, the polarity of the power supply is reversed and the same voltage is applied, that is, one of the pins is connected to the negative pole and the other pin is connected to the positive pole, and a predetermined voltage is applied to the two pins. The second abnormal bright spot is obtained by infrared detection. Then, according to the positional relationship between the first abnormal bright spot and the second abnormal bright spot, combined with the circuit schematic, circuit characteristics, circuit function block diagram and other comprehensive analysis and judgment, the abnormal failure site is located.

[0047] In some embodiments, locating the abnormal failure location according to the first abnormal bright spot and the second abnormal bright spot includes:

[0048] The position of the first abnormal bright spot corresponds to the position of the second abnormal bright spot. If there is only one component between the two pins with abnormal IV curve, the circuit area where the component is located is the failure site where the abnormality occurs.

[0049] In this embodiment, if the positions of the first abnormal bright spot and the second abnormal bright spot detected correspond to each other and are approximately the same, and combined with the circuit principle diagram and the circuit function block diagram, it is determined that there is only one component between the two pins, then the circuit area where the component is located can be determined as the failure location. For example, there is only one clamping diode between the output terminal (e.g., one of the pins 10-16) and the common terminal (pin 9).

[0050] In some embodiments, locating the abnormal failure location according to the first abnormal bright spot and the second abnormal bright spot includes:

[0051] The position of the first abnormal bright spot corresponds to the position of the second abnormal bright spot. If there are multiple components between the two pins with abnormal IV curves, at least one normal bright spot is detected by using the EMMI test method.

[0052] A normal bright spot corresponding to the positions of the first abnormal bright spot and the second abnormal bright spot is selected from a plurality of normal bright spots, and a failure location where the abnormality occurs is determined according to the location corresponding to the normal bright spot.

[0053] In this embodiment, if the positions of the first abnormal bright spot and the second abnormal bright spot detected correspond to each other, combined with the circuit schematic diagram and the circuit function block diagram, etc., it is determined that there are multiple components between the two pins, then it can only be preliminarily determined that one or more of the multiple components may be abnormal; in order to determine the specific failure location from the multiple components, the EMMI test method is used for detection to obtain multiple normal bright spots, and a normal bright spot corresponding to the positions of the first abnormal bright spot and the second abnormal bright spot is selected from the multiple normal bright spots, and the failure location corresponding to the abnormal bright spot is determined according to the location corresponding to the selected normal bright spot.

[0054] In some embodiments, the two pins with abnormal IV curves correspond to the input terminal and the ground terminal respectively;

[0055] When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including:

[0056] The input terminal is connected to the positive electrode, the ground terminal is connected to the negative electrode, and a first voltage is applied to detect to obtain a first abnormal bright spot. The input terminal is connected to the negative electrode, the ground terminal is connected to the positive electrode, and a first voltage is applied to detect to obtain a second abnormal bright spot.

[0057] According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including:

[0058] If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the failure site where the abnormality is suspected to occur includes the circuit area where the two transistors, the resistor and the diode are located between the input terminal and the ground terminal.

[0059] In this embodiment, when the IV curve between the pin corresponding to the input terminal and the pin corresponding to the ground terminal is abnormal, the input terminal is connected to the positive electrode and the ground terminal is connected to the negative electrode, and a first voltage is applied to detect to obtain a first abnormal bright spot, and then the input terminal is connected to the negative electrode and the ground terminal is connected to the positive electrode, and a first voltage is applied to detect to obtain a second abnormal bright spot. If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, it can be seen from the circuit schematic diagram and the circuit function block diagram that the suspected abnormal failure location includes the circuit area where the two transistors, resistors and diodes are located between the input terminal and the ground terminal.

[0060] Among them, the first voltage is greater than the junction voltage drop between the base and emitter of the two transistors. For example, the second voltage is 2V. When the input terminal is connected to the positive electrode and the ground terminal is connected to the negative electrode, the base and emitter of the two transistors are both forward-conducted, and the circuit functional block corresponding to the bright spot position on the chip surface is a composite transistor composed of two transistors.

[0061] In some embodiments, after determining the suspected abnormal failure location, the method further includes: using the EMMI test method to detect and obtain at least one normal bright spot; selecting a normal bright spot corresponding to the first abnormal bright spot and the second abnormal bright spot from multiple normal bright spots, and determining the abnormal failure location according to the location corresponding to the normal bright spot. That is, when there are multiple suspected failure locations, the EMMI test method is further used to check each location, and the determined failure location is obtained after checking.

[0062] For Darlington transistor arrays, the process is mainly composed of bipolar process, and the PN junction structure is the basic unit of diodes, triodes and other structures. Its abnormality is usually manifested as PN junction short circuit or increased leakage current, so infrared thermal imaging detection or micro-light microscope (EMMI) detection can be used to detect the heat distribution or leakage position on the surface of the device chip. During the detection, a certain voltage needs to be applied between the two pins with abnormal IV curves, and the power supply polarity needs to be reversed and then the same voltage needs to be applied for re-detection. The purpose of reversing the power supply polarity is to find out through IV curve troubleshooting and analysis that the power supply polarity between the two pins is different, and there are differences in the circuit path, and the corresponding IV curves are also different. Through infrared thermal imaging detection and EMMI detection, abnormal hot spots or leakage bright spots can be effectively found on the chip surface for situations such as PN junction short circuit or leakage inside the chip.

[0063] In some embodiments, the two pins with abnormal IV curves correspond to the input terminal and the ground terminal respectively;

[0064] When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including:

[0065] The input terminal is connected to the positive pole, the ground terminal is connected to the negative pole, and a second voltage is applied to detect to obtain a first abnormal bright spot; the input terminal is connected to the negative pole, the ground terminal is connected to the positive pole, and a second voltage is applied to detect to obtain a second abnormal bright spot;

[0066] According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including:

[0067] If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the failure site where the abnormality occurs is located as the circuit area where the diode between the input terminal and the ground terminal is located.

[0068] In this embodiment, when the IV curve between the pin corresponding to the input terminal and the pin corresponding to the ground terminal is abnormal, the input terminal is connected to the positive electrode and the ground terminal is connected to the negative electrode, and a second voltage is applied to detect to obtain a first abnormal bright spot, and then the input terminal is connected to the negative electrode and the ground terminal is connected to the positive electrode, and a second voltage is applied to detect to obtain a second abnormal bright spot. If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, it can be known from the circuit schematic diagram and the circuit function block diagram that the failure site where the abnormality occurs is located as the circuit area where the diode between the input terminal and the ground terminal is located.

[0069] Among them, the second voltage is greater than the forward voltage drop of the diode, for example, the second voltage is greater than 1V. When the ground terminal is connected to the positive electrode and the input terminal is connected to the negative electrode, the diode between the ground terminal and the input terminal is forward-conducted, and the failure location corresponding to the bright spot position on the chip surface is the circuit area where the diode between the input terminal and the ground terminal is located.

[0070] In some embodiments, the two pins with abnormal IV curves correspond to the output terminal and the ground terminal respectively;

[0071] When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including:

[0072] The ground terminal is connected to the positive electrode, the output terminal is connected to the negative electrode, and a third voltage is applied to detect to obtain a first abnormal bright spot, and the ground terminal is connected to the negative electrode, the output terminal is connected to the positive electrode, and a third voltage is applied to detect to obtain a second abnormal bright spot;

[0073] According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including:

[0074] If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the failure site where the abnormality occurs is located as the circuit area where the diode between the ground terminal and the output terminal is located.

[0075] In this embodiment, when the IV curve between the pin corresponding to the output terminal and the pin corresponding to the ground terminal is abnormal, the output terminal is connected to the positive pole and the ground terminal is connected to the negative pole, and a third voltage is applied to detect to obtain a first abnormal bright spot, and then the output terminal is connected to the negative pole and the ground terminal is connected to the positive pole, and a third voltage is applied to detect to obtain a second abnormal bright spot. If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, it can be known from the circuit schematic diagram and the circuit function block diagram that the failure site where the abnormality occurs is located as the diode between the output terminal and the ground terminal.

[0076] Among them, the third voltage is greater than the forward voltage drop of the diode, for example, the third voltage is greater than 1V. When the ground terminal is connected to the positive pole and the output terminal is connected to the negative pole, the diode between the ground terminal and the output terminal is forward-conducted, and the failure location corresponding to the bright spot position on the chip surface is the circuit area where the diode between the ground terminal and the output terminal is located; after the power supply polarity is reversed, no abnormal bright spot is visible on the chip surface.

[0077] In some embodiments, the two pins with abnormal IV curves correspond to the output terminal and the common terminal respectively;

[0078] When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including:

[0079] The output terminal is connected to the positive electrode, the common terminal is connected to the negative electrode, and a fourth voltage is applied to detect to obtain a first abnormal bright spot; the output terminal is connected to the negative electrode, the common terminal is connected to the positive electrode, and a fourth voltage is applied to detect to obtain a second abnormal bright spot;

[0080] According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including:

[0081] If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the element where the abnormality occurs is located to be the diode between the common terminal and the output terminal.

[0082] In this embodiment, when the IV curve between the pin corresponding to the output terminal and the pin corresponding to the common terminal is abnormal, the output terminal is connected to the positive electrode and the common terminal is connected to the negative electrode, and a fourth voltage is applied to detect to obtain a first abnormal bright spot, and then the output terminal is connected to the negative electrode and the common terminal is connected to the positive electrode, and a fourth voltage is applied to detect to obtain a second abnormal bright spot. If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, it can be known from the circuit schematic diagram and the circuit function block diagram that the failure site where the abnormality occurs is located as the clamping diode between the output terminal and the common terminal.

[0083] Among them, the fourth voltage is greater than the forward voltage drop of the clamping diode, for example, the fourth voltage is greater than 1V. When the output terminal is connected to the positive electrode and the common terminal is connected to the negative electrode, the clamping diode between the output terminal and the common terminal is forward-conducted, and the failure location corresponding to the bright spot position on the chip surface is the circuit area where the clamping diode between the output terminal and the common terminal is located; after the power supply polarity is reversed, no abnormal bright spot is visible on the chip surface.

[0084] In some embodiments, the detection method further comprises:

[0085] Use a stereo microscope to check whether there are any abnormalities in the connection between the device pins and the tube shell, and whether there is any damage on the device surface;

[0086] Use an X-ray detector to check whether there is any burn-in, abnormal bonding, or abnormal bonding wire inside the device;

[0087] For plastic-encapsulated devices, acoustic scanning is used to detect whether there is delamination between the chip and the pins; for air-encapsulated devices, particle collision noise is used to detect whether there is any excess material inside the device, and the sealing test method is used to detect the sealing of the device;

[0088] For plastic-sealed devices, use chemical methods to open the devices and conduct visual inspection on the internal surface of the devices; for air-sealed devices, use mechanical methods to open the devices and conduct visual inspection on the internal surface of the devices.

[0089] This embodiment provides a complete detection method for Darlington transistor array devices, specifically including: using a stereo microscope to check the appearance of the device, mainly checking whether there is any abnormality in the connection between each functional pin of the device and the tube shell, and whether there are any damage marks on the surface of the device; using an X-ray detector to check the inside of the device, mainly checking whether there is any burn-in, chip bonding abnormality, whether the bonding wire is fused, broken, etc.; using a transistor tester to perform IV curve testing on the functional pins of the device, and testing the differences between the pins of the device through the IV curve to qualitatively judge whether there is any abnormality in the device. For Darlington transistor arrays, the IV curve can be used to preliminarily judge whether there are any abnormalities in internal diodes, triodes and other components; for plastic-encapsulated devices, use Use ultrasonic microscope (SAM) to scan and detect whether there is delamination between the chip and pins inside the device. For unsealed devices, particle impact noise detection (PIND) is used to detect whether there is any excess material inside the device, and the sealing of the device is detected by sealing detection method. For devices with abnormal IV curves, further positioning detection is performed on the two abnormal pins to determine the failure location and the corresponding circuit functional block. For plastic-sealed devices, the device is opened by chemical method to expose the chip surface inside the device, and the internal surface of the device is visually inspected. For unsealed devices, the cover is removed by mechanical method to expose the chip surface inside the device, and the internal surface of the device is visually inspected. The main inspection is to check whether there is abnormal chip bonding inside the device, and whether there is damage to the bonding system and chip surface.

[0090] In some embodiments, after locating the abnormal failure site, the method further includes:

[0091] The device is stripped and visually inspected, and the cause of failure is determined based on the visual inspection results and the failure location.

[0092] In this embodiment, after locating the failure site, if there is obvious damage morphology on the chip surface, the possible cause of the failure is analyzed and determined. If the damage on the chip surface is not visible, chip stripping or focused ion beam (FIB) is used for detection. During the detection process, the damage morphology of the lower layer of the chip or the chip process cross-sectional structure is observed, and the cause of device failure is determined based on the damage morphology.

[0093] Generally speaking, there are two situations: there is obvious damage on the chip surface and there is no damage. For the situation where there is obvious damage on the chip surface, it is necessary to analyze and judge the damage morphology and the circuit functional blocks corresponding to the burnt position, and determine the cause of failure in combination with the located failure location and circuit functional blocks. For the situation where there is no damage on the chip surface, further analysis can be carried out in combination with low-light microscopy, stripping and other means to determine the burnt position and the corresponding functional blocks, and analyze and determine the cause of failure.

[0094] The detection method of the present application is described in detail below in conjunction with specific embodiments.

[0095] SG2003 Darlington transistor array was used as the test sample. F1 and F2 were the numbers of the two failed samples. The failure of device F1 was manifested by the reduction of impedance values ​​of some pins. Among them, the resistance between pin 1 and pin 8 was 159Ω, and the normal value was 7.4kΩ. The failure of device F2 was manifested by the resistance between pin 9 and pin 15 and between pin 9 and pin 16, both of which were 0.49MΩ, while the normal product was greater than 500MΩ.

[0096] The devices F1 and F2 are tested according to the testing method of the present application, specifically including:

[0097] Use a stereo microscope to inspect the appearance of the two devices. Figure 5A , 5B As shown, the structures of the two devices are intact, with no obvious abnormalities such as cracking and burning.

[0098] Use X-ray detector to inspect the inside of the two devices respectively, such as Fig. 6A , 6B As shown, the internal chips of the two devices are well bonded, no bonding wire morphology is observed, and no abnormalities such as burning are observed.

[0099] Use a transistor tester to perform IV curve testing on the functional pins of the device, such as Figure 7 As shown, the IV curve between pin 1 and pin 8 of device F1 is abnormal, that is, there is a resistance abnormality between the input terminal corresponding to pin 1 and the ground terminal corresponding to pin 8, the IV curve between pin 15 and pin 9 of device F2 is abnormal, and the IV curve between pin 16 and pin 9 is abnormal, that is, there is a resistance abnormality between the output terminal corresponding to pin 15 and the common terminal corresponding to pin 9, and there is a resistance abnormality between the output terminal corresponding to pin 16 and the common terminal corresponding to pin 9. In some embodiments, the scale value of the horizontal grid line of the IV curve is 0.2V / grid, and the scale value of the vertical grid line is 20μA / grid.

[0100] Particle collision noise was used to detect whether there were any extraneous materials inside the two devices, and the sealing performance of the two devices was tested using a sealing test method. Both test results of the two devices were qualified.

[0101] Use mechanical method to unpack the two devices and inspect them visually after unpacking; Figure 8 , 9 As shown in FIG. 1 , there are defect traces in the partial area between the inner bonding points of pins 1 and 2 on the chip surface of device F1, such as Fig.10 As shown, there is no sign of damage on the chip surface of device F2.

[0102] The chip surface of device F1 was inspected using a field emission scanning electron microscope (SEM). Fig.11As shown, there is a defect in the area between the inner bonding points of pin 1 and pin 2 on the chip surface of device F1, and the defect surface structure is concave; energy spectrum analysis of device F1 is performed, as shown Fig.12 As shown, the composition of the defective part and the non-defective part on the chip surface is basically the same and no corrosive elements are found. The main components of sites 1-5 are C, N, O, Al, and Si.

[0103] Infrared thermal imaging equipment is used to detect the heat distribution on the chip surface of the two devices. For device F2, pin 9 is connected to the positive pole, pin 15 is connected to the negative pole, and a 2.2V voltage is applied between pin 9 and pin 15. Fig.16A As shown, the detection found that the local circuit attached to the inner bonding point of pin 15 had the first abnormal bright spot. The power polarity was reversed (i.e., pin 9 was connected to the negative pole and pin 15 was connected to the positive pole) and a 2.2V voltage was applied. Fig. 16B As shown, the second abnormal bright spot is detected, and the positions of the first abnormal bright spot and the second abnormal bright spot are substantially consistent.

[0104] Connect pin 9 to the positive terminal and pin 16 to the negative terminal, and apply a 2.2V voltage between pin 9 and pin 16, such as Fig. 16C As shown, the detection found that the local circuit attached to the inner bonding point of pin 16 had the first abnormal bright spot. The power polarity was reversed (i.e., pin 9 was connected to the negative pole and pin 16 was connected to the positive pole) and a 2.2V voltage was applied. Fig.16D As shown, the second abnormal bright spot is detected, and the positions of the first abnormal bright spot and the second abnormal bright spot are basically consistent. Fig.17 As shown, combined with the analysis of the circuit diagram, it can be seen that there is only one clamping diode between pin 9 and pin 15, and between pin 9 and pin 16. It can be determined that the area corresponding to the first abnormal brightness and the second abnormal bright spot is the circuit functional block where the clamping diode is located, and the circuit area where the clamping diode is located is located as the failure site.

[0105] For device F1, connect pin 1 to the positive terminal, pin 8 to the negative terminal, and apply a 2.2V voltage between pin 1 and pin 8. Fig.13A As shown, the detection found that the local circuit attached to the inner bonding point of pin 1 had the first abnormal bright spot. The power polarity was reversed (i.e., pin 1 was connected to the negative pole and pin 8 was connected to the positive pole) and a 2.2V voltage was applied. Fig. 13B , 14 As shown in 15, the second abnormal bright spot is detected, and the positions of the first abnormal bright spot and the second abnormal bright spot are basically consistent, both of which are located at the defect position.

[0106] Since there are resistors, diodes, two transistors and other components between pin 1 and pin 8, that is, between the input terminal and the ground terminal, it is impossible to directly determine the circuit functional block corresponding to the abnormal bright spot without knowing the process layout. Therefore, in order to accurately locate the failure site and circuit functional block, a low-light microscope is further used to check the functional block, and the failure site and circuit functional block are located in combination with the abnormal bright spot and the circuit diagram. Specifically:

[0107] Select other qualified input pins, such as pin 2 and pin 3, for testing. Pin 2 is connected to the positive pole, and pin 8 is connected to the negative pole. A certain voltage is applied between pin 2 and pin 8 to observe the position of the bright spot on the device surface. When the applied voltage is lower than 1.2V, there is no bright spot on the chip surface. When the applied voltage exceeds 1.2V, normal bright spots can be seen on the chip surface. The normal bright spots correspond to the circuit areas corresponding to the two transistors. Fig.18A As shown, combined with the circuit diagram analysis, when the voltage exceeds 1.2V, that is, when the two PN junction voltage drops are reached, the base and emitter of the two transistors between the input terminal and the ground terminal are turned on, and the conduction path flows from the input terminal through the 2.7 kilo-ohm resistor and the base and emitter of the two transistors to the ground terminal. The detection method of pin 3 is the same, that is, pin 3 is connected to the positive electrode, pin 8 is connected to the negative electrode, and a certain voltage is applied between pin 3 and pin 8 to observe the position of the bright spot on the surface of the device. When the applied voltage is lower than 1.2V, there is no bright spot on the chip surface. When the applied voltage exceeds 1.2V, bright spots can be seen on the chip surface.

[0108] Reverse the polarity of the power supply, connect pin 2 to the negative pole and pin 8 to the positive pole. Apply a voltage lower than 0.5V between pin 2 and pin 8, and there will be no bright spot on the chip surface. When the applied voltage exceeds 0.5V, normal bright spots can be seen on the chip surface. The normal bright spots correspond to the circuit area corresponding to the diode between the input terminal and the ground terminal. Fig.18B As shown, combined with the circuit diagram analysis, after the power supply is reversed, when the voltage exceeds 0.5V (i.e., the forward conduction voltage drop of the diode), the diode between the ground terminal and the input terminal is forward-conducted, and the conduction path is from the ground terminal through the diode to the input terminal. The detection method of pin 3 is the same, that is, pin 3 is connected to the negative pole, pin 8 is connected to the positive pole, a voltage lower than 0.5V is applied between pin 3 and pin 8, and bright spots are observed on the chip surface. A voltage higher than 0.5V is applied, and bright spots are observed on the chip surface.

[0109] According to the multiple normal bright spots in the troubleshooting process, the normal bright spot corresponding to the position of the first abnormal bright spot and the second abnormal bright spot of pin 1 located by infrared thermal imaging is determined, and the failure position corresponding to the first abnormal bright spot and the second abnormal bright spot is determined according to the position corresponding to the normal bright spot. If the position corresponding to the normal bright spot corresponding to the position of the abnormal bright spot is a diode, it can be determined that the circuit area where the diode between pin 1 and pin 8 is located is the failure position, such as Fig.19shown.

[0110] The two components are peeled off, the underlying structure of the chip is gradually exposed and visually inspected. During the peeling process, if Fig. 20 , 21A As shown in FIG. 21B , the defect trace in the area between the inner bonding points of pins 1 and 2 of device F1 always exists, indicating that the defect trace exists in the functional structure below the chip passivation layer. Fig. 22 , 23A As shown in FIGS. 23B, 23C, and 23D, there are traces of damage in the lower layer circuit near the inner bonding points of pins 15 and 16 of device F2, and these traces correspond to the positions of the abnormal bright spots.

[0111] Based on the above detection process, combined with the damage morphology, damage characteristics and functional block analysis of the two devices, it can be concluded that the failure cause of device F1 is the damage of the local circuit under the diode between pins 1 and 8, and the damage cause may be related to the defect near the bonding area of ​​pin 1. The failure cause of device F2 is that the clamping diode between the common terminal and the output terminal is broken down by the instantaneous narrow pulse over-electric stress.

[0112] The Darlington transistor array device detection method provided in the embodiment of the present application adopts multiple detection means such as appearance inspection, X-ray inspection, IV curve test, particle collision noise detection, sealing detection, internal visual inspection, infrared thermal imaging detection, chip peeling visual inspection, etc. For the abnormal bright spots detected, the failure parts and functional blocks are accurately located in combination with the circuit schematic, circuit characteristics and internal structure characteristics, and a complete and effective failure analysis method is provided, which can achieve accurate positioning of the failure of the Darlington transistor array, especially when the functional test cannot be carried out and insufficient technical support such as process layout is not provided, the failure parts and functional blocks of the device can still be accurately located. The method is simple, feasible, scientific and effective, and solves the technical difficulty that such failure analysis cannot accurately locate.

[0113] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0114] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0115] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present disclosure.

Claims

1. A Darlington transistor array detection method, characterized in that: include: Use a transistor tester to test the pins of the device in pairs to obtain the IV curve between the pins; For the two pins with abnormal IV curves, when a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection; According to the first abnormal bright spot and the second abnormal bright spot, the failure site where the abnormality occurs is located.

2. The method according to claim 1, characterized in that The method of locating the abnormal failure part according to the first abnormal bright spot and the second abnormal bright spot comprises: The position of the first abnormal bright spot corresponds to the position of the second abnormal bright spot. If there is only one component between the two pins with abnormal IV curve, the circuit area where the component is located is the failure location where the abnormality occurs.

3. The method according to claim 1, characterized in that The method of locating the abnormal failure part according to the first abnormal bright spot and the second abnormal bright spot comprises: The position of the first abnormal bright spot corresponds to the position of the second abnormal bright spot. If there are multiple components between the two pins with abnormal IV curves, at least one normal bright spot is detected by using the EMMI test method; A normal bright spot corresponding to the positions of the first abnormal bright spot and the second abnormal bright spot is selected from a plurality of normal bright spots, and a failure location where the abnormality occurs is determined according to the location corresponding to the normal bright spot.

4. The method according to claim 1, characterized in that The two pins with abnormal IV curve correspond to the input terminal and the ground terminal respectively; When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including: The input terminal is connected to the positive electrode, the ground terminal is connected to the negative electrode, and a first voltage is applied to detect to obtain a first abnormal bright spot. The input terminal is connected to the negative electrode, the ground terminal is connected to the positive electrode, and a first voltage is applied to detect to obtain a second abnormal bright spot. According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including: If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, it is determined that the failure location suspected of abnormality includes the circuit area where the two transistors, the resistor and the diode between the input terminal and the ground terminal are located.

5. The method according to claim 4, characterized in that After determining the suspected abnormal failure site, the following also need to be done: Detect and obtain at least one normal bright spot using the EMMI test method; A normal bright spot corresponding to the positions of the first abnormal bright spot and the second abnormal bright spot is selected from a plurality of normal bright spots, and a failure location where the abnormality occurs is determined according to the location corresponding to the normal bright spot.

6. The method according to claim 1, characterized in that The two pins with abnormal IV curve correspond to the input terminal and the ground terminal respectively; When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including: The input terminal is connected to the positive electrode, the ground terminal is connected to the negative electrode, and a second voltage is applied to detect to obtain a first abnormal bright spot. The input terminal is connected to the negative electrode, the ground terminal is connected to the positive electrode, and a second voltage is applied to detect to obtain a second abnormal bright spot. According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including: If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the failure site where the abnormality occurs is located as the circuit area where the diode between the input terminal and the ground terminal is located.

7. The method according to claim 1, characterized in that The two pins with abnormal IV curve correspond to the output terminal and the ground terminal respectively; When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including: The ground terminal is connected to the positive electrode, the output terminal is connected to the negative electrode, and a third voltage is applied to detect to obtain a first abnormal bright spot. The ground terminal is connected to the negative electrode, the output terminal is connected to the positive electrode, and a third voltage is applied to detect to obtain a second abnormal bright spot. According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including: If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the failure site where the abnormality occurs is located as the circuit area where the diode between the ground terminal and the output terminal is located.

8. The method according to claim 1, characterized in that The two pins with abnormal IV curve correspond to the output terminal and the common terminal respectively; When a predetermined voltage is applied, a first abnormal bright spot is obtained by infrared thermal imaging detection, and the polarity of the power supply is reversed and the voltage is applied, and a second abnormal bright spot is obtained by infrared thermal imaging detection, including: The output terminal is connected to the positive electrode, the common terminal is connected to the negative electrode, and a fourth voltage is applied to detect to obtain a first abnormal bright spot; the output terminal is connected to the negative electrode, the common terminal is connected to the positive electrode, and a fourth voltage is applied to detect to obtain a second abnormal bright spot; According to the first abnormal bright spot and the second abnormal bright spot, the abnormal failure part is located, including: If the positions of the first abnormal bright spot and the second abnormal bright spot correspond to each other, the element where the abnormality occurs is located in the circuit region where the clamping diode between the common terminal and the output terminal is located.

9. The method according to claim 1, characterized in that: Also includes: Use a stereo microscope to check whether there are any abnormalities in the connection between the device pins and the tube shell, and whether there is any damage on the device surface; Use an X-ray detector to check whether there is any burn-in, abnormal bonding, or abnormal bonding wire inside the device; For plastic-encapsulated devices, use an ultrasonic microscope to detect whether there is delamination between the chip and pins inside the device; For sealed devices, particle collision noise is used to detect whether there are any extra objects inside the device, and sealing detection methods are used to detect the sealing of the device; For plastic-encapsulated devices, use chemical methods to open the device and conduct visual inspection of the internal surface of the device; For unsealed devices, use mechanical methods to open the device and perform visual inspection on the internal surface of the device to check whether there is chip bonding inside the device and whether there is damage to the bonding system and chip surface.

10. The method according to claim 1, characterized in that After locating the abnormal failure site, it also includes: The device is stripped and visually inspected, and the cause of failure is determined based on the visual inspection results and the failure location.

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