High-voltage MOS array module reliability test method and test circuit thereof

Abstract

The invention discloses a high-voltage MOS array module reliability test method and a test circuit thereof, and belongs to the technical field of hybrid integrated circuit test. The high-voltage MOS array module comprises two or more than two high-voltage MOS array unit modules and corresponding load modules, each high-voltage MOS device control circuit is in one-to-one correspondence with the damping protection circuit, and each high-voltage MOS device control circuit with the damping protection circuit is independent. The test method comprises a gate-source electrode high-temperature reverse bias test method of the high-voltage MOS device control circuit, a damping protection circuit high-temperature reverse bias test method, a damping protection circuit pulse power-on test method and a high-voltage MOS array module high-temperature power aging test method. The problem that an existing MOS tube reliability test system is not suitable for a multi-channel high-voltage MOS array reliability test is solved, and the defect of power aging of high-voltage driving module products is overcome. The switch driving module is widely applied to the technical field of high-voltage signal controlled switch driving modules.

Description

Technical Field

[0001] The present invention belongs to the technical field of hybrid integrated circuit testing, and further relates to the technical field of high-voltage MOS driver testing, and in particular to a high-voltage MOS array module reliability testing method and a testing circuit thereof. Background Art

[0002] High-voltage MOS drivers are used for low-loss high-power switching devices, and have the characteristics of high power density, high reliability, and high conversion efficiency. In particular, MOS tube array chips have the characteristics of high-density integration, high performance, and low loss, and are widely used in various electronic devices. As a field-effect transistor made based on metal oxide semiconductor materials, MOS tubes can control the flow of current between the drain and the source by applying voltage on the gate, and are highly controllable. In a MOS tube array chip, each MOS tube can work independently, and different functions can be achieved by controlling the gate voltage. The existing MOS tube reliability test system can only be used for testing single-channel MOS tubes and is not compatible with the testing of multi-channel MOS tube array chips. In view of this, the present invention is specially proposed. Summary of the invention

[0003] The technical problem to be solved by the present invention is to solve the problem that the existing MOS tube reliability test system is not suitable for multi-channel high-voltage MOS array reliability test, and to achieve the deficiency in power aging of high-voltage drive module products.

[0004] To this end, the present invention provides a high voltage MOS array module, such as Figure 1-4 As shown, it includes two or more high-voltage MOS array unit modules and corresponding load modules.

[0005] The high-voltage MOS array unit module includes a high-voltage MOS device control circuit and a damping protection circuit. The damping protection circuit is connected in reverse parallel to the positive power supply and output end (i.e., source end and drain end) of the high-voltage MOS device control circuit. The output end of each unit module is connected to one end of a load module, and the other end of the load module is connected to a negative power supply end (or ground end).

[0006] The high-voltage MOS device control circuit and the damping protection circuit of each channel correspond to each other one by one, and the high-voltage MOS device control circuit with the damping protection circuit of each channel is independent of each other.

[0007] The reliability test method of the high-voltage MOS array module includes the following test methods according to the composition structure of the high-voltage MOS array module.

[0008] (1) High-temperature reverse bias test of gate-source of high-voltage MOS device control circuit: The gate-source of the MOS device in the high-voltage MOS device control circuit operates for at least 48 hours at a specified temperature and 80% of the maximum rated gate-source voltage.

[0009] (2) High temperature reverse bias test of damping protection circuit: A high temperature reverse bias test is performed on the damping protection circuit under the specified test conditions and test temperature to assess the time stability of the leakage current of the product under reverse bias conditions.

[0010] (3) Pulse power-on test of damping protection circuit: A power pulse test is carried out on the damping protection circuit under the specified test conditions and test temperature to assess the pulse peak current and pulse peak power that the product can withstand.

[0011] (4) High-temperature power aging circuit of high-voltage MOS array module: When the product is at the highest operating temperature (such as T = 125°C), the set power is applied to the product so that the chips in the high-voltage MOS array module operate at the highest junction temperature to assess product reliability.

[0012] The reliability test circuit of a high voltage MOS array module is as follows: Figure 5-7 shown.

[0013] Source-drain reverse bias test circuit: The gate and source are short-circuited, and a source-drain reverse bias test voltage is applied between the source and drain terminals.

[0014] Gate-source reverse bias test circuit: The drain and source are short-circuited, and a gate-source reverse bias test voltage is applied between the source terminal and the gate terminal.

[0015] Power aging test circuit: The output end of the unit module is connected to one end of the load module, the other end of the load module is connected to the negative power supply end (or ground), a bias voltage is applied to the gate end, and a power aging working voltage is applied between the positive power supply end and the negative power supply end (or ground).

[0016] Beneficial effects of the reliability test scheme: The above three aging circuits: gate-source aging circuit, source-drain aging circuit, array high temperature power aging circuit. In addition to testing the source-drain and gate-drain of the MOS device in the high-voltage MOS device control circuit, the damping protection circuit as protection can also be tested, effectively improving the reliability screening rate of the high-voltage MOS array module.

[0017] During high-temperature power aging, the power supply voltage value can be adjusted and the voltage across the load module can be monitored to calculate the source-drain saturation voltage drop of the MOS device in the high-voltage MOS device control circuit. Based on the thermal resistance formula, it can effectively ensure that the chip works under safe junction temperature conditions, effectively improving product reliability.

[0018] The high-voltage MOS array module of the present invention has the characteristics of high power density, high reliability, high conversion efficiency, etc. Each channel mainly uses the voltage across the gate-source to control the conduction and shutdown of the channel between the source and the drain, and adds a damping protection circuit to prevent transient overvoltage pulses from appearing in the circuit. It has a strong load capacity and can directly drive the load to work. The product adopts a metal ceramic patch airtight package. Among similar products, it has the characteristics of small size, light weight, wide application, high integration, and convenient use. It can directly drive the load to work and has a strong load capacity.

[0019] The module has low coupling, and even if abnormalities occur in individual branches, it will not affect the normal operation of the entire module, and has higher stability.

[0020] The present invention is mainly used in the field of low-loss high-power switch technology, as a voltage-controlled high-voltage driver in various electronic circuits, and a switch drive module for high-voltage signal control. It is widely used in the fields of aviation, aerospace, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the high-voltage MOS array unit module structure.

[0022] Figure 2 It is a schematic diagram of the connection structure between the high-voltage MOS array unit module and the load module.

[0023] Figure 3 It is a schematic diagram of the connection structure between the high-voltage PMOS array unit circuit and the load circuit.

[0024] Figure 4 This is a schematic diagram of the six-channel high-voltage PMOS array module with load circuit structure.

[0025] Figure 5 This is a schematic diagram of the structure of the source-drain reverse bias test circuit for a six-channel high-voltage PMOS array module.

[0026] Figure 6 Schematic diagram of the gate-source reverse bias circuit structure of the six-channel high-voltage PMOS array module.

[0027] Figure 7 This is a schematic diagram of the power aging circuit structure of a six-channel high-voltage PMOS array module.

[0028] Figure 8 This is a schematic diagram of the package shape of a six-channel high-voltage PMOS array module. DETAILED DESCRIPTION

[0029] like Figure 1-7As shown, the reliability test method and test circuit of a high-voltage MOS array module are described, taking a six-channel high-voltage PMOS driver module as an example, and the specific implementation method is as follows: The high-voltage MOS device control circuit is a high-voltage PMOS device chip (PMOS chip for short).

[0030] The damping protection circuit is a damping diode chip (referred to as TVS chip).

[0031] The load module is a resistor.

[0032] The packaging process of the high voltage MOS array module is as follows: The high-voltage PMOS device chip (PMOS chip for short) and the damping diode chip (TVS chip for short) are assembled on a set ceramic substrate according to the hybrid integrated circuit integration technology, wire-bonded according to the circuit connection method, and packaged with metal packaging or ceramic packaging.

[0033] The working principle of the high voltage MOS array module is as follows: (1) When the gate-source voltage of PMOS |U GS |Greater than the threshold voltage |U GS（th） |, PMOS is turned on, generating I D The current flows from the S pole to the D pole, the circuit does work, and the voltage across the TVS device is pulled down by the PMOS conduction voltage drop and is in a reverse biased cut-off state.

[0034] (2) When the gate-source voltage of PMOS |U GS |Less than the threshold voltage |U GS（th） |, PMOS is turned off, no ID current is generated, and an external voltage is applied to both ends of the parallel circuit of the PMOS device and the TVS device. At this time, the voltage across the PMOS device and the TVS device is V CC , both the PMOS device and the TVS device are in the reverse bias cut-off state, and the circuit does not do work at this time. When there is a transient overvoltage pulse in the power supply circuit, the TVS device breaks down and releases the pressure before the PMOS device. Since the source-drain breakdown voltage of the PMOS device is higher than the TVS breakdown voltage, the PMOS device is still in the cut-off state at this time, and the PMOS device is protected from damage.

[0035] The six-channel high-voltage PMOS driver module is a hybrid driver module suitable for up to 350V, such as Figure 8As shown, it adopts metal ceramic airtight packaging, integrates six independent PMOS gate drivers, and also has six built-in TVS protection devices, which mainly solves the use environment that requires high-voltage PMOS. A switch drive module for high-voltage signal control, using metal ceramic patch airtight packaging, has the characteristics of small size and light weight. The array has a total of six channels. The module has low coupling, even if an individual branch is abnormal, it will not affect the normal operation of the entire module, so the product has higher stability. Product features: (1) Working voltage: ≥-350V.

[0036] (2) Light weight: ≤3g, which is half the total weight of the original 6-piece plastic package (TO-252) PMOS device.

[0037] (3) Small size, using chip-level integrated packaging (device-level integration), the product area is only 10-15% of the equivalent driver built with discrete devices.

[0038] (4) High cohesion: adopting 2.5D advanced packaging, low coupling: effectively improving functional stability.

[0039] (5) The TVS device provides overvoltage protection for the drain-source of each PMOS.

[0040] Each path mainly uses the voltage between the gate and the source to control the conduction and shutdown of the channel between the source and the drain, which can directly drive the load to work. It has a strong load capacity and is mainly used as a voltage-controlled high-voltage driver in various electronic circuits.

[0041] Specifically: If the purpose is only to implement clamping protection for the voltage across the source and drain of the PMOS device, the use of a Zener diode can also achieve the same effect as the TVS device. The difference is that due to the large thermal capacity design of the TVS device, the transient spike absorption capacity of the TVS device is much greater than that of the Zener diode, usually more than 10 times that of the Zener diode. During the design, if it can be confirmed that there is no possibility of high-energy spike pulses in the circuit, the Zener diode can be used. Compared with the TVS device, the package size can also be reduced.

[0042] The quantitative analysis of the PMOS control circuit is as follows: When the gate-source voltage of PMOS |U GS |Greater than the threshold voltage |U GS（th） |, PMOS is turned on. Assuming the threshold voltage |U GSth |=4V, and when |U GS When |(I=1A)=10V, the on-resistance R of the PMOS device DS（ON） =8.5Ω, then when the gate-source voltage |U GS|≥10V, the channel resistance R at both ends of the source and drain of the device DS ≤8.5Ω, so at this time PMOS is equivalent to a closed switch, PMOS is turned on, and I is generated at both ends of the source and drain D The current flows, the circuit does work, and the voltage across the TVS device is pulled down to a reverse biased cutoff state.

[0043] When the voltage between gate and source |U GS |≤Threshold voltage|U GSth |=4V, the channel resistance R at both ends of the source and drain of the PMOS device DS Much larger than 8.5Ω, even R DS tends to infinity, so at this time the PMOS device is equivalent to a switch disconnected, PMOS is cut off, and there is no I D Current is generated, and VCC voltage is applied across the parallel loop of the PMOS device and the TVS device. Both the PMOS device and the TVS device are in the cut-off state, and the circuit does no work at this time.

[0044] The TVS device protection circuit analysis is as follows: When there is no high-energy transient overvoltage shock in the circuit, the TVS device is in a reverse-biased cutoff high-impedance state; when an abnormal overvoltage appears in the circuit, the TVS device quickly changes from a high-impedance state to a low-impedance state, discharging the transient overcurrent caused by the abnormal overvoltage to the ground, and at the same time embedding the abnormal overvoltage into the TVS device embedding voltage value Vc, thereby protecting the source and drain of the PMOS device from breakdown damage caused by the abnormal overvoltage.

[0045] Power consumption of TVS device: Connect load RL to the drain of the circuit schematic, such as Figure 3 shown.

[0046] Assume Vcc=300V. When the circuit is working normally, the maximum operating current in the circuit is IDmax=2mA. The source and drain voltage drop of the PMOS device is VDS=200V. Then the load RL resistance is calculated as: .

[0047] .

[0048] Assume that the circuit has a transient high voltage Vcc = 1500V, the breakdown voltage of the TVS device is V BR =400V, the transient high voltage duration is 1ms, and the TVS device breaks down before the PMOS device. At this time, I D The current is: .

[0049] The power dissipation Ptot generated across the TVS device is: .

[0050] Then the energy Q single (TVS) generated across the TVS device is approximately: .

[0051] Therefore, when the transient high voltage is 1500V and the duration is 1ms, the energy generated by the TVS is approximately, so the total energy Qtotal (TVS) of the six-channel TVS device is approximately: .

[0052] For reliability test circuit: Based on the characteristics of 6 groups of high-voltage MOS array circuits with damping diodes, the main core of the product reliability test circuit can be divided into four aspects: (1) High-temperature reverse bias test for TVS devices: This test mainly involves conducting high-temperature reverse bias tests on TVS devices in products under specified test conditions and test temperatures to assess the time stability of leakage current of the product under reverse bias conditions.

[0053] (2) TVS device pulse power-on test: Mainly conduct power pulse test on TVS devices in the product under specified test conditions and test temperature to assess the pulse peak current and pulse peak power that the product can withstand.

[0054] (3) High temperature reverse bias test of gate-source of PMOS device: Mainly for the PMOS gate-source in the product to work at the specified temperature and 80% of the maximum rated gate-source voltage for at least 48 hours.

[0055] (4) High-temperature power aging circuit of high-voltage MOS array module: It mainly applies a certain power to the product when it is at high temperature (T=125℃) to make the chip work at the highest junction temperature, so as to evaluate the product reliability.

[0056] The specific test method of the reliability test circuit of the high-voltage MOS array is as follows: TVS device high temperature reverse bias test method: set the ambient temperature T = 125 ° C, short the gate-source of the PMOS device, and apply an aging voltage of V to both ends of the TVS device (i.e. between the source and the drain). CC =V BR×80%=375×80%=300V, test time t=240h. In order to prevent abnormal overcurrent in the circuit and damage the device, two resistors are connected in series at the voltage input end (i.e. the source input end), namely a resistor with a resistance of 10k and a power of 1 / 16W, and a resistor with a resistance of 20k and a power of 1w. The purpose of this design is to limit the maximum allowable current in the circuit to 10mA. In addition, if the current in the circuit exceeds 10mA, the power of the resistor with a resistance of 10k is P=(10mA*10mA)2*10k=1W>1 / 16W, so the 10k resistor will first overheat and burn out due to excessive power, thus forming a circuit breaker protection circuit. Figure 5 shown.

[0057] PMOS device gate-source high temperature reverse bias test method: set the ambient temperature T = 125℃, short the drain-source of the PMOS device, and apply an aging voltage V across the gate-source of the PMOS GS = Maximum rated voltage V GS ×80%=20V×0.8=16V, test time t=240h. In order to prevent abnormal overcurrent in the circuit and damage the device, a resistor with a resistance of 16k and a power of 1W is connected in series at the voltage input end (i.e. the gate input end) to limit the maximum current allowed in the circuit to 1mA. Figure 6 shown.

[0058] High-temperature power aging test method for high-voltage MOS array modules: Given the source input power supply voltage V of the six channels in the product CC =10V, the drain output terminal is connected to the load R L =68Ω, let each working current I=100mA, at this time the saturation voltage drop V between the source and drain of the module SD =2V. Then the power dissipation between the source and drain of a single module is P tot（单） =2x0.1=0.2w, so the total current of the six circuits is I 总 =0.6A, total power dissipation P tot (Total) = 0.2*6 = 1.2W. The specific high temperature power aging circuit diagram is as follows Figure 7 shown.

[0059] Beneficial effects of the reliability test scheme: According to the requirements of the burn-in design circuit, three aging circuits are designed for this product: gate-source aging circuit, source-drain aging circuit, and array high-temperature power aging circuit. This design can not only test the source-drain and gate-drain of PMOS, but also include the TVS chip as protection in the test, effectively improving the screening rate.

[0060] During high-temperature power aging, the power supply voltage value can be adjusted and the voltage across the load resistor can be monitored to calculate the PMOS source-drain saturation voltage drop. Based on the thermal resistance formula, the chip can be effectively guaranteed to work under junction temperature conditions, effectively improving product reliability.

[0061] Finally, it should be noted that the above embodiments are merely examples for the purpose of clear explanation. The present invention includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods exhaustively. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. All implementation methods that meet the requirements of the present invention belong to the protection scope of the present invention.

Claims

1. A reliability test method for a high voltage MOS array module, characterized in that: The high-voltage MOS array module includes two or more high-voltage MOS array unit modules and corresponding load modules; The high-voltage MOS array unit module includes a high-voltage MOS device control circuit and a damping protection circuit; The damping protection circuit is connected in reverse parallel to the positive power supply and output end of the high-voltage MOS device control circuit, the output end of each unit module is connected to one end of the load module, and the other end of the load module is connected to the negative power supply end or the ground end; The high-voltage MOS device control circuit and the damping protection circuit of each channel correspond to each other, and the high-voltage MOS device control circuit of each channel with the damping protection circuit is independent of each other; The high voltage MOS array module includes the following test methods: (1) High-temperature reverse bias test method for gate-source of high-voltage MOS device control circuit: The gate-source of the MOS device in the high-voltage MOS device control circuit is operated for at least 48 hours at a specified temperature and 80% of the maximum rated gate-source voltage; (2) High temperature reverse bias test method for damping protection circuit: Perform a high temperature reverse bias test on the damping protection circuit under specified test conditions and test temperature to assess the time stability of the leakage current of the product under reverse bias conditions; (3) Pulse power-on test method for damping protection circuit: Perform a power pulse test on the damping protection circuit under the specified test conditions and test temperature to examine the pulse peak current and pulse peak power that the product can withstand; (4) High-voltage MOS array module high-temperature power aging test method: When the product is at the highest operating temperature, a set power is applied to the product so that the chips in the high-voltage MOS array module operate at the highest junction temperature to assess product reliability.

2. The test circuit of a high voltage MOS array module reliability test method according to claim 1, characterized in that: For the source-drain reverse bias test circuit, the gate and the source are short-circuited and connected, and a source-drain reverse bias test voltage is applied between the source terminal and the drain terminal.

3. The test circuit of a high voltage MOS array module reliability test method according to claim 1, characterized in that: For the gate-source reverse bias test circuit, the drain and the source are short-circuited and connected, and a gate-source reverse bias test voltage is applied between the source terminal and the gate terminal.

4. The test circuit of a high voltage MOS array module reliability test method according to claim 1, characterized in that: For the power aging test circuit: the output end of the unit module is connected to one end of the load module, the other end of the load module is connected to the negative power supply end or the ground end, a bias voltage is applied to the gate end, and a power aging working voltage is applied between the positive power supply end and the negative power supply end or the ground end.

5. A high voltage MOS array module reliability test method as claimed in claim 1, characterized in that: The high-voltage MOS device control circuit is a high-voltage PMOS device chip (PMOS chip for short); The damping protection circuit is a damping diode chip (referred to as TVS chip); The load module is a resistor.

6. A high voltage MOS array module reliability test method as claimed in claim 5, characterized in that: The packaging process of the high voltage MOS array module is as follows: The PMOS chip and the TVS chip are assembled on a set ceramic substrate according to the hybrid integrated circuit integration technology, wire-bonded according to the circuit connection method, and packaged with metal packaging or ceramic packaging.

7. A reliability test method for a high voltage MOS array module as claimed in claim 5, characterized in that: TVS device high temperature reverse bias test method: set the ambient temperature T = 125 ° C, short the gate-source of the PMOS device, and apply an aging voltage across the TVS device: V CC =V BR ×80%=375×80%=300V, test time t=240h; two resistors are connected in series at the voltage input end, namely a resistor with a resistance of 10k and a power of 1 / 16W, and a resistor with a resistance of 20k and a power of 1w.

8. A reliability test method for a high voltage MOS array module as claimed in claim 5, characterized in that: PMOS device gate-source high temperature reverse bias test method: set the ambient temperature T = 125℃, short the drain-source of the PMOS device, and apply an aging voltage V across the gate-source of the PMOS GS = Maximum rated voltage V GS ×80%=20V×0.8=16V, test time t=240h; a resistor with a resistance of 16k and a power of 1W is connected in series at the voltage input end.

9. A reliability test method for a high voltage MOS array module as claimed in claim 5, characterized in that: High-temperature power aging test method for high-voltage MOS array modules: Given the source input power supply voltage V of each channel CC =10V, the drain output terminal is connected to the load R L =68Ω.

10. A reliability test method for a high voltage MOS array module as claimed in claim 9, characterized in that: The gate bias voltage of each channel is provided by a series circuit consisting of a Zener diode and a resistor, the cathode terminal of the Zener diode is connected to the power supply voltage terminal, the anode terminal of the Zener diode is connected to the gate of the MOS device and one end of the resistor, and the other end of the resistor is connected to the ground terminal.

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