Data processing method and device, equipment and storage medium
By using the global address access space in a multi-core controller environment for data mapping and transfer, the problem of data access exceptions in a multi-core environment is solved, and data accuracy and software deployment flexibility are improved.
Patent Information
- Application Number
- CN202310961193.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-01
- Publication Date
- 2025-02-14
AI Technical Summary
In a multi-core controller environment, data access exceptions lead to low data accuracy and insufficient software deployment flexibility.
By selecting the second access address associated with the first access address in the global address access space, the second kernel is allowed to write the target data to the address, and the first kernel reads the data from the address, avoiding direct from the second The kernel's access address reads data to solve the problem of data access exceptions.
Improves data accuracy and enhances the flexibility of software deployment, so that software deployment is not necessary to be considered on the same core.
Smart Images
Figure CN119440865A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, device, equipment and storage medium. Background Art
[0002] The program in the controller is designed and developed by software engineers. Initially, these parameters cannot be accurately set to reasonable values. These parameters need to be set in experiments based on economy, power, comfort and meeting emission regulations. This part of the work is done by calibration engineers after software development, who use repeated iterations to analyze the performance by changing parameters for final determination. Therefore, calibration engineers need to obtain different parameters in the software, and then conduct problem analysis or performance optimization.
[0003] When the controller is a single-core controller, the data of the variable is written into the corresponding address space according to the calibration protocol, and after the kernel receives the observation request, it accesses the address space corresponding to the observation request.
[0004] When the controller is a multi-core controller, the controller includes multiple cores. The running processes of each core of the controller are independent of each other. A single core directly accesses the address space corresponding to other cores. When the accessed address space is performing data operations, data access anomalies will occur, reducing data accuracy. In addition, because data access between different cores may cause anomalies, software engineers need to deploy related interactive software on the same core as much as possible when deploying software, which reduces the flexibility of software deployment. Summary of the invention
[0005] The present disclosure provides a data processing method, device, equipment and storage medium to at least solve the technical problem of low accuracy of data of multiple controllers.
[0006] The present disclosure provides a data processing method, including:
[0007] Receive a data read request for a first access address sent by a data requester;
[0008] If the first access address does not belong to the first kernel, determining a second kernel to which the first access address belongs;
[0009] Selecting a second access address associated with the first access address from a global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide idle access addresses for access address mapping by the first core and the second core;
[0010] The target data is read from the second access address.
[0011] Optionally, determining the second kernel to which the first access address belongs includes:
[0012] A mapping relationship table between access addresses and kernels is queried to obtain the second kernel to which the first access address belongs.
[0013] Optionally, after determining the second core to which the first access address belongs, the method further includes:
[0014] generating a second kernel address read request, wherein the second kernel address read request carries the first access address;
[0015] The second kernel address read request is written into the global address access space so that the second kernel can read the second kernel address read request.
[0016] Optionally, selecting a second access address associated with the first access address from the global address access space includes:
[0017] According to the priority of the access address in the global address space, an access address in a null state is selected from the global address access space as the second access address associated with the first access address.
[0018] The present disclosure also provides a data processing method, including:
[0019] querying whether a second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address, the global address access space can provide an idle access address for the first kernel and the second kernel to perform access address mapping, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space;
[0020] In a case where the second kernel address read request is stored in the global address access space, obtaining a second access address associated with the first access address;
[0021] Writing target data corresponding to the first access address into the second access address, so that the first core reads the target data from the second access address.
[0022] Optionally, after writing the target data corresponding to the first access address into the second access address, the method further includes:
[0023] A target data write completion flag is written into the second access address.
[0024] The present disclosure also provides a data processing device, including:
[0025] A receiving module, used for receiving a data read request of a first access address sent by a data requester;
[0026] a determination module, configured to determine, when the first access address does not belong to the first kernel, a second kernel to which the first access address belongs;
[0027] a selection module, configured to select a second access address associated with the first access address from a global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide idle access addresses for access address mapping by the first core and the second core;
[0028] A reading module is used to read the target data from the second access address.
[0029] The present disclosure also provides a data processing device, including:
[0030] a query module, configured to query whether a second kernel address read request is stored in a global address access space, wherein the second kernel address read request carries the first access address, the global address access space can provide an idle access address for access address mapping between the first kernel and the second kernel, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space;
[0031] an acquisition module, configured to acquire a second access address corresponding to the first access address when the second kernel address read request is stored in the global address access space;
[0032] A writing module is used to write target data corresponding to the first access address into the second access address, so that the first kernel can read the target data from the second access address.
[0033] The present disclosure also provides an electronic device, characterized in that it includes: a memory and a processor;
[0034] The memory is used to store computer programs;
[0035] The processor is used to execute the computer program to implement each step in the above method.
[0036] The embodiment of the present disclosure also provides a controller, including: a memory and a processor;
[0037] The memory is used to store computer programs;
[0038] The processor comprises: a first core and a second core;
[0039] The first kernel receives a data read request for a first access address sent by a data requester; if the first access address does not belong to the first kernel, determines a second kernel to which the first access address belongs; selects a second access address associated with the first access address from a global address access space, so that the second kernel writes target data corresponding to the first access address into the second access address, wherein the global address space can provide an idle access address for access address mapping between the first kernel and the second kernel; and reads the target data from the second access address;
[0040] The second kernel is used to query whether the second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address; in the case where the second kernel address read request is stored in the global address access space, obtain a second access address corresponding to the first access address; write target data corresponding to the first access address into the second access address, so that the first kernel can read the target data from the second access address.
[0041] The embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements each step of the above method when executed by a processor.
[0042] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:
[0043] In some embodiments of the present disclosure, when the processor is a multi-core processor, the first core in the processor receives a data read request for a first access address sent by a data requester; when the first access address does not belong to the first core, the second core to which the first access address belongs is re-determined; the global address space can provide the first core and the second core with an idle access address for access address mapping, the second core can write the target data corresponding to the first access address into the second access address of the global address access space, and the first core reads the target data from the second access address. The present disclosure sets an independent global address access space, and the first core can read data from the independent global address access space, thereby avoiding the situation where the first core directly reads data from the access address corresponding to the second core, causing data access anomalies, and improving data accuracy; in this regard, when deploying software, it is not necessary to consider whether the software needs to be deployed on the same core, thereby increasing the flexibility of software deployment. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 A flowchart of a data processing method provided for an exemplary embodiment of the present disclosure;
[0045] Figure 2 A flowchart of another data processing method provided for an exemplary embodiment of the present disclosure;
[0046] Figure 3 A flowchart of another data processing method provided for an exemplary embodiment of the present disclosure;
[0047] Figure 4 A schematic diagram of the structure of a data processing device provided for an exemplary embodiment of the present disclosure;
[0048] Figure 5 A schematic diagram of the structure of a data processing device provided for an exemplary embodiment of the present disclosure;
[0049] Figure 6 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of the present disclosure;
[0050] Figure 7 A schematic structural diagram of another electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0051] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0052] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0054] It should be noted that the user information involved in this disclosure includes but is not limited to: user device information and user personal information; the collection, storage, use, processing, transmission, provision and disclosure of user information in this disclosure comply with the relevant laws and regulations and do not violate public order and good morals.
[0055] Currently, the following two data reading methods are used for multi-core data access.
[0056] In response to the above-mentioned technical problems, in some embodiments of the present disclosure, when the processor is a multi-core processor, the first core in the processor receives a data read request for a first access address sent by a data requester; when the first access address does not belong to the first core, the second core to which the first access address belongs is re-determined; the global address space can provide the first core and the second core with an idle access address for access address mapping, the second core can write the target data corresponding to the first access address into the second access address of the global address access space, and the first core reads the target data from the second access address. The present disclosure sets an independent global address access space, and the first core can read data from the independent global address access space, thereby avoiding the situation where the first core directly reads data from the access address corresponding to the second core, causing data access anomalies, and improving data accuracy; in addition, when deploying software, there is no need to consider whether the software needs to be deployed on the same core, which increases the flexibility of software deployment.
[0057] The technical solutions provided by various embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.
[0058] Figure 1 A flowchart of a data processing method provided by an exemplary embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the method includes:
[0059] S101: receiving a data read request for a first access address sent by a data requester;
[0060] S102: if the first access address does not belong to the first core, determine the second core to which the first access address belongs;
[0061] S103: Selecting a second access address associated with the first access address from the global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide idle access addresses for access address mapping between the first core and the second core;
[0062] S104: Read target data from the second access address.
[0063] Figure 2 FIG. 1 is a flow chart of another data processing method provided by an exemplary embodiment of the present disclosure. Figure 2 As shown, the method includes:
[0064] S201: Query whether a second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address; the global address access space can provide an idle access address for the first kernel and the second kernel to perform access address mapping, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space;
[0065] S202: When a second kernel address read request is stored in the global address access space, obtain a second access address associated with the first access address;
[0066] S203: Write the target data corresponding to the first access address into the second access address, so that the first core can read the target data from the second access address.
[0067] In this embodiment, the execution subjects of the above two data processing methods can be different cores of the same controller. The controller in the present disclosure is a multi-core controller, the controller includes a processor, and the processor includes multiple cores. Among them, the present disclosure does not limit the type of controller, and the controller can be a microcontroller, an electric vehicle controller, a combinational logic controller, a CPU controller, etc.
[0068] In addition, it should be noted that the execution entities of the above two data processing methods can also be two different processors or two different devices.
[0069] In this embodiment, a different address space is allocated to each core in the memory of the controller. In the disclosed embodiment, an independent global address access space is also provided for temporary storage of data.
[0070] It should be noted that the global address access space in the embodiment of the present disclosure is an address space independent of the address space of the first kernel and the address space of the second kernel. The global address access space can provide the first kernel and the second kernel with free access addresses for address mapping. The global address access space is a memory area for storing global variables and global objects. During program execution, global variables can be accessed by any function or module, not limited to the scope in which they are defined.
[0071] For example, the address space of the first core includes: access address a1, access address a2 and access address a3; the address space of the second core includes: access address b1, access address b2 and access address b3. Accordingly, the global address access space can reserve corresponding access addresses for the access addresses sent by the data requester, so as to provide data access for the first core and the second core.
[0072] In this embodiment, the first core in the processor receives a data read request for the first access address sent by the data requester; when the first access address does not belong to the first core, the second core to which the first access address belongs is re-determined; the global address space can provide the first core and the second core with an idle access address for access address mapping, the second core writes the target data corresponding to the first access address into the second access address of the global address access space, and the first core reads the target data from the second access address. The present disclosure sets an independent global address access space, and the first core can read data from the independent global address access space, avoiding the situation where the first core directly reads data from the access address corresponding to the second core, causing data access abnormality, and improving data accuracy. In this regard, when deploying software, it is not necessary to consider whether the software needs to be deployed on the same core, which increases the flexibility of software deployment.
[0073] In some embodiments of the present disclosure, the first kernel receives a data read request for a first access address sent by a data requester, and reads target data corresponding to the first access address when the first access address belongs to the first kernel. When the first access address that the data requester needs to access belongs to the first kernel, the first kernel can directly read the target data corresponding to the first access address.
[0074] For example, the first kernel receives a data read request for access address a1 sent by the data requester, queries the mapping table between access address and kernel, and obtains that access address a1 belongs to the first kernel. Then, the first kernel directly reads the target data corresponding to access address a1.
[0075] It should be noted that the first core and the second core in the above embodiment may be any core in the processor, and the second core may be any core in the processor except the first core. The first core may be preset, and the data read request of the data requesting party may be sent to the first core first. Alternatively, the core to which the data read request is currently sent may be determined based on the current actual usage of multiple cores.
[0076] In some embodiments of the present disclosure, a mapping relationship table between access addresses and cores is pre-set. For example, the first core corresponds to access addresses 1 to 11, the second core corresponds to access addresses 11 to 20, and the third core corresponds to access addresses 21 to 30.
[0077] In some embodiments of the present disclosure, after receiving a data read request for a first access address sent by a data requester, the first kernel queries the mapping relationship table between the access address and the kernel to query whether the first access address belongs to the first kernel. If the first access address does not belong to the first kernel, the mapping relationship table between the access address and the kernel is queried to determine the second kernel to which the first access address belongs. The present disclosure can quickly query the kernel to which the access address belongs by presetting the mapping relationship table between the access address and the kernel, thereby improving data reading efficiency.
[0078] For example, after the first kernel receives a data read request for access address b1 sent by the data requester, it queries the mapping relationship table between the access address and the kernel. The access address b1 does not belong to the first kernel, but belongs to the second kernel. By setting the mapping relationship table between the access address and the kernel, the kernel to which the access address belongs can be quickly queried, thereby improving data reading efficiency.
[0079] In some embodiments of the present disclosure, a second access address associated with a first access address is selected from a global address access space. In one achievable manner, an access address in an empty state is selected from the global address access space according to the priority of the access address in the global address space as the second access address associated with the first access address. In another achievable manner, an access address in an empty state is randomly selected from the global address access space as the second access address associated with the first access address.
[0080] For example, after determining that access address b1 belongs to the second core, the first core selects access address c1 in the global address access space in the empty state as the access address associated with access address b1 according to the priority of the access address in the global address space.
[0081] For another example, after determining that the access address b1 belongs to the second core, the first core randomly selects an access address c2 in a blank state from all access addresses in the global address access space as the access address associated with the access address b1.
[0082] In the above embodiment, an address identification number is added to each access address in the global address space, and the priority of the access address in the global address space can be distinguished according to the address identification number, and the larger the sequence number in the address identification number, the higher the priority, or the smaller the sequence number in the address identification number, the higher the priority. For example, for access address c1, access address c2 and access address c3 in the global address space, access address c1 has the smallest sequence number and the highest priority.
[0083] In some embodiments of the present disclosure, after determining the second core to which the first access address belongs, the first core generates a second core address read request, wherein the second core address read request carries the first access address; and writes the second core address read request into the global address access space so that the second core can read the second core address read request.
[0084] For example, after the first core determines that the access address b1 belongs to the second core, it generates a second core address read request carrying the access address b1 and writes the second core address read request into the global address access space. The second core can read the second core address read request from the global address access space.
[0085] In some embodiments of the present disclosure, the second core queries whether the second core address read request is stored in the global address access space. One achievable manner is that in response to the set period arrival operation, the second core queries whether the second core address read request is stored in the global address access space. It should be noted that the present disclosure does not limit the set period, and it can be adjusted according to actual conditions. The set period is, for example, 1 second, 2 seconds or 5 seconds.
[0086] In some embodiments of the present disclosure, when a second core address read request is stored in the global address access space, the second core obtains a second access address corresponding to the first access address; and writes target data corresponding to the first access address to the second access address so that the first core can read the target data from the second access address.
[0087] For example, when the second core queries and finds that a second core address read request is stored in the global address access space, the second core obtains the access address c1 corresponding to the access address b1 from the global address access space, and writes the target data A corresponding to the access address b1 into the access address c1. The first core can directly read the target data A from the access address c1 of the global address access space.
[0088] In the above embodiment, after the second core writes the target data corresponding to the first access address to the second access address, it writes the target data write completion flag to the second access address and sets the target data write completion flag to be valid; after the first core reads the target data from the second access address, it sets the target data write completion flag to be invalid. Then, after the second core queries whether the second core address read request is stored in the global address access space, if the target data write completion flag is set to be valid, the first core has not read data from the global address access space.
[0089] For example, after the second core writes the target data A of the access address b1 into the access address c1 of the global address access space, it adds a write completion flag to the access address c1 and sets the write completion flag to be valid; after the first core reads the target data A from the access address c1, it sets the write completion flag to be invalid. The second core can determine whether the first core reads the target data A from the global address access space based on whether the write completion flag is valid. If the write completion flag is set to be valid, the first core has not read the target data A from the global address access space.
[0090] In some embodiments of the present disclosure, after the first kernel reads the target data from the second access address in the global address access space, it deletes the target data, the second kernel address read request and the target data write completion flag from the global address access space to complete the acquisition of the target data. The second access address in the global address access space can also be used for writing subsequent data, thereby improving the utilization rate of the access address.
[0091] In combination with the description of the above embodiments, when developing multi-core controller software, it is not necessary to place all observation data in one core; and after the observation data is obtained, data analysis can be performed directly without outlier filtering.
[0092] In combination with the description in the above embodiments, Figure 3 FIG. 1 is a flow chart of another data processing method provided by an exemplary embodiment of the present disclosure. Figure 3 As shown, the method includes:
[0093] S301: A first core of a processor receives a data read request of a first access address sent by a data requester;
[0094] S302: The first kernel determines, when the first access address does not belong to the first kernel, a second kernel to which the first access address belongs;
[0095] S303: The first kernel selects a second access address associated with the first access address from the global address access space;
[0096] S304: The second kernel queries whether a second kernel address read request is stored in the global address access space;
[0097] S305: When the second kernel stores the second kernel address read request in the global address access space, the second kernel obtains a second access address corresponding to the second kernel address read request;
[0098] S306: The second kernel writes the target data corresponding to the first access address into the second access address;
[0099] S307: The first kernel reads target data from the second access address.
[0100] In this embodiment, the main device of the above method can be a controller. The controller in the present disclosure is a multi-core controller, which includes a processor, and the processor includes multiple cores. The present disclosure does not limit the type of controller, and the controller can be a microcontroller, an electric vehicle controller, a combinational logic controller, a CPU controller, etc.
[0101] The implementation method of each step in this embodiment can refer to the description of the above embodiments, and will not be repeated in this embodiment.
[0102] In the above-mentioned method embodiment of the present disclosure, when the processor is a multi-core processor, the first core in the processor receives a data read request for a first access address sent by a data requester; when the first access address does not belong to the first core, the second core to which the first access address belongs is re-determined; the second core writes the target data corresponding to the first access address into the second access address of the global address access space, and the first core reads the target data from the second access address. The global address access space is different from the address space corresponding to the first core and the second core. The present disclosure sets an independent global address access space, and the first core can read data from the independent global address access space, thereby avoiding the situation where the first core directly reads data from the access address corresponding to the second core, causing data access abnormalities, and improving data accuracy.
[0103] Figure 4 FIG. 4 is a schematic diagram of a data processing device 40 provided by an exemplary embodiment of the present disclosure. Figure 4 As shown, the data processing device 40 includes: a receiving module 41, a determining module 42, a selecting module 43 and a reading module 44.
[0104] The receiving module 41 is used to receive a data read request of a first access address sent by a data requester;
[0105] A determination module 42, for determining a second core to which the first access address belongs when the first access address does not belong to the first core;
[0106] A selection module 43 is used to select a second access address associated with the first access address from the global address access space, so that the second core writes the target data corresponding to the first access address into the second access address, wherein the global address space can provide an idle access address for the first core and the second core to perform access address mapping;
[0107] The reading module 44 is configured to read target data from the second access address.
[0108] Optionally, the reading module 44 may also be used to read target data corresponding to the first access address when the first access address belongs to the first kernel.
[0109] Optionally, when determining the second kernel to which the first access address belongs, the determination module 42 is configured to:
[0110] The mapping relationship table between the access address and the kernel is queried to obtain the second kernel to which the first access address belongs.
[0111] Optionally, after determining the second core to which the first access address belongs, the determination module 42 may also be used to:
[0112] generating a second kernel address read request, wherein the second kernel address read request carries the first access address;
[0113] The second core address read request is written into the global address access space so that the second core can read the second core address read request.
[0114] Optionally, when selecting the second access address associated with the first access address from the global address access space, the selection module 43 is configured to:
[0115] According to the priority of the access address in the global address space, an access address in a null state is selected from the global address access space as the second access address associated with the first access address.
[0116] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.
[0117] Figure 5 FIG. 5 is a schematic diagram of a data processing device 50 provided by an exemplary embodiment of the present disclosure. Figure 5 As shown, the data processing device 50 includes: a query module 51, an acquisition module 52 and a writing module 53.
[0118] The query module 51 is used to query whether a second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address, the global address space can provide an idle access address for the first kernel and the second kernel to perform access address mapping, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space;
[0119] an acquisition module 52, for acquiring a second access address associated with the first access address when a second kernel address read request is stored in the global address access space;
[0120] The writing module 53 is used to write the target data corresponding to the first access address into the second access address, so that the first core can read the target data from the second access address.
[0121] Optionally, after writing the target data corresponding to the first access address into the second access address, the writing module 53 may also be used to:
[0122] The target data write completion flag is written into the second access address.
[0123] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.
[0124] Figure 6 FIG. 1 is a schematic diagram of a structure of an electronic device provided by an exemplary embodiment of the present disclosure. Figure 6 As shown, the electronic device includes: a memory 61 and a processor 62. In addition, the electronic device also includes a power supply component 63 and a communication component 64.
[0125] The memory 61 is used to store computer programs and can be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application program or method operating on the electronic device.
[0126] Memory 61 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
[0127] The communication component 64 is used for data transmission with other devices.
[0128] The processor 62 can execute computer instructions stored in the memory 61 to: receive a data read request of a first access address sent by a data requester;
[0129] If the first access address does not belong to the first core, determining the second core to which the first access address belongs;
[0130] Selecting a second access address associated with the first access address from the global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide an idle access address for the first core and the second core to perform access address mapping;
[0131] The target data is read from the second access address.
[0132] Optionally, the processor 62 may also be configured to: read target data corresponding to the first access address when the first access address belongs to the first core.
[0133] Optionally, when determining the second core to which the first access address belongs, the processor 62 is configured to:
[0134] The mapping relationship table between the access address and the kernel is queried to obtain the second kernel to which the first access address belongs.
[0135] Optionally, after determining the second core to which the first access address belongs, the processor 62 may further be configured to:
[0136] generating a second kernel address read request, wherein the second kernel address read request carries the first access address;
[0137] The second core address read request is written into the global address access space so that the second core can read the second core address read request.
[0138] Optionally, when the processor 62 selects the second access address associated with the first access address from the global address access space, it is configured to:
[0139] According to the priority of the access address in the global address space, an access address in a null state is selected from the global address access space as the second access address associated with the first access address.
[0140] Figure 7 FIG. 1 is a schematic diagram of another electronic device provided by an exemplary embodiment of the present disclosure. Figure 7 As shown, the electronic device includes: a memory 71 and a processor 72. In addition, the electronic device also includes a power supply component 73 and a communication component 74.
[0141] The memory 71 is used to store computer programs and can be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application or method operating on the electronic device.
[0142] The memory 71 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
[0143] The communication component 74 is used for data transmission with other devices.
[0144] The processor 72 can execute the computer instructions stored in the memory 71, so as to: query whether a second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address, the global address access space can provide an idle access address for the first kernel and the second kernel to perform access address mapping, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space;
[0145] In a case where a second kernel address read request is stored in the global address access space, obtaining a second access address associated with the first access address;
[0146] The target data corresponding to the first access address is written into the second access address, so that the first core reads the target data from the second access address.
[0147] Optionally, after writing the target data corresponding to the first access address into the second access address, the processor 72 may further be configured to:
[0148] The target data write completion flag is written into the second access address.
[0149] Accordingly, the present disclosure also provides a computer-readable storage medium storing a computer program. When the computer-readable storage medium stores the computer program and the computer program is executed by one or more processors, the one or more processors execute Figure 1 or Figure 2 Each step in the method embodiment.
[0150] Accordingly, the present disclosure also provides a computer program product, the computer program product includes a computer program / instruction, the computer program / instruction is executed by a processor Figure 1 or Figure 2 Each step in the method embodiment.
[0151] In the above-mentioned apparatus, device, storage medium and computer program product embodiments of the present disclosure, when the processor is a multi-core processor, the first core in the processor receives a data read request for a first access address sent by a data requester; when the first access address does not belong to the first core, the second core to which the first access address belongs is re-determined; the local address space can provide the first core and the second core with an idle access address for access address mapping, the second core can write the target data corresponding to the first access address into the second access address of the global address access space, and the first core reads the target data from the second access address. The global address access space is different from the address space corresponding to the first core and the second core. The present disclosure sets an independent global address access space, and the first core can read data from the independent global address access space, thereby avoiding the situation where the first core directly reads data from the access address corresponding to the second core, causing data access abnormality, and improving data accuracy; in this regard, when deploying software, it is not necessary to consider whether the software needs to be deployed on the same core, which increases the flexibility of software deployment.
[0152] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0153] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0154] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0155] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0156] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0157] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.
[0158] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.
[0159] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0160] The above are only specific embodiments of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A data processing method, characterized in that: include: Receive a data read request for a first access address sent by a data requester; If the first access address does not belong to the first kernel, determining a second kernel to which the first access address belongs; Selecting a second access address associated with the first access address from a global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide idle access addresses for access address mapping by the first core and the second core; The target data is read from the second access address.
2. The method according to claim 1, characterized in that The determining the second core to which the first access address belongs includes: A mapping relationship table between access addresses and kernels is queried to obtain the second kernel to which the first access address belongs.
3. The method according to claim 1, characterized in that After determining the second core to which the first access address belongs, the method further includes: generating a second kernel address read request, wherein the second kernel address read request carries the first access address; The second kernel address read request is written into the global address access space so that the second kernel can read the second kernel address read request.
4. The method according to claim 1, characterized in that The selecting a second access address associated with the first access address from the global address access space includes: According to the priority of the access address in the global address space, an access address in a null state is selected from the global address access space as the second access address associated with the first access address.
5. A data processing method, characterized in that: include: querying whether a second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address, the global address access space can provide an idle access address for the first kernel and the second kernel to perform access address mapping, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space; In a case where the second kernel address read request is stored in the global address access space, obtaining a second access address associated with the first access address; Writing target data corresponding to the first access address into the second access address, so that the first core reads the target data from the second access address.
6. The method according to claim 5, characterized in that After writing the target data corresponding to the first access address into the second access address, the method further includes: A target data write completion flag is written into the second access address.
7. A data processing device, characterized in that: include: A receiving module, used for receiving a data read request of a first access address sent by a data requester; a determination module, configured to determine, when the first access address does not belong to the first kernel, a second kernel to which the first access address belongs; a selection module, configured to select a second access address associated with the first access address from a global address access space, so that the second core writes target data corresponding to the first access address into the second access address, wherein the global address space can provide idle access addresses for access address mapping by the first core and the second core; A reading module is used to read the target data from the second access address.
8. A data processing device, characterized in that: include: a query module, configured to query whether a second kernel address read request is stored in a global address access space, wherein the second kernel address read request carries the first access address, the global address access space can provide an idle access address for access address mapping between the first kernel and the second kernel, the second kernel address read request is a request generated by the first kernel after determining the second kernel to which the first access address belongs when the first access address does not belong to the first kernel, and the first kernel writes the second kernel address read request into the global address access space; an acquisition module, configured to acquire a second access address corresponding to the first access address when the second kernel address read request is stored in the global address access space; A writing module is used to write target data corresponding to the first access address into the second access address, so that the first kernel can read the target data from the second access address.
9. An electronic device, characterized in that: include: Memory and processor; The memory is used to store computer programs; The processor is used to execute the computer program to implement each step in the method as described in any one of claims 1-4 or 5-6.
10. A controller, characterized in that: include: Memory and processor; The memory is used to store computer programs; The processor comprises: a first core and a second core; The first kernel receives a data read request for a first access address sent by a data requester; if the first access address does not belong to the first kernel, determines a second kernel to which the first access address belongs; selects a second access address associated with the first access address from a global address access space, so that the second kernel writes target data corresponding to the first access address into the second access address, wherein the global address space can provide an idle access address for access address mapping between the first kernel and the second kernel; and reads the target data from the second access address; The second kernel is used to query whether the second kernel address read request is stored in the global address access space, wherein the second kernel address read request carries the first access address; in the case where the second kernel address read request is stored in the global address access space, obtain a second access address corresponding to the first access address; write target data corresponding to the first access address into the second access address, so that the first kernel can read the target data from the second access address.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the method according to any one of claims 1 to 4 or 5 to 6 is implemented.