Multi-scene multi-algorithm adaptive vector memory access controller implementation method

Abstract

The invention relates to the technical field of vector processors, and discloses a multi-scene multi-algorithm adaptive vector memory access controller implementation method, which comprises the following steps that a memory access control module acquires a configuration signal of an upper computer, determines a data reading mode and algorithm parallelism and generates a memory access control signal; the memory access state module responds to the memory access control signal and generates a reading control instruction and a writing control instruction; the source data module responds to the reading control instruction, reads source data from a storage resource, and sends the source data to a computing resource for data operation to obtain result data; and the result data module responds to the writing control instruction, obtains result data from the computing resources and writes the result data into the storage resources. According to the method, the algorithm implementation modes can be flexibly selected according to the algorithm parallelism degree, the data batch number and the data point number, so that better vector memory access performance is obtained under different application scenes or different data dimensions.

Description

Technical Field

[0001] The present invention relates to the technical field of vector processors, and in particular to a method for implementing a vector memory access controller adapted for multiple scenarios and multiple algorithms. Background Art

[0002] Vector operations can perform calculations on one or more groups of data at the same time, which can significantly increase the data processing speed, and is therefore particularly suitable for parallel processing architectures. However, to fully utilize the advantages of vector operations, it is necessary to ensure that data can be quickly and accurately read from the memory to the computing unit, and that the calculation results can be efficiently written back to the memory. This requires not only that the storage system has high bandwidth characteristics, but also that there is an effective mechanism to manage the data flow so that data can reach the correct processing unit at the right time.

[0003] At present, there are many vector processor design solutions optimized for specific scenarios in the industry. For example, SIMD (single instruction multiple data) architecture is widely used in graphics processing units (GPUs) to accelerate large-scale parallel computing tasks; and in some application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) solutions, highly optimized data paths are implemented through customized hardware logic. Although these solutions perform well in their respective application scopes, they are often difficult to flexibly respond to diverse computing needs or require high development costs. Many existing solutions are specially designed to solve a certain type of problem, lack sufficient versatility and configurability, and may need to redesign the entire system once the application scenario changes. When the data set processed is small or the features are irregular, existing vector processors may have a large number of idle cycles, resulting in overall performance degradation. Even when technologies such as caches are used, frequent memory access is still an important factor limiting overall performance. This is particularly prominent in tasks involving large amounts of small batches of data. In the face of the above situation, it is particularly important to build a vector memory access control system that is both widely applicable and can provide excellent performance.

[0004] For example, a Chinese patent with the authorization announcement number CN102279818B discloses a vector data access control method and vector memory supporting limited sharing, and the method steps are as follows: 1) uniformly addressing the vector memory; 2) obtaining access information, decomposing, expanding, and shifting and cyclically arranging the vector address in the access information to generate N sets of access information; 3) sending the N sets of access information to the access pipeline of the vector storage body respectively; if the current vector access instruction is a read instruction, reversely shifting and cyclically arranging the N-way write-back data according to the shared shift address to obtain N sets of write-back data and sending them to the corresponding vector processing unit in the vector processor; the vector memory includes a vector address generator, a vector storage body unit, and a memory access management control unit, and the memory access management control unit includes a vector address arranging unit and a vector data arranging unit. The invention has the advantages of low hardware implementation cost, supporting limited sharing of vector data and non-aligned access.

[0005] For example, the patent application with publication number CN104699458A discloses a vector processor for online time series prediction. It is to solve the problem that the existing vector processor cannot be optimized for a specific method, resulting in low versatility and inability to meet the needs of online computing. The fixed-point vector processor described in the invention includes a program counter, a microcode memory, a vector memory, an arithmetic logic unit and a data control unit. Through the signal processing flow between the various modules of the aforementioned fixed-point vector processor, a complete fixed-point vector processor is constructed. Through the heterogeneous ALU design, the ALU structure of each data path can be flexibly changed according to the computing needs, realizing flexible configuration of the instruction set. It is suitable for occasions with complex computing needs.

[0006] The above patents all have the problem raised by this background technology: memory access does not distinguish data configuration information, and all use the same method to implement algorithms under different configurations, resulting in low resource utilization and low transfer efficiency.

[0007] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgement or any form of suggestion that the information constitutes the prior art already known to ordinary technicians in this field. Summary of the invention

[0008] The technical problem to be solved by the present invention is to overcome the defects of the prior art, provide a method for implementing a vector memory access controller that is adapted to multiple scenarios and multiple algorithms, separate the design of data storage and data processing based on the design concept of storage and calculation decoupling, extract the common factors between vector algorithms, and design a vector memory access controller that supports both stream mode and batch mode implementations, which can implement vector algorithms such as vector addition and subtraction, vector dot multiplication, vector multiplication, vector summation, and vector mean based on the configuration information sent by the host computer. For the same algorithm, two implementation methods, stream mode and batch mode, are proposed, and the algorithm implementation method can be flexibly selected according to the algorithm parallelism, the number of data batches, and the number of data points, so as to achieve better vector memory access performance in different application scenarios or different data dimensions.

[0009] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0010] On the one hand, the present invention provides a method for implementing a vector memory access controller adapted for multiple scenarios and multiple algorithms, wherein the vector memory access controller comprises a memory access state module, a memory access control module, a source data module and a result data module; the method comprises the following steps:

[0011] The memory access control module obtains the configuration signal of the host computer, determines the source data reading mode, the result data writing mode and the algorithm parallelism, and generates the memory access control signal;

[0012] The memory access state module generates a read control instruction and a write control instruction in response to the memory access control signal;

[0013] The source data module responds to the reading control instruction, reads the source data from the storage resource, and sends it to the computing resource for data operation to obtain result data;

[0014] The result data module responds to the write control instruction, obtains the result data from the computing resource and writes it into the storage resource.

[0015] As a preferred solution of the method for implementing the vector memory access controller for multi-scenario multi-algorithm adaptation of the present invention, wherein: the source data reading mode includes a stream mode and a batch mode; the method for determining the source data reading mode is as follows:

[0016] If the data collected by a single sensor is collected sequentially in a data stream manner and the data is horizontally stored in the storage resource, the source data reading mode adopts a stream mode; wherein the horizontal storage means that the data received in each clock cycle of length Δt is horizontally arranged in the storage resource in time order;

[0017] If a single type of data collected by multiple sensors is collected in the form of multiple batches of data, and the data is stored vertically in the storage resource by batches, then the source data reading mode adopts the batch mode; the vertical storage by batches means that the data collected by different sensors are stored in the form of a two-dimensional array in the storage resource, wherein any row of the two-dimensional array represents the same batch of data collected by different sensors, and any column represents different batches of data collected by the corresponding sensor.

[0018] As a preferred solution of the method for implementing the vector memory access controller for multi-scenario multi-algorithm adaptation of the present invention, wherein: the algorithm parallelism represents the number of source data read when reading source data from the storage resource at any one time;

[0019] The configuration signal is a signal sent from the host computer to the vector memory access controller, and is used to configure the behavior of the controller;

[0020] The memory access control signal is used to control the state jump of the main state machine, the source data state machine, and the result data state machine.

[0021] As a preferred solution of the implementation method of the vector memory access controller adapted for multiple scenarios and multiple algorithms described in the present invention, wherein: the memory access state module includes a main state machine, a source data state machine, and a result data state machine; wherein the main state machine is used to respond to a memory access control signal, and control the working state of the vector memory access controller, including controlling the state jump of the source data state machine and the result data state machine; the source data state machine is used to generate a reading control instruction, and drive the source data module to perform source data reading operations; the result data state machine is used to generate a writing control instruction, and control the result data module to perform result data writing operations.

[0022] As a preferred solution of the implementation method of the vector memory access controller for multi-scenario multi-algorithm adaptation described in the present invention, wherein: if the source data reading mode is the stream mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data horizontally from the storage resource each time, where m is the algorithm parallelism; the m source data read horizontally each time are consecutive m in the same batch of source data, wherein any batch of source data is collected based on the same sensor; if there are n remaining source data in a single batch involved in the i-th reading of the source data, and n is less than m, and i is any positive integer, then the control module generates a batch end zeroing signal, the source data module responds to the batch end zeroing signal, reads the remaining n source data, and adds mn data assigned to 0 after the n source data, and transmits them together to the computing resource; if the reading of all batches of data is not completed at this time, then at the beginning of the i+1-th reading of the source data, the control module generates a batch beginning zeroing signal, the source data module responds to the batch beginning zeroing signal, reads mn source data in the next batch of source data, and adds n data assigned to 0 before the mn source data, and transmits them together to the computing resource.

[0023] As a preferred solution for the implementation method of the vector memory access controller adapted for multiple scenarios and multiple algorithms described in the present invention, wherein: if the source data reading mode is a batch mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data horizontally from the storage resource each time, where m is the algorithm parallelism; the m source data read horizontally each time are m batches of source data at the same time point, where the m batches of source data are respectively collected based on m sensors; if the number of source data batches involved in the j-th reading of the source data is k, and k is less than m, and j is an arbitrary positive integer, the algorithm parallelism is adjusted to k, and k source data are read horizontally and sent to the computing resource.

[0024] As a preferred solution of the method for implementing the vector memory access controller for multi-scenario multi-algorithm adaptation of the present invention, if the source data reading mode is the stream mode, the method for performing data operation is as follows: using the algorithm-level API to call the vector algorithm, or using the unit-level API to call the stream mode of the computing unit, and calling the multiplication-accumulation tree to perform the vector operation;

[0025] If the source data reading mode is the batch mode, the method for performing data operations is as follows: the batch mode of the computing unit is called using the unit-level API, and multiplication and accumulation are called to perform vector operations.

[0026] As a preferred solution of the method for implementing the vector memory access controller for multi-scenario multi-algorithm adaptation of the present invention, wherein: the source data module is instantiated in the vector memory access controller where m is the parallelism of the algorithm and is a positive integer. Indicates rounding up; each source data module generates two sets of source data channels, and the control vector memory access controller simultaneously interacts with the storage resources and computing resources in the two sets of source data channels;

[0027] The result data module is instantiated in the vector memory controller Each result data module generates two groups of result data channels, and the control vector memory access controller interacts with the storage resources and the computing resources in the two groups of result data channels at the same time.

[0028] In a second aspect, the present invention provides an electronic device, comprising: a memory for storing instructions; a processor for executing the instructions, so that the device performs operations of the method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation described in the present invention.

[0029] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation described in the present invention is implemented.

[0030] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0031] The present invention proposes a method for implementing a vector memory access controller that is adaptable to multiple scenarios and multiple algorithms. The controller can adaptively adjust its working mode according to different application scenarios and algorithm requirements, thereby providing wider applicability while maintaining high performance. By supporting two data reading modes, stream mode and batch mode, the present invention can efficiently utilize computing resources in different scenarios. The stream mode is suitable for continuous data streams generated by a single sensor, ensuring real-time processing capabilities; while the batch mode is suitable for data collected by multiple sensors at the same time, which can reduce the number of memory accesses and improve overall efficiency. This flexibility enables the controller to optimize performance for specific applications.

[0032] The present invention sends a configuration signal to the vector memory access controller through the host computer to determine the specific source data reading mode, result data writing mode and algorithm parallelism. This design gives the system a high degree of configurability, enabling it to adapt to diverse computing tasks and environmental changes, and improves the versatility and expansion capability of the entire system. When encountering a situation where the size of the complete data block is not met, the present invention fills the insufficient part by generating a batch end zero signal or a batch beginning zero signal to ensure that the data input to the computing unit always has a fixed format, which can not only simplify the computing logic, but also prevent the result errors caused by data inconsistency, and ensure the accuracy and reliability of the calculation results.

[0033] In summary, the present invention solves some key problems existing in the current technology through innovative design of the vector memory access controller, achieves higher performance, better adaptability and lower power consumption, and lays a solid foundation for further development in related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0035] Figure 1 A flow chart of a method for implementing a vector memory access controller with multi-scenario and multi-algorithm adaptation provided by the present invention;

[0036] Figure 2 A schematic diagram of a data flow path for reading source data based on a stream mode provided by the present invention;

[0037] Figure 3 A schematic diagram of a data flow path for reading source data based on batch mode provided by the present invention. DETAILED DESCRIPTION

[0038] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other unless there is a conflict.

[0039] Example 1

[0040] This embodiment introduces a method for implementing a vector memory access controller adapted for multiple scenarios and multiple algorithms. The vector memory access controller includes a memory access state module, a memory access control module, a source data module, and a result data module. Figure 1 , the method comprises the following steps:

[0041] The memory access control module obtains the configuration signal of the host computer, determines the source data reading mode, the result data writing mode and the algorithm parallelism, and generates the memory access control signal;

[0042] The source data reading mode includes a stream mode and a batch mode; the method for determining the source data reading mode is as follows:

[0043] If the data collected by a single sensor is collected sequentially in the form of a data stream, and the data is stored horizontally in the storage resource, the source data reading mode adopts the stream mode; wherein, the horizontal storage means that the data received in each clock cycle of length Δt is arranged horizontally in the storage resource in chronological order; in this state, the stream mode will be used to sequentially send the data to the computing unit for calculation, and at this time all the computing resources in the computing unit can be mobilized, so the operation is highly real-time, and fast real-time calculation of a single data stream can be achieved.

[0044] If the single type of data collected by multiple sensors is collected in the form of multiple batches of data, and the data is stored vertically in the storage resource by batches, then the source data reading mode adopts the batch mode; the vertical storage by batches means that the data collected by different sensors are stored in the storage resource in the form of a two-dimensional array, and any row of the two-dimensional array represents the same batch of data collected by different sensors, and any column represents different batches of data collected by the corresponding sensors. In this state, the batch mode will read the data horizontally, that is, the data collected by multiple sensors are sent to the computing unit in batches for calculation at the same time; a batch of data only contains one data collected by each sensor. For a single sensor, the data is read and calculated one by one in batches, rather than a continuous data stream, so the computing resources are not fully utilized, resulting in poor real-time performance; however, it can process multiple device information at the same time, read a batch of data at one time, and reduce the number of times the data is read, which has a great advantage in reducing the number of memory accesses and improving the overall efficiency when the amount of data is large.

[0045] The algorithm parallelism represents the number of source data read from the storage resource at any one time;

[0046] The configuration signal is a signal sent by the host computer to the vector memory access controller, which is used to configure the behavior of the controller. The configuration signal may include configuration information such as start and stop signals, read and write addresses, data width, and algorithm type.

[0047] The memory access control signal is used to control the state jump of the main state machine, the source data state machine, and the result data state machine, including read and write enable signals, address signals, data valid signals, etc. Through the control of the memory access control signal, the behavior of each module in the memory access process can be coordinated to ensure that data is correctly read from the storage resource to the computing resource, or written from the computing resource back to the storage resource, to achieve orderly reading and writing of data, and to ensure the normal operation of the vector memory access controller.

[0048] The memory access state module generates a read control instruction and a write control instruction in response to the memory access control signal;

[0049] The memory access state module includes a main state machine, a source data state machine, and a result data state machine; wherein the main state machine is used to respond to the memory access control signal and control the working state of the vector memory access controller, including controlling the state jump of the source data state machine and the result data state machine; it also includes the main control logic of the entire vector memory access controller, such as initialization, start, stop and other global states; the source data state machine is used to generate a reading control instruction to drive the source data module to perform source data reading operations; the result data state machine is used to generate a write control instruction to control the result data module to perform result data writing operations; the working process of the memory access state module is as follows:

[0050] First, the main state machine, source data state machine, and result data state machine are all in the initialization state; under the control of the memory access control signal, the main state machine jumps to the startup state, and controls the source data state machine and the result data state machine to jump to the startup state; the source data state machine controls the source data module to read data from the storage resource, and the result data state machine controls the result data module to write the result data back to the storage resource; when all data processing is completed, the main state machine switches to the end state, controls the source data state machine and the result data state machine to jump to the end state, and sends an end signal to the host computer, indicating that the entire vector memory access process has been completed.

[0051] The source data module responds to the reading control instruction, reads the source data from the storage resource, and sends it to the computing resource for data operation to obtain result data;

[0052] If the source data reading mode is the stream mode, the method for reading source data from the storage resource is as follows: the source data module reads m source data horizontally from the storage resource each time, where m is the algorithm parallelism; the m source data read horizontally each time are consecutive m in the same batch of source data, where any batch of source data is collected based on the same sensor, and this data reading method can ensure that the source data is sent to the computing resource in chronological order; if there are n remaining single batches of source data involved in the i-th reading of the source data, and n is less than m, and i is any positive integer, the control module generates a batch end zeroing signal, the source data module responds to the batch end zeroing signal, reads the remaining n source data, and adds mn data assigned to 0 after the n source data, and transmits them together to the computing resource; if the reading of all batches of data is not completed at this time, then at the beginning of the i+1-th reading of the source data, the control module generates a batch beginning zeroing signal, the source data module responds to the batch beginning zeroing signal, reads mn source data in the next batch of source data, and adds n data assigned to 0 before the mn source data, and transmits them together to the computing resource.

[0053] By controlling the zero-assigning signal at the end of a batch, the data positions that are less than m are assigned zeros and transmitted to the computing resources, which can ensure the consistency of the data format, so that the next batch of source data will not affect the calculation results of the current batch of source data. Similarly, by controlling the zero-assigning signal at the beginning of a batch, the data positions that are less than m in the previous batch are assigned zeros and transmitted to the computing module, which can also ensure the consistency of the data format, so that the source data at the end of the previous batch will not affect the calculation results of the current batch of source data.

[0054] If the source data reading mode is batch mode, the method for reading source data from storage resources is as follows: the source data module reads m source data horizontally from the storage resources each time, where m is the algorithm parallelism; the m source data read horizontally each time are m batches of source data at the same time point, where the m batches of source data are collected based on m sensors respectively; if the number of source data batches involved in the j-th reading of source data is k, and k is less than m, and j is any positive integer, the algorithm parallelism is adjusted to k, and k source data are read horizontally and sent to the computing resources.

[0055] By reading data in multiple batches at a time and adaptively adjusting the algorithm parallelism, the vector memory access controller can be used to transmit multiple batches of data in scenarios with a single type of signal on multiple devices, thereby simplifying data transfer and reducing the number of transfers.

[0056] If the source data reading mode is the stream mode, the method for performing data operations is as follows: using the algorithm-level API to call the vector algorithm, or using the unit-level API to call the stream mode of the computing unit, and calling the multiplication-accumulation tree to perform vector operations;

[0057] In stream mode, you can directly call functions through the algorithm-level API to implement vector operations, or access and control the underlying computing unit through the algorithm-level API, so that it uses the stream mode to process the continuous data stream of the source data, and call the multiplication-accumulation tree (MAC Tree) to specifically perform vector multiplication and accumulation operations. The computing unit is a computing resource that performs specific computing tasks, which can be a hardware or software component, such as a computing unit in a CPU, GPU, or FPGA. The multiplication-accumulation tree is a data structure used to efficiently process multiplication and accumulation operations in continuous data streams. In stream mode, data enters the system one by one, and a multiplication operation is performed for each incoming data and the result is accumulated to the current result. This data structure is suitable for processing continuous input streams and can maintain low latency. Since the stream mode processes a continuous data stream, the amount of data processed each time is small, and the data processing logic is relatively simple, the algorithm-level API can also be used to directly call the vector algorithm.

[0058] If the source data reading mode is batch mode, the method for performing data operations is as follows: using the unit-level API to call the batch mode of the computing unit, and calling multiplication and accumulation to perform vector operations;

[0059] In batch mode, the batch mode of the computing unit needs to be called through the algorithm-level API so that it can process multiple batches of data at the same time, and call the multiplication-accumulation (MAC) to perform vector multiplication and accumulation operations. The multiplication-accumulation operation is performed on a batch of data at the same time, which means that a batch of data is collected first, and then batch multiplication and accumulation operations are performed on this batch of data. This method is suitable for processing large amounts of data because it can improve efficiency through parallel processing while reducing the storage and transmission times of intermediate results. In stream mode, since data flows in one by one, the structure of the multiplication-accumulation tree may be required to continuously update the multiplication-accumulation results. In batch mode, a batch of data is loaded at a time, so batch multiplication-accumulation operations can be performed directly on this batch of data. By calling the multiplication-accumulation tree or multiplication-accumulation, common vector operations such as vector addition and subtraction, point multiplication, multiplication, summation, and averaging can be implemented.

[0060] The result data module responds to the write control instruction, obtains the result data from the computing resource and writes it into the storage resource.

[0061] The source data module is instantiated in the vector memory controller where m is the parallelism of the algorithm and is a positive integer. Indicates rounding up; each source data module generates two sets of source data channels, and the control vector memory access controller simultaneously interacts with the storage resources and computing resources in the two sets of source data channels;

[0062] The result data module is instantiated in the vector memory controller Each result data module generates two groups of result data channels, and the control vector memory access controller interacts with the storage resources and the computing resources in the two groups of result data channels at the same time.

[0063] By creating multiple identical source data module instances and multiple identical result data module instances, parallel processing of multiple sets of data can be achieved; each source data module or result data module generates two sets of data channels, which means that two data streams can be processed simultaneously, further improving the parallelism of data processing.

[0064] Example 2

[0065] Based on the same concept as the first embodiment, this embodiment introduces a data reading method based on a stream mode in combination with a specific vector operation task.

[0066] Taking the vector memory access controller introduced in Example 1 as the control basis, taking the vector operation with algorithm parallelism of 16, batch number of 2, and single batch number of 102 as an example, when the flow mode is adopted, the data flow path is as follows: Figure 2 As shown. Each row of squares represents that the source data module reads source data from the storage resource once, and each square represents a source data read or a data point assigned to 0; wherein, the shaded squares represent the source data read from the storage resource, and the blank squares represent the data points with an amplitude of 0 added before or after the source data based on the control of the batch end zero signal or the batch beginning zero signal; the source data read 1-7 times is the first batch, and the source data read 8-14 times is the second batch;

[0067] Reference Figure 2 , when reading source data for the first time to the sixth time, based on the parallelism of the algorithm, 16 source data are read from the first batch of source data each time; when reading source data for the seventh time, since the first batch of source data is less than 16, based on the control of the batch end zero signal, the remaining 6 source data are read and 10 zeros are added thereto to complete the reading of the first batch of source data; when reading source data for the eighth time, since the source data read last time is less than 16, based on the control of the batch beginning zero signal, 6 zeros are added to the corresponding positions of the source data read last time at the beginning, and then 10 are read from the second batch of source data; when reading from the ninth to the thirteenth time, 16 are read from the second batch of source data; when reading for the fourteenth time, since the second batch of source data is less than 16, based on the control of the batch end zero signal, the remaining 12 source data are read and 4 zeros are added thereto to complete the reading of the second batch of source data, and a total of 14 times are used to complete the reading of all data. In this scenario, if batch mode is used, 102 data reads are required, and the vector operation efficiency is greatly reduced.

[0068] For vector memory access scenarios with few devices and many points, the stream mode has the advantages of high resource utilization and fast response speed compared with the batch mode. Taking the complex vector multiplication with algorithm parallelism of 16 and batch number and point configuration as shown in Table 1 as an example, the data processing speed of the vector memory access controller in the stream mode is improved by multiples compared with the batch mode as shown in Table 1; the batch number represents the number of devices (such as sensors), and the single batch number represents the amount of data for each device; the values ​​in Table 1 are the multiples of the stream mode handling speed compared with the batch mode handling speed under the corresponding batch number and point configuration. For example, when the batch number is 1 and the single point batch number is 16, the corresponding multiple is 16x, which means that the data processing speed of the stream mode in this scenario is 16 times that of the batch mode.

[0069] Table 1 The improvement of data processing speed in stream mode compared with batch mode

[0070]

[0071] Example 3

[0072] Based on the same concept as other embodiments, this embodiment introduces a batch-based data reading method in combination with a specific vector operation task.

[0073] Taking the vector memory access controller introduced in Example 1 as the control basis, taking the vector operation with the algorithm parallelism of 16, the batch number of 28, and the single batch number of 8 as an example, when the batch mode is adopted, the data flow path is as follows: Figure 3 Each row of squares represents a source data module reading source data from a storage resource once, each square represents a source data read, and the number on the square represents the batch number of the source data, that is, the number of the device from which the source data comes;

[0074] Reference Figure 3 , when reading data from the storage resource for the 1st to 8th time, the parallelism is 16, and one source data is read from each of the 1-16 batches of source data in turn. After 8 rounds of reading, the reading of the 1-16 batches of source data is completed. When reading the source data for the 9th time, there are 12 batches of source data left, which is less than 16 batches, so the parallelism is adjusted to 12, and one source data is read from each of the 17-28 batches of source data each time; until the 16th reading, the reading of all source data is completed. In this scenario, if the streaming mode is used, 28 data reads are required, compared with Figure 3 In batch mode as shown, vector operations are less efficient.

[0075] For the scenario of multi-device single-type signal processing, the batch mode has the advantages of fewer transfer times and higher data processing efficiency compared to the stream mode. Taking the complex vector multiplication with an algorithm parallelism of 16 and a batch number point configuration as shown in Table 2 as an example, the data processing speed of the vector memory controller in batch mode is improved by multiples compared to the stream mode as shown in Table 2; the batch number represents the number of devices (such as sensors), and the single batch point number represents the amount of data for each device; the values ​​in Table 2 are the multiples of the stream mode transfer speed compared to the batch mode transfer speed under the corresponding batch number and point number configuration. For example, when the batch number is 32 and the single point batch number is 1, the corresponding multiple is 16x, which means that the data processing speed of the batch mode is 16 times that of the stream mode in this scenario.

[0076] Table 2 The improvement of batch mode data processing speed compared with stream mode

[0077]

[0078]

[0079] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] Example 4

[0081] Based on the same inventive concept as other embodiments, this embodiment introduces an electronic device, including a memory and a processor, the memory being used to store instructions, and the processor being used to execute the instructions, so that the computer device executes a method for implementing a vector memory access controller that is adapted to multiple scenarios and multiple algorithms as provided in the above embodiments.

[0082] Since the electronic device introduced in this embodiment is an electronic device used to implement a method for implementing a vector memory access controller that is adapted for multiple scenarios and multiple algorithms in the embodiment of the present application, based on the method for implementing a vector memory access controller that is adapted for multiple scenarios and multiple algorithms introduced in the embodiment of the present application, a person skilled in the art can understand the specific implementation of the electronic device of the present embodiment and its various variations, so how the electronic device implements the method in the embodiment of the present application is not described in detail here. As long as a person skilled in the art implements the electronic device used by a method for implementing a vector memory access controller that is adapted for multiple scenarios and multiple algorithms in the embodiment of the present application, it belongs to the scope of protection to be provided by the present application.

[0083] Example 5

[0084] Based on the same inventive concept as other embodiments, this embodiment introduces a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, a method for implementing a vector memory access controller that is adapted to multiple scenarios and multiple algorithms as provided in the above embodiments is implemented.

[0085] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the purpose and scope of protection of the present invention, which are all within the protection of the present invention.

Claims

1. A method for implementing a vector memory access controller adapted for multiple scenarios and multiple algorithms, characterized in that: The vector memory access controller includes a memory access state module, a memory access control module, a source data module and a result data module; the method includes the following steps: The memory access control module obtains the configuration signal of the host computer, determines the source data reading mode, the result data writing mode and the algorithm parallelism, and generates the memory access control signal; The memory access state module generates a read control instruction and a write control instruction in response to the memory access control signal; The source data module responds to the reading control instruction, reads the source data from the storage resource, and sends it to the computing resource for data operation to obtain result data; The result data module responds to the write control instruction, obtains the result data from the computing resource and writes it into the storage resource.

2. The method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 1, characterized in that: The source data reading mode includes a stream mode and a batch mode; the method for determining the source data reading mode is as follows: If the data collected by a single sensor is collected sequentially in a data stream manner and the data is horizontally stored in the storage resource, the source data reading mode adopts a stream mode; wherein the horizontal storage means that the data received in each clock cycle of length Δt is horizontally arranged in the storage resource in time order; If a single type of data collected by multiple sensors is collected in the form of multiple batches of data, and the data is stored vertically in the storage resource by batches, then the source data reading mode adopts the batch mode; the vertical storage by batches means that the data collected by different sensors are stored in the form of a two-dimensional array in the storage resource, wherein any row of the two-dimensional array represents the same batch of data collected by different sensors, and any column represents different batches of data collected by the corresponding sensor.

3. The method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 2, characterized in that: The algorithm parallelism represents the number of source data read from the storage resource at any one time; The configuration signal is a signal sent from the host computer to the vector memory access controller, and is used to configure the behavior of the controller; The memory access control signal is used to control the state jump of the main state machine, the source data state machine, and the result data state machine.

4. The method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 3, characterized in that: The memory access status module includes a main state machine, a source data state machine, and a result data state machine; wherein the main state machine is used to respond to a memory access control signal and control the working state of the vector memory access controller, including controlling the state jump of the source data state machine and the result data state machine; the source data state machine is used to generate a reading control instruction to drive the source data module to perform source data reading operations; the result data state machine is used to generate a writing control instruction to control the result data module to perform result data writing operations.

5. The method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 4, characterized in that: If the source data reading mode is the stream mode, the method of reading the source data from the storage resource is as follows: the source data module reads m source data horizontally from the storage resource each time, where m is the parallelism of the algorithm; the m source data read horizontally each time are continuous m in the same batch of source data, where any batch of source data is collected based on the same sensor; If there are n remaining source data in a single batch when the source data is read for the i-th time, and n is less than m, and i is any positive integer, the control module generates a batch end zeroing signal, and the source data module responds to the batch end zeroing signal, reads the remaining n source data, and adds mn data with a value of 0 after the n source data, and transmits them together to the computing resource; If the reading of data of all batches is not completed at this time, then at the beginning of the i+1th reading of source data, the control module generates a batch start zeroing signal, and the source data module responds to the batch start zeroing signal, reads the mn source data in the next batch of source data, and adds n data with a value of 0 before the mn source data, and transmits them together to the computing resources.

6. A method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 5, characterized in that: If the source data reading mode is batch mode, the method of reading source data from the storage resource is as follows: the source data module reads m source data horizontally from the storage resource each time, where m is the algorithm parallelism; the m source data read horizontally each time are m batches of source data at the same time point, where the m batches of source data are collected based on m sensors respectively; If the number of source data batches involved in the j-th reading of source data is k, and k is less than m, and j is any positive integer, the algorithm parallelism is adjusted to k, and k source data are read horizontally and sent to the computing resources.

7. A method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 6, characterized in that: If the source data reading mode is the stream mode, the method for performing data operations is as follows: using the algorithm-level API to call the vector algorithm, or using the unit-level API to call the stream mode of the computing unit, and calling the multiplication-accumulation tree to perform vector operations; If the source data reading mode is the batch mode, the method for performing data operations is as follows: use the unit-level API to call the batch mode of the computing unit, and call multiplication and accumulation to perform vector operations.

8. The method for implementing a vector memory access controller for multi-scenario and multi-algorithm adaptation as claimed in claim 7, characterized in that: The source data module is instantiated in the vector memory controller where m is the parallelism of the algorithm and is a positive integer. Indicates rounding up; each source data module generates two sets of source data channels, and the control vector memory access controller simultaneously interacts with the storage resources and computing resources in the two sets of source data channels; The result data module is instantiated in the vector memory controller Each result data module generates two groups of result data channels, and the control vector memory access controller interacts with the storage resources and the computing resources in the two groups of result data channels at the same time.

9. An electronic device, characterized in that: include: A memory for storing instructions; A processor is used to execute the instruction so that the device performs the operation of implementing a method for implementing a vector memory access controller adapted for multiple scenarios and multiple algorithms as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, a method for implementing a vector memory access controller that is adapted for multiple scenarios and multiple algorithms as described in any one of claims 1 to 8 is implemented.

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