High-speed serial signal generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention relates to a high-speed serial signal generation method and device, electronic equipment and a storage medium, and relates to the technical field of signal sources. The high-speed serial signal generation method comprises the following steps: acquiring a mode selection signal, wherein the mode selection signal comprises first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; if the first selection control information is control opening information and the second selection control information is control closing information, determining an intermediate sampling rate according to an expected code rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate; and generating a high-speed serial signal according to the first output sampling rate. According to the embodiment of the invention, by calculating and using the intermediate sampling rate, the calculation amount can be effectively reduced at a low bit rate, the calculation precision and quality of the high-speed serial signal can be effectively improved at a high bit rate, and meanwhile, multiple modes are supported, so that a user can flexibly select.

Description

Technical Field

[0001] The present application relates to the technical field of signal sources, and in particular to a method, device, electronic device and storage medium for generating a high-speed serial signal. Background Art

[0002] In the AWG (Arbitrary Waveform Generator) signal source, the high-speed serial signal option supports users to set any code rate to generate high-speed serial signals. When the user sets the code rate to be very low or very high, the following defects may occur: if the code rate is very low, it may cause too many sampling points to be included in the duration of each code element, resulting in a very large amount of calculation for each code element, and in the case of a long code element length, the required storage space will be very large; if the code rate is very high, it may cause too few sampling points, and the edge of each code element will be difficult to accurately construct, resulting in low quality of the generated high-speed serial signal. Summary of the invention

[0003] In view of this, embodiments of the present application provide a method, device, electronic device and storage medium for generating a high-speed serial signal to solve at least one problem existing in the background technology.

[0004] In a first aspect, an embodiment of the present application provides a method for generating a high-speed serial signal, comprising:

[0005] Acquire a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0006] If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate;

[0007] A high speed serial signal is generated according to the first output sampling rate.

[0008] In combination with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to the expected bit rate set by the user includes:

[0009] Determine the reference sampling rate according to the expected bit rate set by the user;

[0010] An intermediate sampling rate is determined according to the reference sampling rate.

[0011] In combination with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to the reference sampling rate includes:

[0012] The intermediate sampling rate is determined according to the multiple relationship between the reference sampling rate and the maximum sampling rate.

[0013] In combination with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to a multiple relationship between the reference sampling rate and the maximum sampling rate includes:

[0014] If the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate;

[0015] An intermediate sampling rate is determined based on the executable decimation factor.

[0016] In combination with the first aspect, in an optional implementation, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0017] Determine a reference decimation multiple according to the reference sampling rate and the maximum sampling rate;

[0018] An integer executable decimation multiple that satisfies a first condition is determined according to the reference decimation multiple, wherein the first condition is that a first deviation between the reference decimation multiple and the executable decimation multiple is within a first preset deviation range.

[0019] In combination with the first aspect, in an optional implementation manner, determining the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate further includes:

[0020] If the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0021] An intermediate sampling rate is determined according to the executable interpolation factor.

[0022] In combination with the first aspect, in an optional implementation manner, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0023] Determine a reference interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0024] An integer executable interpolation multiple that satisfies a second condition is determined according to the reference interpolation multiple, wherein the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0025] In conjunction with the first aspect, in an optional implementation manner, the method further includes:

[0026] If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate;

[0027] A high speed serial signal is generated according to the second output sampling rate.

[0028] In conjunction with the first aspect, in an optional implementation manner, the method further includes:

[0029] If the first selection control information is control-off information and the second selection control information is control-on information, determining the intermediate sampling rate as the maximum sampling rate and determining the third output sampling rate as the maximum sampling rate;

[0030] A high speed serial signal is generated according to the third output sampling rate.

[0031] In a second aspect, an embodiment of the present application provides a device for generating a high-speed serial signal, comprising:

[0032] An acquisition unit, configured to generate a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0033] A first mode unit, configured to determine an intermediate sampling rate according to an expected bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate if the first selection control information is control-on information and the second selection control information is control-off information;

[0034] The first high-speed serial signal generating unit is configured to generate a high-speed serial signal according to the first output sampling rate.

[0035] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0036] Processor; and

[0037] A memory having computer executable instructions stored therein, wherein the computer executable instructions are executed by the processor to execute the above-mentioned method for generating a high-speed serial signal.

[0038] In a fourth aspect, an embodiment of the present application provides a storage medium having computer executable instructions stored thereon, and the computer executable instructions, when executed by a processor, execute the above-mentioned method for generating a high-speed serial signal.

[0039] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include: by selecting the first control information of the intermediate sampling rate mode as the control-on information and the second control information of the fixed output sampling rate mode as the control-off information, the intermediate sampling rate is determined according to the expected bit rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, so that the sampling rate corresponding to the expected bit rate set by the user is adjusted to the intermediate sampling rate, the intermediate sampling rate is reasonably selected, and then the output sampling rate can be reasonably selected, that is, when the expected bit rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, effectively improving the quality of the generated high-speed serial signal.

[0040] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the embodiments of the present application and constitute a part of the embodiments of the present application. The illustrative embodiments of the embodiments of the present application and their descriptions are used to explain the embodiments of the present application and do not constitute an improper limitation on the embodiments of the present application. In the drawings:

[0042] Figure 1 A flowchart of a specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0043] Figure 2 A flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0044] Figure 3 A flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0045] Figure 4 A flowchart of another specific example of a method for generating a high-speed serial signal in an embodiment of the present application;

[0046] Figure 5 A principle block diagram of a specific example of a process for generating a high-speed serial signal in an embodiment of the present application;

[0047] Figure 6 A schematic block diagram of a specific example of a high-speed serial signal generating device in an embodiment of the present application;

[0048] Figure 7 It is a principle block diagram of a specific example of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical solutions and beneficial effects of the embodiments of the present application more obvious and easy to understand, the following is a detailed description by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as those in the technical field to which the embodiments of the present application belong.

[0050] It should be noted that the terms "first", "second", etc. may be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. When describing "first", it does not mean that there must be a "second"; and when discussing "second", it does not mean that there must be a "first" in this application. The singular forms of "one", "an" and "said / the" may also be intended to include plural forms, unless the context clearly indicates otherwise. The term "includes" is to determine the existence of the included features, but does not exclude the existence or addition of one or more other features. The term "and / or" includes any and all combinations of the relevant listed items.

[0051] It should be noted that in the AWG signal source, the high-speed serial signal option supports users to set any bit rate and the bit rate range is very wide, such as from 500Kbps to the maximum sampling rate Fs (usually the maximum sampling rate of the AWG signal source is up to 5GSa / s, or up to 10GSa / s, or even more than 100GSa / s). At the same time, it supports users to set the bit rate with very high precision resolution, such as setting the bit rate of the high-speed serial signal to 1.1235Mbps.

[0052] As a result, the following situations are usually encountered:

[0053] 1. The code rate is very low, much lower than the maximum sampling rate. When generating a high-speed serial signal, the duration of each code element will be many times the sampling period corresponding to the maximum sampling rate, and each code element duration contains many sampling points. For example, when a high-speed serial signal with a code rate of 1Mbps needs to be generated, assuming the maximum sampling rate is 5GSa / s, each code element duration will contain 5000 sampling points, so the amount of calculation for each code element will be very large.

[0054] If the symbol length is very long, the storage space required will often be very large. For example, a 100Mbit symbol generates a high-speed serial signal with a bit rate of 1Mbps. Assuming the maximum sampling rate is 5GSa / s, a storage space that can store 500G sampling points is required. Usually, AWGs are rarely configured with such a large storage space.

[0055] 2. The code rate is very high, close to the maximum sampling rate. At this time, when generating high-speed serial signals, the number of sampling points contained in each code element duration is too small. For example, when you need to generate a high-speed serial signal with a code rate of 2500Mbps, assuming that the maximum sampling rate is 5GSa / s, each code element duration will only contain 2 sampling points. The number of sampling points is too small, and the edge of each code element will be difficult to construct accurately, and the quality of the generated high-speed serial signal is low.

[0056] 3. Since arbitrary bit rate settings and high-precision settings are supported, there is usually a non-integer multiple relationship between the bit rate and the maximum sampling rate. Each code element duration contains a non-integer multiple of sampling points, which affects the accuracy of the generated high-speed serial signal.

[0057] The present application embodiment provides a method for generating a high-speed serial signal, which can be applied to instruments such as AWG signal sources, such as Figure 1 As shown, the method for generating the high-speed serial signal includes:

[0058] S100, obtaining a mode selection signal, where the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0059] S200: If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate;

[0060] S300 , generating a high-speed serial signal according to a first output sampling rate.

[0061] In an embodiment of the present application, the first selection control information is used to indicate whether to turn on the intermediate sampling rate mode, and the second selection control information is used to indicate whether to turn on the fixed output sampling rate mode. If the first selection control information is the control turn-on information (ON), it indicates that the intermediate sampling rate mode is turned on. If the first selection control information is the control turn-off information (OFF), it indicates that the intermediate sampling rate mode is turned off. If the second selection control information is the control turn-on information (ON), it indicates that the fixed output sampling rate mode is turned on. If the second selection control information is the control turn-off information (OFF), it indicates that the fixed output sampling rate mode is turned off. The expected bit rate set by the user can be an integer bit rate or a small bit rate of arbitrary precision. The maximum sampling rate is the DAC (digital to analog) sampling rate set by the user. The intermediate sampling rate is used to control the number of sampling points within a reasonable range, thereby reducing the amount of calculation and the required storage space, and can also improve the quality of the generated high-speed serial signal. By setting the first selection control information of the intermediate sampling rate mode as the control-on information and the second selection control information of the fixed output sampling rate mode as the control-off information, the intermediate sampling rate is determined according to the expected bit rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, so that the sampling rate corresponding to the expected bit rate set by the user is adjusted to the intermediate sampling rate, the intermediate sampling rate is reasonably selected, and then the output sampling rate can be reasonably selected. In other words, when the expected bit rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, thereby effectively improving the quality of the generated high-speed serial signal.

[0062] In an alternative embodiment, if Figure 2 As shown, determining the intermediate sampling rate according to the expected bit rate set by the user includes:

[0063] S201, determining a reference sampling rate according to an expected bit rate set by a user;

[0064] S202: Determine an intermediate sampling rate according to a reference sampling rate.

[0065] In an optional implementation, determining the intermediate sampling rate according to the reference sampling rate includes:

[0066] S202-1. Determine an intermediate sampling rate according to a multiple relationship between a reference sampling rate and a maximum sampling rate.

[0067] Preferably, according to the multiple relationship between the reference sampling rate and the maximum sampling rate, the intermediate sampling rate is determined as follows:

[0068] S202-11, if the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate;

[0069] S202-12, determining an intermediate sampling rate according to the executable decimation multiple;

[0070] S202-13, if the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate;

[0071] S202-14. Determine an intermediate sampling rate according to the executable interpolation multiple.

[0072] In the embodiment of the present application, as a preferred method, the expected code rate set by the user can be expanded by a multiple to obtain the reference sampling rate. The expected code rate set by the user can also be reduced by a multiple to obtain the reference sampling rate. The expansion multiple and the reduction multiple can be set according to actual needs, which can be a user-settable amount or an empirical value inside the instrument. The value is used to adjust the reference sampling rate to achieve control of the amount of calculation, storage space or quality of the generated high-speed serial signal.

[0073] Since the expected bit rate may be a small bit rate, by obtaining executable decimation multiples and executable interpolation multiples that are both integers, and based on the executable decimation multiples and executable interpolation multiples, the intermediate sampling rate obtained is an integer, which is an integer multiple of the maximum sampling rate, meeting the requirement that the sampling rate is an integer.

[0074] In an optional implementation, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0075] S202-111, determining a reference decimation multiple according to a reference sampling rate and a maximum sampling rate;

[0076] S202-112, determine an integer executable decimation multiple that satisfies a first condition according to the reference decimation multiple, wherein the first condition is that a first deviation between the reference decimation multiple and the executable decimation multiple is within a first preset deviation range.

[0077] In an optional implementation, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate includes:

[0078] S202-131, determining a reference interpolation multiple according to a reference sampling rate and a maximum sampling rate;

[0079] S202-132, determine an integer executable interpolation multiple that satisfies a second condition according to the reference interpolation multiple, where the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0080] As a specific example, the calculation formula of the reference sampling rate RefVFs is:

[0081] RefVFs=Rs×RefTimes (1)

[0082] Wherein, Rs represents the expected bit rate, and RefTimes represents the reference multiplication factor.

[0083] If the reference sampling rate is greater than or equal to the maximum sampling rate, the reference interpolation multiple interpTimes is 1, and the calculation formula for the reference decimation multiple decTimes is:

[0084] decTimes=RefVFs / MaxFs (2)

[0085] Among them, RefVFs represents the reference sampling rate, and MaxFs represents the maximum sampling rate.

[0086] An integer executable decimation multiple realDecTimes satisfying a first condition is determined according to the reference decimation multiple decTimes.

[0087] The calculation formula for the intermediate sampling rate VFs is:

[0088] VFs=MaxFs / realInterpTimes×realDecTimes

[0089] =MaxFs×realDecTimes (3)

[0090] Among them, MaxFs represents the maximum sampling rate, realDecTimes represents the executable decimation multiple, realInterpTimes represents the executable interpolation multiple, and realInterpTimes=interpTimes=1.

[0091] If the reference sampling rate is less than the maximum sampling rate, the reference decimation multiple decTimes is 1, and the calculation formula for the reference interpolation multiple interpTimes is:

[0092] interpTimes=MaxFs / RefVFs (4)

[0093] Among them, RefVFs represents the reference sampling rate, and MaxFs represents the maximum sampling rate.

[0094] An integer executable interpolation time realInterpTimes satisfying a second condition is determined according to the reference interpolation time interpTimes.

[0095] The calculation formula for the intermediate sampling rate VFs is:

[0096] VFs=MaxFs / realInterpTimes×realDecTimes

[0097] =MaxFs / realInterpTimes (5)

[0098] Among them, MaxFs represents the maximum sampling rate, realInterpTimes represents the executable interpolation multiple, realDecTimes represents the executable decimation multiple, and realDecTimes=decTimes=1.

[0099] In an embodiment of the present application, the first preset deviation range is used to control the degree to which the executable decimation multiple is close to the reference decimation multiple. The smaller the first preset deviation range, the closer the executable decimation multiple of the obtained integer is to the reference decimation multiple. The first deviation indicates that the corresponding executable decimation multiple is the integer closest to the reference decimation multiple within the first preset range. Similarly, the second preset deviation range is used to control the degree to which the executable interpolation multiple is close to the reference interpolation multiple. The smaller the second preset deviation range, the closer the executable interpolation multiple of the obtained integer is to the reference interpolation multiple. The second deviation indicates that the corresponding executable interpolation multiple is the integer closest to the reference interpolation multiple within the second preset range. This eliminates the influence that the reference decimation multiple and the reference interpolation multiple may be a decimal, thereby making the intermediate sampling rate meet the requirements.

[0100] As a specific example, the calculation formula of the first output sampling rate Fs1 is:

[0101] Fs1=VFs / realDecTimes (6)

[0102] Among them, VFs represents the intermediate sampling rate, and realDecTimes represents the executable decimation multiple.

[0103] In the embodiment of the present application, the first output sampling rate can be adjusted according to the intermediate sampling rate. Thus, the output sampling rate can flexibly select the appropriate sampling rate output according to the bit rate, maximum sampling rate, storage depth, etc. set by the user. When facing a low bit rate signal, the algorithm calculation amount can be effectively reduced and the calculation time can be saved; when facing a high bit rate signal, it can be calculated based on the intermediate sampling rate that exceeds the maximum sampling rate, effectively improving the calculation accuracy, improving the output quality of high-speed serial signals, and effectively reducing the storage requirements of signal waveforms.

[0104] In an alternative embodiment, if Figure 3 As shown, the method for generating a high-speed serial signal also includes:

[0105] S400: If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate;

[0106] S500 , generating a high-speed serial signal according to a second output sampling rate.

[0107] In the embodiment of the present application, the second output sampling rate is determined as the maximum sampling rate according to the intermediate sampling rate. Thus, although the maximum sampling rate output set by the user is still maintained, multiple intermediate calculation links are calculated at a suitable intermediate sampling rate, and finally the second output sampling rate is determined to be the maximum sampling rate according to the intermediate sampling rate. When facing a low bit rate signal, the amount of algorithm calculation can be effectively reduced and the calculation time can be saved; when facing a high bit rate signal, it can be calculated based on the intermediate sampling rate that exceeds the maximum sampling rate, effectively improving the calculation accuracy and improving the output quality of the high-speed serial signal. The step of determining the intermediate sampling rate according to the expected bit rate set by the user in step S400 is the above steps S201-S202.

[0108] As a specific example, the calculation formula of the second output sampling rate Fs2 is:

[0109] Fs2=VFs×realInterpTimes / realDecTimes (7)

[0110] Among them, VFs represents the intermediate sampling rate, realInterpTimes represents the executable interpolation times, and realDecTimes represents the executable decimation times.

[0111] In an alternative embodiment, if Figure 4 As shown, the method for generating a high-speed serial signal also includes:

[0112] S600: If the first selection control information is control-off information and the second selection control information is control-on information, the intermediate sampling rate is determined as the maximum sampling rate, and the third output sampling rate is determined as the maximum sampling rate;

[0113] S700 , generating a high-speed serial signal according to a third output sampling rate.

[0114] In the embodiment of the present application, when the first selection control information of the intermediate sampling rate mode is the control shutdown information, the intermediate sampling rate VFs and the third output sampling rate Fs3 are both the DAC sampling rates (maximum sampling rates) set by the user. As a preferred method, when the code rate is too small or the code stream bit is too long, resulting in the storage requirement exceeding the storage space of the instrument, an alarm is issued when a high-speed serial signal is generated according to the third output sampling rate. Through the control of the three mode selection signals, users can flexibly implement multiple mode combinations to meet the application requirements of different scenarios.

[0115] like Figure 5As shown in the figure, in the high-speed serial signal generation process, three signal sampling rates are involved. Step ⑴: In the user setting code rate, the signal sampling rate is involved = the expected code rate Rs set by the user. At this time, the bit stream and code type encoding and modulation of the signal are processed. The bit stream settings include PRBS (pseudo-random code), COLCK (clock) and file import bit stream. The code type encoding and modulation settings include NRZ (non-return-to-zero encoding) / NRZ-I (non-return-to-zero inverted encoding) / RZ (return-to-zero encoding) / RZPolar (polar return-to-zero encoding), 8B / 10B, PAM (pulse amplitude modulation) 4 / 5 / 8 / 10 / 12 / 16 and Scrambling.

[0116] Step (2): In the intermediate sampling rate, the signal sampling rate = intermediate sampling rate VFs is involved. It can be applied to the embodiment of the present application, when the first selection control information for the intermediate sampling rate mode is the control opening information and the second selection control information for the fixed output sampling rate mode is the control closing information, or when the first selection control information for the intermediate sampling rate mode is the control opening information and the second selection control information for the fixed output sampling rate mode is the control opening information, the step of determining the intermediate sampling rate according to the expected code rate set by the user. The intermediate sampling rate VFs is automatically calculated internally according to certain rules to realize the conversion from the code rate to the intermediate sampling rate VFs and the corresponding function realization, such as serial signal function blocks, filtering and interference and sampling rate conversion. The serial signal function block settings include PWM (pulse width) modulation, periodic jitter injection, SSC (spread spectrum clock), random jitter injection, DCD (duty cycle distortion) and edge construction. The filtering and interference settings include Low-PassFilter (low-pass filtering), ISI (inter-symbol interference), band-limited noise interference and single-tone noise interference. The sampling rate conversion settings include interpolation filtering and extraction filtering.

[0117] Step (3): In the output sampling rate, the signal sampling rate = output sampling rate is involved. It can be applied to the embodiment of the present application, when the first selection control information for the intermediate sampling rate mode is the control opening information and the second selection control information for the fixed output sampling rate mode is the control closing information, the first output sampling rate is determined according to the intermediate sampling rate; or when the first selection control information for the intermediate sampling rate mode is the control opening information and the second selection control information for the fixed output sampling rate mode is the control opening information, the second output sampling rate is determined as the maximum sampling rate according to the intermediate sampling rate. At this time, the first output sampling rate or the second output sampling rate is automatically calculated according to certain rules, and the signal is interpolated or extracted from the intermediate sampling rate VFs to the first output sampling rate or the second output sampling rate, and then the signal is output from the AWG. For example, sampling rate conversion is performed. The sampling rate conversion setting also includes linear interpolation and linear extraction.

[0118] Several specific examples are introduced below to illustrate the method for generating a high-speed serial signal according to an embodiment of the present application.

[0119] When the intermediate sampling rate mode = ON and the fixed output sampling rate mode = ON:

[0120] Case 1: User sets the expected bit rate Rs = 1.0000000000000Mbps

[0121] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0122] Reference multiplication factor RefTimes = 24.000000000000

[0123] Reference sampling rate RefVFs = 0.024000000000GSa / s

[0124] Executable interpolation times realInterpTimes = 250.0

[0125] Executable extraction multiple realDecTimes = 1.0

[0126] Intermediate sampling rate VFs = 0.020000000000GSa / s

[0127] Second output sampling rate Fs2 = 5.0000000000000GSa / s

[0128] Case 2: User-set expected bit rate Rs = 1.511287427978 Mbps

[0129] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0130] Reference multiplication factor RefTimes = 24.000000000000

[0131] Reference sampling rate RefVFs = 0.036270898271GSa / s

[0132] Executable interpolation times realInterpTimes = 160.0

[0133] Executable extraction multiple realDecTimes = 1.0

[0134] Intermediate sampling rate VFs = 0.031250000000GSa / s

[0135] Second output sampling rate Fs2 = 5.0000000000000GSa / s

[0136] Case 3: User-set expected bit rate Rs = 125.0000000000000Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0137] Reference multiplication factor RefTimes = 24.000000000000

[0138] Reference sampling rate RefVFs = 3.0000000000000GSa / s

[0139] Executable interpolation times realInterpTimes = 2.0

[0140] Executable extraction multiple realDecTimes = 1.0

[0141] Intermediate sampling rate VFs = 2.5000000000000GSa / s

[0142] Second output sampling rate Fs2 = 5.0000000000000GSa / s Case 4: User-set expected bit rate Rs = 325.001983654685Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0143] Reference multiplication factor RefTimes = 24.000000000000

[0144] Reference sampling rate RefVFs = 7.800047607712GSa / s

[0145] Executable interpolation times realInterpTimes = 1.0

[0146] Executable extraction multiple realDecTimes = 2.0

[0147] Intermediate sampling rate VFs = 10.0000000000000GSa / s

[0148] Second output sampling rate Fs2 = 5.0000000000000GSa / s

[0149] Case 5: User-set expected bit rate Rs = 1250.0000000000000Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0150] Reference multiplication factor RefTimes = 24.000000000000

[0151] Reference sampling rate RefVFs = 30.0000000000000GSa / s

[0152] Executable interpolation times realInterpTimes = 1.0

[0153] Executable extraction multiple realDecTimes = 5.0

[0154] Intermediate sampling rate VFs = 25.0000000000000GSa / s

[0155] Second output sampling rate Fs2 = 5.0000000000000GSa / s

[0156] When the intermediate sampling rate mode = ON and the fixed output sampling rate mode = OFF:

[0157] Case 6: User-set expected bit rate Rs = 1.0000000000000Mbps

[0158] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0159] Reference multiplication factor RefTimes = 24.000000000000

[0160] Reference sampling rate RefVFs = 0.024000000000GSa / s

[0161] Executable interpolation times realInterpTimes = 250.0

[0162] Executable extraction multiple realDecTimes = 1.0

[0163] Intermediate sampling rate VFs = 0.020000000000GSa / s

[0164] First output sampling rate Fs1 = 0.020000000000GSa / s

[0165] Case 7: User-set expected bit rate Rs = 1.511287427978 Mbps

[0166] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0167] Reference multiplication factor RefTimes = 24.000000000000

[0168] Reference sampling rate RefVFs = 0.036270898271GSa / s

[0169] Executable interpolation times realInterpTimes = 160.0

[0170] Executable extraction multiple realDecTimes = 1.0

[0171] Intermediate sampling rate VFs = 0.031250000000GSa / s

[0172] First output sampling rate Fs1 = 0.031250000000GSa / s

[0173] Case 8: User-set expected bit rate Rs = 125.0000000000000Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0174] Reference multiplication factor RefTimes = 24.000000000000

[0175] Reference sampling rate RefVFs = 3.0000000000000GSa / s

[0176] Executable interpolation times realInterpTimes = 2.0

[0177] Executable extraction multiple realDecTimes = 1.0

[0178] Intermediate sampling rate VFs = 2.5000000000000GSa / s

[0179] First output sampling rate Fs1 = 2.500000000000GSa / s

[0180] Case 9: User-set expected bit rate Rs = 325.001983654685Mbps Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0181] Reference multiplication factor RefTimes = 24.000000000000

[0182] Reference sampling rate RefVFs = 7.800047607712GSa / s

[0183] Executable interpolation times realInterpTimes = 1.0

[0184] Executable extraction multiple realDecTimes = 2.0

[0185] Intermediate sampling rate VFs = 10.0000000000000GSa / s

[0186] First output sampling rate Fs1 = 5.0000000000000GSa / s

[0187] Case 10: User-set expected bit rate Rs = 1250.0000000000000Mbps

[0188] Maximum sampling rate MaxFs = 5.0000000000000GSa / s

[0189] Reference multiplication factor RefTimes = 24.000000000000

[0190] Reference sampling rate RefVFs = 30.0000000000000GSa / s

[0191] Executable interpolation times realInterpTimes = 1.0

[0192] Executable extraction multiple realDecTimes = 5.0

[0193] Intermediate sampling rate VFs = 25.0000000000000GSa / s

[0194] First output sampling rate Fs1 = 5.0000000000000GSa / s

[0195] It can be seen that the method for generating a high-speed serial signal in the embodiment of the present application can effectively reduce the amount of calculation and the required storage space under the premise of ensuring that the accuracy is not lost at a low bit rate by calculating and using an intermediate sampling rate; the calculation accuracy and quality of the high-speed serial signal can be effectively improved at a high bit rate, and multiple modes are supported at the same time, and users can flexibly choose. However, in some AWG signal sources, in order to reduce the amount of calculation at a low bit rate, the low bit rate is usually directly multiplied by a multiple and used as the output sampling rate to generate a high-speed serial signal. For example, TekAWG5200 directly generates a high-speed serial signal with a 6-fold bit rate as the output sampling rate at a low bit rate, lacks the setting of the user's autonomous selection mode, and may lose accuracy. When the required storage space exceeds the maximum storage space of the AWG signal source, there is no way to generate a high-speed serial signal normally. For example, KeysightM8195A will calculate the final required storage space in real time according to parameters such as bit rate and symbol length. If the maximum storage space is exceeded, an error will be prompted, allowing the user to re-modify parameters such as symbol length or bit rate, and lacks autonomous adjustment of the sampling rate.

[0196] The embodiment of the present application provides a device for generating a high-speed serial signal, which corresponds to the method for generating a high-speed serial signal in the above embodiment. Figure 6 As shown, the high-speed serial signal generating device 100 includes:

[0197] An acquisition unit 101 is used to acquire a mode selection signal, where the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode;

[0198] The first mode unit 102 is configured to determine an intermediate sampling rate according to an expected bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate if the first selection control information is control-on information and the second selection control information is control-off information;

[0199] The first high-speed serial signal generating unit 103 is configured to generate a high-speed serial signal according to a first output sampling rate.

[0200] In an embodiment of the present application, by using the first selection control information of the intermediate sampling rate mode as control-on information and the second selection control information of the fixed output sampling rate mode as control-off information, the intermediate sampling rate is determined according to the expected bit rate set by the user, and the first output sampling rate is determined according to the intermediate sampling rate, thereby adjusting the sampling rate corresponding to the expected bit rate set by the user to the intermediate sampling rate, reasonably selecting the intermediate sampling rate, and then reasonably selecting the output sampling rate. In other words, when the expected bit rate is very low or very high, the number of sampling points is more reasonable, which can effectively reduce the amount of calculation, save calculation time, and improve the accuracy of the code element edge construction, thereby effectively improving the quality of the generated high-speed serial signal.

[0201] In an optional implementation, the first mode unit 102 includes:

[0202] A reference sampling rate determination unit, used to determine a reference sampling rate according to an expected bit rate set by a user;

[0203] The first intermediate sampling rate determining unit is used to determine the intermediate sampling rate according to the reference sampling rate.

[0204] In an optional implementation, the first intermediate sampling rate determining unit includes:

[0205] The second intermediate sampling rate determining unit is used to determine the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate.

[0206] In an optional implementation manner, the second intermediate sampling rate determining unit includes:

[0207] A first multiple determination unit, configured to determine an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is greater than or equal to the maximum sampling rate;

[0208] The third intermediate sampling rate determining unit is used to determine the intermediate sampling rate according to the executable decimation multiple.

[0209] In an optional implementation manner, the first multiple determination unit includes:

[0210] A reference decimation multiple determining unit, used to determine a reference decimation multiple according to a reference sampling rate and a maximum sampling rate;

[0211] The executable decimation factor determination unit is used to determine an integer executable decimation factor that satisfies a first condition according to the reference decimation factor, wherein the first condition is that a first deviation between the reference decimation factor and the executable decimation factor is within a first preset deviation range.

[0212] In an optional implementation manner, the second intermediate sampling rate determining unit further includes:

[0213] A second multiple determination unit, configured to determine an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate if the reference sampling rate is less than the maximum sampling rate;

[0214] The fourth intermediate sampling rate determining unit is used to determine the intermediate sampling rate according to the executable interpolation multiple.

[0215] In an optional implementation manner, the second multiple determination unit includes:

[0216] A reference interpolation multiple determination unit, used for determining a reference interpolation multiple according to a reference sampling rate and a maximum sampling rate;

[0217] The executable interpolation multiple determining unit is used to determine an integer executable interpolation multiple that meets a second condition according to the reference interpolation multiple. The second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

[0218] In an optional implementation, the high-speed serial signal generating device further includes:

[0219] A second mode unit, configured to determine an intermediate sampling rate according to an expected bit rate set by a user, and determine a second output sampling rate as a maximum sampling rate according to the intermediate sampling rate if the first selection control information is control-on information and the second selection control information is control-on information;

[0220] The second high-speed serial signal generating unit is used to generate a high-speed serial signal according to the second output sampling rate.

[0221] In an optional implementation, the high-speed serial signal generating device further includes:

[0222] a third mode unit, configured to determine the intermediate sampling rate as the maximum sampling rate and the third output sampling rate as the maximum sampling rate if the first selection control information is control-off information and the second selection control information is control-on information;

[0223] The third high-speed serial signal generating unit is used to generate a high-speed serial signal according to a third output sampling rate.

[0224] The present application also provides an electronic device, such as Figure 7 As shown, the electronic device 200 includes a processor 201 and a memory 202; the memory 202 stores computer executable instructions, and the computer executable instructions are executed by the processor 201 to execute the above-mentioned method for generating a high-speed serial signal.

[0225] The processor 201 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0226] The memory 202 may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 201 may execute the program instructions to implement the steps in the above method for generating a high-speed serial signal and / or other desired functions.

[0227] In one example, the electronic device 200 may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown in the figure).

[0228] In addition, the input device may also include, for example, a keyboard, a mouse, a microphone, etc. The output device may output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0229] Of course, to simplify, Figure 7 Only a part of the components related to the embodiment of the present application in the electronic device 200 is shown, and components such as a bus, an input device / output interface, etc. are omitted. In addition, according to specific application conditions, the electronic device 200 may also include any other appropriate components.

[0230] The embodiment of the present application further provides a storage medium having computer executable instructions stored thereon. When the computer executable instructions are executed by a processor, the method for generating a high-speed serial signal is executed.

[0231] The present application embodiment can be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium, which is loaded with computer-readable program instructions for making a processor realize the various aspects of the present application embodiment. The computer program product can be written in any combination of one or more programming languages ​​to perform the program code for the operation of the present application embodiment, and the programming language includes an object-oriented programming language, such as Java, C++, etc., and also includes a conventional procedural programming language, such as "C" language or similar programming language. The program code can be executed completely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device, partially on the remote computing device, or completely on the remote computing device or server. In the case of a remote computer, the remote computer can be connected to the user computer through any kind of network-including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, using an Internet service provider to connect through the Internet). In some embodiments, by utilizing the state information of computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the embodiments of the present application.

[0232] Computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. Computer readable storage medium is a tangible device that can keep and store instructions used by an instruction execution device. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage medium include: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding device, such as a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination of the above. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0233] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0234] Various aspects of the embodiments of the present application are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0235] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0236] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0237] It should be noted that the high-speed serial signal generation method embodiment, high-speed serial signal generation device embodiment, computer-readable storage medium embodiment and electronic device embodiment provided in the embodiments of the present application belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict.

[0238] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for generating a high-speed serial signal, characterized in that: include: Acquire a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; If the first selection control information is control-on information and the second selection control information is control-off information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining a first output sampling rate according to the intermediate sampling rate; A high speed serial signal is generated according to the first output sampling rate.

2. The method for generating a high-speed serial signal according to claim 1, wherein: Determining the intermediate sampling rate according to the expected bit rate set by the user includes: Determine the reference sampling rate according to the expected bit rate set by the user; An intermediate sampling rate is determined according to the reference sampling rate.

3. The method for generating a high-speed serial signal according to claim 2, characterized in that: Determining the intermediate sampling rate according to the reference sampling rate comprises: An intermediate sampling rate is determined according to a multiple relationship between the reference sampling rate and the maximum sampling rate.

4. The method for generating a high-speed serial signal according to claim 3, characterized in that: Determining the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate comprises: If the reference sampling rate is greater than or equal to the maximum sampling rate, determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate; An intermediate sampling rate is determined based on the executable decimation factor.

5. The method for generating a high-speed serial signal according to claim 4, characterized in that: The step of determining an integer executable decimation multiple according to the reference sampling rate and the maximum sampling rate comprises: Determine a reference decimation multiple according to the reference sampling rate and the maximum sampling rate; An integer executable decimation multiple that satisfies a first condition is determined according to the reference decimation multiple, wherein the first condition is that a first deviation between the reference decimation multiple and the executable decimation multiple is within a first preset deviation range.

6. The method for generating a high-speed serial signal according to claim 4, characterized in that: The determining of the intermediate sampling rate according to the multiple relationship between the reference sampling rate and the maximum sampling rate further comprises: If the reference sampling rate is less than the maximum sampling rate, determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate; An intermediate sampling rate is determined according to the executable interpolation factor.

7. The method for generating a high-speed serial signal according to claim 6, characterized in that: The determining an integer executable interpolation multiple according to the reference sampling rate and the maximum sampling rate comprises: Determine a reference interpolation multiple according to the reference sampling rate and the maximum sampling rate; An integer executable interpolation multiple that satisfies a second condition is determined according to the reference interpolation multiple, wherein the second condition is that a second deviation between the reference interpolation multiple and the executable interpolation multiple is within a second preset deviation range.

8. The method for generating a high-speed serial signal according to claim 1, wherein: Also includes: If the first selection control information is control-on information and the second selection control information is control-on information, determining an intermediate sampling rate according to an expected bit rate set by a user, and determining the second output sampling rate as a maximum sampling rate according to the intermediate sampling rate; A high speed serial signal is generated according to the second output sampling rate.

9. The method for generating a high-speed serial signal according to claim 1, wherein: Also includes: If the first selection control information is control-off information and the second selection control information is control-on information, determining the intermediate sampling rate as the maximum sampling rate and determining the third output sampling rate as the maximum sampling rate; A high speed serial signal is generated according to the third output sampling rate.

10. A device for generating a high-speed serial signal, characterized in that: include: An acquisition unit, configured to generate a mode selection signal, wherein the mode selection signal includes first selection control information of an intermediate sampling rate mode and second selection control information of a fixed output sampling rate mode; A first mode unit, configured to determine an intermediate sampling rate according to an expected bit rate set by a user, and determine a first output sampling rate according to the intermediate sampling rate if the first selection control information is control-on information and the second selection control information is control-off information; The first high-speed serial signal generating unit is configured to generate a high-speed serial signal according to the first output sampling rate.

11. An electronic device, characterized in that: include: processor; as well as A memory having computer executable instructions stored thereon, wherein the computer executable instructions, when executed by the processor, execute the method for generating a high-speed serial signal according to any one of claims 1 to 9.

12. A storage medium, characterized in that: The storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the method for generating a high-speed serial signal according to any one of claims 1 to 9 is executed.

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