Dynamic reconstruction method of two-dimensional memory access controller

Abstract

The invention discloses a dynamic reconstruction method of a two-dimensional memory access controller, which belongs to the technical field of memory access controllers, and specifically comprises the following steps of: extracting the parallelism degree and the operation characteristic of a matrix algorithm, determining the partitioning mode of a storage module according to the parallelism degree and the operation characteristic, and storing matrix source data in a partitioning manner; based on the degree of parallelism, the number of enabled source data channels is determined, and efficient transmission of data from storage to calculation is achieved; according to the degree of parallelism and the operation characteristics, matrix source data are moved from the storage module to the calculation module through the source data channel, and matrix operation is executed; after the operation is finished, determining the number of enabled result data channels according to the degree of parallelism and a result, and transmitting the result back to the storage module; the configuration of each module is dynamically adjusted according to an algorithm and operation requirements, and the flexibility and efficiency of matrix operation are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of memory access controllers, in particular to a dynamic reconstruction method of a two-dimensional memory access controller. Background Art

[0002] With the rapid development of information technology, especially the rise of big data, cloud computing and artificial intelligence, the performance and flexibility of computing systems are increasingly required. Traditional computing systems often use fixed hardware architectures and algorithms, which are difficult to meet the high performance and flexibility requirements of these emerging applications. Therefore, dynamic reconstruction technology has emerged, which allows the hardware architecture or algorithm implementation to be dynamically changed according to actual needs during the computing process, thereby improving the flexibility and adaptability of the computing system.

[0003] The memory controller is responsible for managing and optimizing the transmission of data between the memory and the processor to improve the execution efficiency of the algorithm. However, traditional memory controllers often adopt a fixed design, which makes it difficult to adapt to the different requirements of different matrix algorithms for memory access modes and data transmission speeds. As a result, when processing complex matrix algorithms, the memory controller may become a performance bottleneck, limiting the performance improvement of the entire computing system.

[0004] For example, the patent with authorization announcement number CN109284231B discloses a method, device and memory controller for processing memory access requests, including: obtaining a number of memory access requests in sequence; extracting the logical channel address in the memory access request; grouping the memory access requests based on the logical channel address to form a number of request groups; preprocessing the memory access request in sequence for each request group to form the instructions required to complete the memory access request; and reconstructing the instructions corresponding to each memory access request in each request group in sequence. This technical solution is based on the fact that the operations of different logical channel address components of the memory do not affect each other during specific operation, and after the pre-charging or activation instructions are issued for the same logical channel address, if another logical channel address is operated, there is no need to wait for the previous operation to be completed, which can avoid the low interface utilization caused by the waiting time of each pre-charging and activation, and improve the memory access efficiency.

[0005] The above existing technologies all have the following problems: 1) The dynamic adjustment capability is limited; 2) Although the memory access efficiency is improved by avoiding the waiting time of pre-charging and activation, this optimization is not sufficient to meet the needs of high-performance matrix operations; 3) There are limitations in the application scenarios. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention proposes a dynamic reconstruction method for a two-dimensional memory access controller. Based on the design concept of storage and calculation decoupling, data storage and data processing are separated and designed, and the parallelism and operation characteristics of the matrix algorithm are extracted. Based on this, the partitioning method of the storage module is determined and the matrix source data is stored in partitions; based on the parallelism, the number of enabled source data channels is determined to achieve efficient transmission of data from storage to calculation; according to the parallelism and operation characteristics, the matrix source data is moved from the storage module to the calculation module through the source data channel to perform matrix operations; after the operation is completed, the number of enabled result data channels is determined according to the parallelism and the result, and the result is transmitted back to the storage module; the configuration of each module is dynamically adjusted according to the algorithm and operation requirements, thereby improving the flexibility and efficiency of matrix operations.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A dynamic reconstruction method of a two-dimensional memory access controller, comprising:

[0009] Step S1: extracting the parallelism and operation characteristics of the matrix algorithm, determining the partitioning mode of the storage module according to the parallelism and operation characteristics of the matrix algorithm, and storing the matrix source data in the matrix storage module by partition, wherein the parallelism of the matrix algorithm is the proportion or number of parts that can be executed in parallel in the matrix algorithm, and the matrix source data is stored vertically in the storage module by columns / rows;

[0010] Step S2: Based on the stored matrix source data determined in step S1, the number of enabled matrix source data channels required is calculated, and the corresponding matrix source data channels are configured;

[0011] Step S3: according to the extracted matrix algorithm parallelism and operation characteristics, the matrix source data is moved from the matrix storage module to the calculation module through the configured matrix source data channel to perform matrix operations;

[0012] Step S4: after the matrix operation is completed, based on the extracted matrix algorithm parallelism and the matrix operation result, the number of enabled matrix operation result data channels is determined, and the corresponding matrix operation result data channels are configured, and the matrix operation result data is moved from the calculation module to the matrix storage module through the matrix operation result data channels;

[0013] Step S5: Use the throughput indicator to dynamically evaluate the performance and efficiency of the current system, and adjust the configuration of the storage module, data channel and computing module according to the evaluation results.

[0014] Specifically, the operation characteristics in step S1 include the number of operands, the input and output mode, and the requirement for enabling the intermediate result area;

[0015] The number of operands num, if num=1, is covariance, if num=2, is matrix algorithm, the matrix algorithm includes matrix addition / subtraction, matrix multiplication, weighted method and generalized inner product;

[0016] The input and output modes include a matrix source data horizontal / vertical broadcast output mode, a matrix source data parallel output mode, a result area sequential input mode, a result area parallel input mode and an intermediate result area input and output mode;

[0017] The requirement for enabling the intermediate result area is that if it is a generalized inner product and covariance algorithm, the intermediate result area needs to be enabled. If it is a matrix algorithm such as matrix addition / subtraction, matrix multiplication, and weighted method, the intermediate result area does not need to be enabled.

[0018] Specifically, the matrix source data partitioning method in step S1 includes:

[0019] If num=1, the matrix source data area is not partitioned, and the matrix source data area is used to store the matrix source data corresponding to a single operand;

[0020] If num=2, the matrix source data area is divided into 2 partitions, each for storing the matrix source data corresponding to 1 operand, and each partition includes m memories, where m represents the parallelism of the matrix algorithm and m is a power of 2.

[0021] Specifically, the extraction of the matrix parallelism m in step S1 includes:

[0022] The ridge performance model is constructed based on the peak floating-point computing power, storage bandwidth, and operation density. Under this model, the operation density is the number of floating-point operations that can be supported by each byte of memory access data. The number of floating-point operations per byte is determined by the operation characteristics and parallelism. The value of the operation density at the "ridge point" of the model is determined based on the peak floating-point computing power and storage bandwidth, and then the parallelism of the matrix algorithm is determined based on the operation characteristics.

[0023] Specifically, the matrix source data channel division in step S2 includes:

[0024] If num=1, the matrix source data channel is not divided, and the matrix source data channel is used for the transmission of the matrix source data corresponding to a single operand;

[0025] If num=2, the matrix source data channels are divided into two groups of matrix source data channels, each group being used to transmit the matrix source data corresponding to one operand, and each group includes m matrix source data channels.

[0026] Specifically, the specific steps of step S3 include:

[0027] S3.1: Determine the required operation unit type and the number of enabled operation units according to the extracted matrix algorithm parallelism and operation characteristics, and determine the output mode of the matrix source data according to the operation unit type;

[0028] If the matrix algorithm is matrix multiplication or weighted method, the output modes of matrix source data area 1 and matrix source data area 2 are both parallel output, and m data are transmitted to m addition operation units for calculation within one clock cycle Δt;

[0029] If the matrix algorithm is a weighted method, the matrix source data area 1 is reconstructed into a horizontal broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode, and within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way multiplication and accumulation calculation unit, and the source data area 2 provides m numbers to the m-way multiplication and accumulation calculation unit for calculation, wherein the matrix source data area 1 is stored in the storage module in a horizontal row order, and the matrix source data area 2 is stored in the storage module in a vertical column order;

[0030] If the matrix algorithm is a generalized inner product, the matrix source data area 1 is reconstructed into a vertical broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode. Within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way conjugate multiplication and accumulation calculation unit, and the matrix source data area 2 provides m numbers to the m-way conjugate multiplication and accumulation calculation unit to complete the calculation, wherein the matrix source data area 1 and area 2 are both stored vertically by column in the storage module;

[0031] If it is covariance, that is, num=1, the matrix source data area is reconstructed into a parallel output mode. Within Δt, the matrix source data provides m numbers to the multiplication-add tree calculation unit to complete the calculation, wherein the matrix source data is stored vertically by column in the storage module.

[0032] Specifically, the specific steps of step S3 also include:

[0033] S3.2: Based on the type, enabled number and output mode of the computing unit determined in S3.1, determine the enabling requirements of the intermediate result area;

[0034] If the intermediate result area is not enabled, the n intermediate results generated by the operation module are directly output as the final results, where n represents the parallelism of the intermediate result calculation and n is a power of 2;

[0035] If the intermediate result area is enabled, after the intermediate result operation unit completes the calculation, m intermediate result data are received and stored in the intermediate result area within Δt;

[0036] S3.3: Perform matrix operations in the configured computational modules.

[0037] Specifically, the specific steps of step S4 include:

[0038] S4.1: Obtain the matrix operation result output by the calculation module in step S3.3, and store the matrix operation result data;

[0039] S4.2: Determine the scale and structure of the matrix operation result data according to the extracted matrix algorithm parallelism, and judge the matrix operation result data input mode according to the scale and structure of the matrix operation result and the interface capability of the matrix storage module, and determine the number of enabled matrix operation result data channels;

[0040] S4.3. If the matrix algorithm uses parallel processing during the operation and the result data can be output in parallel, the matrix operation result advance mode is the parallel advance mode;

[0041] If the matrix operation result carry mode is the parallel carry mode, then every time a calculation end signal within Δt is received from the calculation module, m result data channels are enabled at the same time, and the m result data are stored in parallel in the matrix storage module through the m result data channels;

[0042] S4.4: If the matrix algorithm uses a sequential processing method during the operation, or the matrix operation result data needs to be output in sequence, the matrix operation result advance mode is the sequential advance mode;

[0043] If the matrix operation result feed mode is a sequential feed mode, then each time a calculation end signal of a clock cycle is received from the calculation module, one result data channel will be enabled, and one result data will be stored in the matrix storage module through the one result data channel.

[0044] An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of a dynamic reconstruction method of a two-dimensional memory access controller when executing the computer program.

[0045] A computer-readable storage medium stores computer instructions, which, when executed, execute the steps of a dynamic reconstruction method of a two-dimensional memory access controller.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] 1. The present invention proposes a dynamic reconstruction method for a two-dimensional memory access controller and a dynamic reconstruction method for a multifunctional vector algorithm accelerator, which can dynamically reconstruct the hardware circuit according to the actual algorithm operation requirements and flexibly perform combined scheduling of storage resources, data paths and computing resources, thereby solving the redundant control logic and data flow path problems existing in the multifunctional vector algorithm accelerator.

[0048] 2. The present invention proposes a dynamic reconstruction method for a two-dimensional memory access controller. By extracting the parallelism and operation characteristics of the matrix algorithm, the flexible configuration of the storage module, data channel and computing module is realized. This customized configuration based on the algorithm characteristics not only improves the parallel processing efficiency of the matrix operation, but also ensures the efficiency and accuracy of the data during storage and transmission. By storing the matrix source data vertically by columns and determining the configuration of the storage partition, data channel and operation unit according to the algorithm parallelism, the process realizes the full utilization of hardware resources, thereby improving the overall performance of the system.

[0049] 3. The present invention proposes a dynamic reconstruction method for a two-dimensional memory access controller, and also realizes continuous optimization of the system configuration by dynamically evaluating the throughput and efficiency of the system; after the matrix operation is completed, the system will automatically adjust the number of enabled data channels according to the operation results and the parallelism of the algorithm to optimize the data transmission efficiency; at the same time, by regularly or in real time evaluating the system performance, potential bottleneck problems can be discovered and resolved in a timely manner, thereby ensuring that the system always maintains an efficient and stable operating state, so that it can show good adaptability and scalability when dealing with matrix operations of different scales and complexities. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of a dynamic reconstruction method of a two-dimensional memory access controller according to the present invention;

[0051] Figure 2 It is a principle flow chart of a dynamic reconstruction method of a two-dimensional memory access controller of the present invention;

[0052] Figure 3 A two-dimensional memory access controller dynamic reconstruction method of the present invention is an implementation flow chart of the two-dimensional memory access controller dynamic reconstruction method;

[0053] Figure 4 A schematic diagram of a dynamic reconstruction method of a two-dimensional memory access controller of the present invention, in which matrix source data is horizontally stored row by row in a storage module with 16 degrees of parallelism;

[0054] Figure 5 A schematic diagram of a dynamic reconstruction method of a two-dimensional memory access controller of the present invention, in which matrix source data is stored vertically by column in a storage module with 16 degrees of parallelism;

[0055] Figure 6 The present invention is a schematic diagram of a dynamic reconstruction method of a two-dimensional memory access controller in which matrix result data is stored horizontally by row in a storage module with 16 degrees of parallelism. DETAILED DESCRIPTION

[0056] Example 1

[0057] See also Figure 1 and Figure 3 The present invention provides an embodiment: a dynamic reconstruction method of a two-dimensional memory access controller. The core idea is to dynamically adjust and optimize the structure and parameters of the memory access controller according to the operation characteristics and requirements of the matrix algorithm to adapt to different algorithms and data scales, thereby ensuring that the algorithm can be executed efficiently and accurately. It is suitable for hardware circuit implementation of matrix algorithm accelerators under different parallelisms and can improve design efficiency. The method includes the following steps:

[0058] Step S1: extracting the parallelism and operation characteristics of the matrix algorithm, determining the partitioning mode of the storage module according to the parallelism and operation characteristics of the matrix algorithm, and storing the matrix source data in the matrix storage module by partition, wherein the matrix source data is stored vertically in the storage module by column / row;

[0059] It should be noted that when performing matrix multiplication / weighting, E=AB, where the A matrix is ​​stored horizontally by rows in the storage module, and the source data matrices of all other algorithms are stored vertically by columns in the module.

[0060] Among them, the parallelism of the matrix algorithm is the proportion or number of parts that can be executed in parallel in the matrix algorithm;

[0061] Furthermore, the specific steps of step S1 include:

[0062] (1) Analyze the parallelism of matrix algorithms and determine the degree of parallelism of matrix algorithm operations;

[0063] The extraction of matrix parallelism m includes:

[0064] The ridge performance model is constructed based on the peak floating-point computing power, storage bandwidth, and operation density. Under this model, the operation density is the number of floating-point operations that can be supported by each byte of memory access data. The number of floating-point operations per byte is determined by the operation characteristics and parallelism. The value of the operation density at the "ridge point" of the model is determined based on the peak floating-point computing power and storage bandwidth, and then the parallelism of the matrix algorithm is determined based on the operation characteristics.

[0065] It should be noted that the determination of algorithm parallelism usually includes the following aspects in addition to performance impact:

[0066] 1) Calculation steps: In matrix algorithms, some calculation steps are independent and can be performed in parallel. For example, in matrix addition, the addition operation of each element is independent and can be performed in parallel.

[0067] 2) Iterative process: For matrix algorithms involving iterative processes, such as matrix power operations or matrix solving, the iterative process can be divided into multiple stages, and each stage can be executed in parallel.

[0068] At the same time, there are some limitations to consider when determining what can be executed in parallel:

[0069] 1) Data dependency: If there is data dependency between the computational steps in a matrix algorithm, these steps cannot be executed in parallel. It is necessary to carefully analyze the data dependency in the algorithm to determine which steps can be executed in parallel.

[0070] 2) Communication overhead: Parallel execution needs to deal with data communication issues between multiple processors. If the communication overhead is too large, it will affect the efficiency of parallel execution. Therefore, when selecting the parts to be executed in parallel, it is necessary to balance the computational overhead and communication overhead.

[0071] 3) Load balancing: To ensure the efficiency of parallel execution, it is necessary to ensure load balance among processors. If the task of one processor is too heavy and the tasks of other processors are too light, it will lead to a decline in overall performance. Therefore, when dividing tasks, it is necessary to consider the issue of load balancing.

[0072] (2) Analyze the operational characteristics of the matrix algorithm, such as the size, shape, and number of source data matrices, and determine the data dependencies and communication overhead in parallel computing based on the operational characteristics;

[0073] Furthermore, the steps of data dependency include:

[0074] 1) Analysis and operation steps:

[0075] Analyze each computational step in a parallel algorithm to determine which steps need to access or modify shared data, and identify which data is reused or interdependent in multiple steps;

[0076] 2) Build the dependency graph:

[0077] A dependency graph is used to intuitively represent the dependency relationship between data. In the dependency graph, nodes represent data items, and edges represent the dependency relationship between data items. By analyzing the dependency graph, it is determined which data items can be processed in parallel and which must be processed in sequence. The dependency graph analysis method is a prior art content in this field, and is not an inventive solution of the present application, and will not be described in detail here.

[0078] 3) Consider the parallel model:

[0079] Further analyze data dependencies based on the parallel computing model used, such as pipeline parallelism, data parallelism, and task parallelism;

[0080] For example, in pipeline parallelism, it is necessary to ensure that the data of each partition can be correctly passed to the next partition after processing.

[0081] Furthermore, the specific steps of determining the communication overhead include:

[0082] 1) Evaluate the amount of data transfer: Calculate the amount of data required to transfer for each step in the parallel algorithm, including data transfer from memory to processor and data transfer between processors;

[0083] 2) Consider the communication mode: Analyze the data transmission mode, such as point-to-point communication, broadcast communication, and network communication. Different communication modes have different effects on communication overhead;

[0084] 3) Evaluate communication delay and bandwidth: Measure the delay and bandwidth of the communication network to understand the speed and efficiency of data transmission. Delay refers to the time required for data to travel from the sender to the receiver, and bandwidth refers to the amount of data that can be transmitted per unit time in the communication network.

[0085] 4) Consider load balancing: Ensure that each processor or computing node in the parallel algorithm is assigned a balanced workload. Unbalanced load will cause some processors to wait for other processors to complete data transfer, thereby increasing communication overhead.

[0086] 5) Optimize communication strategy: Use data compression to reduce the amount of data transmission, and use overlapping communication and computing technology, that is, data transmission while the processor is performing calculations, to hide communication delays.

[0087] (3) Designing a partitioning method of the storage module according to the parallelism and operation characteristics of the matrix algorithm. In the present invention, a row-column partitioning method is selected;

[0088] (4) Store the matrix source data in the matrix storage module according to the designed partitioning method to ensure that the storage module can support parallel access and efficient data transmission.

[0089] Step S2: Based on the stored matrix source data determined in step S1, the number of enabled matrix source data channels required is calculated, and the corresponding matrix source data channels are configured;

[0090] (1) configuring the matrix source data channel, including but not limited to the path, rate, and format of data transmission, and setting data handling strategies, such as direct memory access or cache strategies, to optimize data transmission efficiency;

[0091] (2) reading matrix source data to be processed from the matrix storage module, and packaging the read matrix source data according to the requirements of the calculation module, wherein packaging includes operations such as data format conversion, data alignment, and data blocking, and the specific implementation process of data packaging is the prior art content in this field, which is not the inventive solution of the present application and is not described in detail here;

[0092] Step S3: according to the extracted matrix algorithm parallelism and operation characteristics, the matrix source data is moved from the matrix storage module to the calculation module through the configured matrix source data channel to perform matrix operations;

[0093] Furthermore, the specific steps of moving the matrix source data from the matrix storage module to the calculation module include:

[0094] (1) Start the data transmission process through the configured data channel and monitor the transmission status during the data transmission process to ensure that the data is correctly and completely transmitted to the computing module. If any transmission error or abnormality is found, timely error handling or retransmission is performed;

[0095] (2) by controlling access to the data receiving interface of the computing module, the computing module receives data transmitted from the matrix storage module, wherein the specific access control is the prior art content in this field, is not the inventive solution of the present application, and is not elaborated here;

[0096] (3) The calculation module parses the received data and restores it to the original matrix data or the format required for calculation, wherein the parsing includes data format conversion and data reorganization operations, and the parsing process is the prior art content in this field and is not the inventive solution of the present application, and is not described in detail here;

[0097] (4) The computing module processes the parsed data, executes the corresponding matrix algorithm, and transmits the matrix algorithm results back to the matrix storage module for further processing.

[0098] It should be noted that in the process of moving matrix source data from the matrix storage module to the computing module, there is an inevitable connection between the matrix blocking strategy and the data handling method. The matrix blocking strategy determines how to divide a large matrix into multiple smaller sub-matrices for parallel computing, while the data handling method focuses on how to efficiently move these sub-matrices from the storage module to the computing module.

[0099] Among them, the relationship between the matrix partitioning strategy and the data handling method includes:

[0100] (1) Block strategy affects the demand for data transfer:

[0101] The size, shape and number of matrix blocks will directly affect the scale and frequency of data transfer. Larger blocks may reduce the number of data transfers, but the amount of data transferred each time will increase; smaller blocks may increase the number of data transfers, but the amount of data transferred each time will be smaller.

[0102] The block strategy also affects the complexity of data handling. For example, if the blocks are irregular in shape or inconsistent in size, it will increase the difficulty and cost of data handling.

[0103] (2) Data handling method optimizes the execution of block strategy:

[0104] Efficient data handling can speed up the data transmission after matrix partitioning, thereby supporting more complex partitioning strategies. For example, using high-speed data transmission interfaces such as PCIe, Ethernet or parallel data transmission technologies such as DMA and multithreading can improve the efficiency of data handling.

[0105] Optimizing data handling methods can also reduce delays and overhead during data transmission, thereby further improving the overall performance of matrix operations.

[0106] On the other hand, the specific steps for determining the data handling method according to the matrix partitioning strategy include:

[0107] (1) Understand the parallelism and operational characteristics of the matrix algorithm, including the algorithm's computational workload, memory access mode, and data dependencies. This information is the basis for determining the matrix partitioning strategy and data handling method;

[0108] (2) Determine the matrix partitioning strategy based on the parallelism and operation characteristics of the matrix algorithm, including selecting the size, shape, and number of blocks, and determining the partitioning method, such as row-by-row, column-by-column, or sub-matrix partitioning;

[0109] (3) Evaluate the feasibility of different data transfer methods, including factors such as data transfer rate, latency, overhead, and the overall system architecture and communication costs. Common data transfer methods include direct memory access, network transmission, and shared memory.

[0110] (4) Select the data transfer method based on the evaluation results of the matrix partitioning strategy and data transfer method, which requires comprehensive consideration of factors such as data transfer efficiency, overhead, and overall system performance;

[0111] (5) Optimize the data transfer process, including adjusting the data transfer rate, optimizing the data transfer scheduling strategy, reducing data transfer delays and overhead, and other measures. At the same time, the efficiency and reliability of data transfer can be further improved by using efficient data transfer protocols and compression algorithms.

[0112] Step S4: after the matrix operation is completed, based on the extracted matrix algorithm parallelism and the matrix operation result, the number of enabled matrix operation result data channels is determined, and the corresponding matrix operation result data channels are configured, and the matrix operation result data is moved from the calculation module to the matrix storage module through the matrix operation result data channels;

[0113] Step S5: Use the throughput indicator to dynamically evaluate the performance and efficiency of the current system, and adjust the configuration of the storage module, data channel and computing module according to the evaluation results. The calculation formula of the throughput indicator is the prior art content in this field, which is not the creative solution of this application and will not be elaborated here.

[0114] In the present invention, the analysis and feature extraction of matrix algorithms, the partition design of storage modules, the configuration of data transmission channels, the execution of matrix operations, the return and storage of results, and the dynamic configuration adjustment are summarized as the decoupling of matrix calculation and memory access, which specifically includes:

[0115] (1) Matrix algorithm analysis and feature extraction:

[0116] Parallelism analysis: First, conduct an in-depth analysis of the matrix algorithm to determine its parallelism. Parallelism refers to the amount of data or number of operations that the algorithm can process simultaneously. For example, in matrix multiplication, multiple element multiplication and accumulation operations can be processed in parallel.

[0117] Operation feature extraction: In addition to the degree of parallelism, it is also necessary to extract the operation features of the algorithm, such as data type, operation mode, and data access mode. The data type includes integers and floating-point numbers, the operation mode includes multiplication and transposition, and the data access mode includes row priority and column priority.

[0118] (2) Storage module partition design:

[0119] Determine the partitioning method: Determine the partitioning method of the storage module according to the extracted parallelism and operation characteristics. For example, if the algorithm has a high degree of row parallelism, the matrix can be partitioned by rows; if the algorithm needs to frequently access the transposed form of the matrix, it may be necessary to partition by columns or blocks;

[0120] Partition storage of matrix source data: According to the determined partitioning method, the matrix source data is stored in the corresponding storage partition. Each partition can be regarded as an independent data block, which is convenient for subsequent parallel processing;

[0121] (3) Data transmission channel configuration:

[0122] Determine the number of enabled channels: Based on the degree of parallelism, determine the number of enabled source data channels, which are used to transfer data from the storage module to the computing module;

[0123] Efficient transmission: Direct memory access is used to achieve efficient data transmission from the storage module to the computing module. Direct memory access can transfer data from the source address to the target address without occupying CPU resources, thereby improving the efficiency of data transmission.

[0124] (4) Matrix operation execution:

[0125] Data migration: Move matrix source data from the storage module to the computing module through the configured source data channel.

[0126] Operation execution: In the calculation module, matrix operations are performed according to the algorithm and operation characteristics. This can be achieved through parallel processors or multi-threaded or multi-core processors;

[0127] Intermediate result processing: During the operation, if the intermediate results need to be processed, they can be stored in the local cache of the computing module, or transferred back to the storage module for further processing as needed;

[0128] (5) Result transmission and storage:

[0129] Result data channel configuration: After the operation is completed, the number of enabled result data channels is determined based on the degree of parallelism and the characteristics of the result data. ;

[0130] Result return: The calculation result is transmitted from the calculation module to the storage module through the configured result data channel;

[0131] Result storage: In the storage module, the operation results are stored and processed as needed. For example, the results can be saved as files, updated to a database, or used for subsequent algorithm processing;

[0132] (6) Dynamic configuration adjustment:

[0133] Module configuration adjustment: Dynamically adjust storage modules, computing modules, and data transmission channels according to changes in algorithms and computing requirements, including adjusting partition sizes, enabling or disabling data channels, and adjusting cache strategies;

[0134] Improved flexibility and efficiency: Through dynamic configuration adjustment, it can adapt to different algorithms and computing requirements, thereby improving the flexibility and efficiency of matrix operations.

[0135] The operation characteristics in step S1 include the number of operands, the input and output mode, and the requirement to enable the intermediate result area;

[0136] The number of operands num, if num=1, it is covariance, if num=2, it is matrix algorithm, the matrix algorithm includes matrix addition / subtraction, matrix multiplication, weighted method and generalized inner product;

[0137] The input and output modes include the horizontal / vertical broadcast output mode of matrix source data, the parallel output mode of matrix source data, the sequential input mode of result area, the parallel input mode of result area and the input and output mode of intermediate result area;

[0138] The requirement to enable the intermediate result area is that if it is the generalized inner product and covariance algorithm, the intermediate result area needs to be enabled. If it is the matrix algorithm of matrix addition / subtraction, matrix multiplication, and weighted method, the intermediate result area does not need to be enabled.

[0139] The matrix source data partitioning method in step S1 includes:

[0140] If num=1, the matrix source data area is not partitioned, and the matrix source data area is used to store the matrix source data corresponding to a single operand;

[0141] If num=2, the matrix source data area is divided into 2 partitions, each for storing the matrix source data corresponding to 1 operand, and each partition includes m memories, where m represents the parallelism of the matrix algorithm and m is a power of 2.

[0142] The matrix source data channel division in step S2 includes:

[0143] If num=1, the matrix source data channel is not divided, and the matrix source data channel is used for the transmission of the matrix source data corresponding to a single operand;

[0144] If num=2, the matrix source data channels are divided into two groups of matrix source data channels, each group being used to transmit the matrix source data corresponding to one operand, and each group includes m matrix source data channels.

[0145] Example 2

[0146] See also Figure 4-Figure 6 ,exist Figure 4-Figure 6In the example, when the large matrix source data is stored in the storage module, the matrix is ​​split into a maximum of 16 rows and n columns, rather than stored row by row. The specific reasons include: 1) The storage module is designed with 16 parallelism, which means that it can process 16 data channels in parallel at the same time. Splitting the matrix into a maximum of 16 rows and n columns can make full use of the parallel processing capabilities of the storage module, so that each data access can be performed in parallel, thereby significantly improving the efficiency and throughput of data access; 2) If the matrix is ​​stored row by row, then when processing large matrices, it is necessary to frequently move data between the storage module and the computing module. By splitting the matrix into 16 rows and n columns, a data block, that is, 16 rows of data, can be moved to the computing module for processing at one time, thereby reducing the number of data moves and overhead; 3) Matrix operations usually have a high degree of data locality, that is, adjacent data elements are often frequently accessed during the operation process. By splitting the matrix into 16 rows and n columns, multiple elements in a data block can be accessed continuously during memory access, thereby optimizing the memory access mode and improving the efficiency of memory access; 4) By splitting the matrix into 16 rows and n columns, it is more convenient to process the data in blocks in the preprocessing stage, and use the cache to store and process these data blocks. The specific steps of step S3 in this embodiment include:

[0147] S3.1: Determine the required operation unit type and the number of enabled operation units according to the extracted matrix algorithm parallelism and operation characteristics, and determine the output mode of the matrix source data according to the operation unit type;

[0148] If the matrix algorithm is matrix addition / subtraction, the output modes of the matrix source data area 1 and the matrix source data area 2 are both parallel output, and m data are transmitted to m addition operation units for calculation within one clock cycle Δt;

[0149] If the matrix algorithm is matrix multiplication or weighted method, the matrix source data area 1 is reconstructed into a horizontal broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode, and within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way multiplication and accumulation calculation unit, and the source data area 2 provides m numbers to the m-way multiplication and accumulation calculation unit for calculation, wherein the matrix source data area 1 is stored in the storage module in a horizontal row order, and the matrix source data area 2 is stored in the storage module in a vertical column order;

[0150] If the matrix algorithm is a generalized inner product, the matrix source data area 1 is reconstructed into a vertical broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode. Within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way conjugate multiplication and accumulation calculation unit, and the matrix source data area 2 provides m numbers to the m-way conjugate multiplication and accumulation calculation unit to complete the calculation, wherein the matrix source data area 1 and area 2 are both stored vertically by column in the storage module;

[0151] If it is covariance, that is, num=1, the matrix source data area is reconstructed into a parallel output mode. Within Δt, the matrix source data provides m numbers to the multiplication-add tree calculation unit to complete the calculation, wherein the matrix source data is stored vertically by column in the storage module.

[0152] The specific steps of step S3 also include:

[0153] S3.2: Based on the type, enabled number and output mode of the computing unit determined in S3.1, determine the enabling requirements of the intermediate result area;

[0154] If the intermediate result area is not enabled, the n intermediate results generated by the operation module are directly output as the final results, where n represents the parallelism of the intermediate result calculation and n is a power of 2;

[0155] If the intermediate result area is enabled, after the intermediate result operation unit completes the calculation, m intermediate result data are received and stored in the intermediate result area within Δt;

[0156] S3.3: Perform matrix operations in the configured computational modules.

[0157] The specific steps of step S4 include:

[0158] S4.1: Obtain the matrix operation result output by the calculation module in step S3.3, and store the matrix operation result data;

[0159] S4.2: Determine the scale and structure of the matrix operation result data according to the extracted matrix algorithm parallelism, and judge the matrix operation result data input mode according to the scale and structure of the matrix operation result and the interface capability of the matrix storage module, and determine the number of enabled matrix operation result data channels;

[0160] S4.3. If the matrix algorithm uses parallel processing during the operation and the result data can be output in parallel, the matrix operation result advance mode is the parallel advance mode;

[0161] If the matrix operation result carry mode is the parallel carry mode, then every time a calculation end signal within Δt is received from the calculation module, m result data channels are enabled at the same time, and the m result data are stored in parallel in the matrix storage module through the m result data channels;

[0162] S4.4: If the matrix algorithm uses a sequential processing method during the operation, or the matrix operation result data needs to be output in sequence, the matrix operation result advance mode is the sequential advance mode;

[0163] If the matrix operation result feed mode is a sequential feed mode, then each time a calculation end signal of a clock cycle is received from the calculation module, one result data channel will be enabled, and one result data will be stored in the matrix storage module through the one result data channel.

[0164] Example 3

[0165] An electronic device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a dynamic reconstruction method of a two-dimensional memory access controller are implemented. For details, please refer to the above method embodiment, which will not be repeated here.

[0166] A computer-readable storage medium stores computer instructions, which, when executed, execute the steps of a dynamic reconstruction method of a two-dimensional memory access controller, wherein the storage medium may be a volatile or non-volatile computer-readable storage medium.

[0167] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in the field may also change, modify, replace and modify the above-mentioned embodiments without departing from the purpose and scope of protection of the present invention, and all of these are within the protection of the present invention.

Claims

1. A dynamic reconstruction method of a two-dimensional memory access controller, characterized in that: include: Step S1: extracting the parallelism and operation characteristics of the matrix algorithm, determining the partitioning mode of the storage module according to the parallelism and operation characteristics of the matrix algorithm, and storing the matrix source data in the matrix storage module by partition, wherein the parallelism of the matrix algorithm is the proportion or number of parts that can be executed in parallel in the matrix algorithm, and the matrix source data is stored vertically in the storage module by columns / rows; Step S2: Based on the stored matrix source data determined in step S1, the number of enabled matrix source data channels required is calculated, and the corresponding matrix source data channels are configured; Step S3: according to the extracted matrix algorithm parallelism and operation characteristics, the matrix source data is moved from the matrix storage module to the calculation module through the configured matrix source data channel to perform matrix operations; Step S4: after the matrix operation is completed, based on the extracted matrix algorithm parallelism and the matrix operation result, the number of enabled matrix operation result data channels is determined, and the corresponding matrix operation result data channels are configured, and the matrix operation result data is moved from the calculation module to the matrix storage module through the matrix operation result data channels; Step S5: Use the throughput indicator to dynamically evaluate the performance and efficiency of the current system, and adjust the configuration of the storage module, data channel and computing module according to the evaluation results.

2. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 1, characterized in that: The operation characteristics in step S1 include the number of operands, the input and output mode, and the requirement for enabling the intermediate result area; The number of operands num, if num=1, is covariance, if num=2, is matrix algorithm, the matrix algorithm includes matrix addition / subtraction, matrix multiplication, weighted method and generalized inner product; The input and output modes include a matrix source data horizontal / vertical broadcast output mode, a matrix source data parallel output mode, a result area sequential input mode, a result area parallel input mode and an intermediate result area input and output mode; The requirement for enabling the intermediate result area is that if it is a generalized inner product and covariance algorithm, the intermediate result area needs to be enabled. If it is a matrix algorithm such as matrix addition / subtraction, matrix multiplication, and weighted method, the intermediate result area does not need to be enabled.

3. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 2, characterized in that: The matrix source data partitioning method in step S1 includes: If num=1, the matrix source data area is not partitioned, and the matrix source data area is used to store the matrix source data corresponding to a single operand; If num=2, the matrix source data area is divided into 2 partitions, each for storing the matrix source data corresponding to 1 operand, and each partition includes m memories, where m represents the parallelism of the matrix algorithm and m is a power of 2.

4. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 3, characterized in that: The extraction of the matrix parallelism m in step S1 includes: A ridge performance model is constructed based on the peak floating-point computing power, storage bandwidth, and operation density. Under the ridge performance model, the operation density is the number of floating-point operations that can be supported by each byte of memory access data. The number of floating-point operations per byte is determined by the operation characteristics and parallelism. The operation density at the "ridge point" of the model is determined based on the peak floating-point computing power and storage bandwidth, and then the parallelism of the matrix algorithm is determined based on the operation characteristics.

5. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 4, characterized in that: The matrix source data channel division in step S2 includes: If num=1, the matrix source data channel is not divided, and the matrix source data channel is used for the transmission of the matrix source data corresponding to a single operand; If num=2, the matrix source data channels are divided into two groups of matrix source data channels, each group being used to transmit matrix source data corresponding to one operand, and each group includes m matrix source data channels.

6. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 5, characterized in that: The specific steps of step S3 include: S3.1: Determine the required operation unit type and the number of enabled operation units according to the extracted matrix algorithm parallelism and operation characteristics, and determine the output mode of the matrix source data according to the operation unit type; If the matrix algorithm is matrix addition / subtraction, the output modes of the matrix source data area 1 and the matrix source data area 2 are both parallel output, and m data are transmitted to m addition operation units for calculation within one clock cycle Δt; If the matrix algorithm is matrix multiplication or weighted method, the matrix source data area 1 is reconstructed into a horizontal broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode, and within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way multiplication and accumulation calculation unit, and the source data area 2 provides m numbers to the m-way multiplication and accumulation calculation unit for calculation, wherein the matrix source data area 1 is stored in the storage module in a horizontal row order, and the matrix source data area 2 is stored in the storage module in a vertical column order; If the matrix algorithm is a generalized inner product, the matrix source data area 1 is reconstructed into a vertical broadcast output mode, and the matrix source data area 2 is reconstructed into a parallel output mode. Within Δt, the matrix source data area 1 provides 1 data broadcast to the m-way conjugate multiplication and accumulation calculation unit, and the matrix source data area 2 provides m numbers to the m-way conjugate multiplication and accumulation calculation unit to complete the calculation, wherein the matrix source data area 1 and area 2 are both stored vertically by column in the storage module; If it is covariance, that is, num=1, the matrix source data area is reconstructed into a parallel output mode. Within Δt, the matrix source data provides m numbers to the multiplication-add tree calculation unit to complete the calculation, wherein the matrix source data is stored vertically by column in the storage module.

7. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 6, characterized in that: The specific steps of step S3 also include: S3.2: Based on the type, enabled number and output mode of the computing unit determined in S3.1, determine the need to enable the intermediate result area; If the intermediate result area is not enabled, the n intermediate results generated by the operation module are directly output as the final results, where n represents the parallelism of the intermediate result calculation and n is a power of 2; If the intermediate result area is enabled, after the intermediate result operation unit completes the calculation, m intermediate result data are received and stored in the intermediate result area within Δt; S3.3: Perform matrix operations in the configured computational modules.

8. A method for dynamic reconstruction of a two-dimensional memory access controller as claimed in claim 7, characterized in that: The specific steps of step S4 include: S4.1: Obtain the matrix operation result output by the calculation module in step S3.3, and store the matrix operation result data; S4.2: Determine the scale and structure of the matrix operation result data according to the extracted matrix algorithm parallelism, and judge the matrix operation result data input mode according to the scale and structure of the matrix operation result and the interface capability of the matrix storage module, and determine the number of enabled matrix operation result data channels; S4.

3. If the matrix algorithm uses parallel processing during the operation and the result data can be output in parallel, the matrix operation result advance mode is the parallel advance mode; If the matrix operation result carry mode is the parallel carry mode, then every time a calculation end signal within Δt is received from the calculation module, m result data channels are enabled at the same time, and the m result data are stored in parallel in the matrix storage module through the m result data channels; S4.4: If the matrix algorithm uses a sequential processing method during the operation, or the matrix operation result data needs to be output in sequence, the matrix operation result advance mode is the sequential advance mode; If the matrix operation result feed mode is a sequential feed mode, then each time a calculation end signal of a clock cycle is received from the calculation module, one result data channel will be enabled, and one result data will be stored in the matrix storage module through the one result data channel.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the processor implements the steps of a dynamic reconstruction method of a two-dimensional memory access controller as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that: Computer instructions are stored thereon, and when the computer instructions are executed, the steps of a dynamic reconstruction method of a two-dimensional memory access controller as described in any one of claims 1-8 are executed.

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