Analog circuit intelligent optimization algorithm based on domain knowledge

Abstract

The invention provides an analog circuit intelligent optimization algorithm based on domain knowledge, and relates to the technical field of analog circuits, and the algorithm comprises the steps: S1, sampling to generate an initial population; s2, simulating the initial population; s3, judging the evolution state of the initial population, and selecting different evolution operators; s4, combining the offspring population with the initial population to obtain a temporary population; s5, performing non-dominated sorting on the temporary population to obtain a non-dominated sequence; s6, sorting the temporary population with the obtained non-dominated sequence based on reference points to obtain a sequence based on the reference points; s7, selecting individuals from the temporary population as a new offspring population by using a niche retention strategy in combination with a sequence based on a reference point; s8, the maximum value of the number of iterations is set, and when the number of iterations does not reach the maximum value, the steps S3-S7 are executed circularly; and when the number of iterations reaches the maximum value, the algorithm is ended. The method has the advantages that the feasible solution exploration process is improved, and the quality of the generated solution is high.

Description

Technical Field

[0001] The present invention relates to the field of analog circuit technology, and in particular to an analog circuit intelligent optimization algorithm based on domain knowledge. Background Art

[0002] Analog circuits play a vital role in modern electronic systems and are widely used in many fields such as communications, signal processing, and sensor interfaces. Traditional analog circuit design methods often rely on the designer's experience and repeated trial and error. Designers need to manually select circuit topology and component parameters based on specific circuit functions and performance requirements. Since the component parameters in analog circuits are interrelated and have a nonlinear impact on circuit performance, this manual design method is not only time-consuming and labor-intensive, but it is also difficult to ensure that the designed circuit can achieve optimal performance.

[0003] In order to improve the efficiency and quality of analog circuit design, many analog circuit optimization algorithms have emerged. Common optimization algorithms include genetic algorithms, particle swarm optimization algorithms, etc. However, existing optimization algorithms are often blind when searching parameter space. For example, in genetic algorithms, crossover and mutation operations are performed randomly, which may produce a large number of individuals that do not conform to the actual circuit design rules, resulting in low efficiency in exploring feasible solutions. Secondly, in multi-objective optimization scenarios, existing optimization algorithms are difficult to effectively balance multiple conflicting objectives, and are prone to falling into local optimal solutions and failing to find the global optimal circuit design solution.

[0004] How to solve the above technical problems is the subject faced by the present invention. Summary of the invention

[0005] In order to address the deficiencies of the prior art, the present invention provides an intelligent optimization algorithm for analog circuits based on domain knowledge, which improves the feasible solution exploration process and generates high-quality solutions.

[0006] The technical solution adopted by the present invention to solve the technical problem is as follows: the present invention provides an analog circuit intelligent optimization algorithm based on domain knowledge, comprising the following steps: S1, using Latin hypercube sampling to generate an initial population P; S2, calling the automatic simulation module of the software Virtuoso to simulate the initial population P; S3, judging the evolutionary state of the initial population P according to the population evaluation index HV, and selecting to use the knowledge base evolution operator or the conventional crossover operator to generate a child population; S4, merging the child population S1 or S2 with the initial population P to obtain a temporary population P1; S5, performing non-dominated sorting on the temporary population P1 to obtain a non-dominated order F;

[0007] S6. Sort the temporary population P1 with the non-dominated order F based on the reference point to obtain the order F1 based on the reference point; S7. Combined with the order F1 based on the reference point, use the niche retention strategy to select individuals as the offspring population NP in the temporary population P1; S8. Set the maximum number of iterations. When the number of iterations does not reach the maximum value, loop through steps S3-S7; when the number of iterations reaches the maximum value, the algorithm ends.

[0008] Preferably, the step S2 calls the automatic simulation module of the software Virtuoso to simulate the initial population, and the specific steps are as follows:

[0009] S20, initializing parameters and converting parameter formats: using MATLAB to generate initial design parameters of the circuit, and using an algorithm to convert these parameters into a simulation parameter format suitable for the automatic simulation module of the software Virtuoso;

[0010] S21, using MATLAB to generate corresponding Ocean scripts for parameters applicable to the Virtuoso automatic simulation module;

[0011] S22. Run the Ocean script to implement a single circuit simulation.

[0012] S23. After the simulation is completed, the Ocean script transmits the simulation result data back to the algorithm, and the algorithm analyzes and processes the simulation result data.

[0013] Preferably, the step S3 determines the evolutionary state of the initial population P according to the population evaluation index HV, and selects to use the knowledge base evolution operator or the conventional crossover operator to generate offspring, and the specific steps are as follows:

[0014] S30, creating an analog circuit domain knowledge base K and calculating a population evaluation index HV;

[0015] S31, after every 5 iterations, compare the difference between the performance index of the current population and the previous 5 generations of populations. If the performance index of the current population is greater than 0.5, indicating that the population is in a normal iteration process, then select the conventional crossover and mutation operators to generate the offspring S1, and jump to step S33; if the performance index of the current population is less than or equal to 0.5, indicating that the population is in an evolutionary stagnation state, then continue to execute step S32;

[0016] S32, for individual target f = {f1, f2, ..., f m}, the algorithm performs a multiplication of each target component ζ={ζ1,ζ2,...,ζ m}Preset priority, and determine the target component in the individual according to the priority i , i = 1, 2, ..., whether m meets the circuit design standard:

[0017] If the target component ζ corresponding to a certain priority i , i = 1, 2, ..., m does not meet the standard, then the heuristic rule of the corresponding indicator in the analog circuit domain knowledge base K is used to generate the offspring S2;

[0018] If the target components ζ corresponding to all priorities i , i = 1, 2, ..., all meet the standard, then find the target component with the highest priority in the current individual, and use the heuristic rules of the corresponding indicators in the analog circuit domain knowledge base K to generate the offspring S2;

[0019] S33, call the automatic simulation module of the software Virtuoso to calculate the target value F of individuals in the S1 or S2 population (x) .

[0020] Preferably, the analog circuit domain knowledge base K includes:

[0021] Gain-bandwidth product rule: If the gain-bandwidth product does not meet the design standard, increase the bias n tube width bias_n_m and the input bias tube width bias_m;

[0022] Common mode rejection ratio rule: If the common mode rejection ratio does not meet the design standard, increase the input tube length in_l and the output tube length o_l;

[0023] Power supply rejection ratio rule: If the power supply rejection ratio does not meet the circuit design standard, reduce the input tube width in_m;

[0024] Slew rate rule: If the slew rate does not meet the design standard, reduce the compensation capacitor C m .

[0025] The beneficial effects of the present invention are: the exploration process of feasible solutions is improved and the quality of the solution finally generated is high. The use of Latin hypercube sampling to generate the initial population can select sample points more evenly and comprehensively in the parameter space, ensuring that the initial population has good diversity and representativeness. Create an analog circuit field knowledge base, judge the evolutionary state of the population, and select different evolutionary operators according to different evolutionary states, effectively improving the efficiency of feasible solution exploration. The population is non-dominated sorted, sorted based on reference points, and individuals are selected as offspring populations in the temporary population using a niche retention strategy, which enhances the ability to handle complex multi-objective problems and avoids premature convergence to a local optimal solution. Set the population target priority, and judge whether the circuit design standard is met in turn according to the population target priority, select the corresponding heuristic rules to generate offspring, and effectively improve the quality of the solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of the steps of the present invention.

[0027] Figure 2 Schematic diagram of the specific process of step S2 of the present invention.

[0028] Figure 3 Schematic diagram of the specific process of step S3 of the present invention.

[0029] Figure 4 4 is a circuit diagram of a two-stage operational amplifier in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to clearly illustrate the technical features of this solution, this solution is described below through specific implementation methods.

[0031] See also Figures 1 to 4 As shown, this embodiment provides an analog circuit intelligent optimization algorithm KLNSGA-III based on domain knowledge, including the following steps: S1, using Latin hypercube sampling to generate an initial population P; S2, calling the automatic simulation module of the software Virtuoso to simulate the initial population P; S3, judging the evolutionary state of the initial population P according to the population evaluation index HV, and selecting to use the knowledge base evolution operator or the conventional crossover operator to generate offspring; S4, merging S1 or S2 with the initial population P to obtain a temporary population P1; S5, performing non-dominated sorting on the temporary population P1 to obtain a non-dominated order F; S6, performing reference point-based sorting on the temporary population P1 that obtains the non-dominated order F to obtain a reference point-based order F1; S7, combining the reference point-based order F1, using the niche retention strategy to select individuals in the temporary population P1 as the offspring population NP; S8, setting the maximum number of iterations, when the number of iterations does not reach the maximum value, looping through steps S3-S7; when the number of iterations reaches the maximum value, the algorithm ends.

[0032] Step S2 calls the automatic simulation module of the software Virtuoso to simulate the initial population. The specific steps are as follows:

[0033] S20, initializing parameters and converting parameter formats: using MATLAB to generate initial design parameters of the circuit, and using an algorithm to convert these parameters into a simulation parameter format suitable for the automatic simulation module of the software Virtuoso;

[0034] S21, using MATLAB to generate corresponding Ocean scripts for parameters applicable to the Virtuoso automatic simulation module;

[0035] S22. Run the Ocean script to implement a single circuit simulation.

[0036] S23. After the simulation is completed, the Ocean script transmits the simulation result data back to the algorithm, and the algorithm analyzes and processes the simulation result data.

[0037] Step S3 determines the evolutionary state of the initial population P according to the population evaluation index HV, and selects to use the knowledge base evolution operator or the conventional crossover operator to generate offspring. The specific steps are as follows:

[0038] S30, creating an analog circuit domain knowledge base K and calculating a population evaluation index HV;

[0039] S31, after every 5 iterations, compare the difference between the performance index of the current population and the previous 5 generations of populations. If the performance index of the current population is greater than 0.5, indicating that the population is in a normal iteration process, then select the conventional crossover and mutation operators to generate the offspring S1, and jump to step S33; if the performance index of the current population is less than or equal to 0.5, indicating that the population is in an evolutionary stagnation state, then continue to execute step S32;

[0040] S32, for individual target f = {f1, f2, ..., f m}, the algorithm performs a multiplication of each target component ζ={ζ1,ζ2,...,ζ m}Preset priority, and determine the target component in the individual according to the priority i , i = 1, 2, ..., whether m meets the circuit design standard:

[0041] If the target component ζ corresponding to a certain priority i , i = 1, 2, ..., m does not meet the standard, then the heuristic rule of the corresponding indicator in the analog circuit domain knowledge base K is used to generate the offspring S2;

[0042] If the target components ζ corresponding to all priorities i , i = 1, 2, ..., all meet the standard, then find the target component with the highest priority in the current individual, and use the heuristic rules of the corresponding indicators in the analog circuit domain knowledge base K to generate the offspring S2;

[0043] S33, call the automatic simulation module of the software Virtuoso to calculate the target value F of individuals in the S1 or S2 population (x) .

[0044] The analog circuit domain knowledge base K includes:

[0045] Gain-bandwidth product rule: If the gain-bandwidth product does not meet the design standard, increase the bias n tube width bias_n_m and the input bias tube width bias_m;

[0046] Common mode rejection ratio rule: If the common mode rejection ratio does not meet the design standard, increase the input tube length in_l and the output tube length o_l;

[0047] Power supply rejection ratio rule: If the power supply rejection ratio does not meet the circuit design standard, reduce the input tube width in_m;

[0048] Slew rate rule: If the slew rate does not meet the design standard, reduce the compensation capacitor C m .

[0049] Next, the optimization of a secondary operational amplifier is taken as an example to illustrate the effectiveness and high efficiency of the algorithm KLNSGA-III proposed in this embodiment. Figure 4 The circuit diagram of the two-stage operational amplifier is shown in Figure 1. The circuit includes four parts: the first-stage input stage amplifier circuit, the second-stage amplifier circuit, the bias circuit and the phase compensation circuit. The input stage amplifier circuit consists of M1~M5. M1 and M2 form a PMOS differential input pair. Compared with the single-ended input, the differential input can effectively suppress the common-mode signal interference; M3 and M4 current mirrors are active loads; M5 provides a constant bias current for the first stage. The output stage amplifier circuit consists of M6 and M7. M6 is a common source amplifier, and M7 provides a constant bias current for it and serves as the second-stage output load. The phase compensation circuit consists of M14 and Cc. M14 works in the linear region and can be equivalent to a resistor. Together with the capacitor Cc, it is connected between the second-stage input and output to form an RC Miller compensation. The bias circuit consists of M8~M13 and RB, which is a common source and common gate Widlar current source. M8 and M9 have the same width-to-length ratio. Compared with M13, M12 has a resistor RB added to the source to form a micro current source and generate current IB. Symmetrical M11 and M12 form a common source and common gate structure to reduce the current error caused by the channel length modulation effect. While providing bias current, it also provides bias voltage for the M14 gate.

[0050] The decision variables and their constraint values ​​of the circuit are shown in Table 2. Table 3 shows the performance index values ​​and constraints of the two-stage operational amplifier circuit. The process library of the experimental circuit is selected using the tsmcN22 process library for simulation.

[0051] Table 2 Decision variables and constraints for the two-stage operational amplifier problem

[0052]

[0053] Table 3 Performance indicators of the secondary operational amplifier and their compliance values

[0054] Performance Indicators Feasible value Gain Bandwidth Product (GBW) <![CDATA[Greater than 100M (1×10 8 )]]> Common Mode Rejection Ratio (CMRR) More than 50 Power Supply Rejection Ratio (PSRR) More than 30 Slew Rate (SR) <![CDATA[Greater than 10M (1×10 7 )]]>

[0055] In order to illustrate the advancedness of the algorithm KLNSGA-III proposed in this embodiment, the present invention selects NSGA-III based on the reference point as the comparison algorithm. The experimental environment is MATLAB 2018a under the Linux system, and the circuit simulation platform is Candence Virtuoso IC618. At the same time, in order to ensure the fairness of this experiment, NSGA-III adopts the evolutionary operator setting recommended by the algorithm, and the population size of KLNAGS-III and NSGA-III, that is, nPop size, is set to 50, and Maxit is set to 50. Each algorithm runs independently 5 times, and takes the maximum value of each target in each run, and calculates the average of the 5 recorded target values. The running results are shown in Table 4.

[0056] Table 4 Comparison of experimental results between KLNSGA-III and NSGA-III

[0057]

[0058] Table 4 shows the maximum value of each performance index of KLNSGA-III and NSGA-III in each optimization of the secondary operational amplifier test and the average value of the maximum value of the five optimization results of each performance index. It can be seen that both algorithms can meet the design standard of the circuit in the final optimization, but by comparing the optimization results of KLNSGA-III and NSGA-III, it can be seen that better performance indicators can be obtained under the same number of evaluations through analog circuit knowledge, which proves that the method proposed in the present invention can quickly and effectively optimize analog circuits.

[0059] Technical features not described in the present invention can be achieved through or by adopting existing technologies and will not be described in detail here. Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. An intelligent optimization algorithm for analog circuits based on domain knowledge, characterized in that: The following steps are involved: S1, use Latin hypercube sampling to generate the initial population P; S2. Call the automatic simulation module of the software Virtuoso to simulate the initial population P; S3. Determine the evolutionary state of the initial population P according to the population evaluation index HV, and choose to use the knowledge base evolution operator or the conventional crossover operator to generate the offspring population; S4. Merge the offspring population S1 or S2 with the initial population P to obtain a temporary population P1; S5. Perform non-dominated sorting on the temporary population P1 to obtain a non-dominated order F; S6. Perform reference point-based sorting on the temporary population P1 that has obtained the non-dominated order F to obtain a reference point-based order F1; S7. Combined with the reference point-based order F1, use the niche retention strategy to select individuals from the temporary population P1 as the offspring population NP; S8. Set the maximum number of iterations. When the number of iterations does not reach the maximum value, loop through steps S3-S7; when the number of iterations reaches the maximum value, the algorithm ends.

2. The analog circuit intelligent optimization algorithm based on domain knowledge according to claim 1 is characterized in that: The step S2 calls the automatic simulation module of the software Virtuoso to simulate the initial population P. The specific steps are as follows: S20, initializing parameters and converting parameter formats: using MATLAB to generate initial design parameters of the circuit, and using an algorithm to convert these parameters into a simulation parameter format suitable for the automatic simulation module of the software Virtuoso; S21, using MATLAB to generate corresponding 0cean scripts for parameters applicable to the Virtuoso automatic simulation module; S22. Run the Ocean script to implement a single circuit simulation. S23. After the simulation is completed, the Ocean script transmits the simulation result data back to the algorithm, and the algorithm analyzes and processes the simulation result data.

3. The analog circuit intelligent optimization algorithm based on domain knowledge according to claim 1 is characterized in that: The step S3 determines the evolutionary state of the initial population P according to the population evaluation index HV, and selects to use the knowledge base evolution operator or the conventional crossover operator to generate offspring. The specific steps are as follows: S30, creating an analog circuit domain knowledge base K and calculating a population evaluation index HV; S31, after every 5 iterations, compare the difference between the performance index of the current population and the previous 5 generations of populations. If the performance index of the current population is greater than 0.5, select the conventional crossover and mutation operators to generate the offspring S1, and jump to step S33; if the performance index of the current population is less than or equal to 0.5, continue to execute step S32; S32, for individual target f = {f1, f2, ..., f m }, the algorithm performs a multiplication of each target component ζ={ζ1,ζ2,...,ζ m }Preset priority, and determine the target component in the individual according to the priority i , i = 1, 2, ..., whether m meets the circuit design standard: If the target component ζ corresponding to a certain priority i , i = 1, 2, ..., m does not meet the standard, then the heuristic rules of the corresponding indicators in the analog circuit domain knowledge base K are used to generate a new individual S2; If the target components ζ corresponding to all priorities i , i = 1, 2, ..., all meet the criteria, then find the target component with the highest priority in the current individual, and use the heuristic rules of the corresponding indicators in the analog circuit domain knowledge base K to generate a new individual S2; S33, call the automatic simulation module of the software Virtuoso to calculate the target value F of individuals in the generation S1 or S2 population (x) .

4. The analog circuit intelligent optimization algorithm based on domain knowledge according to claim 3 is characterized in that: The analog circuit domain knowledge base K includes: Gain-bandwidth product rule: If the gain-bandwidth product does not meet the design standard, increase the bias n tube width bias_n_m and the input bias tube width bias_m; Common mode rejection ratio rule: If the common mode rejection ratio does not meet the design standard, increase the input tube length in_l and the output tube length o_l; Power supply rejection ratio rule: If the power supply rejection ratio does not meet the circuit design standard, reduce the input tube width in_m; Slew rate rule: If the slew rate does not meet the design standard, reduce the compensation capacitor C m .

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