Network-on-chip AI reasoning system, method and equipment based on collaborative approximation strategy

Abstract

The invention discloses a network-on-chip AI inference system, method and device based on a collaborative approximation strategy, and belongs to the technical field of network-on-chip communication, and the key points of the technical scheme are that the system comprises at least one first approximation processing core and at least one second approximation processing core; the first approximate processing core is used for performing approximate calculation on the currently distributed calculation task unit to obtain an approximate calculation result and generate an original data packet, performing bit cutting processing on the original data packet according to an algorithm error of the approximate calculation and the non-approximate calculation to obtain an approximate data packet, and finally performing routing processing on the approximate data packet through a corresponding routing unit. Sending the data packet to a routing unit corresponding to the processing core receiving the approximate data packet; the second approximate processing core is used for receiving an approximate data packet and performing data recovery on the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet, and the collaborative approximation strategy is adopted, so that the improvement of energy efficiency is ensured to the greatest extent under extremely low inference precision loss.

Description

Technical Field

[0001] The present invention relates to the field of network-on-chip communication technology, and more specifically to a network-on-chip AI reasoning system, method and device based on a collaborative approximation strategy. Background Art

[0002] The rapid development of artificial intelligence has brought about problems such as large data set processing and complex computing tasks. Traditional precise computing methods often face huge challenges of computational complexity and time delay. At the same time, the increasingly invalid limit of Moore's Law also makes it difficult to design precise computing circuits. In order to meet these challenges, approximate computing has begun to attract widespread attention as an emerging computing paradigm. The core idea of ​​approximate computing is to balance the relationship between computing accuracy, computing speed, and power consumption and area in the computing process.

[0003] The on-chip network is an architecture that applies the communication measures of the macro network to the chip. Each IP core is an independent unit. The IP core is connected to a specific routing unit through a network interface, thereby converting the communication between IP cores into communication between routing units. However, in communication-intensive applications, the multi-core system will inevitably encounter congestion, resulting in unsatisfactory indicators such as latency and power consumption. At this time, the approximation strategy is introduced. Under the condition of acceptable quality loss, by sacrificing a certain degree of accuracy, approximation is introduced in the data transmission and processing process, thereby improving indicators such as power consumption and latency.

[0004] For example, the Chinese invention patent with authorization announcement number CN109547263B provides an on-chip network optimization method based on approximate computing. This method can optimize the performance of the on-chip network by maximizing the use of error tolerance in the application without violating the user's requirements for output quality.

[0005] However, approximate calculations sacrifice accuracy to a certain extent in exchange for improved performance, which may result in an unacceptable decrease in accuracy, so the existing technology has shortcomings. Summary of the invention

[0006] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an on-chip network AI reasoning system, method and device based on a collaborative approximation strategy, which integrates three key components: an approximate processing core, an approximate control strategy analysis unit and a data recovery unit, so as to achieve a balance between high efficiency and high precision.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] The present invention provides an on-chip network AI reasoning method based on a collaborative approximation strategy, wherein the on-chip network includes a plurality of approximate processing cores that can communicate with each other, and the on-chip network AI reasoning method is applied to the processing core that currently sends data, and the on-chip network AI reasoning method includes:

[0009] Perform approximate calculation on the currently assigned computing task unit, obtain the approximate calculation result and generate the original data packet, wherein the computing task unit is the smallest computing unit constituting the AI ​​reasoning task;

[0010] According to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet;

[0011] The approximate data packet is sent to the routing unit corresponding to the receiving data processing core through the corresponding routing unit, so that the processing core currently receiving the data performs data recovery according to the approximate data packet to obtain a recovered data packet.

[0012] As a further improvement of the present invention, the original data packet is truncated according to the algorithm error between the approximate calculation and the non-approximate calculation, including:

[0013] Calculating a normalized error distance according to the algorithm error, and using the normalized error distance as an approximate calculation reward;

[0014] The original data packet is truncated according to the approximate calculation reward.

[0015] As a further improvement of the present invention, the truncation processing of the original data packet according to the approximate calculation reward includes:

[0016] If the approximate calculation reward is less than 0.5%, the original data packet is truncated to 25% of the original length;

[0017] If the approximate calculation reward is greater than 0.5% and less than 1%, the original data packet is truncated to 50% of the original length;

[0018] If the approximate calculation reward is greater than 1% and less than 2%, the original data packet is truncated to 62.5% of the original length;

[0019] If the approximate calculation reward is greater than 2%, the original data packet is truncated to 75% of the original length.

[0020] The present invention provides an on-chip network AI reasoning method based on a collaborative approximation strategy, wherein the on-chip network includes a plurality of approximate processing cores that can communicate with each other, and the on-chip network AI reasoning method is applied to the approximate processing core that currently receives data, and the on-chip network AI reasoning method includes:

[0021] Receiving an approximate data packet, wherein the approximate data packet is passed through an approximate processing core that sends data, performs approximate calculation on a currently assigned computing task unit to obtain an approximate calculation result and generates an original data packet, and then performs truncation processing on the original data packet according to an algorithm error between the approximate calculation and the non-approximate calculation, wherein the computing task unit is the smallest computing unit constituting an AI reasoning task;

[0022] The approximate data packet is restored according to the header packet information of the approximate data packet to obtain a restored data packet.

[0023] As a further improvement of the present invention, the step of recovering data of the approximate data packet according to the header packet information of the approximate data packet comprises:

[0024] According to the header packet information of the approximate data packet, obtaining the truncated length of the approximate data packet and the overall distribution of the data in the original data packet;

[0025] According to the truncated length of the approximate data packet, restoring the approximate data packet to the length of the original data packet;

[0026] According to the overall distribution of the data in the original data packet, the approximated part in the approximate data packet is supplemented to obtain the restored data packet.

[0027] The on-chip network AI reasoning system based on the collaborative approximation strategy provided by the present invention comprises at least one first approximation processing core and at least one second approximation processing core, each approximation processing core being communicatively connected via a corresponding routing unit;

[0028] The first approximate processing core is used to perform approximate calculation on the currently assigned computing task unit to obtain an approximate calculation result and generate an original data packet, the computing task unit is the smallest computing unit constituting the AI ​​reasoning task, and according to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet, and finally the approximate data packet is sent to the routing unit corresponding to the processing core receiving the approximate data packet through the corresponding routing unit;

[0029] The second approximate processing core is used for receiving an approximate data packet, and performing data recovery on the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet.

[0030] As a further improvement of the present invention, the first approximate processing core and the second approximate processing core include an approximate operator unit and an approximate calculation reward storage area unit,

[0031] The approximate operator unit is used to provide a plurality of configurable approximate operators, wherein the configurable approximate operators include an approximate multiplier, an approximate adder, an approximate activation function and an approximate normalization, which are used to complete the approximate calculation in combination or individually;

[0032] The approximate calculation reward storage area unit is used to store the approximate calculation reward, which is determined according to the algorithm error between the approximate calculation and the non-approximate calculation, and is used to measure the approximate degree of the approximate calculation.

[0033] As a further improvement of the present invention, the first approximate processing core and the second approximate processing core include an approximate control strategy analysis unit, which is used to obtain the approximate computing reward and truncate the original data packet according to the approximate computing reward to obtain the approximate data packet.

[0034] As a further improvement of the present invention, the first approximate processing core and the second approximate processing core include a data recovery unit, and the data recovery unit is used to perform data recovery on the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet.

[0035] The present invention provides a SOC chip, which is applied to the above-mentioned on-chip network AI reasoning system based on collaborative approximation strategy.

[0036] The present invention provides a terminal device, which is applied to the above-mentioned SOC chip.

[0037] The present invention sets up three key components: an approximate processing core, an approximate control strategy analysis unit and a data recovery unit. The approximate processing core reduces the operation complexity by introducing errors within an acceptable range. The approximate control strategy analysis unit further performs approximate processing on the data packet through approximate calculation rewards. The data recovery unit is used to recover the data packet. The three components work together to improve the performance of data transmission while ensuring data accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the overall hardware architecture of the present invention;

[0039] Figure 2 This is a commonly used two-dimensional Mesh architecture diagram for on-chip networks;

[0040] Figure 3 It is a structural schematic diagram of the approximate processing core in the present invention;

[0041] Figure 4 A schematic diagram of data packet transmission in the present invention;

[0042] Figure 5A schematic diagram of data packet recovery in the present invention;

[0043] Figure 6 Schematic diagram of the collaborative approximation strategy in the present invention. DETAILED DESCRIPTION

[0044] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations of the technical solution of the present invention.

[0045] The term "and / or" in the following text is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0046] The on-chip network AI reasoning method based on the collaborative approximation strategy provided in the embodiment of the present application includes a plurality of approximate processing cores that can communicate with each other. When the on-chip network AI reasoning method is applied to the processing core currently sending data, the on-chip network AI reasoning method includes:

[0047] Perform approximate calculation on the currently assigned computing task unit, obtain the approximate calculation result and generate the original data packet, wherein the computing task unit is the smallest computing unit constituting the AI ​​reasoning task;

[0048] According to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet;

[0049] The approximate data packet is sent to the routing unit corresponding to the receiving data processing core through the corresponding routing unit, so that the processing core currently receiving the data performs data recovery according to the approximate data packet to obtain a recovered data packet.

[0050] When the on-chip network AI reasoning method is applied to an approximate processing core currently receiving data, the on-chip network AI reasoning method includes:

[0051] Receiving an approximate data packet, wherein the approximate data packet is passed through an approximate processing core that sends data, performs approximate calculation on a currently assigned computing task unit to obtain an approximate calculation result and generates an original data packet, and then performs truncation processing on the original data packet according to an algorithm error between the approximate calculation and the non-approximate calculation, wherein the computing task unit is the smallest computing unit constituting an AI reasoning task;

[0052] The approximate data packet is restored according to the header packet information of the approximate data packet to obtain a restored data packet.

[0053] Among them, AI reasoning is reasoning through artificial intelligence algorithms such as neural networks. It is the process of inferring, predicting, judging or generating output results through input data based on a trained model. Approximate computing is calculation performed through approximate algorithms, and non-approximate computing is precise calculation without using approximate algorithms.

[0054] The method provided in this embodiment significantly reduces the power consumption and delay of data packet transmission through approximate calculation and truncation processing, and ensures data accuracy through data recovery. That is, while ensuring the accuracy of reasoning, it significantly improves computing efficiency and reduces energy consumption, providing a solution for improving data transmission and processing pressure of on-chip networks.

[0055] Further, according to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated, including:

[0056] Calculate the normalized error distance based on the algorithm error, and use the normalized error distance as the approximate calculation reward;

[0057] The original data packet is truncated according to the approximate calculation reward.

[0058] Specifically, the approximate calculation reward refers to the normalized error distance (Normalized Error Distanc, NMED), which is defined as:

[0059]

[0060] ED=|Exact out -Approx out |

[0061] Among them, Exact out To calculate the result accurately, Approx out is the approximate calculation result, ED is the error distance (ED), which is used to represent the absolute value of the difference between the approximate calculation result and the exact calculation result, MED is the mean error distance (MED), which is used to represent the average error distance of all possible approximate operator combinations, n is the number of circuit inputs, 2 n Indicates all input conditions of the circuit. For example, if there are 3 inputs, there are 2 possible input combinations. 3 =8 kinds, namely: 000, 001, 010, 011, 100, 101, 110 and 111.

[0062] Furthermore, the original data packet is truncated according to the approximate calculation reward as follows: if the approximate calculation reward is less than 0.5%, the original data packet is truncated to 25% of the original length to obtain a first type of approximate data packet; if the approximate calculation reward is greater than 0.5% and less than 1%, the original data packet is truncated to 50% of the original length to obtain a second type of approximate data packet; if the approximate calculation reward is greater than 1% and less than 2%, the original data packet is truncated to 62.5% of the original length to obtain a third type of approximate data packet; if the approximate calculation reward is greater than 2%, the original data packet is truncated to 75% of the original length to obtain a third type of approximate data packet. For example, if the length of the original data packet is 64, after the original data packet is truncated to 25% of the original length, the obtained approximate data packet is 64×25%=16 bits.

[0063] Further, according to the header information of the approximate data packet, data recovery is performed on the approximate data packet, including:

[0064] According to the header information of the approximate data packet, the truncated length of the approximate data packet and the overall distribution of the data in the original data packet are obtained;

[0065] According to the truncated length of the approximate data packet, the approximate data packet is restored to the length of the original data packet;

[0066] According to the overall distribution of data in the original data packet, the approximated part in the approximate data packet is supplemented to obtain a restored data packet.

[0067] Specifically, the data recovery unit first obtains the header packet information of the approximate data packet, analyzes the approximate truncation type of the approximate data packet and the overall data distribution information of the original data packet, the former is used to fill in the format length of the original data packet, and the latter is used to supplement the "0" value data during recovery. Specifically, the mean of the approximate truncated part is calculated through the overall data distribution of the original data packet. The mean reflects the sparsity to a certain extent. By adjusting the number of supplemented "0" during recovery, the accuracy of the original data packet can be approached to a certain extent, thereby achieving the effect of error compensation and correction and balancing the overall accuracy.

[0068] The on-chip network AI reasoning method based on the collaborative approximation strategy provided in the embodiment of the present application improves efficiency through approximate computing, ensures reasoning accuracy through data recovery, and achieves an improvement in overall energy efficiency at the cost of a small loss in reasoning accuracy in AI reasoning applications.

[0069] Further, such as Figure 1As shown, an embodiment of the present application provides an on-chip network AI reasoning system based on a collaborative approximation strategy, which is applied to the above-mentioned on-chip network AI reasoning method based on a collaborative approximation strategy, including: at least one first approximation processing core and at least one second approximation processing core, each approximation processing core is communicatively connected through a corresponding routing unit;

[0070] The first approximate processing core is used to perform approximate calculation on the currently assigned computing task unit to obtain an approximate calculation result and generate an original data packet, the computing task unit is the smallest computing unit constituting the AI ​​reasoning task, and according to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet, and finally the approximate data packet is sent to the routing unit corresponding to the processing core receiving the approximate data packet through the corresponding routing unit;

[0071] The second approximate processing core is used for receiving an approximate data packet, and performing data recovery on the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet.

[0072] The first approximate processing core is an approximate processing core for sending data, and the second approximate processing core is an approximate processing core for receiving data.

[0073] On-chip network is an architecture that applies the communication measures of macro networks to chips, such as Figure 2 As shown, this embodiment provides a common two-dimensional Mesh architecture of an on-chip network, including a proximate processing core (PE), a network interface (NI), and a routing unit (Router). Each proximate processing core can be used to send data or receive data, that is, each proximate processing core can be both a first proximate processing core and a second proximate processing core, and each proximate processing core has a corresponding routing unit. The architecture is based on a specific routing algorithm, connects the proximate processing core to a specific routing unit through a network interface, converts the communication between the proximate processing cores into the communication between the routing units, and greatly improves the communication capability of the many-core system.

[0074] However, many-core systems will inevitably encounter congestion in communication-intensive applications, resulting in unsatisfactory indicators such as latency and power consumption. At this time, approximation strategies can be introduced in the data transmission and processing process at the expense of a certain degree of accuracy, while maintaining an acceptable quality loss, thereby improving indicators such as power consumption and latency.

[0075] Existing approximation strategies include approximate computing and approximate communication. The consumption of computing resources in the AI ​​reasoning process is mainly concentrated in the multiply-accumulate (MAC) operation. Advanced neural networks integrate thousands of MACs, which brings huge energy consumption. However, the powerful error recovery ability of neural networks can introduce approximate computing in the computing process to reduce energy consumption. However, approximate computing will eventually bring a certain loss of accuracy. The purpose of introducing approximate communication is also to effectively reduce the average delay and energy consumption caused by on-chip system communication. Approximation is introduced in the data transmission and processing process, but the characteristics of the data that are usually not considered will also bring further loss of accuracy.

[0076] Approximate computing and approximate communication both aim to improve performance by sacrificing accuracy to a certain extent. However, approximation without collaborative optimization may lead to an unacceptable decrease in accuracy. The on-chip network AI reasoning system based on the collaborative approximation strategy provided in this embodiment compensates for the accuracy loss caused by approximate computing and approximate communication through the coordinated cooperation of three components, greatly improving the overall energy efficiency of the system with extremely low loss of reasoning accuracy.

[0077] Further, such as Figure 3 As shown, the approximate processing core provided by this embodiment includes an approximate operator unit and an approximate computing reward storage area unit and a network interface, wherein the approximate operator unit is used to provide multiple configurable approximate operators, and the configurable approximate operators include approximate multipliers, approximate adders, approximate activation functions and approximate normalizations, which are used to complete approximate calculations in combination or individually; the approximate computing reward storage area unit is used to store approximate computing rewards, which are determined according to the algorithmic error of the approximate calculation and are used to measure the degree of approximation of the approximate calculation.

[0078] Specifically, the approximate processing cores are key components in this AI system. They process other AI reasoning tasks such as neural networks by performing approximate multiplication and accumulation operations and approximate activation operations. The design of the approximate processing core allows an acceptable error range to be introduced during the calculation process, thereby significantly reducing the complexity, power consumption and latency of the operation. The high configurability of the approximate operator unit enables it to adjust the approximate operator used according to the needs of specific applications, enabling the system to find the optimal solution between performance and accuracy.

[0079] In the on-chip network architecture, the approximate processing core is particularly suitable for real-time AI application scenarios that require fast response, such as edge devices and mobile devices. In these scenarios, traditional high-precision calculations may become impractical due to their high energy consumption and long latency. By using approximate computing, the system can achieve lower energy consumption and faster processing speed while maintaining sufficient accuracy.

[0080] In addition, the approximate processing core also includes an approximate computing reward cache unit, which is responsible for inputting the algorithm error of the approximate calculation while configuring the approximate operator in the approximate processing core. The algorithm error is described by the approximate computing reward. The configurable approximate operators provided by the approximate operator unit include four types: approximate multiplier, approximate adder, approximate activation function and approximate normalization. The approximate operator unit allows users to select appropriate approximate operators through a specific application programming interface (Application Programming Interface, API). The system will compile and load the corresponding hardware logic in real time according to the user's selection to complete the calculation task. For each approximate operator, compared with non-approximate calculations, they have their own algorithm error. Their algorithm error will be measured by approximate computing rewards and stored in the approximate computing reward storage unit to record the approximate degree of approximate calculations and provide data basis for subsequent joint optimization with approximate communication.

[0081] The approximate processing core provided in this embodiment optimizes the energy efficiency and performance of the AI ​​system by introducing algorithm errors. At the same time, in order to enable it to adapt to the development and changes of future AI algorithms, the approximate processing core has great flexibility and can meet different computing needs through different approximate operators.

[0082] Furthermore, the approximate combing core provided in this embodiment includes an approximate collaborative communication module, the approximate collaborative communication module includes an approximate control strategy analysis unit, the approximate control strategy analysis unit is used to obtain approximate computing rewards, and truncate the original data packet according to the approximate computing rewards to obtain an approximate data packet.

[0083] Specifically, the approximate cooperative communication module is set in the network interface of each approximate processing core. For the approximate result calculated by a certain approximate processing core, the approximate control strategy analysis unit in the approximate processing core will receive the approximate calculation reward and original data packet transmitted by the approximate processing core, and the approximate control strategy analysis unit will analyze the approximate data information of the original data packet. Figure 4 As shown, specifically, in AI reasoning, due to the sparsity of data, the input data will generate a large amount of "0" value data. By counting the distribution of 0 value data in the statistical data packet, the approximate information is stored in the header packet (head flit) of the original data packet, and the approximate calculation reward of the approximate calculation is obtained from the approximate reward storage area unit. According to the different approximate calculation rewards, the original data packet will be subjected to 4 types of approximate processing of different degrees, while retaining the head packet of the storage data distribution, so as to obtain different types of approximate data packets, and select different transmission methods according to the type of approximate data packet, wherein the approximate processing is to perform truncation processing on the data packet.

[0084] Different transmission modes are selected for different types of approximate data packets, that is, when the approximate calculation error is high (when the approximate calculation reward is large), the transmission type mode with a small approximate communication error is selected, and when the approximate calculation error is low (when the approximate calculation reward is small), the transmission type mode with a large approximate communication error is selected. In this way, both the approximate calculation error and the approximate communication error are considered at the same time, so that the system can achieve a balance between energy efficiency and accuracy.

[0085] The approximate cooperative communication module provided in this embodiment adopts an approximate cooperative communication algorithm, which is an advanced adaptive communication mechanism. The core of the algorithm lies in its adaptability and flexibility. It can intelligently determine the best transmission method for data packets according to the current network status and the characteristics of the computing task. Specifically, the data transmission strategy is dynamically adjusted according to the computational approximation situation inside the approximate processing core, thereby optimizing the data transmission method between nodes. In addition, the approximate cooperative communication algorithm also uses a truncation method to measure the approximation degree of data. Different lengths of truncation represent different types of approximate processing. By adjusting the length of the truncation, the approximation rate of the system can be further fine-tuned. This method not only helps to alleviate communication pressure, but also reduces the accumulation of errors during the communication process, thereby improving the overall performance of the system. Therefore, the approximate cooperative communication module provided in this embodiment effectively balances the relationship between communication efficiency and computational accuracy through its adaptive communication mechanism and flexible data processing strategy.

[0086] Furthermore, the approximate processing core provided in this embodiment includes an approximate data recovery module, the approximate data recovery module includes a data recovery unit, and the data recovery unit is used to recover data of the approximate data packet according to the header packet information of the approximate data packet to obtain a recovered data packet.

[0087] Specifically, Figure 5 As shown, after receiving the approximate data packet, the data recovery unit in the approximate data recovery module determines the approximation of the system through the approximate information in the approximate data packet and the algorithm error information of the approximate operator inside the approximate processing core, and then recovers the approximate data packet and supplements it to the format of the original data packet to complete the compensation of the approximate error.

[0088] The approximate data recovery module provided in this embodiment is located in the network interface of each approximate processing core in the on-chip network architecture. Figure 6As shown, it works closely with the approximate computing module and the approximate collaborative communication module. When an approximate data packet is received, the approximate data recovery module in the network interface will simultaneously receive the algorithm error of the approximate computing and the transmission strategy of the approximate data packet. The data recovery unit will recover the approximate data through the built-in data recovery mechanism based on the coordinated optimization of the information of the two, and recover the errors caused by the approximate computing and approximate communication to a certain extent to compensate for the errors caused by the approximation, avoid the decrease in accuracy caused by the excessive approximation rate of the system, and use the built-in data recovery mechanism to restore the content of each data packet in a targeted manner before the approximate data packet arrives at its target location, so as to correct the errors caused by the approximate computing and ensure the quality of the output results.

[0089] Furthermore, an embodiment of the present application provides a SOC chip, which is applied to the above-mentioned on-chip network AI reasoning system based on the collaborative approximation strategy.

[0090] Furthermore, an embodiment of the present application provides a terminal device, which is applied to the above-mentioned SOC chip.

[0091] The on-chip network AI reasoning system, method and device based on the collaborative approximation strategy provided in the embodiments of the present application can improve the data transmission and processing pressure of the on-chip network while ensuring the accuracy of reasoning through the application of the collaborative approximation strategy, and obtain the overall energy efficiency improvement at the cost of a small loss of reasoning accuracy in AI reasoning applications, thereby promoting the wider popularization of AI technology in practical applications.

[0092] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0094] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0095] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0096] The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A network-on-chip AI reasoning method based on a collaborative approximation strategy, wherein the network-on-chip includes a plurality of approximate processing cores that can communicate with each other, and the network-on-chip AI reasoning method is applied to the processing core that currently sends data, characterized in that: The on-chip network AI reasoning method includes: Perform approximate calculation on the currently assigned computing task unit, obtain the approximate calculation result and generate the original data packet, wherein the computing task unit is the smallest computing unit constituting the AI ​​reasoning task; According to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet; The approximate data packet is sent to the routing unit corresponding to the receiving data processing core through the corresponding routing unit, so that the processing core currently receiving the data performs data recovery according to the approximate data packet to obtain a recovered data packet.

2. The on-chip network AI reasoning method based on collaborative approximation strategy according to claim 1 is characterized in that: According to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated, including: Calculating a normalized error distance according to the algorithm error, and using the normalized error distance as an approximate calculation reward; The original data packet is truncated according to the approximate calculation reward.

3. The on-chip network AI reasoning method based on collaborative approximation strategy according to claim 2 is characterized in that: The truncation of the original data packet according to the approximate calculation reward includes: If the approximate calculation reward is less than 0.5%, the original data packet is truncated to 25% of the original length; If the approximate calculation reward is greater than 0.5% and less than 1%, the original data packet is truncated to 50% of the original length; If the approximate calculation reward is greater than 1% and less than 2%, the original data packet is truncated to 62.5% of the original length; If the approximate calculation reward is greater than 2%, the original data packet is truncated to 75% of the original length.

4. A network-on-chip AI reasoning method based on a collaborative approximation strategy, wherein the network-on-chip includes a plurality of approximate processing cores that can communicate with each other, and the network-on-chip AI reasoning method is applied to the approximate processing core currently receiving data, characterized in that: The on-chip network AI reasoning method includes: Receiving an approximate data packet, wherein the approximate data packet is passed through an approximate processing core that sends data, performs approximate calculation on a currently assigned computing task unit to obtain an approximate calculation result and generates an original data packet, and then performs truncation processing on the original data packet according to an algorithm error between the approximate calculation and the non-approximate calculation, wherein the computing task unit is the smallest computing unit constituting an AI reasoning task; The approximate data packet is restored according to the header packet information of the approximate data packet to obtain a restored data packet.

5. The on-chip network AI reasoning method based on collaborative approximation strategy according to claim 4 is characterized in that: The step of recovering data of the approximate data packet according to the header packet information of the approximate data packet comprises: According to the header packet information of the approximate data packet, obtaining the truncated length of the approximate data packet and the overall distribution of the data in the original data packet; According to the truncated length of the approximate data packet, restoring the approximate data packet to the length of the original data packet; According to the overall distribution of the data in the original data packet, the approximated part in the approximate data packet is supplemented to obtain the restored data packet.

6. On-chip network AI reasoning system based on collaborative approximation strategy, characterized by: The system includes at least one first approximate processing core and at least one second approximate processing core, each approximate processing core being communicatively connected via a corresponding routing unit; The first approximate processing core is used to perform approximate calculation on the currently assigned computing task unit to obtain an approximate calculation result and generate an original data packet, the computing task unit is the smallest computing unit constituting the AI ​​reasoning task, and according to the algorithm error between the approximate calculation and the non-approximate calculation, the original data packet is truncated to obtain an approximate data packet, and finally the approximate data packet is sent to the routing unit corresponding to the processing core receiving the approximate data packet through the corresponding routing unit; The second approximate processing core is used for receiving an approximate data packet, and performing data recovery on the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet.

7. The on-chip network AI reasoning system based on collaborative approximation strategy according to claim 6, characterized in that: The first approximate processing core and the second approximate processing core include an approximate operator unit and an approximate calculation reward storage area unit, The approximate operator unit is used to provide a plurality of configurable approximate operators, wherein the configurable approximate operators include an approximate multiplier, an approximate adder, an approximate activation function and an approximate normalization, which are used to complete the approximate calculation in combination or individually; The approximate calculation reward storage area unit is used to store the approximate calculation reward, which is determined according to the algorithm error between the approximate calculation and the non-approximate calculation, and is used to measure the approximate degree of the approximate calculation.

8. The on-chip network AI reasoning system based on collaborative approximation strategy according to claim 6, characterized in that: The first approximate processing core and the second approximate processing core include an approximate control strategy analysis unit, which is used to obtain the approximate computing reward and perform truncation processing on the original data packet according to the approximate computing reward to obtain the approximate data packet.

9. The on-chip network AI reasoning system based on collaborative approximation strategy according to claim 6, characterized in that: The first approximate processing core and the second approximate processing core include a data recovery unit, and the data recovery unit is used to recover data of the approximate data packet according to header packet information of the approximate data packet to obtain a recovered data packet.

10. A SOC chip, characterized in that: Applied to the on-chip network AI reasoning system based on the collaborative approximation strategy as described in any one of claims 6-9.

11. A terminal device, characterized in that: Applicable to a SOC chip as claimed in claim 10.

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