Driving chip, display panel and driving method of display panel

Abstract

The embodiment of the invention discloses a driving chip, a display panel and a driving method of the display panel, the driving chip comprises a rapid discharge circuit, the rapid discharge circuit comprises an input port for accessing a rapid discharge signal, a judgment sub-circuit, a buffer sub-circuit and a power-off sub-circuit, the judgment sub-circuit responds to a falling edge of the rapid discharge signal, and the buffer sub-circuit is connected to the input port. Generating a judgment signal within a preset time according to the target signal; the buffer sub-circuit responds to the judgment signal, generates a control signal and sends the control signal to the power-off sub-circuit; the power-off circuit responds to the control signal to control the driving chip to execute or not execute the power-off operation. The preset time is set as a buffer stage, and a judgment condition is added in the buffer stage to further determine whether the signal is an effective rapid discharge signal, so as to determine whether to execute a power-off operation.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving chip, a display panel, and a driving method for the display panel. Background Art

[0002] The total capacitance of the In-Plane Switching Panel (IPS Panel) is relatively stable and has good stability when driven, so it is widely used in the current display panel field. However, the IPS Panel discharges slowly when the driver chip is powered off, which can cause flickering or screen noise. By setting a fast discharge pin (XON pin) on the driver chip, the timing controller outputs a fast discharge signal (XON signal) to the driver chip, which can short-circuit the output signals of all driving circuits with the common voltage signal at the moment the driver chip is powered off, thereby achieving rapid discharge of the panel. However, when there is other interference on the XON pin, misoperation is prone to occur. Summary of the invention

[0003] The embodiments of the present application provide a driving chip, a display panel and a method for driving the display panel, so as to at least solve the problem that erroneous operation is likely to occur when there is other interference on the XON pin.

[0004] In a first aspect, an embodiment of the present application provides a driver chip, comprising a fast discharge circuit, wherein the fast discharge circuit comprises: an access port configured to access a fast discharge signal; wherein the fast discharge signal is used to indicate that the driver chip is powered off; a sensing subcircuit connected to the access port and a power supply voltage, wherein the sensing subcircuit is configured to sense a falling edge of the fast discharge signal; a buffer subcircuit connected to the sensing subcircuit, a judgment subcircuit and a power-off electronic circuit, wherein the buffer subcircuit is configured to generate a control signal and send it to the power-off electronic circuit in response to a judgment signal output by the judgment subcircuit within a preset time after the sensing subcircuit senses the falling edge of the fast discharge signal; the judgment subcircuit is connected to the buffer subcircuit and configured to generate the judgment signal according to the state of the target signal within the preset time and send it to the buffer subcircuit; and the power-off electronic circuit is connected to the buffer subcircuit and configured to control the driver chip to perform or not perform a power-off operation in response to the control signal.

[0005] In some embodiments, the judgment subcircuit is further configured to: generate a first judgment signal in response to a rising edge of the target signal within the preset time and send the first judgment signal to the buffer subcircuit.

[0006] In some embodiments, the judgment subcircuit is further configured to: generate the first judgment signal and send it to the buffer subcircuit in response to the rising edge of the fast discharge signal within the preset time; or generate the first judgment signal and send it to the buffer subcircuit in response to the rising edge of the scan drive start pulse signal within the preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0007] In some embodiments, the buffer subcircuit is further configured to: generate a first control signal in response to the first judgment signal within the preset time, and send it to the power-off electronic circuit; the power-off electronic circuit is further configured to: control the driver chip not to perform a power-off operation in response to the first control signal.

[0008] In some embodiments, the judgment subcircuit is further configured to: within the preset time, in response to a continuous low level state of the target signal, generate a second judgment signal and send it to the buffer subcircuit.

[0009] In some embodiments, the judgment subcircuit is further configured to: generate the second judgment signal and send it to the buffer subcircuit in response to the continuous low level state of the fast discharge signal within the preset time; or generate the second judgment signal and send it to the buffer subcircuit in response to the continuous low level state of the scan drive start pulse signal within the preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0010] In some embodiments, the buffer subcircuit is further configured to: generate a second control signal in response to the second judgment signal within the preset time, and send it to the power-off electronic circuit; the power-off electronic circuit is further configured to: control the driver chip to perform a power-off operation in response to the second control signal.

[0011] In some embodiments, the driver chip is suitable for CSPI transmission protocol.

[0012] In a second aspect, an embodiment of the present application further provides a display panel, comprising the driving chip described in any one of the above embodiments.

[0013] In the third aspect, an embodiment of the present application also provides a method for driving a display panel, which is applied to a driving chip, wherein the driving chip includes a fast discharge circuit, and the fast discharge circuit includes an input port connected to a fast discharge signal, a judgment subcircuit, a buffer subcircuit and a power-off electronic circuit. The method includes: the judgment subcircuit responds to the falling edge of the fast discharge signal, and generates a judgment signal according to a target signal within a preset time; the buffer subcircuit responds to the judgment signal, generates a control signal and sends it to the power-off electronic circuit; and the power-off electronic circuit controls the driving chip to perform or not perform a power-off operation in response to the control signal.

[0014] In some embodiments, the judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: within the preset time, in response to the rising edge of the target signal, generating a first judgment signal and sending it to the buffer subcircuit.

[0015] In some embodiments, within the preset time, in response to the rising edge of the target signal, a first judgment signal is generated and sent to the buffer sub-circuit, including: within the preset time, in response to the rising edge of the fast discharge signal, the first judgment signal is generated and sent to the buffer sub-circuit; or within the preset time, in response to the rising edge of the scan drive start pulse signal, the first judgment signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0016] In some embodiments, the method further includes: within the preset time, the buffer subcircuit generates a first control signal in response to the first judgment signal and sends it to the power-off electronic circuit; the power-off electronic circuit controls the driver chip not to perform a power-off operation in response to the first control signal.

[0017] In some embodiments, the judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: within the preset time, in response to the continuous low level state of the target signal, generating a second judgment signal and sending it to the buffer subcircuit.

[0018] In some embodiments, within the preset time, in response to the continuous low level state of the target signal, a second judgment signal is generated and sent to the buffer sub-circuit, including: within the preset time, in response to the continuous low level state of the fast discharge signal, the second judgment signal is generated and sent to the buffer sub-circuit; or within the preset time, in response to the continuous low level state of the scan drive start pulse signal, the second judgment signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0019] In some embodiments, the method further includes: within the preset time, the buffer subcircuit generates a second control signal in response to the second judgment signal and sends it to the power-off electronic circuit; the power-off electronic circuit controls the driver chip to perform a power-off operation in response to the second control signal.

[0020] In some embodiments, the driving method is applicable to the CSPI transmission protocol.

[0021] The beneficial effects provided by the embodiments of the present application include at least:

[0022] The embodiment of the present application provides a driving chip, a display panel and a driving method of the display panel, wherein the driving chip includes a fast discharge circuit, the fast discharge circuit includes an input port connected to a fast discharge signal, a judgment subcircuit, a buffer subcircuit and a power-off electronic circuit, the judgment subcircuit responds to the falling edge of the fast discharge signal, and generates a judgment signal according to the target signal within a preset time; the buffer subcircuit responds to the judgment signal, generates a control signal and sends it to the power-off electronic circuit; the power-off electronic circuit responds to the control signal to control the driving chip to perform or not perform a power-off operation. By setting a preset time as a buffer stage, adding a judgment condition in the buffer stage to further determine whether it is a valid fast discharge signal, and then determining whether to perform a power-off operation, at least the problem of erroneous operation that is prone to occur when there is other interference on the XON pin can be solved, and the accuracy of performing a fast power-off according to the XON signal is effectively improved.

[0023] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a display panel provided in an optional embodiment of the present application;

[0025] Figure 2 is a signal timing diagram provided in an optional embodiment of the present application;

[0026] Figure 3is a structural schematic diagram of a fast discharge circuit provided in an optional embodiment of the present application;

[0027] Figure 4 is an iSTB signal timing diagram provided in an optional embodiment of the present application;

[0028] Figure 5 It is another iSTB signal timing diagram provided in an optional embodiment of the present application;

[0029] Figure 6 is a timing diagram of an XON signal provided in an optional embodiment of the present application;

[0030] Figure 7 is another XON signal timing diagram provided in an optional embodiment of the present application;

[0031] Figure 8 It is a schematic flow chart of a method for driving a display panel provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0036] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the embodiments of the present application.

[0037] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0038] The use of "configured to" in the embodiments of the present application is meant to be open and inclusive language, which does not exclude devices adapted for or configured to perform additional tasks or steps.

[0039] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0040] Reference Figure 1As shown, an embodiment of the present application provides a display panel 1000, which can be integrated in a display device, which can be a TV, a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto. A display panel refers to a component for displaying an image, which may include many pixel units, each of which may emit light, display a color, or reflect light to produce an image. The type of display panel can be set according to actual conditions. For example, the display panel may be a liquid crystal panel (LCD), an organic light-emitting diode (OLED) panel, a mini light-emitting diode display (Mini-LED) panel, or a micro-light-emitting diode display (Micro-LED) panel, and the embodiments of the present application are not limited thereto. The pixel units included in the display panel may exist in the form of rows and / or columns.

[0041] The display panel 1000 includes an effective display area AA and a peripheral area NA located around the effective display area AA. A circuit board 1100 is provided in the peripheral area of ​​the display panel 1000 for providing a clock signal to the circuit inside the display panel 1000. The above-mentioned effective display area AA includes a plurality of sub-pixels 1500. For the convenience of explanation, the above-mentioned plurality of sub-pixels 1500 in the present application are described as an example of a matrix arrangement. In this case, the sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and the sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light-emitting control signal line EM, and a column of sub-pixels can be connected to a data line DL, and the X direction intersects the Y direction perpendicularly.

[0042] Each sub-pixel 1500 may include a pixel driving circuit 1510 and a light emitting device 1520. The light emitting device 1520 may emit at least three primary colors, for example, red (Red, R), green (Green, G) and blue (Blue, B).

[0043] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300 and a light emitting control circuit 1400 arranged in the NA region. The gate driving circuit 1200 includes a plurality of cascaded gate driving sub-circuits 1210, and the light emitting control circuit 1400 includes a plurality of cascaded light emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 via at least one DL, each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 via at least one GL, and each row of sub-pixels is connected to at least one light emitting control sub-circuit 1410 via at least one EM. It should be noted that, according to different circuit application scenarios, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits via two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light emitting control sub-circuits via two or three or more EMs. Figure 1 Only one signal line is used as an example for illustrative description, which is not intended to limit the scope of the present application.

[0044] In some embodiments, the light emitting device 1520 may be an organic light emitting diode, and its luminous efficiency is positively correlated with the magnitude of the current or the current density flowing through the light emitting device 1520. That is, when the magnitude of the current flowing through the light emitting device 1520 is small, the luminous efficiency of the light emitting device 1520 is low, and when the magnitude of the current flowing through the light emitting device 1520 is large, the luminous efficiency of the light emitting device 1520 is high. In order to improve the luminous efficiency of the light emitting device 1520 when displaying a low gray scale, the luminous time of the light emitting device 1520 may be modulated by the light emitting control signal EM, that is, pulse width modulation (PWM for short), so as to change the luminous duty ratio of the light emitting device 1520 within one frame, thereby shortening the luminous time of the light emitting device 1520. By shortening the luminous time of the light emitting device 1520 and increasing the magnitude of the current flowing through the light emitting device 1520 during the luminous process of the light emitting device 1520, the luminous efficiency of the light emitting device 1520 may be improved.

[0045] The pixel driving circuit 1510, the gate driving circuit 1200 and the data driving circuit 1300 in the embodiment of the present application can be implemented using any circuit in the art that can realize the corresponding functions, and no further specific description is given. It should be noted that the above-mentioned gate driving circuit 1200 and the data driving circuit 1300 can be integrated on a driving chip.

[0046] Since the IPS Panel discharges slowly when the power is off, there will be visible flicker or screen noise. In order to solve this problem, an XON access pin is set on the driver chip to receive the XON signal. Figure 2As shown, in the stage where there is no data signal input, all data output signals Y1 to Yn are connected to the common voltage signal Vcom. Under normal working conditions, XON is at a high potential and the Yn signal changes periodically. When it is necessary to power off and not receive data input, the XON signal has a falling edge, and all data output signals are shorted to Vcom and connected to a preset low potential (usually VSS or GND). Under normal circumstances or when conducting experiments, when noise or interference occurs on the XON pin, the XON pin will recognize it as a falling edge, thereby causing malfunction. For example, the phenomenon that the driver chip suddenly loses power during electrostatic protection (ESD) evaluation, or the phenomenon that the driver chip suddenly loses power during other evaluation tests. The malfunction is caused by the XON pin recognizing it as a falling edge when the GND of the driver chip jitters or external signal noise occurs.

[0047] In order to solve the above problems, an embodiment of the present application provides a driving chip, including a fast discharge circuit 100. Figure 3 As shown, the fast discharge circuit 100 includes an access port 110 , a sensing subcircuit 120 , a buffer subcircuit 130 , a determination subcircuit 140 and a cut-off subcircuit 150 .

[0048] Among them, the access port 110 is configured to access the XON signal; the sensing subcircuit 120 is connected to the access port 110 and the power supply voltage VDD, and the sensing subcircuit 120 is configured to sense the falling edge of the fast discharge signal; the buffer subcircuit 130 is connected to the sensing subcircuit 120, the judgment subcircuit 140 and the power-off electronic circuit 150, and the buffer subcircuit 130 is configured to respond to the judgment signal output by the judgment subcircuit 140 within a preset time T after the sensing subcircuit 120 senses the falling edge of the fast discharge signal, and generate a control signal to send to the power-off electronic circuit 150; the judgment subcircuit 140 is connected to the buffer subcircuit 130, and is configured to generate a judgment signal according to the state of the target signal within the preset time, and send it to the buffer subcircuit 130; and the power-off electronic circuit 150, connected to the buffer subcircuit 130, is configured to control the driver chip to perform or not perform the power-off operation in response to the control signal.

[0049] The judgment subcircuit responds to the falling edge of the fast discharge signal and generates a judgment signal according to the target signal within a preset time; the buffer subcircuit responds to the judgment signal and generates a control signal to send to the power-off electronic circuit; the power-off electronic circuit responds to the control signal to control the driver chip to perform or not perform the power-off operation. By setting the preset time as the buffer stage, adding a judgment condition in the buffer stage to further determine whether it is a valid fast discharge signal, and then determining whether to perform the power-off operation, at least the problem of erroneous operation that is prone to occur when there is other interference on the XON pin can be solved, and the accuracy of performing fast power-off according to the XON signal is effectively improved.

[0050] In some embodiments, the judgment subcircuit 140 is further configured to: generate a first judgment signal in response to a rising edge of the target signal within a preset time and send the first judgment signal to the buffer subcircuit 130. The preset time here can be a time greater than 1 frame, for example, 1 frame, 2 frames, 3 frames, or 1.5 frames, 2.5 frames, which is not limited in the embodiments of the present application.

[0051] In some embodiments, the buffer subcircuit 130 is also configured to: obtain a first judgment signal output by the judgment subcircuit 140 within a preset buffering time; generate a first control signal in response to the first judgment signal, and send it to the power-off electronic circuit 150; the power-off electronic circuit 150 is also configured to: control the driving chip not to perform a power-off operation in response to the first control signal.

[0052] The target signal can be a scan driver start pulse signal (Scan Driver Start Pulse, referred to as STB or STV), which is used to indicate the start of transmission of a frame of image signal. Among them, the STB signal is generally used in the new high-speed point-to-point interface transmission (China Standard Point-to-Point Interface, referred to as CSPI) protocol, indicating the start of each frame signal transmission. iSTB (Internal STB function) is an internal signal of the CSPI driver chip, which is used to inform the CSPI protocol of the start of a frame. The target signal can also be an XON signal, which will be described in detail in subsequent embodiments.

[0053] In some embodiments, the judgment subcircuit 140 is further configured to: generate a first judgment signal and send it to the buffer subcircuit 130 in response to the rising edge of the fast discharge signal within a preset time; or generate a first judgment signal and send it to the buffer subcircuit in response to the rising edge of the scan drive start pulse signal within a preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0054] Reference Figure 4 As shown, when the target signal is the iSTB signal, within the preset buffer time, it is determined whether a rising edge occurs in the iSTB signal, that is, whether a new frame of signal is input. If a rising edge occurs, the judgment subcircuit 140 generates a first judgment signal and sends it to the buffer subcircuit 130. The buffer subcircuit 130 resets the XON signal and restores the high potential, so that the power-off electronic circuit does not perform the power-off operation.

[0055] Reference Figure 6As shown, when the target signal is an XON signal, within the preset buffer time, it is determined whether a rising edge occurs in the XON signal, that is, whether a new frame of signal is input. If a rising edge occurs, the judgment subcircuit 140 generates a first judgment signal and sends it to the buffer subcircuit 130. The buffer subcircuit 130 resets the XON signal and restores the high potential, so that the power-off electronic circuit does not perform the power-off operation.

[0056] In some embodiments, the judgment subcircuit 140 is further configured to: generate a second judgment signal and send it to the buffer subcircuit in response to a continuous low level state of the fast discharge signal within a preset time; or generate a second judgment signal and send it to the buffer subcircuit in response to a continuous low level state of the scan drive start pulse signal within a preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0057] When the target signal is the iSTB signal, within the preset buffer time, it is determined whether a rising edge appears in the iSTB signal, that is, whether a new frame signal is input. If no rising edge appears, it is maintained in a low level state. The judgment subcircuit 140 generates a second judgment signal and sends it to the buffer subcircuit 130. The buffer subcircuit 130 sends a second control signal to enable the power-off electronic circuit to perform a power-off operation.

[0058] When the target signal is an XON signal, within the preset buffer time, it is determined whether a rising edge appears in the XON signal, that is, whether a new frame of signal is input. If no rising edge appears, it is maintained in a low level state. The judgment subcircuit 140 generates a second judgment signal and sends it to the buffer subcircuit 130. The buffer subcircuit 130 sends a second control signal to enable the power-off electronic circuit to perform a power-off operation.

[0059] An exemplary description is given by taking the target signal as an iSTB signal. Figure 4 As shown, when a falling edge occurs in the XON signal, a buffer preset time T is set to avoid power failure immediately when a falling edge occurs in the XON signal, that is, to avoid all data output signals being short-circuited with Vcom immediately when a falling edge occurs in the XON signal. The preset time T here is greater than the transmission time of 1 frame of display data. For example, it can be the transmission time of 1 frame, 2 frames, 3 frames, 1.5 frames, or 2.5 frames of display data, which is not limited in the embodiments of the present application. Within the buffer preset time T, determine whether a rising edge occurs in the iSTB signal, that is, determine whether a new frame of signal is input. If a rising edge occurs, the buffer subcircuit resets the XON signal to a high potential, and the data output signal is not short-circuited with Vcom, so that the power-off subcircuit does not perform a power-off operation. For example Figure 4 As shown, within the preset time T, a rising edge of iSTB appears, so the power-off operation is not performed, and the driver chip continues to work normally.

[0060] Reference Figure 5 As shown, in the CSPI data transmission protocol, each rising edge of iSTB marks the start of the next frame. During the data frame transmission, the Lock signal is maintained at a high level to ensure that the display panel can receive data normally. Among them, BK (blanking Time) represents the spare information of each frame during the data transmission process, that is, non-valid information, BAC (Begin active command) indicates the start of the execution of various signal commands in a frame, POL (Polarity) is used to confirm the polarity of this frame data, and EOL (Cmmand End) indicates the end command signal. Figure 5 As shown, the first three frames are initialization information, the fourth frame transmits the first column of data information, that is, 1st line data, and so on, the next frame is 2nd line data.

[0061] In some embodiments, the target signal may be a fast discharge signal XON signal. If the XON pin is triggered by mistake, within a preset time T, the XON signal may automatically restore to a high level.

[0062] The target signal is an XON signal. Figure 6 As shown, a buffer function is added when the XON pin inputs a falling edge, which can be a preset buffer time. The preset time T here can be a time greater than 1 frame, for example, 1 frame, 2 frames, 3 frames, or 1.5 frames, 2.5 frames, and the embodiment of the present application does not limit this. Prevent power failure immediately when the XON falling edge is input, that is, immediately short-circuit all data output signals with Vcom. Within the preset buffer time, determine whether the XON signal has a rising edge, that is, determine whether a new frame of signal is input. If a rising edge occurs, do not short-circuit all data output signals with Vcom, so that the electronic circuit does not perform a power-off operation. For example Figure 6 As shown, within the preset time T, the rising edge of XON appears, so the power-off operation is not performed, and the driver chip continues to work normally.

[0063] Reference Figure 7 As shown, within the preset buffer time, it is determined whether the XON signal has a rising edge, that is, whether a new frame of signal is input. If the XON signal has a rising edge, the data output signal is not short-circuited with Vcom, so that the power-off electronic circuit does not perform the power-off operation. If the XON signal does not have a rising edge, it is determined that the XON signal is valid and the power-off operation is performed. For example Figure 7 As shown, within the preset time T, no rising edge of XON appears, and the situation of XON false triggering is ruled out, and it is determined to execute the power-off operation.

[0064] In some embodiments, the fast discharge circuit further includes: an electrostatic protection subcircuit 160 connected to the access port 110 and the sensing subcircuit 120 , and the electrostatic protection subcircuit 160 is configured to discharge static electricity from the driving chip.

[0065] In some embodiments, the electrostatic protection subcircuit 160 includes: a diode, including a positive electrode connected to a preset low potential and a negative electrode connected to the access port 110 and the sensing subcircuit 120; and a MOS tube, including a control electrode connected to a preset low potential, a first electrode connected to a preset low potential, and a second electrode connected to the access port 110 and the sensing subcircuit 120.

[0066] It should be noted that the transistors used in all the embodiments of the present application may be thin film transistors (TFT), field effect transistors (MOS), or other devices with the same characteristics, and the embodiments of the present application are not limited to this.

[0067] Exemplarily, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low temperature polysilicon (LTPS) process, or a high temperature polysilicon (HTPS) process. The embodiments of the present application are not limited thereto.

[0068] The embodiments of the present application do not limit the type of transistor. The transistor may be an N-type transistor, or a P-type transistor, or an enhancement-type transistor, or a depletion-type transistor. In the embodiments of the present application, the present application is exemplarily described by taking all transistors as P-type transistors as an example. The P-type transistor is turned on by a low-level voltage signal and turned off by a high-level voltage signal; that is, the operating voltage of the P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0069] In the embodiments of the present application, the gate of the transistor is the control electrode. At the same time, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode. At this time, the first electrode of the transistor can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure.

[0070] In some embodiments, the power-off electronic circuit 150 includes: a latch unit 151 configured to generate a latch signal in response to a control signal and send the latch signal to the power-off unit 152; and a power-off unit 152 configured to perform or not perform a power-off operation in response to the latch signal.

[0071] An embodiment of the present application further provides a display panel, comprising the driving chip described in any one of the above embodiments, and the contents already stated will not be repeated here.

[0072] The embodiment of the present application also provides a display panel driving method, which is applied to a driving chip, wherein the driving chip includes a fast discharge circuit, wherein the fast discharge circuit includes an input port for receiving a fast discharge signal, a judgment subcircuit, a buffer subcircuit, and a disconnection subcircuit. The driving method can be applied to the driving chip described in any of the above embodiments, and the contents already described will not be repeated here. Figure 8 As shown, the method includes:

[0073] Step S801, the judgment sub-circuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal;

[0074] Step S802, the buffer sub-circuit generates a control signal in response to the determination signal and sends it to the electronic circuit for interruption; and

[0075] Step S803: the power-off electronic circuit controls the driving chip to execute or not execute the power-off operation in response to the control signal.

[0076] In some embodiments, the judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: generating a first judgment signal and sending it to the buffer subcircuit in response to the rising edge of the target signal within the preset time.

[0077] In some embodiments, within a preset time, in response to a rising edge of a target signal, a first judgment signal is generated and sent to a buffer subcircuit, including: within a preset time, in response to a rising edge of a fast discharge signal, a first judgment signal is generated and sent to a buffer subcircuit; or within a preset time, in response to a rising edge of a scan drive start pulse signal, a first judgment signal is generated and sent to a buffer subcircuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signals.

[0078] In some embodiments, the driving method of the display panel further includes: within a preset time, the buffer subcircuit generates a first control signal in response to a first judgment signal and sends it to the power-off electronic circuit; the power-off electronic circuit controls the driving chip not to perform a power-off operation in response to the first control signal.

[0079] In some embodiments, the judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: within the preset time, in response to the continuous low level state of the target signal, generating a second judgment signal and sending it to the buffer subcircuit.

[0080] In some embodiments, within a preset time, in response to a continuous low level state of a target signal, a second judgment signal is generated and sent to a buffer sub-circuit, including: within a preset time, in response to a continuous low level state of a fast discharge signal, a second judgment signal is generated and sent to a buffer sub-circuit; or within a preset time, in response to a continuous low level state of a scan drive start pulse signal, a second judgment signal is generated and sent to a buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

[0081] In some embodiments, the method further includes: within a preset time, the buffer subcircuit generates a second control signal in response to the second judgment signal and sends it to the power-off electronic circuit; the power-off electronic circuit controls the driving chip to perform a power-off operation in response to the second control signal.

[0082] In some embodiments, the driving method is applicable to the CSPI transmission protocol.

[0083] In an embodiment of the present application, a preset time is set as a buffer stage, and a judgment condition is added in the buffer stage to further determine whether it is a valid fast discharge signal, and then determine whether to perform a power-off operation. This can at least solve the problem of misoperation that is prone to occur when there is other interference on the XON pin, and effectively improve the accuracy of performing fast power-off according to the XON signal.

[0084] The embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the above-mentioned display panel driving method are implemented. The non-transitory computer-readable storage medium has all the beneficial effects of the above-mentioned display panel driving method, and the present application will not repeat them here.

[0085] The embodiment of the present application also provides an electronic device, comprising: a memory and a processor, wherein a computer program is stored in the memory; and the processor is used to execute the computer program in the memory to implement the steps of the above-mentioned display panel driving method. The electronic device has all the beneficial effects of the above-mentioned display panel driving method, and the present application will not repeat them here.

[0086] The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof, which is not specifically limited in the present application. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0087] In some embodiments of the present application, computer-readable storage media may be any tangible media that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0088] The computer-readable storage medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0089] Computer program code for performing the operations of some embodiments of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0090] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a portion of a code, which contains one or more executable instructions for implementing a specified logical function.

[0091] It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures.

[0092] In the embodiments of the present application, specific examples are used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driver chip, characterized in that: The driving chip includes a fast discharge circuit, and the fast discharge circuit includes: An access port configured to receive a fast discharge signal; wherein the fast discharge signal is used to instruct the driver chip to power off; a sensing subcircuit, connected to the access port and a power supply voltage, the sensing subcircuit being configured to sense a falling edge of the fast discharge signal; a buffer subcircuit, connected to the sensing subcircuit, the judging subcircuit and the electronic circuit breaker, wherein the buffer subcircuit is configured to generate a control signal and send it to the electronic circuit breaker in response to the judging signal output by the judging subcircuit within a preset time after the sensing subcircuit senses the falling edge of the fast discharge signal; The judgment subcircuit is connected to the buffer subcircuit and is configured to generate the judgment signal according to the state of the target signal within the preset time, and send the judgment signal to the buffer subcircuit; and The power-off sub-circuit is connected to the buffer sub-circuit and is configured to control the driving chip to perform or not perform a power-off operation in response to the control signal.

2. The driver chip according to claim 1, characterized in that: The judgment subcircuit is further configured as: Within the preset time, in response to a rising edge of the target signal, a first determination signal is generated and sent to the buffer sub-circuit.

3. The driver chip according to claim 2, characterized in that: The judgment subcircuit is further configured as: generating the first determination signal in response to a rising edge of the fast discharge signal within the preset time and sending the first determination signal to the buffer sub-circuit; or Within the preset time, in response to the rising edge of the scan drive start pulse signal, the first determination signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

4. The driver chip according to claim 2 or 3, characterized in that: The buffer subcircuit is further configured as: generating a first control signal in response to the first judgment signal within the preset time, and sending the first control signal to the electronic circuit; The electronic circuit is further configured as follows: In response to the first control signal, the driving chip is controlled not to perform a power-off operation.

5. The driver chip according to claim 1, characterized in that: The judgment subcircuit is further configured as: In response to the target signal being in a continuous low level state within the preset time, a second determination signal is generated and sent to the buffer sub-circuit.

6. The driver chip according to claim 5, characterized in that: The judgment subcircuit is further configured as: In response to the continuous low level state of the fast discharge signal within the preset time, generating the second determination signal and sending it to the buffer sub-circuit; or In response to the continuous low level state of the scan drive start pulse signal within the preset time, the second judgment signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

7. The driver chip according to claim 5 or 6, characterized in that: The buffer subcircuit is further configured as: generating a second control signal in response to the second judgment signal within the preset time, and sending the second control signal to the electronic circuit; The electronic circuit is further configured as follows: The driving chip is controlled to perform a power-off operation in response to the second control signal.

8. The driver chip according to claim 1, characterized in that: The driver chip is suitable for the CSPI transmission protocol.

9. A display panel, characterized in that: A driver chip comprising any one of claims 1 to 8.

10. A method for driving a display panel, characterized in that: Applied to a driver chip, the driver chip includes a fast discharge circuit, the fast discharge circuit includes an input port connected to a fast discharge signal, a judgment subcircuit, a buffer subcircuit and a disconnection subcircuit, the method includes: The judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal; The buffer sub-circuit generates a control signal in response to the determination signal and sends it to the interrupt sub-circuit; and The power-off electronic circuit controls the driving chip to perform or not perform a power-off operation in response to the control signal.

11. The method for driving a display panel according to claim 10, wherein: The judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: Within the preset time, in response to a rising edge of the target signal, a first determination signal is generated and sent to the buffer sub-circuit.

12. The method for driving a display panel according to claim 11, characterized in that: The method of generating a first determination signal in response to a rising edge of the target signal within the preset time and sending the first determination signal to the buffer sub-circuit comprises: generating the first determination signal in response to a rising edge of the fast discharge signal within the preset time and sending the first determination signal to the buffer sub-circuit; or Within the preset time, in response to the rising edge of the scan drive start pulse signal, the first determination signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

13. The method for driving a display panel according to claim 11 or 12, characterized in that: The method further comprises: Within the preset time, the buffer subcircuit generates a first control signal in response to the first judgment signal and sends the first control signal to the interrupt subcircuit; The power-off electronic circuit controls the driving chip not to perform a power-off operation in response to the first control signal.

14. The method for driving a display panel according to claim 10, wherein: The judgment subcircuit generates a judgment signal according to the target signal within a preset time in response to the falling edge of the fast discharge signal, including: In response to the target signal being in a continuous low level state within the preset time, a second determination signal is generated and sent to the buffer sub-circuit.

15. The method for driving a display panel according to claim 14, characterized in that: The method of generating a second determination signal in response to a continuous low level state of the target signal within the preset time and sending the second determination signal to the buffer sub-circuit comprises: In response to the continuous low level state of the fast discharge signal within the preset time, generating the second determination signal and sending it to the buffer sub-circuit; or In response to the continuous low level state of the scan drive start pulse signal within the preset time, the second judgment signal is generated and sent to the buffer sub-circuit; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame of image signal.

16. The method for driving a display panel according to claim 14 or 15, characterized in that: The method further comprises: Within the preset time, the buffer subcircuit generates a second control signal in response to the second judgment signal and sends the second control signal to the interrupt subcircuit; The power-off electronic circuit controls the driving chip to perform a power-off operation in response to the second control signal.

17. The method for driving a display panel according to claim 10, wherein: The driving method is suitable for the CSPI transmission protocol.

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