CAM content addressing circuit and addressing method based on memristor in-memory calculation

Abstract

The invention relates to the technical field of memories, in particular to a CAM content addressing circuit and method based on memristor in-memory calculation, and aims at overcoming the defects of a traditional memory in the aspects of high-speed data retrieval and processing. According to the main scheme, the circuit comprises a PWM modulation unit, a multiplexer, a memristor array, a Ref voltage lookup table unit, an SA array and an encoder. A 4-bit digital signal is input through the PWM modulation unit, the multiplexer activates a specific storage row in the memristor array, and content addressing is carried out through conductance matching of the memristor array. Bit line voltage of the memristor array is output to the SA array and compared with reference voltage output by the Ref voltage lookup table unit, and matching signals are output through the SA array according to the comparison result, input to the encoder and decoded into address information. The method has the characteristics of high efficiency, simplicity and high integration level, meets the requirements of large-scale storage and calculation, and is widely applied to the fields of high-speed cache, network routers, database query and the like.

Description

Technical Field

[0001] The invention relates to the technical field of memory, and provides a CAM content addressing circuit and an addressing method based on memristor in-memory calculation. Background Art

[0002] With the rapid development of computer technology, in the context of big data and artificial intelligence, the demand for data processing is growing, and the demand for data storage is increasing. Although traditional random access memory (RAM) performs well in data access speed and capacity, it is incapable of meeting the requirements in specific application scenarios, such as high-speed data retrieval and processing. In order to solve this problem, content-addressable memory (CAM) came into being. Traditional storage methods usually require address addressing, while CAM can directly find matching items in data storage through content addressing, which significantly improves the efficiency of data retrieval. This makes CAM an important technology in the fields of cache, network routers, database queries, etc.

[0003] There are several mainstream ways to implement existing content addressing technology, including static content addressable memory (StaticCAM, SCM), dynamic content addressable memory (Dynamic CAM, DCM), hybrid content addressable memory, etc. SCM uses static logic units (such as SRAM) to store data and implements content addressing through comparators. It has fast speed and strong data retention capability, but also high power consumption, especially in large-scale applications. DCM is based on dynamic storage units (such as DRAM) and requires periodic refresh when storing data. It has high storage density and low cost, but periodic refresh increases design complexity and its rate is slower than SCM. Hybrid content addressable memory combines the advantages of SCM and DCM, and better balances the operating speed and cost, but it makes the overall design more complex and power consumption difficult to control. Summary of the invention

[0004] The present invention aims to provide a CAM content addressing circuit based on memristor in-memory computing, aiming to solve the shortcomings of traditional memories in high-speed data retrieval and processing, and to achieve more efficient, simpler and highly integrated data retrieval and processing by combining key technologies such as PWM modulation, multiplexer, 1T1R memristor array, SA array and Ref voltage lookup table, so as to meet the needs of large-scale storage and computing.

[0005] In order to achieve the above purpose, the present invention adopts the following technical solutions: The present invention provides a CAM content addressing circuit based on memristor in-memory calculation, comprising a PWM modulation unit, a multiplexer, a memristor array, a Ref voltage lookup table unit, an SA array, and an encoder; The input signal of the PWM modulation unit is a 4-bit digital signal, and the output signal of the PWM modulation unit is used as the input of the multiplexer. The output port of the multiplexer is connected to the WL of the memristor array unit, WL represents the Word Line, and the BL of the memristor array is connected to the input port on one side of the SA array, BL represents the Bit Line. At the same time, the input of the Ref voltage lookup table unit is also a 4-bit digital signal, and the output port Out is connected to the input port on the other side of the SA array. The output port of the SA array unit is connected to the input port of the encoder.

[0006] In the above solution, the width of the pulse signal output by the PWM modulation unit is proportional to the size of the input 4-bit digital signal, and different input signal values ​​correspond to different pulse widths.

[0007] In the above solution, the number of output ports of the multiplexer is N, where N is the number of rows of memristor array units, and the output ports of the multiplexer correspond one-to-one to the WL input ports of the memristor array.

[0008] In the above solution, the number of input ports of the SA array is M+2, where M is the number of columns of the memristor array, and the M input ports of the SA array correspond one-to-one to the BL output ports of the memristor array.

[0009] In the above solution, the SA array includes M units, each of which is composed of two voltage comparators and an AND gate.

[0010] In the above scheme, the Ref voltage lookup table unit looks up two output voltages, namely Vref1 and Vref2, according to the 4-bit digital signal input. Vref1 and Vref2 are sent to the two input ports corresponding to "2" in "M+2" of the SA array through two output ports.

[0011] In the above solution, all the units in each row of the memristor share the same WL; all the units in each column share a BL and a SL, where SL represents a Source Line.

[0012] In the above scheme, the memristor array unit is a 1T1R structure, each unit is composed of an RRAM and a transistor, in each unit, the transistor source is connected to SL; the transistor drain is connected to the upper electrode of the memristor, the lower electrode of the memristor is connected to BL; the gate of the transistor is connected to WL.

[0013] In the above solution, the conductance value of the RRAM is a preset value. The conductance value of each RRAM is between gmmin and gmmax, and there are 16 conductance values in total. The conductance values are matched one by one from small to large with the 0-15 sixteen inputs that can be represented by the 4-bit input signal, where gmmin represents the minimum conductance value of the memristor, and gmmax represents the maximum conductance value of the memristor.

[0014] The present invention also provides a CAM content addressing method based on in-memory computing of memristors, including the following steps: Input the 4-bit digital signal into the PWM modulation unit and convert it into a pulse width modulation signal; According to the output signal of the PWM modulation unit, selectively activate a specific memory row in the memristor array through a multiplexer; In the activated specific memory row, perform content addressing through the conductance matching of the memristor array; Output the bit line voltage of the memristor array to the SA array and compare it with the reference voltage output by the Ref voltage lookup table unit; According to the comparison result, output a matching signal through the SA array; Input the output signal of the SA array into the encoder and decode it into address information.

[0015] Furthermore, perform reference voltage lookup, bit line voltage matching, and output address encoding, specifically including the following steps: Store 32 preset reference voltage values in the registers of the Ref voltage lookup table unit, divided into two groups, with 16 in each group; Use the 4-bit input signal as the address and input it into the lookup table; Determine the lookup address according to the 4-bit input signal and output two reference voltages Vref1 and Vref2 corresponding to this address; Output the bit line voltage VBL of each column of the 1T1R memristor array into the corresponding SA array; Input the two reference voltages output by the lookup table into the two voltage comparators of the SA array; According to the results of the voltage comparators, if Vref1 < VBL < Vref2, the AND gate of the SA array outputs a high level; All SA arrays output a high level or a low level according to the voltage comparison result; Use the outputs of all SA arrays as the parallel input of the encoder; The encoder decodes the high and low levels of the parallel input and outputs the address encoding; Complete the content addressing operation, and the output address is the encoding result.

[0016] Because the present invention adopts the above technical means, it has the following beneficial effects: (1) The present invention combines computation with storage by utilizing the conductivity characteristics of memristors. Through conductivity matching, the circuit can perform computation directly in the storage unit without transmitting data to an external processing unit, thereby improving processing efficiency.

[0017] (2) The present invention realizes the function of content addressing by comparing the input signal with the conductance of the memristor. Without address lines, the circuit can directly search according to the data content, which improves the data access speed.

[0018] (3) The use of PWM modulation in the present invention allows the input signal to flexibly control the duty cycle of the output signal, thereby accurately selecting and activating the storage unit. This modulation method enhances the controllability and adaptability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A theoretical schematic diagram of a CAM circuit based on memristor memory calculation of the present invention; Figure 2 A theoretical schematic diagram of the 1T1R memristor array portion of the present invention; Figure 3 A theoretical schematic diagram of the Ref voltage lookup table portion of the present invention; Figure 4 A theoretical schematic diagram of an SA array in the SA array part of the present invention; Figure 5 A schematic diagram of an intermediate signal waveform and an output waveform corresponding to an input signal waveform of the present invention. DETAILED DESCRIPTION

[0020] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions made to the present invention should all be included in the scope of the claims of the present invention.

[0021] In addition, in order to better illustrate the present invention, numerous specific details are given in the following specific embodiments. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0022] The present invention provides a CAM content addressing circuit based on memristor in-memory computing, comprising: PWM modulation unit: The input is a 4-bit digital signal, and the output is a pulse width modulation signal. The pulse signal width is proportional to the input signal size, and the frequency is a fixed frequency; Multiplexer: The number of output ports is N, where N is the number of rows of the 1T1R RRAM array, and the output ports are connected to the Word Lines of the 1T1RRRAM array; 1T1R memristor array: It is composed of multiple 1T1R memristor units, each unit consists of an RRAM and a transistor. The conductance value of the RRAM is preset to 16 different values ​​between gmmin and gmmax, which correspond to the 16 inputs 0-15 that can be represented by the 4-bit input signal. The top electrode of the RRAM is connected to the bit line, the bottom electrode is connected to the drain of the transistor, the source of the transistor is connected to the Source Line, and the gate of the transistor is connected to the Word Line. Ref voltage lookup table unit: input is 4-bit digital signal, output is two reference voltages Vref1 and Vref2; SA array: contains M units, each unit consists of two voltage comparators and an AND gate. M is the number of columns of the 1T1R RRAM array. The M input ports of each unit correspond one-to-one to the Bit Line of the 1T1R RRAM array. The input ends of the two voltage comparators are connected to VBL and Vref1, Vref2 respectively. Encoder: Encode the output of the SA array and output the content-addressed address.

[0023] In order to facilitate those skilled in the art to better understand the technical concept of the present invention, the following further explanation is made: 1. Input signal modulation and output to 1T1R memristor array As attached Figure 1 As shown in the figure, the 4-bit input signal is first input into the PWM modulation part. The DAC (digital-to-analog converter) in the PWM modulator converts the digital signal into a corresponding analog voltage signal to ensure that it represents a continuous voltage value. At this time, a fixed-frequency triangle wave signal is generated in the PWM modulator as the reference signal of the PWM modulator, and the converted analog voltage is compared with the reference waveform. In each clock cycle, the PWM modulator compares the input analog voltage with the current value of the reference waveform. If the input analog voltage is higher than the current value of the reference waveform, a high level is output; if it is lower, a low level is output. Depending on the amplitude of the input voltage, the duty cycle of the PWM output signal will change accordingly. When the multiplexer receives the output signal of the PWM modulator, it will use the state of the signal to determine which output signal is pulled high, and this pulled-up output signal will activate a row of word lines in the 1T1R memristor array.

[0024] 2. 1T1R memristor array conductance preset and in-memory computing operation As a common memristor array structure, 1T1R memristor array has been applied to many RRAM memories and RRAM storage and computing integrated designs, such as the attached Figure 2 As shown. In this array structure, the top electrode of the RRAM cell is connected to the bit line, the bottom electrode is connected to the drain of an N-type MOS tube, the gate of the MOS tube is connected to the word line, and the source is connected to a new line, the source line, and then such cells are arrayed. In this 1T1R array, the switch of the array cell is controlled by the gate of the transistor, that is, the word line. Before any operation is performed on the cell, the voltage of the word line must be adjusted to be higher than the source line by a transistor threshold voltage to ensure that the transistor is turned on. In the RRAM array, when setting, the bit line end is set to a high voltage and the source line end is grounded. Conversely, in the reset phase, the source line is set to a high voltage and the bit line end is grounded. In storage and computing applications, the 1T1R memristor array can provide data expansion or share other data traffic in the analog domain, thereby obtaining higher data density and lower power consumption. Before performing content addressing operations, the required conductivity data needs to be stored in each RRAM in the memristor array in advance. The conductivity state of the memristor is modified by the flow of current and the applied voltage. Different voltages and time lengths will cause phase changes or ion migration in the memristor material, thereby changing its conductivity to achieve the purpose of storing data. When the conductivity is preset, a voltage is first applied to the word line to turn on the transistor, and then different voltages are applied to the bit line connected to the corresponding memristor unit according to different storage values ​​to cause different degrees of ion migration, so that the conductivity value of each memristor unit reaches the preset situation.

[0025] When content addressing is performed, the output signal of the multiplexer is sent to the 1T1R memristor array. During this process, the word line of a specific row is pulled high to form a reference signal. Since the conductance value of each memristor unit is pre-stored during the previous writing process, these values ​​are different. The voltage signal on the word line affects the current of each memristor unit, causing the current value flowing through each unit to differ. These differentiated current signals ultimately generate different voltage signals (VBL) on the bit line connected to each memristor unit. Specifically, the current flowing through the memristor unit with a higher conductance value is larger, so that the voltage on the bit line appears as a higher value; while the current flowing through the unit with a lower conductance value will result in a lower voltage. These bit line voltages will then be output to the SA array for further operations.

[0026] 3. Reference voltage search, bit line voltage matching and output address encoding As an example Figure 3As shown in the Ref voltage lookup table unit structure, 32 voltage values (16 for reference voltage 1 and 16 for reference voltage 2) are preset and stored as constants in the registers of the Ref voltage lookup table unit. A 4-bit input signal is input into the lookup table as an address. For example, if the 4-bit input signal is 0110, the lookup address is 6, and the reference voltage 1 (Vref1) and reference voltage 2 (Vref1) at address 6 are output as the two reference voltages of the lookup table to the units of the SA array.

[0027] The bit-line voltage output of each column of the 1T1R memristor array mentioned in the previous part will enter the corresponding SA array as the VBL input, and the two reference voltages output by the Ref voltage lookup table will also be input into the two voltage comparators of the SA array as shown in the appendix. If Vref1 < VBL < Vref2, the AND gate output of this SA array is at a high level. The remaining SA arrays will also output a high level or a low level according to the results of the voltage comparators. Figure 3 Then, the outputs of all SA arrays are used as the parallel inputs of the encoder, and the encoder decodes these input high and low levels. For example, if the input of the encoder is 10110010, the encoding is 178, indicating that the address obtained by the content-addressing operation is 178, and this content-addressing operation is completed.

[0028] In short, the present invention proposes a content-addressing circuit based on in-memory computing with memristors, which systematically combines key components such as PWM modulation, multiplexers, 1T1R memristor arrays, signal amplifiers (SA) arrays, and reference voltage lookup tables. This circuit design demonstrates high efficiency and flexibility in content-addressing operations and can perform precise data access through 4-bit input signals. First, the input signal is converted into a corresponding analog voltage signal through the PWM modulation part, and a specific word line is selectively activated using a multiplexer. Then, the conductance values of the 1T1R memristor array are stored during a preset stage and are ready for matching. During the content-addressing operation, the raised word-line signal affects the current of each memristor, generating different bit-line voltages, and finally these voltage signals are input into the SA array for comparison. Finally, the reference voltages provided by the reference voltage lookup table are matched with the bit-line voltages. If the conditions are met, the corresponding SA array outputs a high level, and the outputs of all SA arrays are decoded by the encoder, finally generating the address of the content-addressing. This process not only simplifies the complexity of data access but also improves the lookup speed and storage density, and has broad application prospects.

[0029] In short, the present invention proposes a content-addressing circuit based on in-memory computing with memristors, which systematically combines key components such as PWM modulation, multiplexers, 1T1R memristor arrays, signal amplifiers (SA) arrays, and reference voltage lookup tables. This circuit design demonstrates high efficiency and flexibility in content-addressing operations and can perform precise data access through 4-bit input signals. First, the input signal is converted into a corresponding analog voltage signal through the PWM modulation part, and a specific word line is selectively activated using a multiplexer. Then, the conductance values of the 1T1R memristor array are stored during a preset stage and are ready for matching. During the content-addressing operation, the raised word-line signal affects the current of each memristor, generating different bit-line voltages, and finally these voltage signals are input into the SA array for comparison. Finally, the reference voltages provided by the reference voltage lookup table are matched with the bit-line voltages. If the conditions are met, the corresponding SA array outputs a high level, and the outputs of all SA arrays are decoded by the encoder, finally generating the address of the content-addressing. This process not only simplifies the complexity of data access but also improves the lookup speed and storage density, and has broad application prospects.

Claims

1. A CAM content addressing circuit based on memristor in-memory computing, characterized in that: include: PWM modulation unit, multiplexer, memristor array, Ref voltage lookup table unit, SA array, encoder; The input signal of the PWM modulation unit is a 4-bit digital signal, and the output signal of the PWM modulation unit is used as the input of the multiplexer. The output port of the multiplexer is connected to the WL of the memristor array unit, WL represents the Word Line, and the BL of the memristor array is connected to the input port on one side of the SA array, BL represents the Bit Line. At the same time, the input of the Ref voltage lookup table unit is also a 4-bit digital signal, and the output port Out is connected to the input port on the other side of the SA array. The output port of the SA array unit is connected to the input port of the encoder.

2. A CAM content addressing circuit based on memristor in-memory computing according to claim 1, characterized in that: The pulse signal width output by the PWM modulation unit is proportional to the size of the input 4-bit digital signal, and different input signal values ​​correspond to different pulse widths.

3. A CAM content addressing circuit based on memristor in-memory computing according to claim 1, characterized in that: The number of output ports of the multiplexer is N, where N is the number of rows of memristor array units, and the output ports of the multiplexer correspond one-to-one to the WL input ports of the memristor array.

4. The CAM content addressing circuit based on memristor in-memory computing according to claim 1, characterized in that: The number of input ports of the SA array is M+2, where M is the number of columns of the memristor array, and the M input ports of the SA array correspond one-to-one to the BL output ports of the memristor array.

5. The CAM content addressing circuit based on memristor in-memory computing according to claim 1, characterized in that: The SA array includes M units, each of which is composed of two voltage comparators and an AND gate.

6. The CAM content addressing circuit based on memristor in-memory computing according to claim 4, characterized in that: The Ref voltage lookup table unit looks up two output voltages, Vref1 and Vref2, according to the 4-bit digital signal input. Vref1 and Vref2 are sent to two input ports corresponding to "2" in "M+2" of the SA array through two output ports.

7. The CAM content addressing circuit based on memristor in-memory computing according to claim 1, characterized in that: All the cells in each row of the memristor share the same WL; all the cells in each column share a BL and a SL, where SL represents a Source Line; The memristor array unit is a 1T1R structure, each unit is composed of an RRAM and a transistor, and in each unit, the transistor source is connected to the SL; The drain of the transistor is connected to the upper electrode of the memristor, and the lower electrode of the memristor is connected to BL; The gate of the transistor is connected to WL.

8. The CAM content addressing circuit based on memristor in-memory computing according to claim 7, characterized in that: The conductivity value of the RRAM is a preset value. Each conductivity value of the RRAM is between gmmin and gmmax. There are 16 conductivity values ​​in total. The conductivity values ​​match the 16 inputs 0-15 that can be represented by the 4-bit input signal from small to large. gmmin represents the minimum value of the conductivity value of the memristor, and gmmax represents the maximum value of the conductivity value of the memristor.

9. A CAM content addressing method based on memristor in-memory computing, characterized in that: Using the CAM circuit as described in any one of claims 1 to 8, the CAM content addressing method comprises the following steps: The input 4-bit digital signal is input to the PWM modulation unit and converted into a pulse width modulation signal; According to the output signal of the PWM modulation unit, a specific storage row in the memristor array is selectively activated through a multiplexer; Content addressing is performed by conductance matching of the memristor array in a specific activated memory row; Outputting the bit line voltage of the memristor array to the SA array and comparing it with the reference voltage output by the Ref voltage lookup table unit; According to the comparison result, a matching signal is output through the SA array; The output signal of the SA array is input to the encoder and decoded into address information.

10. A CAM content addressing method based on memristor in-memory computing according to claim 9, characterized in that: The reference voltage search, bit line voltage matching and output address coding are performed, specifically including the following steps: 32 preset reference voltage values ​​are stored in the register of the Ref voltage lookup table unit, divided into two groups, each with 16 values; Enter the 4-bit input signal as the address into the lookup table; Determine the search address according to the 4-bit input signal, and output two reference voltages Vref1 and Vref2 corresponding to the address; Input the bit line voltage VBL output of each column of the 1T1R memristor array to the corresponding SA array; The two reference voltages output from the lookup table are input into two voltage comparators of the SA array; According to the voltage comparator result, if Vref1 < VBL < Vref2, the AND gate of the SA array outputs a high level; All SA arrays output high or low levels according to the voltage comparison results; The outputs of all SA arrays are used as parallel inputs of the encoder; The encoder decodes the high and low levels of the parallel input and outputs the address code; The content addressing operation is completed, and the output address is the encoding result.

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