Extensible 5T-SRAM architecture and control method thereof
By introducing word voltage switch and word line group selection module in the 5T-SRAM architecture, the power management and data operation of the memory are optimized, and the problem of reading operation energy increases when word size is expanded is solved, achieving low power consumption and high reliability memory design.
Patent Information
- Application Number
- CN202411512852.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-14
AI Technical Summary
When the word size of the existing 5T-SRAM and 6T-SRAM are expanded, the read operation performance is affected, and the increase in bit line capacitance leads to a sharp increase in read operation energy, which in turn causes a significant increase in overall power consumption.
A scalable 5T-SRAM architecture is proposed, including a 5T-SRAM array, a byte decoder, a weight mapping network, a word line group selection module and a word voltage switch. The power supply voltage of 5T-SRAM is adjusted through word voltage switches, a single transmission gate write operation is realized, and word line activation and data allocation are optimized through word line group selection module and weight mapping network.
It reduces the leakage power of the memory in standby state, achieves low power consumption operation, and improves the reliability and stability of the memory.
Smart Images
Figure CN119446220A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and in particular to an expandable 5T-SRAM architecture and a control method thereof. Background Art
[0002] With the increasing demand for modern computing and the diversification of application scenarios, memory technology faces challenges such as storage density, latency, and power consumption. Especially in large-scale integrated circuit (VLSI) design, the size of storage cells has become an inevitable trend to increase the capacity of memory and meet the needs of data processing and storage. However, the performance of existing 5T-SRAM and 6T-SRAM read operations is significantly affected as the word size increases. In particular, the bit line capacitance in the memory shows a significant upward trend as the word size increases. This increase in capacitance leads to a sharp increase in the energy required for each read operation, which in turn causes a significant increase in overall power consumption. In the traditional SRAM architecture, the bit line is connected to multiple storage cells. As the word size increases, the length of the bit line and the corresponding capacitance value will increase. When the memory performs a read operation, the amount of current required to charge and discharge increases sharply, and the power consumption caused by this increases exponentially.
[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention
[0004] The main purpose of the embodiments of the present application is to propose an expandable 5T-SRAM architecture and a control method thereof, which can reduce the leakage power of the memory in the standby state, thereby reducing the operating power consumption of the memory and improving the reliability and stability of the memory.
[0005] To achieve the above-mentioned object, an embodiment of the present application proposes an expandable 5T-SRAM architecture in one aspect, the architecture comprising a 5T-SRAM array, a byte decoder, a weight mapping network, a word line group selection module and a word voltage switch, the byte decoder, the weight mapping network, the word line group selection module and the word voltage switch are electrically connected to the 5T-SRAM array respectively, wherein:
[0006] The byte decoder is used to decode the byte data to be processed and obtain the selected byte data;
[0007] The word line group selection module is used to activate the corresponding word line according to the selected byte data to obtain the activated word line;
[0008] The weight mapping network is used to distribute the selected byte data to the activated word line;
[0009] The word voltage switch is used to assign a corresponding voltage state to the activated word line;
[0010] The 5T-SRAM array is used to read, hold or write the selected byte data according to the voltage state of the activated word line.
[0011] In some embodiments, the 5T-SRAM array includes a plurality of 5T-SRAM cells.
[0012] In some embodiments, the 5T-SRAM unit includes an inverter module and an NMOS transmission gate, the inverter module includes a first inverter and a second inverter, wherein the first inverter and the second inverter are connected by cross-coupling, the drain of the NMOS transmission gate is connected to the inverter module, the gate of the NMOS transmission gate is connected to the read-write word line, and the source of the NMOS transmission gate is connected to the read-write bit line.
[0013] In some embodiments, the word voltage switch includes a first NMOS transistor, a first PMOS transistor and a second PMOS transistor, wherein the drain of the first NMOS transistor is connected to a low power supply voltage, the source of the first PMOS transistor is connected to a high power supply voltage, the gate of the first NMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected to the read-write bit line, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second PMOS transistor and connected to the read-write word line.
[0014] In some embodiments, the weight mapping network includes a sign bit decoder and a calculation unit, wherein the sign bit decoder is used to perform address decoding and data mapping processing on input data, and the calculation unit is used to perform weight calculation.
[0015] To achieve the above object, another aspect of the embodiment of the present application provides a control method for a scalable 5T-SRAM architecture, the method comprising the following steps:
[0016] Decoding the byte data to be processed and activating the corresponding word line according to the selected byte data to obtain the activated word line;
[0017] allocating the selected byte data to the activated word line;
[0018] assigning a corresponding voltage state to the activated word line;
[0019] The selected byte data is read, held or written according to the voltage state of the activated word line.
[0020] In some embodiments, the decoding process of the byte data to be processed and activating the corresponding word line according to the selected byte data to obtain the activated word line includes:
[0021] Obtain the binary address of the byte data to be processed and decode it into a one-hot code, set the selected byte data to 1, and set the unselected byte data to 0, to obtain the selected byte data;
[0022] The binary address of the word line is obtained and decoded into a one-hot code, and the word line is selected according to the selected byte data, and the selected word line is set to 1 and the unselected word line is set to 0 to obtain the activated word line.
[0023] In some embodiments, the activated word line includes a holding mode, a writing mode or a reading mode, the voltage state includes a low power supply voltage state and a high power supply voltage state, and the corresponding voltage state is assigned to the activated word line, including:
[0024] If the activated word line is in a holding mode or a writing mode, assigning the low power supply voltage state to the activated word line;
[0025] If the activated word line is in a read mode, the high power supply voltage state is assigned to the activated word line.
[0026] In some embodiments, it also includes:
[0027] The corresponding voltage state is allocated to the activated word line, thereby adjusting the power supply voltage of the 5T-SRAM array, thereby realizing the write operation of the data single transmission gate.
[0028] In some embodiments, it also includes:
[0029] For the write mode, data is written into the 5T-SRAM array, the word voltage switch is electrically connected to the low power supply voltage state, the binary address of the byte data to be processed is written into the byte decoder and word line group selection module, so that the transmission gate of the activated word line is opened, and the byte data to be processed is input through the read and write bit lines and distributed to the activated word lines through the weight mapping network;
[0030] For the read mode, data is read out from the 5T-SRAM array, the word voltage switch is electrically connected to the high power supply voltage state, and the binary address of the byte data to be processed is written into the byte decoder and word line group selection module, so that the transmission gate of the activated word line is opened, and the data is read out from the bit line of the 5T-SRAM array and transmitted to the computing unit.
[0031] The embodiments of the present application include at least the following beneficial effects: The present application provides an expandable 5T-SRAM architecture and a control method thereof, which decodes the byte data to be processed through a byte decoder, obtains the selected byte data, and then activates the corresponding word line according to the selected byte data through a word line group selection module, obtains the activated word line, further allocates the selected byte data to the activated word line, and allocates the corresponding voltage state to the activated word line through a word voltage switch, and adjusts the power supply voltage of the 5T-SRAM through the word voltage switch to realize the write operation of a single transmission gate. The switch can switch the power supply voltage of two adjacent storage rows, thereby reducing the leakage power of the memory in the standby state, realizing low-power operation, and improving the reliability and stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a structural schematic diagram of an expandable 5T-SRAM architecture provided in an embodiment of the present application;
[0033] Figure 2 It is a schematic diagram of the steps of a control method for an expandable 5T-SRAM architecture provided in an embodiment of the present application;
[0034] Figure 3 It is a schematic diagram of the connection between the structure of the word voltage switch provided in the embodiment of the present application and the 5T-SRAM array;
[0035] Figure 4 It is a structural diagram of a weight mapping network provided in an embodiment of the present application;
[0036] Figure 5 It is a schematic diagram of weight resolution expansion calculation in a low-precision mode provided in an embodiment of the present application;
[0037] Figure 6 It is a schematic diagram of weight resolution expansion calculation in the high-precision mode provided in an embodiment of the present application;
[0038] Figure 7 It is a schematic diagram of read energy optimization data of an expandable 5T-SRAM architecture provided in an embodiment of the present application;
[0039] Figure 8 This is a schematic diagram of read disturbance optimization data of an expandable 5T-SRAM architecture provided in an embodiment of the present application;
[0040] Fig. 9 It is a schematic diagram of the readout delay improvement of the scalable 5T-SRAM architecture provided in an embodiment of the present application. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.
[0042] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".
[0043] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0045] Reference Figure 1 , Figure 1 A schematic diagram of a scalable 5T-SRAM architecture provided by an embodiment of the present invention, referring to Figure 1 The architecture includes a 5T-SRAM array, a byte decoder, a weight mapping network, a word line group selection module and a word voltage switch, and the byte decoder, the weight mapping network, the word line group selection module and the word voltage switch are electrically connected to the 5T-SRAM array, wherein:
[0046] The byte decoder is used to decode the byte data to be processed and obtain the selected byte data;
[0047] The word line group selection module is used to activate the corresponding word line according to the selected byte data and obtain the activated word line;
[0048] The weight mapping network is used to assign the selected byte data to the activated word line;
[0049] The weight mapping network includes a sign bit decoder and a calculation unit, wherein the sign bit decoder is used to perform address decoding and data mapping processing on input data, and the calculation unit is used to perform weight calculation.
[0050] In this embodiment, if Figure 4 As shown in the figure, the weight mapping network supports the expansion of bit-serial weight resolution, and a flexible weight mapping network is applied, which can support the expansion of bit-serial weight resolution. Through this design, the resolution of the weight can be flexibly adjusted according to different application requirements, so as to further optimize the performance of the memory while ensuring the calculation accuracy. The design of the weight mapping network is ingenious, and the occupied area is less than 1% of the chip area. This small area design will not cause too much impact on the overall layout of the chip, and it also leaves more space for other functional modules, which is conducive to the miniaturization and integration of the chip.
[0051] The word voltage switch is used to assign a corresponding voltage state to the activated word line;
[0052] Among them, Figure 3 As shown, the word voltage switch includes a first NMOS transistor M LN1 , the first PMOS transistor M LP1 The second PMOS transistor M LP2 , wherein the drain of the first NMOS transistor is connected to a low power supply voltage, the source of the first PMOS transistor is connected to a high power supply voltage, the gate of the first NMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected to a read / write bit line, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second PMOS transistor and connected to a read / write word line.
[0053] In this embodiment, the power supply voltage of the 5T-SRAM is adjusted by a word voltage switch to realize the write operation of a single transmission gate. The switch can switch the power supply voltage of two adjacent storage rows (at the retention / write voltage (V DD,RW :0.3V) and read voltage (V DD,R Two adjacent memory rows share the power supply voltage and N-well to increase cell density. During operation, only the power supply voltage of the memory row pair being read is switched to V DD,R, so all other storage rows will remain in retention / write mode. This approach reduces leakage power by 6.4 times. This high-density storage design can meet the storage needs of large-scale model parameters and provide a large-scale storage and low-energy solution for AIOT Nodes.
[0054] The 5T-SRAM array is used to read, hold or write selected byte data according to the voltage state of the activated word line.
[0055] The 5T-SRAM array includes a plurality of 5T-SRAM cells, the 5T-SRAM cells include an inverter module and an NMOS transmission gate, the inverter module includes a first inverter and a second inverter, wherein the first inverter and the second inverter are connected through cross-coupling, the drain of the NMOS transmission gate is connected to the inverter module, the gate of the NMOS transmission gate is connected to the read-write word line, and the source of the NMOS transmission gate is connected to the read-write bit line.
[0056] In this embodiment, a high-density 16KB scalable 5T-SRAM array is designed with an array size of 1024×128, which can effectively store the speaker verification auxiliary keyword detection model of the transfer calculation. The 5T-SRAM consists of two cross-coupled inverters and an NMOS transmission gate, while the traditional 6T-SRAM requires 2 transmission gates to ensure the write operation. Each device is a UHVT device and uses the minimum size to save area. The 5T-SRAM array has a word voltage switch to solve the leakage problem. The word voltage switch is V DD,R Two PMOS are used in the branch to reduce leakage. LP1 The substrate is connected to VDD to reduce drain-source leakage current. LP2 The substrate of the cascode is connected to its source to reduce substrate leakage. According to simulation, the word voltage switch of the cascode structure reduces leakage power consumption by 80%. The 5T-SRAM array is closely matched with the hybrid intermediate frequency domain computing circuit and is located near it to reduce wiring capacitance and read energy. Through this layout optimization, the power loss during signal transmission is reduced and the overall energy efficiency of the system is improved.
[0057] In summary, the byte decoder in the expandable 5T-SRAM array in the embodiment of the present invention is used to select a word line. It obtains the binary address of the byte to be read or stored from the outside, decodes it into a one-hot code, sets the selected word line to one, and the rest are zero. The weight mapping network is used to allocate and select bit lines for the data to be written. The word line group selection is used to select a word line group. It obtains the binary address of the word line group to be read or stored from the outside, decodes it into a one-hot code, sets the selected word line group to one, and the rest are zero. The word voltage switch is used to adjust the power supply voltage of the selected word line in the 5T-SRAM array. The word voltage switch can switch the power supply voltage of two adjacent storage rows (between the retention / write voltage (V DD,RW :0.3V) and read voltage (V DD,R : 0.9V) to ensure the success of different operations. Finally, the designed scalable 5T-SRAM architecture is system-integrated with other functional modules (such as hybrid intermediate frequency domain computing circuit, voice activity detector, etc.). During the integration process, the layout and routing are optimized to reduce signal interference and power loss to ensure the stable operation of the entire system.
[0058] See also Figure 2 The embodiment of the present application also provides a control method for an expandable 5T-SRAM architecture, which can implement the above-mentioned expandable 5T-SRAM architecture. The control method includes the following steps:
[0059] S100, decoding the byte data to be processed and activating the corresponding word line according to the selected byte data to obtain the activated word line;
[0060] It should be noted that, in some embodiments, step S100 may include: S110, obtaining the binary address of the byte data to be processed and decoding it into a one-hot code, setting the selected byte data to 1, setting the unselected byte data to 0, and obtaining the selected byte data; S120, obtaining the binary address of the word line and decoding it into a one-hot code, selecting the word line according to the selected byte data, setting the selected word line to 1, setting the unselected word line to 0, and obtaining the activated word line.
[0061] S200, allocating the selected byte data to the activated word line;
[0062] S300, assigning a corresponding voltage state to the activated word line;
[0063] It should be noted that, in some embodiments, step S300 may include: S310, if the activated word line is in a hold mode or a write mode, a low power supply voltage state is assigned to the activated word line; S320, if the activated word line is in a read mode, a high power supply voltage state is assigned to the activated word line.
[0064] It should be noted that the write operation of the data single transmission gate is realized by allocating corresponding voltage states to the activated word lines and then adjusting the power supply voltage of the 5T-SRAM array.
[0065] In some specific embodiments, in the hold mode, the power supply voltage of the 5T-SRAM is always connected to a low voltage (0.35V) using a word voltage switch. This low-voltage power supply method significantly reduces the leakage power of the memory in the standby state, thereby achieving low-power operation. Compared with the traditional power supply method, the leakage power is reduced by 84.3%, which greatly extends the battery life of the device.
[0066] In write mode, the write data is transmitted by BL (read-write bit line), (read-write word line) WL WO Set to 1 to open the transmission gate, the word voltage switch always connects the power supply voltage of 5T-SRAM to low voltage (0.35V), which ensures the stability of single-ended writing. Figure 1 As shown in the figure, when BL is 1, it means writing 1, and the Q point will rise to the supply voltage (0.35V). When BL is 0, it means writing 0, and the Q point will drop to 0V.
[0067] When the 5T-SRAM is in read mode, the word voltage switch of the selected 5T-SRAM always connects the supply voltage of the 5T-SRAM to a high voltage (0.9V) and pulls up WL WO To open the transmission gate. At this time, if the voltage on BL is 1, the read data is regarded as 1, and if the voltage on BL is 0, the read data is regarded as 0. In this embodiment, each BL is connected to an inverter, and the inverter is used to shape the read data into a rail-to-rail digital signal for use by the near-storage computing unit. This method not only ensures the correctness of the read, but also ensures that the unselected 5T-SRAM is always in a low-voltage holding mode, thereby minimizing power consumption.
[0068] In summary, by optimizing the power supply strategy, the power consumption is minimized while ensuring the normal operation of the memory. This low-power design is crucial for edge devices that rely on battery power, and can extend the use time of the device without sacrificing performance.
[0069] S400, performing a read, hold or write operation on the selected byte data according to the voltage state of the activated word line;
[0070] It should be noted that some embodiments also include:
[0071] For the write mode, data is written to the 5T-SRAM array, the word voltage switch is electrically connected to the low power supply voltage state, the binary address of the byte data to be processed is written into the byte decoder and the word line group selection module, so that the transmission gate of the activated word line is opened, and the byte data to be processed is input through the read-write bit line and distributed to the activated word line through the weight mapping network.
[0072] Specifically, to write data to the scalable 5T-SRAM array, the word voltage switch is set to the retention / write voltage (V DD,RW : 0.3V) electrically connected, the external input binary address is passed to the word line decoder and the word line group selection to open the transmission gate of the selected word line, and the data to be written is input by the bit line and distributed to the selected bit line through the weight mapping network.
[0073] For the read mode, the data is read out from the 5T-SRAM array, the word voltage switch is electrically connected to the high power supply voltage state, and the binary address of the byte data to be processed is written into the byte decoder and the word line group selection module, so that the transmission gate of the activated word line is opened, and the data is read out from the bit line of the 5T-SRAM array and transmitted to the calculation unit. According to the byte bit line readout configuration, the number of binary capacitors of the calculation unit is calculated. If the corresponding bit number is 1, the capacitor is connected, and if it is 0, the bit capacitor is disconnected. The calculation can be efficiently completed using the method of analog switch capacitor charge sharing, and read out using an analog-to-digital converter.
[0074] Specifically, to read data from the scalable 5T-SRAM array, the word voltage switch is set to the same voltage as the read voltage (V DD,R :0.9V) electrical connection, the external input binary address is passed to the word line decoder and the word line group selection to open the transmission gate of the selected word line, and the data to be read is output from the bit line to the calculation unit. If the resolution expansion calculation is performed, we can also repeat the same data twice to express the higher 1, and similarly, we can repeat it four times to express the higher 1 of the two bits, such as Figure 5 and Figure 6 shown.
[0075] In some specific embodiments, Figure 7As shown, the embodiments of the present invention provide a unique solution to the problem of read energy in traditional memories. When the word size of traditional 5-SRAM and 6T-SRAM is enlarged, the read energy will increase exponentially due to the increase in bit line capacitance, resulting in a sharp increase in power consumption. In order to solve this problem, a clustering method is adopted to divide the 128 word lines into 4 clusters, and the load capacitance of the bit lines is minimized by separating them. This design effectively reduces the read energy, and the read power is reduced by 2.5 times compared with the traditional 5T-SRAM; compared with the traditional 6T-SRAM, the read power is reduced by 10.7 times. This innovation significantly improves the energy efficiency of the memory and reduces the overall power consumption of the system.
[0076] like Figure 8 As shown, in 5T-SRAM, the word voltage switch needs to be adjusted accordingly as the word size expands to prevent the generation of read interference. However, conventional designs often lead to increased complexity and power consumption of the word voltage switch. The scalable 5T-SRAM proposed in the embodiment of the present invention reduces the word voltage switch width requirement by 34 times at 128 word lines through a clever design. This not only reduces the leakage power of the system (reduced by 7.2 times), but also simplifies the circuit design and improves the reliability and stability of the memory.
[0077] like Fig. 9 As shown in the figure, read latency is an important indicator of memory performance and directly affects the response speed of the system. The read latency of traditional memory is mainly determined by the bit line capacitance charging time. As the word size increases, the read latency will increase significantly. To overcome this problem, this technology successfully reduced the read latency by 2.3 times by reducing the bit line load capacitance. In addition, a method of inserting a pre-charge phase before reading is introduced. By presetting the bit line voltage to VCM, the bit line capacitance charging and discharging time is reduced, thereby further compressing the read latency and improving the access speed of the memory. This improvement enables the keyword detection system to respond to the user's voice commands more quickly, improving the user experience.
[0078] In summary, the 5T-SRAM architecture in the embodiment of the present invention has the following advantages:
[0079] 1) Low power consumption: Low power consumption of the memory is achieved by adopting low voltage power supply, optimizing read energy and reducing read interference. Compared with traditional memory, the power consumption is significantly reduced, which prolongs the battery life of the device and is particularly suitable for battery-powered edge devices.
[0080] 2) High performance: While reducing power consumption, the memory access speed and calculation accuracy are improved by improving read latency and supporting weight resolution expansion. This enables the keyword detection system to process voice data faster and improves the accuracy and real-time performance of keyword detection.
[0081] 3) Strong scalability: The design of the scalable 5T-SRAM array has good scalability, and can flexibly adjust the capacity and performance of the memory according to different application requirements. This scalability enables the technology to adapt to the growing keyword detection tasks and more complex models in the future.
[0082] 4) High area efficiency: Compared with traditional memory, 5T-SRAM reduces one transistor and one bit line, reducing area overhead. At the same time, through designs such as clustering and separating bit lines, the area efficiency of the memory is further improved, which is conducive to the miniaturization and integration of chips.
[0083] In addition, it should be noted that the embodiments of the present invention can be widely used in various voice-controlled edge devices, such as smart phones, smart speakers, smart home devices, etc. In these devices, keyword detection is a key technology for realizing voice interaction, and low-power, high-performance memory is an important basis for ensuring the stable operation of the keyword detection system. For example, in smart phones, scalable 5T-SRAM can provide fast and accurate keyword detection services for voice assistants, while reducing power consumption and extending the battery life of mobile phones. In smart speakers and smart home devices, this technology can achieve real-time response to user voice commands and enhance user experience. In addition, this technology can also be applied to other fields that require low-power, high-performance memory, such as Internet of Things devices, wearable devices, etc.
[0084] It can be understood that the contents of the above-mentioned architecture embodiments are all applicable to the present method embodiments, the functions specifically implemented by the present method embodiments are the same as those of the above-mentioned architecture embodiments, and the beneficial effects achieved are also the same as those achieved by the above-mentioned method embodiments.
[0085] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.
Claims
1. A scalable 5T-SRAM array architecture, characterized in that: The architecture includes a 5T-SRAM array, a byte decoder, a weight mapping network, a word line group selection module and a word voltage switch, wherein the byte decoder, the weight mapping network, the word line group selection module and the word voltage switch are electrically connected to the 5T-SRAM array respectively, wherein: The byte decoder is used to decode the byte data to be processed and obtain the selected byte data; The word line group selection module is used to activate the corresponding word line according to the selected byte data to obtain the activated word line; The weight mapping network is used to distribute the selected byte data to the activated word line; The word voltage switch is used to assign a corresponding voltage state to the activated word line; The 5T-SRAM array is used to read, hold or write the selected byte data according to the voltage state of the activated word line.
2. The architecture according to claim 1, characterized in that The 5T-SRAM array includes a plurality of 5T-SRAM cells.
3. The architecture according to claim 2, characterized in that: The 5T-SRAM unit includes an inverter module and an NMOS transmission gate, the inverter module includes a first inverter and a second inverter, wherein the first inverter and the second inverter are connected by cross-coupling, the drain of the NMOS transmission gate is connected to the inverter module, the gate of the NMOS transmission gate is connected to the read-write word line, and the source of the NMOS transmission gate is connected to the read-write bit line.
4. The architecture according to claim 1, characterized in that The word voltage switch includes a first NMOS transistor, a first PMOS transistor and a second PMOS transistor, wherein the drain of the first NMOS transistor is connected to a low power supply voltage, the source of the first PMOS transistor is connected to a high power supply voltage, the gate of the first NMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected to the read-write bit line, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first NMOS transistor is connected to the drain of the second PMOS transistor and connected to the read-write word line.
5. The architecture according to claim 1, characterized in that: The weight mapping network includes a sign bit decoder and a calculation unit, wherein the sign bit decoder is used to perform address decoding and data mapping processing on input data, and the calculation unit is used to perform weight calculation.
6. A control method for a scalable 5T-SRAM array architecture, characterized in that: The method comprises the following steps: Decoding the byte data to be processed and activating the corresponding word line according to the selected byte data to obtain the activated word line; allocating the selected byte data to the activated word line; assigning a corresponding voltage state to the activated word line; The selected byte data is read, held or written according to the voltage state of the activated word line.
7. The method according to claim 6, characterized in that The decoding process of the byte data to be processed and activating the corresponding word line according to the selected byte data to obtain the activated word line includes: Obtain the binary address of the byte data to be processed and decode it into a one-hot code, set the selected byte data to 1, and set the unselected byte data to 0, to obtain the selected byte data; The binary address of the word line is obtained and decoded into a one-hot code, and the word line is selected according to the selected byte data, and the selected word line is set to 1 and the unselected word line is set to 0 to obtain the activated word line.
8. The method according to claim 6, characterized in that The activated word line includes a holding mode, a writing mode or a reading mode, the voltage state includes a low power supply voltage state and a high power supply voltage state, and the corresponding voltage state is assigned to the activated word line, including: If the activated word line is in a holding mode or a writing mode, assigning the low power supply voltage state to the activated word line; If the activated word line is in a read mode, the high power supply voltage state is assigned to the activated word line.
9. The method according to claim 8, characterized in that Also includes: The corresponding voltage state is allocated to the activated word line, thereby adjusting the power supply voltage of the 5T-SRAM array, thereby realizing the write operation of the data single transmission gate.
10. The method according to claim 8, characterized in that Also includes: For the write mode, data is written into the 5T-SRAM array, the word voltage switch is electrically connected to the low power supply voltage state, the binary address of the byte data to be processed is written into the byte decoder and word line group selection module, so that the transmission gate of the activated word line is opened, and the byte data to be processed is input through the read and write bit lines and distributed to the activated word lines through the weight mapping network; For the read mode, data is read out from the 5T-SRAM array, the word voltage switch is electrically connected to the high power supply voltage state, and the binary address of the byte data to be processed is written into the byte decoder and word line group selection module, so that the transmission gate of the activated word line is opened, and the data is read out from the bit line of the 5T-SRAM array and transmitted to the computing unit.