Storage device

Abstract

A novel storage device is provided. A plurality of memory cells including two vertical transistors are connected in series. One of the two transistors is used as a transistor for writing information, and the other is used as a transistor for reading information written in the memory cell. The information written in the memory cell is held at the gate of the read transistor. A transistor having a small off-state current is used as the write transistor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input-output device, a driving method thereof, or a manufacturing method thereof can be cited. Background Art

[0003] In recent years, as the amount of data processed increases, semiconductor devices with larger storage capacity are needed. In order to increase the storage capacity per unit area, it is effective to stack storage cells (see Patent Document 1 and Patent Document 2). By stacking storage cells, the storage capacity per unit area can be increased according to the number of stacked storage cells. Patent Document 3 and Patent Document 4 disclose a storage device using an oxide semiconductor.

[0004] In Patent Documents 1 and 2, a plurality of memory elements (also referred to as memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also referred to as a memory string).

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0065270 [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0149004 [Patent Document 3] Japanese Patent Application Publication No. 2018-207038 [Patent Document 4] Japanese Patent Application Publication No. 2019-008862 Summary of the invention

[0006] In Patent Document 1, a semiconductor arranged in a columnar shape is in contact with an insulator including a charge accumulation layer. In Patent Document 2, a semiconductor arranged in a columnar shape is in contact with an insulator used as a tunneling medium. In both Patent Document 1 and Patent Document 2, information is written to a memory cell by extracting and injecting charges through an insulator. In this case, a trap center is sometimes formed at the interface where the semiconductor and the insulator are in contact. The trap center sometimes captures electrons, causing the threshold voltage (also called "Vth") of the transistor to vary. As a result, there is a possibility of a negative impact on the reliability of the memory device.

[0007] One of the purposes of one embodiment of the present invention is to provide a storage device with high reliability. One of the purposes of one embodiment of the present invention is to provide a storage device with large storage capacity. One of the purposes of one embodiment of the present invention is to provide a storage device with small occupied area. One of the purposes of one embodiment of the present invention is to provide a storage device with high storage density. One of the purposes of one embodiment of the present invention is to provide a storage device with low manufacturing cost. One of the purposes of one embodiment of the present invention is to provide a novel storage device. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with low manufacturing cost. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device.

[0008] Note that the description of these purposes does not prevent the existence of other purposes. Purposes other than the above can be extracted from the description of the specification, drawings, claims, etc. Note that one embodiment of the present invention does not need to achieve all of the above purposes and purposes other than the above. One embodiment of the present invention achieves at least one of the above purposes and purposes other than the above.

[0009] One embodiment of the present invention is a storage device, which includes n (n is an integer greater than 3) storage cells, a first wiring, n second wirings, n third wirings, and n fourth wirings, wherein the n storage cells each include a first transistor and a second transistor, and the first transistor and the second transistor each include a first conductive layer, a first insulating layer on the first conductive layer, a fourth conductive layer on the first insulating layer, a second insulating layer on the fourth conductive layer, a second conductive layer on the second insulating layer, a semiconductor layer having a region along the side of the fourth conductive layer, and a third conductive layer having a region along the side of the fourth conductive layer separated by the semiconductor layer, and the i-th (i is an integer greater than 2 and less than n-1) storage cell includes a first The second conductive layer of transistor [i] is electrically connected to the first wiring, the first conductive layer of the first transistor [i] is electrically connected to the third conductive layer of the second transistor [i] included in the i-th storage unit, the third conductive layer of the first transistor [i] is electrically connected to the i-th second wiring, the fourth conductive layer of the first transistor [i] is electrically connected to the i-th third wiring, the fourth conductive layer of the second transistor [i] is electrically connected to the i-th fourth wiring, the first conductive layer of the second transistor [i] is electrically connected to the second conductive layer of the second transistor [i-1] included in the i-1-th storage unit, and the second conductive layer of the second transistor [i] is electrically connected to the first conductive layer of the second transistor [i+1] included in the i+1-th storage unit.

[0010] The first transistor [i] and the second transistor [i] preferably have regions that overlap each other when viewed from a plane. The first conductive layer of the first transistor [i] can be used as the third conductive layer of the second transistor [i]. By providing a capacitor element electrically connected to the third conductive layer of the second transistor [i] in each of the n memory cells, information written to the memory cell can be more stably maintained.

[0011] According to one embodiment of the present invention, a storage device with high reliability can be provided. According to one embodiment of the present invention, a storage device with large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupied area can be provided. According to one embodiment of the present invention, a storage device with high storage density can be provided. According to one embodiment of the present invention, a storage device with low manufacturing cost can be provided. According to one embodiment of the present invention, a novel storage device can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing cost can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0012] Note that the description of these effects does not prevent the existence of other effects. Effects other than the above can be extracted from the description of the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of the above effects and effects other than the above. One embodiment of the present invention has at least one of the above effects and effects other than the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1A to 1C is a diagram showing an example of a circuit configuration of a semiconductor device; Figure 2 is a three-dimensional schematic diagram of a semiconductor device; Figure 3 This is a diagram when the semiconductor device is viewed from the X direction; Figure 4A is a plan view showing an example of a semiconductor device; FIG. 4B to FIG. 4E is a cross-sectional view showing an example of a semiconductor device; Figure 5 is a cross-sectional view showing an example of a semiconductor device; Fig. 6A is a diagram showing an example of a circuit configuration of a semiconductor device; Figure 6B is a plan view showing an example of a semiconductor device; Figure 6C is a perspective schematic diagram showing an example of a semiconductor device; Fig.6D This is a diagram when the semiconductor device is viewed from the Y direction; Fig. 6E This is a diagram when the semiconductor device is viewed from the X direction; Fig. 7Aand Figure 7B is a cross-sectional view showing an example of a semiconductor device; Figure 8 is a cross-sectional view showing an example of a semiconductor device; Fig.9A is a diagram showing an example of a circuit configuration of a semiconductor device; Fig. 9B is a plan view showing an example of a semiconductor device; Fig. 9C is a perspective schematic diagram showing an example of a semiconductor device; Fig.9D This is a diagram when the semiconductor device is viewed from the Y direction; Fig.9E This is a diagram when the semiconductor device is viewed from the X direction; Fig. 10A and Fig. 10B is a plan view showing an example of a semiconductor device; Fig.11A is a diagram showing an example of a circuit configuration of a semiconductor device; Fig. 11B is a plan view showing an example of a semiconductor device; Fig. 11C is a perspective schematic diagram showing an example of a semiconductor device; Fig.11D This is a diagram when the semiconductor device is viewed from the Y direction; Fig.11E This is a diagram when the semiconductor device is viewed from the X direction; Fig. 12A is a plan view showing an example of a semiconductor device; Fig. 12B is a cross-sectional view showing an example of a semiconductor device; Fig. 12C is a diagram showing an example of a circuit configuration of a semiconductor device; FIG. 13A to FIG. 13D is a diagram showing an example of a circuit configuration of a semiconductor device; Fig.14 is a timing chart showing an operation example of a semiconductor device; Fig.15 is a circuit diagram showing an operation example of a semiconductor device; Fig.16 is a circuit diagram showing an operation example of a semiconductor device; Fig.17 is a circuit diagram showing an operation example of a semiconductor device; Fig.18 is a circuit diagram showing an operation example of a semiconductor device; Fig.19 is a circuit diagram showing an operation example of a semiconductor device; Fig. 20 is a circuit diagram showing an operation example of a semiconductor device; Fig.21 is a circuit diagram showing an operation example of a semiconductor device; FIG. 22A to FIG. 22Dis a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention; FIG. 23A to FIG. 23D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention; Fig.24A and Fig. 24B is a diagram illustrating an example of a semiconductor device; Fig.25 is a cross-sectional view showing an example of a semiconductor device; Fig.26A and Fig.26B is a diagram showing various storage devices in a hierarchical manner; Fig.27A and Fig.27B is a diagram showing an example of an electronic component; FIG. 28A to FIG. 28C is a diagram showing an example of a large computer; Fig.28D is a diagram showing an example of a space device; Fig.28E is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0014] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different ways, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0015] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.) and a device having the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes include semiconductor devices.

[0016] In the drawings and the like of this specification, the size, thickness of a layer, or region may be exaggerated for ease of understanding. Therefore, the present invention is not necessarily limited to the size or aspect ratio, etc. in the drawings. Note that the drawings schematically show ideal examples, and therefore are not limited to the shapes, values, etc. shown in the drawings.

[0017] Note that in the structure of the invention in the embodiment, the same symbol is sometimes used in common in different drawings to show the same part or part with the same function, and repeated description is sometimes omitted. In addition, when showing parts with the same function, the same hatching is sometimes used without adding a special symbol. In addition, in order to facilitate understanding, the description of some constituent elements is sometimes omitted in a stereogram or a plan view, etc.

[0018] In this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion among constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, a constituent element with "first" in one embodiment of this specification, etc. may be a constituent element with "second" in other embodiments or claims, etc. In addition, for example, a constituent element with "first" in one embodiment of this specification, etc. may be omitted in other embodiments or claims, etc.

[0019] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper", "lower", "above" or "below" are sometimes used to illustrate the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located on the bottom surface of a conductor".

[0020] In addition, the words "above" and "below" do not limit the positional relationship of the components to the situation where they are directly above or below and in direct contact. For example, if it is expressed as "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the situation where other components are included between insulating layer A and electrode B may also be included.

[0021] In this specification, the words "overlap" and the like do not limit the state of the stacking order of the constituent elements. For example, when it is expressed as "electrode B overlapping with insulating layer A", it is not limited to the state where electrode B is formed on insulating layer A, and may also include the state where electrode B is formed under insulating layer A or the state where electrode B is formed on the right side (or left side) of insulating layer A, etc.

[0022] In this specification, the words "adjacent" and "close to" are not limited to the state where the components are in direct contact. For example, if it is expressed as "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are in direct contact, and it may also include the case where other components are included between insulating layer A and electrode B.

[0023] In addition, in this specification, etc., the words "film" and "layer" can be interchanged depending on the situation. For example, "conductive layer" can sometimes be replaced with "conductive film". For example, "insulating film" can sometimes be replaced with "insulating layer". Or, depending on the situation or state, the words "film", "layer" and the like are not used and can be replaced with other words. For example, "conductive layer" or "conductive film" can sometimes be replaced with "conductor". Or, "conductor" can sometimes be replaced with "conductive layer" or "conductive film". For example, "insulating layer" or "insulating film" can sometimes be replaced with "insulator". Or, "insulator" can sometimes be replaced with "insulating layer" or "insulating film".

[0024] Note that voltage refers to the potential difference between two points, while potential refers to the electrostatic energy (potential energy) of a unit charge in an electrostatic field at a certain point. Note that, in general, the potential difference between the potential of a certain point and a reference potential (e.g., ground potential) is referred to as potential or voltage, and potential and voltage are synonymous in many cases. Therefore, in this specification, except for special cases, potential may be referred to as voltage, and voltage may be referred to as potential.

[0025] In this specification, etc., the words "electrode", "wiring", "terminal", etc. do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, an "electrode" or a "wiring" includes a case where a plurality of "electrodes" or a plurality of "wirings" are formed as one body, etc. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode, and vice versa. Furthermore, the word "terminal" includes a case where a plurality of "electrodes", a plurality of "wirings", a plurality of "terminals", etc. are formed as one body, etc. Thus, for example, an "electrode" can be a part of a "wiring" or a "terminal", and, for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, sometimes the words "electrode", "wiring", "terminal", etc. are replaced with words "region", "conductive layer", etc.

[0026] In this specification, etc., depending on the situation or status, the words "wiring", "signal line, "power line", etc. can sometimes be interchanged. For example, "wiring" can sometimes be replaced with "signal line". In addition, for example, "wiring" can sometimes be replaced with "power line", etc. Vice versa, "signal line", "power line" can sometimes be replaced with "wiring". Sometimes "power line" etc. can be replaced with "signal line", etc. Vice versa, "signal line" etc. can sometimes be replaced with "power line", etc. In addition, depending on the situation or status, the "potential" applied to the wiring can be replaced with "signal", etc. Vice versa, "signal", etc. can sometimes be replaced with "potential".

[0027] In this specification, "source" refers to a source region or a source electrode. The source region refers to a region in a semiconductor layer whose resistivity is less than a certain value. The source electrode refers to a conductive layer having a portion connected to the source region.

[0028] In this specification, "drain" refers to a drain region or a drain electrode. The drain region refers to a region in a semiconductor layer whose resistivity is less than a certain value. The drain electrode refers to a conductive layer having a portion connected to the drain region.

[0029] In this specification, when it is clearly stated that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to the specified connection relationship such as the connection relationship shown in the drawings or text, and also includes the connection relationship other than the connection relationship shown in the drawings or text.

[0030] As an example of a case where X and Y are electrically connected, there is a case where one or more elements (for example, switches, transistors, inductors, resistors, etc.) capable of electrically connecting X and Y are connected between X and Y.

[0031] As an example of a case where X and Y are functionally connected, there is a case where one or more circuits that can realize the functional connection between X and Y are connected between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), a level conversion circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.). In addition, as an example, even if another circuit is included between X and Y, it can be said that X and Y are functionally connected when a signal output from X is transmitted to Y.

[0032] In this specification, etc., "parallel" refers to a state in which two straight lines are arranged at an angle of more than -10° and less than 10°. Therefore, a state in which the angle is more than -5° and less than 5° is also included. In addition, "approximately parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of more than -15° and less than 15°. In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of more than 80° and less than 100°. Therefore, a state in which the angle is more than 85° and less than 95° is also included. In addition, "approximately perpendicular" or "roughly perpendicular" refers to a state in which two straight lines are arranged at an angle of more than 60° and less than 120°.

[0033] In addition, in many cases, voltage means the potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, voltage and potential can be interchanged in many cases. In this specification, etc., voltage and potential can be interchanged unless otherwise specified.

[0034] In this specification, the "on state" of a transistor refers to a state where the source and drain of the transistor are electrically short-circuited (also referred to as a "conductive state"). In addition, the "off state" of a transistor refers to a state where the source and drain of the transistor are electrically disconnected (also referred to as a "non-conductive state").

[0035] In addition, in this specification, etc., "on-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, "off-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0036] In addition, unless otherwise stated, the transistors shown in this specification are enhanced (normally closed) n-channel field effect transistors. Therefore, their threshold voltage is greater than 0V. In addition, unless otherwise stated, sometimes "supplying a potential H to the gate of the transistor" means "putting the transistor in an on state. In addition, unless otherwise stated, sometimes "supplying a potential L to the gate of the transistor" means "putting the transistor in an off state".

[0037] In this specification, etc., the potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor"), and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). In addition, the potential L is a potential that turns off an n-type transistor, and turns on a p-type transistor. Therefore, the potential H is a higher potential than the potential L.

[0038] In the drawings, in order to clearly indicate the potential of wiring, electrodes, etc., "H" indicating the potential H or "L" indicating the potential L is sometimes attached to a position adjacent to the wiring, electrodes, etc. In addition, "H" or "L" is attached to the wiring, electrodes, etc. whose potential changes in the form of a frame. In addition, when a transistor is in an off state, "×" is sometimes attached to overlap with the transistor. In addition, an arrow indicating the direction in which the current flows is sometimes attached.

[0039] In this specification, unless otherwise stated, the terms "same", "identical", "equal", or "uniform" (including synonyms of these terms) for count values ​​and measurement values ​​include an error of ±10%.

[0040] In addition, in the drawings of this specification, arrows indicating the X direction, Y direction, and Z direction are sometimes attached. In this specification, "X direction" refers to the direction along the X axis, and unless otherwise stated, the forward and reverse directions are sometimes not distinguished. The same applies to "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that intersect each other. More specifically, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, one of the X direction, Y direction, and Z direction is sometimes referred to as the "first direction". In addition, the other one of the above directions is sometimes referred to as the "second direction". In addition, the remaining one of the above directions is sometimes referred to as the "third direction".

[0041] Generally speaking, a "capacitor" has a structure in which two electrodes are opposite to each other via an insulator (dielectric). In this specification, etc., a "capacitor element" includes the above-mentioned capacitor. That is, in this specification, etc., a "capacitor element" includes a structure in which two electrodes are opposite to each other via an insulator, a structure in which two wirings are opposite to each other via an insulator, or a structure in which two wirings are arranged via an insulator.

[0042] In this specification, when the same symbol is used for multiple components, especially when it is necessary to distinguish them, the symbol is sometimes displayed with an identification symbol such as "A", "b", "_1", "[n]", "[m, n]", etc.

[0043] Note that ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between constituent elements, and do not indicate a certain order or sequence such as the process sequence or the stacking sequence. In addition, in order to avoid confusion between constituent elements, even if there are no ordinal numbers in this specification, ordinal numbers may be added to them in the claims. In addition, even if there are ordinal numbers in this specification, ordinal numbers different from those in the claims may be added to them. In addition, even if there are ordinal numbers in this specification, ordinal numbers may be omitted in the claims.

[0044] Note that in this specification, one of a source and a drain of a transistor may be referred to as a “first terminal”, and the other of a source and a drain of a transistor may be referred to as a “second terminal”.

[0045] Implementation Method 1 A memory cell 10 and a memory string 100 including the memory cell 10 according to one embodiment of the present invention will be described.

[0046] <Memory string configuration example> Figure 1A A circuit configuration example of a memory string 100 including n (n is an integer greater than or equal to 2) memory cells 10 is shown. Figure 23 is a schematic three-dimensional diagram of the memory string 100 when n is 3. The memory string 100 extends in the Z direction. The Z direction is, for example, a direction perpendicular to a substrate (not shown). Figure 3 From the X direction Figure 2 A schematic diagram of a memory string 100 is shown.

[0047] The memory string 100 includes n (n is an integer greater than or equal to 3) memory cells 10 , n wirings WWL, n wirings COM, n wirings WBG, n wirings RBG, wirings RBL, wirings WBL, wirings SL, transistors 121 , and transistors 122 .

[0048] The n memory cells 10 are provided between the transistor 121 and the transistor 122. In this specification, the first (also referred to as "first-level") memory cell 10 is referred to as memory cell 10[1], the second-level memory cell 10 is referred to as memory cell 10[2], and the n-th-level memory cell 10 is referred to as memory cell 10[n]. In addition, the i-th-level (i is an integer greater than or equal to 2 and less than or equal to n-1) memory cell 10 is referred to as memory cell 10[i]. Note that the other components are described similarly.

[0049] The memory cell 10 includes a transistor WTr, a transistor RTr, and a capacitor Cs. Figures 1A to 1C In the embodiment, the transistor WTr in the memory cell 10[1] is referred to as the transistor WTr[1], the transistor RTr in the memory cell 10[1] is referred to as the transistor RTr[1], and the capacitor Cs in the memory cell 10[1] is referred to as the capacitor Cs[1].

[0050] In addition, the wiring COM, wiring RBG, and wiring WWL connected to the memory cell 10 [ 1 ] are referred to as wiring COM [ 1 ], wiring RBG [ 1 ], and wiring WWL [ 1 ], respectively.

[0051] In addition, the transistor WTr in the memory cell 10[i] is referred to as the transistor WTr[i], the transistor RTr in the memory cell 10[i] is referred to as the transistor RTr[i], and the capacitor Cs in the memory cell 10[i] is referred to as the capacitor Cs[i]. In addition, the wiring WBL, wiring COM, wiring RBG, and wiring WWL connected to the memory cell 10[i] are referred to as wiring WBL[i], wiring COM[i], wiring RBG[i], and wiring WWL[i], respectively.

[0052] Similarly, the transistor WTr in the memory cell 10[n] is referred to as the transistor WTr[n], the transistor RTr in the memory cell 10[n] is referred to as the transistor RTr[n], and the capacitor Cs in the memory cell 10[n] is referred to as the capacitor Cs[n]. In addition, the wiring COM, wiring RBG, and wiring WWL connected to the memory cell 10[n] are referred to as wiring COM[n], wiring RBG[n], and wiring WWL[n], respectively.

[0053] As transistors WTr and RTr, transistors including a gate and a back gate are used. The gate and the back gate are configured in a manner that sandwiches the channel formation region of the semiconductor layer. In addition, both the gate and the back gate are formed using a conductive layer or a semiconductor layer with low resistivity. The back gate can have the same function as the gate. In the case of using the gate to control the on state and the off state of the transistor, the potential of the back gate can be the same potential as the gate, or it can be a ground potential (GND) or an arbitrary potential. In addition, when the transistor is in the on state, by supplying the potential H to both the gate and the back gate, the on-state current can be further increased compared to the case where the potential H is supplied to only one of the gate and the back gate. In addition, by making the potential of the back gate change independently without being linked to the gate, the threshold voltage of the transistor can be changed. In addition, since the gate and the back gate are formed using a conductive layer or a semiconductor layer with low resistivity, they have the function of preventing the electric field generated outside the transistor from affecting the semiconductor forming the channel (especially the electric field shielding function for static electricity, etc.). By providing a back gate in addition to the gate, the characteristics of the transistors can be reduced.

[0054] In the memory cell 10, the first terminal of the transistor WTr is connected to the gate of the transistor RTr and one electrode of the capacitor Cs, and the second terminal is connected to the wiring WBL. The gate of the transistor WTr is connected to the wiring WWL, and the back gate of the transistor WTr is connected to the wiring WBG. The back gate of the transistor RTr is connected to the wiring RBG. The other electrode of the capacitor Cs is connected to the wiring COM. The region to which the first terminal of the transistor WTr, the gate of the transistor RTr, and one electrode of the capacitor Cs are connected is used as a holding node SN.

[0055] Note that the connection destination of the first terminal of the transistor RTr included in the memory cell 10 differs depending on the number of stages of the memory cell 10 in which the transistor RTr is located. The first terminal of the transistor RTr included in the memory cell 10[1] (transistor RTr[1]) is connected to the transistor 121, and the first terminal of the transistor RTr included in the memory cell 10[n] (transistor RTr[n]) is connected to the transistor 122.

[0056] Specifically, the first terminal of the transistor 121 is connected to the wiring SL, and the second terminal is connected to the wiring WBL and the first terminal of the transistor RTr[1]. In addition, the first terminal of the transistor RTr[n] is connected to the second terminal of the transistor RTr (transistor RTr[n-1]) included in the memory cell 10[n-1], and the second terminal of the transistor RTr[n] is connected to the first terminal of the transistor 122. In addition, the second terminal of the transistor 122 is connected to the wiring RBL.

[0057] In addition, the first terminal of the transistor RTr (transistor RTr[i]) included in the memory cell 10[i] is connected to the second terminal of the transistor RTr[i-1]. The second terminal of the transistor RTr[i] is connected to the first terminal of the transistor RTr[i+1].

[0058] Notice, Figure 1A 1 and 122 are transistors each including a back gate. The back gate may be used independently of the gate or may be used as shown in FIG. Figure 1B The gate of transistor 121 is connected to the back gate as shown. Figure 1C As shown, transistors that do not include a back gate may also be used.

[0059] Figure 2 and Figure 3 The following example is shown: the second terminal of transistor 121 is connected to the first terminal of transistor RTr[1] (conductive layer 220R[1]) through conductive layer 246[0], the second terminal of transistor RTr[1] (conductive layer 240R[1]) is connected to the first terminal of transistor RTr[2] (conductive layer 220R[2]) through conductive layer 246[1], and the second terminal of transistor RTr[2] (conductive layer 240R[2]) is connected to the first terminal of transistor RTr[3] (conductive layer 220R[3]) through conductive layer 246[2]. In addition, when Figure 2 and Figure 3 In the illustrated memory string 100 , when n=3, the second terminal (conductive layer 240R[ 3 ]) of transistor RTr[ 3 ] is connected to the first terminal of transistor 122 via conductive layer 246[ 3 ].

[0060] The first terminal of the transistor 122 is connected to the second terminal of the transistor 121 via the channel formation regions of the transistors RTr[1] to RTr[n]. Therefore, the transistor 121, the transistor 122, and the transistors RTr[1] to RTr[n] are connected in series.

[0061] Furthermore, second terminals of the transistors WTr[1] to WTr[n] are respectively connected to one another. Figure 2 and Figure 3 An example is shown in which the second terminal (conductive layer 240W[1]) of transistor WTr[1] is connected to the second terminal (conductive layer 240W[2]) of transistor WTr[2] via conductive layer 245[2], and the second terminal (conductive layer 240W[2]) of transistor WTr[2] is connected to the second terminal (conductive layer 240W[3]) of transistor WTr[3] via conductive layer 245[3]. In addition, Figure 2 and Figure 3 An example is shown in which the second terminal of the transistor WTr[ 1 ] is connected to the second terminal of the transistor 121 through the conductive layer 245 [ 1 ].

[0062] Each of the plurality of conductive layers 245 is used as a part of the wiring WBL. In addition, a part of the second terminal of each of the plurality of transistors WTr is used as a part of the wiring WBL.

[0063] The memory string 100 is used as a NAND type memory device in which a plurality of memory cells 10 are connected in series.

[0064] <Structural Example of Transistor> Reference FIG. 4A to FIG. 4E and Figure 5 An example of the structure of the transistor 200 which can be used for the transistor WTr and the transistor RTr included in the memory cell 10 is described.

[0065] Figure 4A is a plan view of transistor 200 . Figure 4B and Figure 5 All along Figure 4A A cross-sectional view along the dashed line A1-A2 is shown. Figure 5 yes Figure 4B An enlarged view of the structure of each layer is shown in detail. Figure 4C It is along Figure 4A A cross-sectional view along the dashed line A3-A4 is shown. Figure 4D It is along Figure 4B and Figure 4C A cross-sectional view along the dashed line A5-A6 is shown. Figure 4D It can also be said to be a cross-sectional view taken along the XY plane including the insulating layer 280 a . Figure 4E It is along Figure 4B and Figure 4C A cross-sectional view along the dashed line A7-A8 is shown. Figure 4E It can also be said that it is a cross-sectional view of the XY plane including the conductive layer 255. Note that for the sake of clarity, Figure 4A Some components are omitted in the plan view of the previous figure. Sometimes some components are also omitted in the subsequent plan view.

[0066] FIG. 4A to FIG. 4E and Figure 5The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280a on the insulating layer 210, and an insulating layer 280b on the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b serve as interlayer films.

[0067] Transistor 200 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 255 on the insulating layer 280a, a conductive layer 240a on the insulating layer 280b, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, a conductive layer 265a on the insulating layer 250, and a conductive layer 265b on the conductive layer 265a.

[0068] Note that in this specification, the conductive layer 220a and the conductive layer 220b are sometimes collectively referred to as the conductive layer 220. Also, the conductive layer 240a and the conductive layer 240b are sometimes collectively referred to as the conductive layer 240. Also, the conductive layer 265a and the conductive layer 265b are sometimes collectively referred to as the conductive layer 265.

[0069] In transistor 200, semiconductor layer 230 is used as a semiconductor layer, conductive layer 265 is used as a first gate electrode, insulating layer 250 is used as a first gate insulating layer, conductive layer 220 is used as one of a source electrode and a drain electrode, conductive layer 240 is used as the other of the source electrode and the drain electrode, conductive layer 255 is used as a second gate electrode, and insulating layer 235 is used as a second gate insulating layer. In addition, conductive layer 265 is also used as a gate wiring.

[0070] When the conductive layer 265 is used as a gate electrode, the conductive layer 255 is used as a back gate electrode. In this case, the insulating layer 250 is used as a gate insulating layer, and the insulating layer 235 is used as a back gate insulating layer. Note that when the conductive layer 265 is used as a back gate electrode, the conductive layer 255 is used as a gate electrode.

[0071] In addition, the transistor 200 has a structure in which the channel formation region is surrounded by an electric field of the conductive layer 255 which can function as a gate electrode. Therefore, this structure can be said to be a type of GAA (Gate All Around) structure.

[0072] The semiconductor layer 230 has a region overlapping with the conductive layer 255 via the insulating layer 235 and a region overlapping with the conductive layer 265 via the insulating layer 250. At least one of the above regions is used as a channel formation region of the transistor 200. One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 is used as a source region, and the other is used as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0073] like Figure 4B and Figure 4C As shown, openings 290 that reach the conductive layer 220 are provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0074] The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and the conductive layer 220b is provided with a recess. In other words, the conductive layer 220 has a recess, the bottom surface of the recess is equivalent to the bottom surface of the recess of the conductive layer 220b, and the side surface of the recess is equivalent to the side surface of the recess of the conductive layer 220b. Specifically, the conductive layer 220b includes a first recess and a second recess located outside the first recess. The depth of the first recess is deeper than the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then the first recess is provided in the conductive layer 220b while processing the insulating layer 235. Thus, in Figure 4B The side surface of the first recess is aligned with the surface of the insulating layer 235 on the semiconductor layer 230 side, and the side surface of the second recess is aligned with the side surface of the insulating layer 280a on the opening 290 side. Hereinafter, the first recess and the second recess are sometimes collectively referred to as recesses.

[0075] The opening 290 overlaps with the concave portion of the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the concave portion of the conductive layer 220b, and the sidewalls of the opening 290 include the side surfaces of the concave portion of the conductive layer 220b, the side surfaces of the insulating layer 280a, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 280b, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b.

[0076] The openings 290 include the openings included in the insulating layer 280a, the openings included in the conductive layer 255, the openings included in the insulating layer 280b, the openings included in the conductive layer 240a, and the openings included in the conductive layer 240b. In other words, the openings included in the insulating layer 280a in the region overlapping with the conductive layer 220a are part of the openings 290, the openings included in the conductive layer 255 in the region overlapping with the conductive layer 220a are another part of the openings 290, the openings included in the insulating layer 280b in the region overlapping with the conductive layer 220a are another part of the openings 290, the openings included in the conductive layer 240a in the region overlapping with the conductive layer 220a are another part of the openings 290, and the openings included in the conductive layer 240b in the region overlapping with the conductive layer 220a are another part of the openings 290. In addition, the shapes and sizes of the openings 290 of each layer may be different when viewed from above. Furthermore, when the top surface shape of the opening 290 is circular, the openings in each layer may be concentric circles or may not be concentric circles.

[0077] At least a part of the components of the transistor 200 is disposed in the opening 290 . Specifically, the insulating layer 235 , the semiconductor layer 230 , the insulating layer 250 , and the conductive layer 265 are disposed so that at least a part of each is located in the opening 290 .

[0078] The insulating layer 235 has a region located between the semiconductor layer 230 and the conductive layer 255. The semiconductor layer 230 has a region in contact with the insulating layer 235 in the opening 290.

[0079] exist Figure 4B In the embodiment of the present invention, the insulating layer 235 has a region in contact with the bottom surface of the second concave portion of the conductive layer 220 and a region in contact with the side surface of the second concave portion of the conductive layer 220. In addition, the insulating layer 235 has a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the conductive layer 255, a region in contact with the side surface of the insulating layer 280b, a region in contact with the side surface of the conductive layer 240a, and a region in contact with the side surface of the conductive layer 240b in the opening 290. The semiconductor layer 230 has a region in contact with the bottom surface of the first concave portion of the conductive layer 220, a region in contact with the side surface of the first concave portion of the conductive layer 220, a region in contact with the insulating layer 235, and a region in contact with the top surface of the conductive layer 240b. The insulating layer 250 is located inside the semiconductor layer 230 in the opening 290, and the conductive layer 265a is located inside the insulating layer 250 in the opening 290.

[0080] The insulating layer 235 is provided along at least a portion of the side wall of the opening 290. In addition, the portions of the semiconductor layer 230 and the insulating layer 250 disposed in the opening 290 are provided to reflect the shape of the opening 290. Specifically, the semiconductor layer 230 is provided to cover the bottom and the side wall of the opening 290, and the insulating layer 250 is provided to cover the semiconductor layer 230. Thus, the conductive layer 265a is provided to fit into at least a portion of the concave portion of the insulating layer 250 reflecting the shape of the opening 290.

[0081] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is disposed in the opening 290. When the conductive layer 265 has a stacked structure, as the transistor 200 is miniaturized, the diameter of the opening 290 becomes smaller, and it becomes more difficult to arrange all the layers constituting the conductive layer 265 in the opening 290. Figure 4B and Figure 4C , an example is shown in which the conductive layer 265 has a two-layer structure, only the conductive layer 265a is provided in the opening 290, and the conductive layer 265b on the conductive layer 265a is provided at a position overlapping with the opening 290. Note that depending on the diameter of the opening 290 and the thickness of the conductive layer 265a, sometimes both the conductive layer 265a and the conductive layer 265b are located in the opening 290.

[0082] In the case where the conductive layer 220b includes a recessed portion at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 in the opening 290 and the height of the bottom surface of the conductive layer 265a can be made lower than the height of the top surface of the conductive layer 220b in contact with the insulating layer 280a based on the top surface of the insulating layer 210, compared with the case where the recessed portion is not included. Here, the height of each surface can be determined based on the surface on which the transistor is formed. Here, the top surface of the insulating layer 210 is used as a reference. The surface used for the reference is not limited to the surface on which the transistor is formed. For example, the top surface of the substrate on which the transistor or the semiconductor device is provided can also be used as a reference.

[0083] like Figure 5 As shown, the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220b in contact with the insulating layer 280a is preferably greater than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. As a result, the contact area between the side surface of the conductive layer 220b and the semiconductor layer 230 can be increased, and the contact resistance between the conductive layer 220b and the semiconductor layer 230 can be reduced. Therefore, the decrease in the on-state current of the transistor 200 caused by the contact resistance between the conductive layer 220b and the semiconductor layer 230 can be suppressed. The shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0084] In addition, if Figure 5 As shown, the shortest distance Tc is more preferably greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 265a, and is further preferably greater than the shortest distance Tb. As a result, the entire region of the semiconductor layer 230 sandwiched between the source region and the drain region is applied with an electric field from the conductive layer 265a. In other words, the entire channel formation region of the semiconductor layer 230 is applied with an electric field from the conductive layer 265a, thereby increasing the on-state current of the transistor 200. As a result, the transistor 200 can have good electrical characteristics. In addition, the gate electric field is also easily applied to the region of the semiconductor layer 230 that contacts the conductive layer 220b, which can further increase the on-state current of the transistor 200. In addition, regardless of whether any of the conductive layer 220 and the conductive layer 240 is used as a drain electrode, the transistor 200 can have good electrical characteristics. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 265a in the opening 290.

[0085] The semiconductor layer 230 contacts the bottom and side surfaces of the recessed portion of the conductive layer 220b and the top surface of the conductive layer 240b. When the conductive layer 220b includes the recessed portion, the area of ​​the semiconductor layer 230 in contact with the conductive layer 220b can be increased. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0086] When an oxide semiconductor, which is one of metal oxides, is used as the semiconductor layer 230, a conductive material containing oxygen is preferably used for the conductive layer 220b. This can reduce the contact resistance between the semiconductor layer 230, which is an oxide semiconductor, and the conductive layer 220b.

[0087] The conductive material containing oxygen has low contact resistance with the oxide semiconductor, and therefore, when the conductive layer 220 and the conductive layer 240 have a stacked-layer structure, the conductive material containing oxygen is preferably used for the layer having the largest contact area with the semiconductor layer 230 which is an oxide semiconductor in the stacked-layer structure. Thus, for example, the conductive material containing oxygen is preferably used for the conductive layer 220b and the conductive layer 240b.

[0088] In addition, when the conductive layer 220 and the conductive layer 240 have a stacked-layer structure, by using a conductive material containing oxygen in the layer closest to the channel formation region in the stacked-layer structure, the on-state current of the transistor using an oxide semiconductor for the semiconductor layer 230 can be increased. Therefore, for example, a conductive material containing oxygen can be used for the conductive layer 220b and the conductive layer 240a.

[0089] As the conductive material containing oxygen, a metal oxide having conductivity (also referred to as “oxide conductor”) is preferably used.

[0090] Figure 4BThe structure in which the ends of the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 are aligned outside the opening 290 is shown. The conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 can be manufactured using the same mask and the same process. Therefore, the number of masks required when manufacturing a semiconductor device can be reduced. Note that any of the ends of the semiconductor layer 230, the ends of the conductive layer 240a, and the ends of the conductive layer 240b can be located inside or outside the other ends in the X direction or the Y direction.

[0091] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. In addition, the conductive layer 240 is preferably not located inside the opening 290 included in the insulating layer 280b and the like. In other words, the conductive layer 240 preferably does not have a region in contact with the side surface of the insulating layer 280b in the opening 290. By adopting such a structure, the opening 290 can be formed in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a at one time. In addition, when the side surface of the conductive layer 240, the side surface of the insulating layer 280b, the side surface of the conductive layer 255, and the side surface of the insulating layer 280a are aligned in the opening 290, the thickness distribution of the insulating layer 235, the semiconductor layer 230, and the like provided inside the opening 290 can be made uniform. In addition, the insulating layer 235, the semiconductor layer 230, and the like can be prevented from being disconnected due to the step or the like of the conductive layer 240 and the insulating layer 280b.

[0092] Note that Figure 4B and Figure 4C 2 shows a structure in which the side surface of the conductive layer 240 in the opening 290 is flush with the side surface of the insulating layer 280b in the opening 290 (it can also be said to be aligned or roughly aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 may also be discontinuous. In addition, the inclination of the side surface of the conductive layer 240 in the opening 290 may also be different from the inclination of the side surface of the insulating layer 280b in the opening 290. In this case, for example, the taper angle of the side surface of the conductive layer 240 in the opening 290 is preferably smaller than the taper angle of the side surface of the insulating layer 280b in the opening 290. By adopting this structure, the coverage of the semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 can be improved, and defects such as voids can be reduced. In addition, in the case where both the insulating layer 280a and the insulating layer 280b have a stacked structure, the inclination of the side surface of each layer in the opening 290 may also be different. Similarly, when the conductive layer 240 has a stacked-layer structure, the inclinations of the side surfaces of the layers in the opening 290 may be different.

[0093] As the semiconductor layer 230 forming the channel, an oxide semiconductor is preferably used. In this specification, a transistor using an oxide semiconductor as a semiconductor layer forming a channel is also referred to as an "OS transistor". Since the band gap of an oxide semiconductor is greater than 2 eV, the off-state current is significantly small. Therefore, by using an OS transistor as the transistor WTr, the data written to the retention node SN can be maintained for a long period of time.

[0094] In addition, the OS transistor operates stably even in a high temperature environment, and the characteristics vary little. For example, even in a high temperature environment, its off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, its off-state current hardly increases. In addition, even in a high temperature environment, the on-state current is not easy to decrease. In addition, the insulation withstand voltage between the source and the drain of the OS transistor is high. Therefore, a storage circuit or storage element (also called "OS memory") using an OS transistor operates stably even in a high temperature environment, and high reliability can be obtained.

[0095] In addition, the OS memory has less variation in electrical characteristics due to exposure to radiation such as cosmic rays, that is, soft errors due to radiation are less likely to occur in the OS memory, so the OS memory has high reliability.

[0096] By using the OS transistor for both the transistor WTr and the transistor RTr, a highly reliable memory element can be realized.

[0097] On the other hand, in an OS transistor, when oxygen vacancies (V O ) and impurities, the electrical characteristics are easily changed, which may lead to a decrease in reliability. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor tends to become a normally-on characteristic. Therefore, in the channel formation region of the oxide semiconductor, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region in the oxide semiconductor is reduced to make it i-type (intrinsic) or substantially i-type.

[0098] On the other hand, the source region and the drain region of the OS transistor are preferably regions where there are more oxygen vacancies than in the channel formation region and V O In other words, the source and drain regions of the OS transistor are preferably n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0099] As described above, the semiconductor layer 230 is provided inside the opening 290. In addition, one of the source electrode and the drain electrode of the transistor 200 (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located above, so that current flows in the vertical direction. In other words, a channel is formed along the side of the opening 290.

[0100] That is, transistor 200 is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. The source region and the drain region of transistor 200 are arranged at different heights from each other. In other words, the source region and the drain region of transistor 200 are respectively arranged at different positions in the Z direction. This transistor is also called a "vertical channel transistor", "vertical channel transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0101] Compared with the existing transistor (for example, a planar transistor) in which a channel formation region, a source region, and a drain region are respectively provided on the XY plane, the vertical transistor can reduce the occupied area. Thus, by using a vertical channel transistor, the occupied area of ​​the memory cell 10 can be reduced. Therefore, the occupied area of ​​the memory device including the memory cell 10 can be reduced. In addition, the storage density of the memory device including the memory cell 10 can be improved. In addition, the storage capacity per unit area of ​​the semiconductor device using the memory cell 10 can be increased. In addition, by using a vertical channel transistor in a semiconductor device, the semiconductor device can be reduced in area and highly integrated.

[0102] Reference Figure 4D and Figure 4E The positional relationship of each layer in the opening 290 is described. The insulating layer 235 is in contact with the outer surface of the semiconductor layer 230. The conductive layer 255 surrounds the entire periphery of the semiconductor layer 230 via the insulating layer 235. In addition, the insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The semiconductor layer 230 surrounds the entire periphery of the conductive layer 265a via the insulating layer 250. Therefore, the channel formation region of the transistor 200 may be formed on the entire outer surface of the semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235). Note that Figure 4E It can also be said that it is a cross-sectional view taken along the XY plane including the channel formation region of the semiconductor layer 230 .

[0103] The channel length of the transistor 200 can be regarded as the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280a, the conductive layer 255, and the insulating layer 280b on the conductive layer 220. That is, it can be said that the channel formation region of the semiconductor layer 230 has a region overlapping with the side surface of the insulating layer 280a, a region overlapping with the side surface of the conductive layer 255, and a region overlapping with the side surface of the insulating layer 280b.

[0104] The transistor 200 includes a conductive layer 255 serving as a back gate, so the threshold voltage of the transistor 200 can be controlled by a potential applied to the conductive layer 255. At this time, the portion of the semiconductor layer 230 that overlaps with the conductive layer 255 through the insulating layer 235 is most susceptible to the influence of the conductive layer 255. Figure 5 , the semiconductor layer 230 is divided into three regions: a region 230n+, a region 230n−, and a region 230i. The region 230i corresponds to a portion of the semiconductor layer 230 that overlaps with the conductive layer 255 via the insulating layer 235.

[0105] Region 230n+ is formed in the semiconductor layer 230 in a region in contact with the conductive layer 240b or the conductive layer 220b and in the vicinity thereof, and can be referred to as a source region or a drain region. The source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region.

[0106] The region 230i is a region in the semiconductor layer 230 that overlaps with the conductive layer 255 via the insulating layer 235 and overlaps with the conductive layer 265a via the insulating layer 250. The region 230i is used as a channel formation region. The channel formation region is preferably controlled by applying a potential to the conductive layer 255 so as to be i-type (intrinsic) or substantially i-type.

[0107] The region 230n- is preferably a region whose resistance is higher than the region 230n+ and lower than the region 230i. However, when there is a region with high resistance between the region 230i and the region 230n+, there is a concern that the on-state current of the transistor 200 will decrease. By forming the region 230n- as a region with low resistance, the on-state current of the transistor 200 can sometimes be increased. In addition, the region 230n- is sometimes used as a channel formation region.

[0108] As described above, when the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be said to be the length L1. On the other hand, since the region 230n- is a region with a lower resistance than the region 230i, the channel formation region of the transistor 200 can be regarded as the region 230i controlled by the conductive layer 255 so as to become a region with a higher resistance. In this case, the channel length of the transistor 200 can be regarded as the length L0 of the region 230i shorter than the length L1. At this time, the length L0 can be said to be the effective channel length of the transistor 200.

[0109] When the resistance of region 230n- is low and the effective channel length of transistor 200 is small, transistor 200 tends to have a normally-on characteristic. On the other hand, a transistor of one embodiment of the present invention includes a back gate. By supplying a potential below the source potential or a potential below 0V (preferably a negative potential) to the back gate, the threshold voltage of the transistor can be shifted in the positive direction to achieve a normally-off characteristic. Thus, a transistor of one embodiment of the present invention can simultaneously achieve a large on-state current and a normally-off characteristic.

[0110] Note that in the transistor of one embodiment of the present invention, either the conductive layer 255 or the conductive layer 265 may be used as a gate and the other may be used as a back gate. In the transistor of one embodiment of the present invention, it is particularly preferable that the conductive layer 265 is used as a gate and the conductive layer 255 is used as a back gate. When the region of the conductive layer 265 facing the semiconductor layer 230 is larger than the region of the conductive layer 255 facing the semiconductor layer 230 and such a conductive layer 265 is used as a gate, a gate electric field is more efficiently applied to the semiconductor layer 230, and thus the electrical characteristics of the transistor may be improved.

[0111] In a planar transistor, the channel length is limited by the exposure of the photolithography method, but in one embodiment of the present invention, the channel length can be set according to the thickness of the insulating layer 280a and the insulating layer 280b. Thus, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of the photolithography method (for example, more than 1nm and less than 60nm, more than 1nm and less than 50nm, more than 1nm and less than 40nm, more than 1nm and less than 30nm, more than 1nm and less than 20nm, or more than 1nm and less than 10nm). As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved. The vertical transistor has a structure that is easy to reduce the channel length, and it is easy to increase the on-state current (reduce the on-state resistance). By adopting a vertical channel transistor, a semiconductor device with a fast operating speed can be provided.

[0112] In addition, if Figure 4DAs shown, the insulating layer 235, the semiconductor layer 230, the insulating layer 250 and the conductive layer 265a are arranged in a concentric shape. Therefore, the side surface of the conductive layer 265a arranged in the center is opposite to the side surface of the semiconductor layer 230 via the insulating layer 250. That is, when viewed from a plane, the entire circumference of the semiconductor layer 230 is set as a channel formation region. At this time, the channel width of the transistor 200 is determined, for example, by the length of the outer circumference of the semiconductor layer 230. In other words, it can be said that the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter when the opening 290 is circular when viewed from a plane). FIG. 4B to FIG. 4E The width D of the opening 290 is shown in FIG. Figure 4E 2 shows the channel width W of the transistor 200. By increasing the width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current.

[0113] Note that the width D of the opening 290 may vary in the depth direction. In particular, when viewed from a cross section perpendicular to the Z direction (for example, Figure 4B or Figure 4C ) is used as the width D. In other words, the minimum value of the width of the opening 290 in the conductive layer 255 when viewed from the Z direction is used as the width D of the opening 290. In addition, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at the position of the middle point between the above two positions, or the average value of these three widths may be used as the width D. Here, an example of determining the width D based on the width of the opening 290 of the conductive layer 255 is shown, and there is no particular limitation on the method for determining the width D. For example, the shortest distance of the width of the opening 290 of any of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b when viewed from the Z direction may be used as the width D. In addition, the width of the opening 290 at the highest position of any one of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a and the conductive layer 240b, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between the above two positions, or the average of these three widths may be used as the width D.

[0114] When the opening 290 is formed by photolithography, the width D of the opening 290 is limited by the exposure of the photolithography. In addition, the width D of the opening 290 is limited by the thickness of the insulating layer 235, the semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening 290. The width D of the opening 290 is preferably, for example, not less than 5 nm, not less than 10 nm, or not less than 20 nm and not more than 100 nm, not more than 60 nm, not more than 50 nm, not more than 40 nm, or not more than 30 nm. Note that when the opening 290 is circular when viewed from a plane, the width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0115] In addition, the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably greater than 0.1 times and less than 0.99 times, and more preferably greater than 0.5 times and less than 0.8 times, of the channel width W of the transistor 200. By adopting such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0116] As described above, the opening 290 is formed into a circular shape when viewed from a plane, so that the insulating layer 235, the semiconductor layer 230, the insulating layer 250 and the conductive layer 265a can be arranged in a concentric shape. As a result, the distance between the conductive layer 255 and the semiconductor layer 230 and the distance between the conductive layer 265a and the semiconductor layer 230 are substantially equal, so that the gate electric field can be applied to the semiconductor layer 230 substantially uniformly.

[0117] In addition, the present embodiment shows an example in which the opening 290 is circular when viewed from a plane, but the present invention is not limited to this. When viewed from a plane, the opening 290 may have, for example, a circle, an ellipse, or other approximate circle, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or other polygons, or the shapes of the above polygons with corner arcs. The polygon may also be a concave polygon (a polygon with at least one internal angle exceeding 180 degrees) or a convex polygon (a polygon with internal angles of less than 180 degrees). Figure 4A As shown in FIG. 1 and FIG. 2 , when viewed from a plane, the opening 290 is preferably circular. By adopting a circular shape, the processing accuracy when forming the opening can be improved, and a fine-sized opening can be formed. In this specification, etc., a circular shape is not limited to a perfect circle.

[0118] <Materials Constituting Semiconductor Devices> Materials that can be used for semiconductor devices such as transistors, memory cells, memory strings, and memory devices according to one embodiment of the present invention are described below. Note that each layer constituting the semiconductor device according to one embodiment of the present invention may have a single-layer structure or a stacked-layer structure. Figure 4B and Figure 4CAn example in which the conductive layer 220a has a single-layer structure is shown. Figure 5 An example in which the conductive layer 220a has a stacked-layer structure is shown.

[0119] [Semiconductor layer 230] As described above, the semiconductor layer 230 has a channel formation region. The semiconductor layer 230 also has a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region. The semiconductor layer 230 may also have a stacked structure of two or more layers.

[0120] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 230, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) may be used. When a single crystal semiconductor or a crystalline semiconductor is used, degradation of transistor characteristics can be suppressed, so it is preferred.

[0121] When an oxide semiconductor, which is one of metal oxides, is used as the semiconductor layer 230, the band gap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the semiconductor layer 230, the off-state current of the transistor can be reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be sufficiently reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0122] For the oxide semiconductor used for the semiconductor layer of the transistor of one embodiment of the present invention, the description in Embodiment 3 can be referred to. Here, detailed description is omitted.

[0123] In addition, transistors using other semiconductor materials in the channel formation region may also be used in the semiconductor device of this embodiment. As the other semiconductor material, for example, a semiconductor composed of a single element or a compound semiconductor may be cited. As a semiconductor composed of a single element, for example, silicon and germanium may be cited. As a compound semiconductor, for example, gallium arsenide and silicon germanium may be cited. In addition, as a compound semiconductor, for example, an organic semiconductor and a nitride semiconductor may be cited. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0124] Examples of silicon semiconductor materials that can be used for transistors include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0125] The semiconductor layer of the transistor may also include a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0126] As the above-mentioned layered substances, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (elements belonging to Group 16). In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0127] [Insulation layer] As the insulating layer (insulating layer 210, insulating layer 235, insulating layer 250, insulating layer 280a, insulating layer 280b, etc.), an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be cited. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film can be cited. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be cited. As the oxynitride insulating film, for example, a silicon nitride film, an aluminum nitride film, an oxynitride gallium film, an oxynitride yttrium film, and an oxynitride hafnium film can be cited. As the nitride oxide insulating film, for example, a silicon nitride oxide film and an aluminum nitride oxide film can be cited. Alternatively, an organic insulating film may be used as an insulating layer included in the semiconductor device.

[0128] For example, with the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thin film of the gate insulating layer. By using high-k materials for insulating layers such as insulating layers 235 and 250 that serve as gate insulating layers, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using materials with low relative dielectric constants for insulating layers used as interlayer films, parasitic capacitance generated between wirings can be reduced. Therefore, the material can be selected according to the function of the insulating layer. In addition, materials with low relative dielectric constants are also materials with high dielectric strength.

[0129] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0130] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. Note that this silicon oxide sometimes contains nitrogen.

[0131] Alternatively, a material having ferroelectricity may be used for the insulating layer 235, the insulating layer 250, and the like. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (the element J1 here is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (the element J2 here is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0132] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. In addition, the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In this case, the ratio of the number of atoms of the element M1, the number of atoms of the element M2 and the number of atoms of the element M3 can be appropriately set.

[0133] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0134] Note that, although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0135] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. Alternatively, the insulating layer can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0136] The metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a thin film of a few nm. In addition, the metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area. Thus, by using the metal oxide containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0137] Note that in this specification, etc., a material processed into a layer that can have ferroelectricity is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including the above-mentioned ferroelectric layer, metal oxide film, or metal nitride film is sometimes referred to as a ferroelectric device.

[0138] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulating layer to exhibit ferroelectricity, the insulating layer needs to contain crystals. In particular, the insulating layer preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. Note that the crystal structure of the crystal contained in the insulating layer can be any one or more selected from the group consisting of cubic system, tetragonal system, orthorhombic system, monoclinic system and hexagonal system. In addition, the insulating layer may also have an amorphous structure. At this time, the insulating layer may also have a composite structure of an amorphous structure and a crystal structure.

[0139] In addition, by adding the third group element (also called IIIa element) in the periodic table to the oxide containing one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide is increased, thereby easily forming a crystal with a crystal structure of an orthorhombic system. Therefore, the existence ratio of the crystal with the crystal structure of the orthorhombic system is increased, so that the residual polarization can be increased, so it is preferred. On the other hand, when the addition amount of the third group element is too much, it is possible that the crystallinity of the oxide is reduced and it is not easy to show ferroelectricity. Therefore, the content of the third group element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and further preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the third group element refers to the ratio of the number of atoms of the third group element in the sum of the number of atoms of all metal elements contained in the layer. The third group element is preferably selected from one or more of scandium, lanthanum and yttrium, and more preferably one or both of lanthanum and yttrium.

[0140] In addition, by surrounding a transistor using a metal oxide with an insulating layer having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulating layer having a function of suppressing the transmission of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for an insulating layer having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0141] Specifically, as an insulating layer having a function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be cited. In addition, as an insulating layer having a function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, as an insulating layer having a function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride can be cited.

[0142] In addition, the insulating layer in contact with the oxide semiconductor layer or the insulating layer provided near the oxide semiconductor layer, such as the insulating layer 235 and the insulating layer 250, is preferably an insulating layer having a region containing oxygen released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when the insulating layer having a region containing excess oxygen is in contact with the oxide semiconductor layer or provided near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. As an insulating layer in which a region containing excess oxygen is easily formed, silicon oxide, silicon oxynitride, or silicon oxide having holes can be cited.

[0143] Since the insulating layer 210 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are suitable for the insulating layer 210 because they have thermal stability.

[0144] In addition, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. In this way, it is possible to suppress the impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230 .

[0145] A hydrogen barrier insulating layer is preferably used as the insulating layer 210. When the insulating layer 210 provided outside the semiconductor layer 230 has a hydrogen barrier property, diffusion of hydrogen into the semiconductor layer 230 can be suppressed.

[0146] Examples of the material of the hydrogen barrier insulating layer include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0147] In this specification, etc., a barrier insulating layer refers to an insulating layer having barrier properties. In addition, barrier properties refer to the property that the corresponding substance is not easily diffused (it can also be said that the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise specified, the impurity recorded as the corresponding substance refers to an impurity in the channel formation region or the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as the corresponding substance refers to at least one of oxygen atoms, oxygen molecules, etc.

[0148] For example, as the insulating layer 210 , a silicon nitride film is preferably used.

[0149] When an oxide semiconductor is used as the semiconductor layer 230, the insulating layer 280a and the insulating layer 280b preferably both include the above-mentioned hydrogen barrier insulating layer. The insulating layer 280a and the insulating layer 280b are provided so as to surround the semiconductor layer 230. When the insulating layer 280a and the insulating layer 280b provided outside the semiconductor layer 230 have hydrogen barrier properties, it is possible to suppress the diffusion of hydrogen into the semiconductor layer 230. For example, the insulating layer 280a and the insulating layer 280b preferably each include one or both of an aluminum oxide film and a silicon nitride film.

[0150] Furthermore, silicon nitride has an oxygen barrier property. Therefore, when silicon nitride is used for the insulating layers 280 a and 280 b , oxygen is extracted from the semiconductor layer 230 , and formation of excessive oxygen vacancies in the semiconductor layer 230 can be suppressed.

[0151] When an oxide semiconductor is used for the semiconductor layer 230, silicon nitride can be used for the insulating layers 280a and 280b to prevent excess oxygen from being supplied to the semiconductor layer 230. This prevents the channel formation region of the semiconductor layer 230 from being in an oxygen-excess state, thereby improving the reliability of the transistor 200.

[0152] In addition, the insulating layer 280a and the insulating layer 280b each preferably include the above-mentioned oxide insulating film, oxynitride insulating film, or an insulating layer having a region containing excess oxygen.

[0153] For example, the insulating layer having the region containing excess oxygen can be formed by sputtering in an atmosphere containing oxygen. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 280a and the insulating layer 280b can be reduced. By depositing a layer constituting at least a portion of the insulating layer 280a and the insulating layer 280b in this way, oxygen can be supplied from the insulating layer 280a and the insulating layer 280b to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0154] When an oxide semiconductor is used as the semiconductor layer 230 , the concentration of impurities such as water and hydrogen in the insulating layers 280 a and 280 b is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230 .

[0155] In addition, the thickness of the insulating layer 280 a and the insulating layer 280 b on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 a and the insulating layer 280 b is appropriately set according to the design value of the channel length of the transistor 200 .

[0156] For example, as the insulating layer 280a and the insulating layer 280b, a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used. Alternatively, for example, as the insulating layer 280a and the insulating layer 280b, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in sequence is preferably used. For example, as the insulating layer 280a and the insulating layer 280b, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in sequence is preferably used.

[0157] When an oxide semiconductor is used as the semiconductor layer 230, the insulating layer 250 preferably has a function of capturing and fixing hydrogen. Thus, the hydrogen concentration of the semiconductor layer 230 (especially, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Thus, the V O H, and the channel formation region can be made i-type or substantially i-type.

[0158] As the material of the insulating layer having the function of capturing or fixing hydrogen, metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, these metal oxides can also contain zirconium, for example, oxides containing hafnium and zirconium can be cited. Here, in the metal oxide having an amorphous structure, since some oxygen atoms have dangling bonds, the ability to capture or fix hydrogen is high. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by making these oxides contain silicon. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Note that sometimes the metal oxide has one or both of a crystalline region and a grain boundary in a part thereof.

[0159] In addition, the function of capturing or fixing the corresponding substance can also be said to be a property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can be replaced by barrier property.

[0160] When an oxide semiconductor is used as the semiconductor layer 230 and the gate insulating layer has a stacked structure, the layer in contact with the semiconductor layer 230 preferably has a function of capturing or fixing hydrogen. Thus, hydrogen in the semiconductor layer 230 can be efficiently captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. For example, hafnium silicate is preferably used as the layer in contact with the semiconductor layer 230 of the insulating layer 250. In addition, the layer preferably has an amorphous structure.

[0161] By making the layer have an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the layer can be improved. As a result, the thickness distribution of the insulating layer 250 becomes uniform, and the extremely thin portion can be reduced, so the withstand voltage of the insulating layer 250 can be improved. In addition, the thickness distribution of the film provided on the insulating layer 250 can be made uniform.

[0162] Furthermore, by suppressing the formation of grain boundaries in this layer, leakage current caused by defect states at the grain boundaries can be reduced. As a result, the insulating layer 250 can be used as an insulating film with less leakage current.

[0163] In addition, since hafnium oxide is a high-k material, hafnium silicate becomes a high-k material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulating layer. In addition, the EOT of the gate insulating layer can be thinned.

[0164] As described above, as the insulating layer 250 , an oxide containing one or both of aluminum and hafnium is preferably used, an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used, and aluminum oxide having an amorphous structure is further preferably used.

[0165] In addition, when an oxide semiconductor is used as the semiconductor layer 230, the above-mentioned hydrogen barrier insulating layer is preferably used as the insulating layer 250. When the hydrogen barrier insulating layer is used as the insulating layer 250, it is possible to suppress the impurities in the conductive layer 265 from being supplied to the semiconductor layer 230. For example, silicon nitride has a high hydrogen barrier property and is therefore suitable for the insulating layer 250. In addition, the insulating layer 250 may include an insulating layer having a thermally stable structure using silicon oxide, silicon oxynitride, or the like.

[0166] By adopting this structure, a semiconductor device having good electrical characteristics can be provided. In addition, a semiconductor device with high reliability can be provided. In addition, a semiconductor device with less uneven electrical characteristics of transistors can be provided. In addition, a semiconductor device with large on-state current can be provided.

[0167] Also, the insulating layer 250 may include an insulating layer having a thermally stable structure such as silicon oxide or silicon oxynitride.

[0168] In addition, the insulating layer 250 may also include an insulating layer having a thermally stable structure between a pair of insulating layers having a function of trapping and fixing hydrogen.

[0169] In addition, the insulating layer 250 preferably includes an oxygen blocking insulating layer. Thus, oxidation of the conductive layer 240 and the conductive layer 265 can be suppressed. In the case where the insulating layer 250 has a stacked structure, the layer in contact with the conductive layer 240 is preferably an oxygen blocking insulating layer. In particular, the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 265 among the layers constituting the insulating layer 250 are preferably both oxygen blocking insulating layers.

[0170] When a hydrogen and oxygen blocking insulating layer is used as a layer in contact with the conductive layer 265 in the insulating layer 250, oxidation of the conductive layer 265 can be suppressed. In addition, when an oxide semiconductor is used as the semiconductor layer 230, oxygen in the semiconductor layer 230 diffuses into the conductive layer 265, thereby suppressing the formation of oxygen vacancies in the semiconductor layer 230.

[0171] As the oxygen blocking insulating layer, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as an oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be cited.

[0172] The layer in contact with the conductive layer 240 in the insulating layer 250 is preferably less likely to be permeated with oxygen than the insulating layer 280b. When the layer has oxygen barrier properties, it is possible to suppress the formation of an oxide film on the side surface due to oxidation of the side surface of the conductive layer 240. Therefore, it is possible to suppress the reduction of the on-state current of the transistor 200 or the reduction of the field effect mobility.

[0173] In addition, each layer constituting the insulating layer 250 is preferably a thin film. For example, by making each layer constituting the insulating layer 250 not less than 1 nm and not more than 20 nm, preferably not less than 3 nm and not more than 10 nm, the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced. The S value refers to the change in gate voltage when the drain current changes by one digit under a constant drain voltage in the subthreshold region.

[0174] In addition, the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, further preferably 0.5 nm to 5 nm, further preferably 1 nm to less than 5 nm, further preferably 1 nm to 3 nm. At least a portion of each layer constituting the insulating layer 250 may include a region having the above thickness.

[0175] In addition, when an oxide semiconductor is used as the semiconductor layer 230, a three-layer structure is preferably used as the insulating layer 250, in which a first insulating layer containing a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a hydrogen and oxygen barrier property are stacked in order from the semiconductor layer 230 side. As the material with a low relative dielectric constant contained in the first insulating layer, silicon oxide or silicon oxynitride is preferably used. The first insulating layer is in contact with the semiconductor layer 230. By using an oxide as the first insulating layer, oxygen can be supplied to the semiconductor layer 230. In addition, by providing the third insulating layer, diffusion of oxygen in the first insulating layer to the conductive layer 265 can be suppressed, thereby suppressing oxidation of the conductive layer 265. In addition, a reduction in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 230 can be suppressed.

[0176] When an oxide semiconductor is used as the semiconductor layer 230, a four-layer structure is preferably used as the insulating layer 250, in which a fourth insulating layer having oxygen barrier properties, a first insulating layer containing a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having hydrogen and oxygen barrier properties are stacked in sequence from the semiconductor layer 230 side. The first insulating layer to the third insulating layer can adopt the same structure as the layers used for the above-mentioned three-layer structure. The fourth insulating layer is in contact with the semiconductor layer 230. When the fourth insulating layer has oxygen barrier properties, oxygen can be suppressed from being separated from the semiconductor layer 230. As the fourth insulating layer, aluminum oxide is preferably used, for example. Aluminum oxide has the function of capturing or fixing hydrogen, and is therefore suitable for use as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked from the semiconductor layer 230 side is preferably used.

[0177] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. By adopting such a structure, good electrical characteristics can be obtained even when the transistor is miniaturized or highly integrated.

[0178] In addition, as the insulating layer 250, a three-layer structure is preferably used, in which a fourth insulating layer having oxygen barrier properties, a first insulating layer containing a material with a relatively low dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked from the semiconductor layer 230 side. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked from the semiconductor layer 230 side is preferably used.

[0179] In addition, the above-mentioned insulating layer having the function of capturing or fixing hydrogen may be used as the insulating layer 210. Thus, hydrogen in the semiconductor layer 230 diffuses to the insulating layer 210 through the conductive layer 220a and the conductive layer 220b, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. For example, as the insulating layer 210, a two-layer structure of a silicon nitride film and a hafnium silicate film on the silicon nitride film may be used.

[0180] The insulating layer 235 may also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, etc.

[0181] When an oxide semiconductor is used as the semiconductor layer 230, the insulating layer 235 preferably includes an insulating layer having a region containing oxygen released by heating. Thus, oxygen can be supplied from the insulating layer 235 to the semiconductor layer 230. For example, silicon oxide or silicon oxynitride is preferably used as the insulating layer 235.

[0182] The insulating layer 235 preferably includes a hydrogen barrier insulating layer. This can suppress diffusion of oxygen into the semiconductor layer 230, thereby improving the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0183] Alternatively, the insulating layer 235 may be made of the above-mentioned material having ferroelectricity.

[0184] For example, as the insulating layer 235, a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film, etc. can be used. In the case of using a two-layer structure of a silicon oxide film and a silicon nitride film, it is preferable to provide a silicon oxide film on the semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side, for example. Thus, oxygen can be efficiently supplied to the semiconductor layer 230, and diffusion of impurities such as hydrogen into the semiconductor layer 230 can be suppressed. Alternatively, a silicon nitride film can be provided on the semiconductor layer 230 side and a silicon oxide film can be provided on the conductive layer 255 side.

[0185] [Conductive layer] As the conductive layer (conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 265, etc.) included in the semiconductor device, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, a nitride of the alloy or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, a nitride containing tungsten, titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and a silicide such as nickel silicide can also be used.

[0186] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Note that as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also called ITO), indium tin oxide containing titanium oxide, indium tin oxide added with silicon (also called ITSO), indium zinc oxide (also called IZO (registered trademark)), and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0187] A conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0188] In addition, a plurality of conductive layers formed by stacking the above materials may also be used. For example, a laminated structure in which a material containing the above metal element and a conductive material containing oxygen are combined may also be used. In addition, a laminated structure in which a material containing the above metal element and a conductive material containing nitrogen are combined may also be used. In addition, a laminated structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be used.

[0189] Note that when a metal oxide is used in the channel formation region of the transistor, a stacked-layer structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined is preferably used as a conductive layer used as a gate electrode of the conductive layer 255, the conductive layer 265, or the like. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen separated from the conductive material can be easily supplied to the channel formation region.

[0190] When an oxide semiconductor is used as the semiconductor layer 230, the conductive layer 220 and the conductive layer 240 are both conductive layers in contact with the semiconductor layer 230, and preferably use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has a function of inhibiting the diffusion of oxygen. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductive layer 220 and the conductive layer 240 can be suppressed from decreasing.

[0191] When a conductive material containing oxygen is used as the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain conductivity even if the conductive layer 220 or the conductive layer 240 absorbs oxygen. In addition, when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 can also maintain conductivity, which is preferable. As the conductive layer 220 and the conductive layer 240, for example, ITO, ITSO, IZO (registered trademark), etc. are preferably used.

[0192] Figure 5 An example of a three-layer structure in which the conductive layer 220 has a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2 is shown. At this time, it is preferred that, for example, a conductive material that is not easily oxidized or a conductive material having a function of inhibiting the diffusion of oxygen is used as the conductive layer 220a1, a material with high conductivity is used as the conductive layer 220a2, and a conductive material containing oxygen (more preferably an oxide conductor) is used as the conductive layer 220b. Specifically, it is preferred that, for example, titanium nitride is used as the conductive layer 220a1, tungsten is used as the conductive layer 220a2, and an oxide conductor (for example, ITO, ITSO or IZO (registered trademark)) is used as the conductive layer 220b. In this case, titanium nitride is in contact with the insulating layer 210, and the oxide conductor is in contact with the semiconductor layer 230 which is an oxide semiconductor. In addition, an oxide conductor is used as the layer closest to the channel formation region in the semiconductor layer 230. Compared with tungsten, the contact resistance between the oxide conductor and the semiconductor layer 230 is low, so the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased. By adopting this structure, conductivity can be maintained even when the conductive layer 220 is in contact with the semiconductor layer 230. In addition, when an oxidized insulating layer is used as the insulating layer 210, excessive oxidation of the conductive layer 220 through the insulating layer 210 can be suppressed. In addition, by using a metal material (here tungsten) whose conductivity is higher than that of the oxide conductor and titanium nitride as the conductive layer 220a2, the conductivity of the conductive layer 220 can be improved.

[0193] Figure 5 An example of a two-layer structure in which the conductive layer 240 has a conductive layer 240a and a conductive layer 240b on the conductive layer 240a is shown. In this case, it is preferable that, for example, a conductive material containing oxygen is used as the conductive layer 240b, and a material having a higher conductivity than the conductive layer 240b is used as the conductive layer 240a. Specifically, it is preferable that, for example, an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) is used as the conductive layer 240b, and tungsten is used as the conductive layer 240a. In addition, ruthenium, titanium nitride, tantalum nitride, etc. may also be used as the conductive layer 240a.

[0194] The main layer in contact with the semiconductor layer 230 in the conductive layer 240 is the conductive layer 240b. When an oxide semiconductor is used as the semiconductor layer 230, it is preferable to use an oxide conductor as the conductive layer 240b because the contact resistance with the semiconductor layer 230 can be reduced. In addition, it is preferable to use a material having a higher conductivity than the oxide conductor as a layer constituting the conductive layer 240 because the conductivity of the conductive layer 240 can be improved.

[0195] Note that a conductive material containing oxygen can be used as the conductive layer 240a, and a material having higher conductivity than the conductive layer 240a can be used as the conductive layer 240b. In this case, an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 230 in the conductive layer 240. Thus, a current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0196] The conductive layer 255 and the conductive layer 265 preferably use a material with high conductivity such as tungsten. In addition, as the conductive layer 255 and the conductive layer 265, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen. As the conductive material, as described above, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thus, the decrease in the conductivity of the conductive layer 255 and the conductive layer 265 can be suppressed.

[0197] In addition, the conductive layer 265 preferably uses a conductive material containing a metal element and oxygen in a metal oxide that forms a channel. In addition, a conductive material containing the above-mentioned metal element and nitrogen (for example, titanium nitride, tantalum nitride, etc.) can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide that forms the channel can sometimes be captured. Alternatively, hydrogen entering from an outer insulating layer or the like can sometimes be captured.

[0198] Figure 5 An example of a two-layer structure in which the conductive layer 265 has a conductive layer 265a and a conductive layer 265b on the conductive layer 265a is shown. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. By adopting such a structure, the conductivity of the conductive layer 265 can be improved.

[0199] Alternatively, the conductive layer 265 may have a stacked structure of three or more layers. For example, the conductive layer 265 may have a three-layer structure of tantalum nitride, titanium nitride on tantalum nitride, and tungsten on titanium nitride.

[0200] Since the conductive layer 265 is a layer used as a gate wiring, it preferably has high conductivity. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten can also be employed.

[0201] The conductive layer 255 is preferably made of, for example, tungsten or tantalum nitride.

[0202] [Substrate] When semiconductor devices such as transistors, memory cells, and storage devices are provided on a substrate, there is no particular restriction on the material used for the substrate. Depending on the purpose, the material may be determined by considering the presence or absence of light transmittance and the degree of heat resistance that can withstand heat treatment. For example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As an insulator substrate, for example, a glass substrate such as borosilicate glass and aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), etc. may be used. In addition, a semiconductor substrate, a flexible substrate, a resin substrate, etc. may also be used.

[0203] As the semiconductor substrate, there are, for example, semiconductor substrates made of silicon or germanium or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide. In addition, there are also semiconductor substrates having an insulator region inside the above-mentioned semiconductor substrates, such as SOI substrates. In addition, the semiconductor substrate can be a single crystal semiconductor or a polycrystalline semiconductor.

[0204] Examples of the conductive substrate include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, examples include substrates containing metal nitrides, substrates containing metal oxides, etc. Furthermore, examples include substrates having a conductive layer or a semiconductor layer provided on an insulating substrate, substrates having a conductive layer or an insulating layer provided on a semiconductor substrate, substrates having a semiconductor layer or an insulating layer provided on a conductive substrate, etc.

[0205] As materials for flexible substrates or resin substrates, for example, polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyether sulfone (PES), polyamide (nylon, aromatic polyamide, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofibers, etc. can be used.

[0206] By using the above material as a substrate, a lightweight semiconductor device can be provided. In addition, by using the above material as a substrate, a semiconductor device with high impact resistance can be provided. In addition, by using the above material as a substrate, a semiconductor device that is not easily damaged can be provided.

[0207] Alternatively, a substrate having an element provided over the above substrate may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switch, a light emitting element, and a memory element.

[0208] <Structure example of storage unit> Fig. 6A An example of a circuit structure of the memory cell 10 in the memory string 100 is shown. Figure 6B From the Z direction Fig. 6A The storage unit 10 is shown as a plan view. Figure 6C yes Fig. 6A A three-dimensional schematic diagram of the storage unit 10 is shown. Fig.6D From the Y direction Fig. 6A A schematic diagram of a storage unit 10 is shown. Fig. 6E From the X direction Fig. 6A A schematic diagram of a storage unit 10 is shown. Fig. 6A The memory cell 10 shown is a "2Tr1C type" memory cell constructed using two transistors and one capacitor element.

[0209] Fig. 7A Shown along Figure 6B An example of a cross-sectional structure along the dashed line B1-B2 in FIG. Figure 7B Shown along Figure 4B An example of a cross-sectional structure along the dashed line B3-B4 in FIG.

[0210] As described above, the transistor 200 can be used as the transistor WTr and the transistor RTr included in the memory cell 10. When the transistor 200, which is a vertical transistor, is used for the transistor WTr and the transistor RTr, the occupied area of ​​the memory cell 10 can be reduced. In addition, when the transistor WTr and the transistor RTr are overlapped, the occupied area of ​​the memory cell 10 can be further reduced.

[0211] Fig. 7A and Figure 7B FIG. 1 shows an example of a structure of the memory cell 10, in which the transistor 200 is used as the transistor WT r and the transistor RTr. FIG. 6A to FIG. 6E , Fig. 7A and Figure 7B Middle Pair FIG. 4A to FIG. 4E and Figure 5The symbols shown are assigned “W” and “R.” Specifically, the symbols of the transistor WTr and components mainly related to the transistor WTr are assigned “W,” and the symbols of the transistor RTr and components mainly related to the transistor RTr are assigned “R.”

[0212] The conductive layer 220R is used as one of the source electrode and the drain electrode of the transistor RTr (first terminal). The conductive layer 240R is used as the other of the source electrode and the drain electrode of the transistor RTr (second terminal). The conductive layer 265R is used as the gate electrode of the transistor RTr, and the conductive layer 255R is used as the back gate electrode of the transistor RTr. In addition, the conductive layer 255R is used as the wiring RBG.

[0213] In addition, a conductive layer 241R is provided on the insulating layer 280bR. The conductive layer 241R has the same structure as the conductive layer 240R. The conductive layer 241R can be formed at one time using the same material and process as the conductive layer 240R. The conductive layer 241R is used as a wiring COM. In addition, the area where the conductive layer 241R and the conductive layer 265R overlap each other across the insulating layer 250R is used as a capacitor Cs. In addition, the conductive layer 265R is used as a holding node SN. Therefore, a part of the conductive layer 241R is used as an electrode of the capacitor Cs, and a part of the conductive layer 265R is used as another electrode of the capacitor Cs. When the capacitor Cs is provided, the holding node SN is not easily affected by the external electric field and the leakage current, and the information written to the storage cell 10 can be stably maintained. In other words, the reliability of the storage cell 10 can be improved.

[0214] The conductive layer 265R is used as the gate electrode of the transistor RTr and is used as one of the source electrode and the drain electrode of the transistor WTr (first terminal). The conductive layer 265R has the functions of the gate electrode of the transistor RTr and one of the source electrode and the drain electrode of the transistor WTr, thereby reducing the conductive layer constituting the memory cell 10. Therefore, the occupied area of ​​the memory cell 10 can be reduced. In addition, the manufacturing cost of the memory cell 10 can be reduced. In addition, the production rate of the memory cell 10 can be improved.

[0215] The conductive layer 240W is used as the other of the source electrode and the drain electrode of the transistor WTr (second terminal). The conductive layer 265W is used as the gate electrode of the transistor WTr, and the conductive layer 255W is used as the back gate electrode of the transistor WTr. In addition, the conductive layer 255W is used as the wiring WBG.

[0216] In addition, Fig. 7A and Figure 7BIn the embodiment, the insulating layer 210 is divided into the insulating layer 210R and the insulating layer 210W, but the insulating layer 210R and the insulating layer 210W may be the same layer. For example, the insulating layer 210W disposed at the i-th level and the insulating layer 210R disposed at the i+1-th level may be the same layer.

[0217] In addition, the conductive layer 240W (conductive layer 240W[1]) serving as the second terminal of the transistor WTr[1] in the first-level memory cell 10[1] is connected to the conductive layer 240W (conductive layer 240W[2]) serving as the second terminal of the transistor WTr[2] in the second-level memory cell 10[2] via the conductive layer 245.

[0218] exist Fig. 7A , the conductive layer 245 is provided in a manner that passes through the insulating layer 280bW, the insulating layer 280aW, the insulating layer 280bR, the insulating layer 280aR, the insulating layer 210R (insulating layer 210W), the insulating layer 250W, and the semiconductor layer 230W along the Z direction. The conductive layer 240W provided at the i-th level is connected to the conductive layer 240W provided at the i-1th level through the conductive layer 245 provided at the i-th level. Note that, in this embodiment, the conductive layer 245 is shown as one conductive layer, but the conductive layer 245 may be constituted by using a plurality of conductive layers.

[0219] In addition, Fig. 7A , the conductive layer 246 is provided in a manner that passes through the insulating layer 210W (insulating layer 210R), the insulating layer 280bW, the insulating layer 280aW, the insulating layer 250R, and the semiconductor layer 230R along the Z direction. The conductive layer 240R provided at the i-th level and the conductive layer 240R provided at the (i+1)-th level are connected through the conductive layer 246 provided at the i-th level. Note that in this embodiment, the conductive layer 246 is shown as one conductive layer, but the conductive layer 246 may be constituted by a plurality of conductive layers.

[0220] In order to maintain the data written to the retention node SN for a long period of time, the smaller the off-state current of the transistor WTr, the better. By increasing the channel length of the transistor WTr, the off-state current of the transistor WTr can be reduced. In addition, in order to increase the read speed of the data written to the retention node SN, the larger the on-state current of the transistor RTr, the better. By shortening the channel length of the transistor RTr, the on-state current of the transistor RTr can be increased. Therefore, it is preferred to increase the channel length of the transistor WTr and shorten the channel length of the transistor RTr. In other words, the channel length of the transistor WTr is preferably longer than the channel length of the transistor RTr. For the same reason, the channel width of the transistor WTr is preferably shorter than the channel width of the transistor RTr.

[0221] Figure 8 is corresponding to Fig. 7AA cross-sectional view of the Figure 8 , the channel length of the transistor WTr is represented as the channel length WL, and the channel length of the transistor RTr is represented as the channel length RL. When the transistor 200 as a vertical transistor is used as the transistor WTr and the transistor RTr, the length of the channel length WL can be controlled according to the thickness of the insulating layer 280aW, the insulating layer 280bW, and the conductive layer 255W. In addition, the length of the channel length RL can be controlled according to the thickness of the insulating layer 280aR, the insulating layer 280bR, and the conductive layer 255R. Therefore, the total thickness of the insulating layer 280aW, the conductive layer 255W, and the insulating layer 280bW in the region where the conductive layer 240W overlaps with the conductive layer 265R when viewed from the Z direction is preferably greater than the total thickness of the insulating layer 280aR, the conductive layer 255R, and the insulating layer 280bR in the region where the conductive layer 240R overlaps with the conductive layer 220R when viewed from the Z direction.

[0222] Each of the conductive layers 245 provided at the first to nth levels and each of the conductive layers 240W provided at the first to nth levels is used as a part of the wiring WBL. Thus, the wiring WBL extends in the Z direction. In addition, the wiring WWL, the wiring WBG, and the wiring RBG extend in the X direction.

[0223] As described above, by using an OS transistor as the transistor WTr, data written to the holding node SN can be held for a long period of time. Fig.9A As shown in the circuit configuration example shown in the figure, a configuration not including the capacitor element Cs may be adopted. Fig. 9B From the Z direction Fig.9A The storage unit 10 is shown as a plan view. Fig. 9C yes Fig.9A A three-dimensional schematic diagram of the storage unit 10 is shown. Fig.9D From the Y direction Fig.9A A schematic diagram of a storage unit 10 is shown. Fig.9E From the X direction Fig.9A A schematic diagram of a storage unit 10 is shown.

[0224] When the structure that does not include the capacitor element Cs is adopted, the electrostatic capacitance of the node SN is kept small, and the writing time of the information can be reduced. In other words, the writing speed can be improved. In addition, when the structure that does not include the capacitor element Cs is adopted, it is not necessary to form the wiring COM. In addition, the size of the conductive layer 265R when viewed from the Z direction can be reduced. Thus, the occupied area of ​​the storage unit 10 can be reduced. Therefore, a storage device with high storage density can be provided.

[0225] Fig. 10A and Fig. 10B FIG. 1 is a plan view of a plurality of memory cells 10 at the i-th level arranged in a matrix. Fig. 10A 1 is a plan view of a case where the memory cell 10 includes a capacitor Cs. Fig. 10B 1 is a plan view of a case where the memory cell 10 does not include the capacitor Cs. When the memory cell 10 does not include the capacitor Cs, the wiring COM is not required, so the storage density can be further improved compared to the case where the memory cell 10 includes the capacitor Cs.

[0226] In addition, when the potential of the wiring WBG is a fixed potential, as shown in FIG. Fig.11A As shown in the circuit configuration example of , the other electrode of the capacitor Cs may be connected to the wiring WBG. Alternatively, a part of the wiring WBG may be used as the other electrode of the capacitor Cs. Fig. 11B From the Z direction Fig.11A The storage unit 10 is shown as a plan view. Fig. 11C yes Fig.11A A three-dimensional schematic diagram of the storage unit 10 is shown. Fig.11D From the Y direction Fig.11A A schematic diagram of a storage unit 10 is shown. Fig.11E From the X direction Fig.11A Schematic diagram of the memory cell 10 shown. A region where the wiring WBG overlaps the conductive layer 265R via the insulating layer is used as a capacitor Cs.

[0227] Fig. 12A FIG. 1 is a plan view of a plurality of memory cells 10 at the i-th level arranged in a matrix. Fig. 12B It is along Fig. 12A Cross-sectional view along the dotted line C1-C2. Fig. 12C yes Fig. 12B In a memory cell 10 of one embodiment of the present invention, two adjacent memory cells 10 share one wiring WBL. In other words, two adjacent memory strings 100 can share one wiring WBL. When two memory strings 100 share one wiring WBL, the number of wirings WBL can be halved. Therefore, the occupied area of ​​the memory device can be further reduced, and a memory device with a higher storage density can be provided.

[0228] By using an OS transistor for the transistor WTr, the memory cell 10 can be made into a 2Tr1C type OS memory. Alternatively, by using an OS transistor for the transistor WTr and the transistor RTr, the memory cell 10 can be made into a 2Tr1C type OS memory.

[0229] Even if the power supply is stopped, the storage unit 10 as the OS memory can retain the written information for more than one year, or even more than ten years. Therefore, the storage unit 10 can also be regarded as a non-volatile memory.

[0230] Furthermore, since the amount of charge written to the OS memory does not easily change over a long period of time, the OS memory can hold multi-value (multi-bit) information in addition to binary (1-bit) information.

[0231] In addition, in the storage cell 10 as the OS memory, a method of writing charges to the holding node through the OS transistor is adopted, so the high voltage required by the existing flash memory is not required, and a high-speed writing operation can be achieved. In addition, the OS memory does not require the deletion operation before data rewriting required by the flash memory. In addition, charge injection to the floating gate or the charge trapping layer and charge extraction from the floating gate or the charge trapping layer are not performed, so the number of times data can be written and read in the OS memory is substantially unlimited. Compared with the existing flash memory, the OS memory has less deterioration and can obtain high reliability.

[0232] Unlike ferroelectric random access memory (FeRAM) or resistive random access memory (ReRAM), no atomic-level structural change occurs in the memory cell 10. Therefore, the memory cell 10 has higher rewrite resistance than ferroelectric random access memory and resistive random access memory.

[0233] In addition, if Fig.13A As shown in the circuit diagram of FIG. 1 , the gate of the transistor WTr may be connected to the back gate. In this case, the wiring WBG may not be included. In addition, when the Vth of the transistor WTr is large in the positive direction, as shown in FIG. Fig. 13B As shown in the circuit diagram of FIG. 1 , a transistor not including a back gate may be used as the transistor WTr. In this case, the wiring WBG may not be included. Fig. 13C As shown in the circuit diagram of FIG. 1 , a ferroelectric capacitor element using a ferroelectric material as a dielectric can also be used as the capacitor element Cs. Fig.13D As shown in the circuit diagram of , a ferroelectric transistor (FeFET: Ferroelectric FET) using a ferroelectric material for a gate insulating layer may be used as the transistor RTr.

[0234] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0235] Implementation Method 2 An operation example of the memory string 100 according to one embodiment of the present invention will be described. In this embodiment, an operation example of the memory string 100 when n=3 will be described. Fig.14 is a timing diagram illustrating the operation of the memory string 100. Figures 15 to 21is a circuit diagram illustrating the operation of the memory string 100.

[0236] <Write Work> In this embodiment, an operation example of writing potential H of two information of potential H and potential L into storage cell 10[2] is described. Specifically, an operation example of writing a charge corresponding to the charge amount of potential H into storage node SN[2] is described. When potential H corresponds to a logical value "1" and potential L corresponds to a logical value "0", 1 bit of information can be stored in one storage cell 10. When one memory string 100 includes n-level storage cells 10, a maximum of n bits of information can be stored in one memory string 100.

[0237] As an initial state, a potential L is written to the memory cell 10[1] and the memory cell 10[3]. In addition, the transistors 121 and 122 are in an off state, and the potential L is supplied to the wirings WWL[1] to WWL[3], the wirings WBG[1] to WBG[3], the holding nodes SN[1] to SN[3], the wirings RBL and SL.

[0238] In addition, the wiring RBG[1] to the wiring RBG[3] are supplied with a potential L. Note that when the gate of the n-type transistor is supplied with a potential H and the back gate is supplied with a potential L, the potentials on the gate side and the back gate side cancel each other out, and 0 V is applied to the semiconductor layer. As a result, the n-type transistor is turned off.

[0239] Note that in order to make the n-type transistor reliably in the off state, a potential LL may be supplied to the gate or the back gate. The potential LL is a potential lower than the potential L. For example, in the case where the Vth of the transistor is highly non-uniform, the transistor may not be reliably in the off state even if the potential L is supplied to the back gate. For example, at this time, by supplying the potential LL to the back gate of the n-type transistor, the n-type transistor can be reliably in the off state even if the gate of the n-type transistor is supplied with the potential H.

[0240] Thus, in this embodiment, when the wiring RBG[1] to the wiring RBG[3] is supplied with the potential L or the potential LL, the transistors RTr[1] to the transistor RTr[3] are in the off state regardless of the potential of the holding node SN[1] to the holding node SN[3].

[0241] [Period T1] During period T1, potential H is supplied to wiring WWL[2] and wiring WBG[2]. In addition, potential R is supplied to wiring RBG[2]. Potential R is a potential between potential H and potential L. In this embodiment, potential R is set to 0 V. In addition, potential H is supplied to wiring SL. In addition, transistor 121 is turned on. As a result, the potential of node SN[2] is kept at potential H (see Fig.14 and Fig.15 ).

[0242] The information written to the memory cell 10 is supplied from the wiring SL to the memory cell 10 via the source and drain of the transistor 121. In addition, by supplying the potential H to both the wiring WWL[2] and the wiring WBG[2], the on-state current of the transistor WTr[2] is increased compared to the case where the potential H is supplied only to the wiring WWL[2], thereby increasing the speed at which information is written.

[0243] [Period T2] During period T2, the potential L is supplied to wiring WWL[2] and wiring WBG[2]. At this time, transistor WT[2] is in the off state and holds the charge written to holding node SN[2]. Here, a charge equivalent to the potential H can be held (see Fig.14 and Fig.16 ). In addition, the potential of wiring RBG[2] is set to potential L.

[0244] In this way, information can be stored in the memory cell 10[2]. The information written to the memory cell 10 is supplied from the wiring SL to the memory cell 10 through the source and drain of the transistor 121. When writing information to the memory cell 10[1], the potential L is supplied to the wiring WWL[2], the wiring WBG[2], the wiring WWL[3], and the wiring WBG[3], and the potential H is supplied to the wiring WWL[1] and the wiring WBG[1]. Similarly, when writing information to the memory cell 10[3], the potential L can be supplied to the wiring WWL[1], the wiring WBG[1], the wiring WWL[2], and the wiring WBG[2], and the potential H can be supplied to the wiring WWL[3] and the wiring WBG[3].

[0245] <Reading Work> An example of the operation of reading the information stored in the memory cell 10[2] is described. As an initial state, the potential L is maintained in the memory cell 10[1] and the memory cell 10[3]. In addition, the transistors 121 and 122 are in the off state, and the wiring WWL[1] to the wiring WWL[3], the wiring WBG[1] to the wiring WBG[3], the storage node SN[1], the storage node SN[3], the wiring RBL, and the wiring SL are supplied with the potential L. In addition, the wiring RBG[1] to the wiring RBG[3] are supplied with the potential L.

[0246] <<When the potential is maintained at H>> First, the read operation when the potential H is maintained in the memory cell 10 [2] will be described.

[0247] [Period T3] During period T3, transistor 122 is turned on and potential HH is supplied to wiring RBG[1] to wiring RBG[3]. Potential HH is a potential higher than potential H. By supplying potential HH to the back gate of the n-type transistor, the transistor can be surely turned on even if the gate of the transistor is supplied with potential L. As a result, transistors RTr[1] to RTr[3] are turned on regardless of the potentials of holding nodes SN[1] to SN[3] (see Fig.14 and Fig.17 ). In addition, the wiring RBL is precharged with the potential H. In other words, after the potential of the wiring RBL is made the potential H, the wiring RBL is placed in a floating state.

[0248] [Period T4] In period T4, potential R as a read potential is supplied to wiring RBG connected to memory cell 10 to be read. Potential R is a potential between potential H and potential L. In the present embodiment, potential R is 0 V. Thus, 0 V as potential R is supplied to wiring RBG[2].

[0249] Since the potential of the holding node SN[2] is at the potential H and the potential of the wiring RBG[2] is at the potential R, the transistor RTr[2] is turned on (see Fig.14 and Fig.18 ). In addition, the potential L is supplied to the wiring SL.

[0250] [Period T5] During period T5, transistor 121 is turned on. At this time, since transistors RTr[1] to RTr[3] and transistor 122 are turned on, wiring RBL and wiring SL are connected via the transistor. As a result, the potential of wiring RBL precharged to potential H is changed to potential L (see Fig.14 and Fig.19 ).

[0251] It can be seen that the potential of the wiring RBL becomes the potential L in the period T5, and thus the potential H is held in the memory cell 10 [2].

[0252] [Period T6] In the period T6, the potentials of the transistors 121, 122, and the wirings RBG[1] to RBG[3] are set to the potential L (see Fig.14 and Fig. 20 ). Note that, when the read operation is performed, the information written to the holding node SN is not erased but is held. Thus, the memory cell 10 is a memory element capable of non-destructive reading.

[0253] <<When the potential L is maintained>> Next, the read operation when the potential L is maintained in the memory cell 10[2] is described. When the potential L is maintained in the memory cell 10[2], the potential change in the period T5 is different. In addition, even if the potential of the wiring RBG[2] is set to the potential R in the period T4, the potential of the node SN[2] is also maintained at the potential L, so that the transistor RTr[2] continues to be in the off state.

[0254] [Period T5x] During period T5x, transistor 121 is turned on. At this time, transistors RTr[1], RTr[3], and 122 are turned on, but transistor RTr[2] is turned off, so wiring RBL is not connected to wiring SL. As a result, the potential of wiring RBL precharged to potential H continues to maintain potential H (see Fig.14 and Fig.21 ).

[0255] In the period T5x, the potential of the wiring RBL continues to be maintained at the potential H, and thus it can be seen that the potential L is maintained in the memory cell 10[2].

[0256] In this way, information can be written to and read from the memory cell 10 .

[0257] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0258] Implementation 3 In this embodiment, an oxide semiconductor layer which can be used as a semiconductor layer of a transistor is described.

[0259] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide for the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Thus, the reliability of the transistor using the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of the memory device including the transistor can be improved.

[0260] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure refers to a crystal structure in which a plurality of crystallites (typically, a plurality of crystallites having a hexagonal crystal structure) have a c-axis orientation and are connected on the ab plane in a manner in which the plurality of crystallites are not oriented. In addition, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM (High Resolution Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal portion. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having a layered crystal portion.

[0261] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED), or by combining a plurality of the above methods.

[0262] In addition, there is no particular restriction on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes contains one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof). When the oxide semiconductor layer has crystallinity, it is possible to suppress the degradation of transistor characteristics.

[0263] As the metal oxide included in the oxide semiconductor layer of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. In addition, element M is a metal element or semi-metal element with high bonding energy with oxygen, for example, a metal element or semi-metal element with higher bonding energy with oxygen than indium. As element M, specifically aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In the case where the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0264] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. In addition, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide) and the like containing silicon may also be mentioned.

[0265] By increasing the ratio of the number of atoms of indium to the total number of atoms of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0266] In addition, the metal oxide may also include one or more of the metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may include one or more of the metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Thus, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As the metal element with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be specifically cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0267] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0268] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0269] In addition, by increasing the ratio of the number of atoms of the element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0270] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0271] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. In addition, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0272] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0273] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following process: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. At this time, as the first deposition method, it is preferred to use a deposition method that causes less damage to the formed surface than the second deposition method. When a deposition method that causes less damage to the formed surface is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer of the formed surface of the oxide semiconductor layer can be suppressed. In addition, impurities such as silicon can be suppressed from mixing into the second layer, so the crystallinity of the oxide semiconductor layer can be improved.

[0274] As the first deposition method, for example, atomic layer deposition (ALD: Atomic Layer Deposition) method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, wet method, etc. can be cited. As the CVD method, for example, plasma CVD (PECVD: Plasma Enhanced CVD) method, thermal CVD method, optical CVD method, metal organic CVD (MOCVD: Metal Organic CVD) method, etc. can be cited. As a wet method, for example, a spraying method can be cited. Compared with the sputtering method described later, the ALD method and the CVD method can suppress the damage to the formed surface, so they are suitable for the first deposition method.

[0275] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant is excited by plasma.

[0276] When using the ALD method, atoms can be deposited layer by layer, so there are the following effects: it can be deposited extremely thinly; it can be deposited on a structure with a high aspect ratio or a surface with a large step; it can be deposited with a method with few defects such as pinholes; it can be deposited with high coverage; and it can be deposited at a low temperature; etc. In addition, the PEALD method uses plasma and can be deposited at a lower temperature, so it is sometimes preferred. Note that as precursors used in the ALD method, there are precursors containing elements such as carbon or chlorine. Therefore, compared with films set by other deposition methods, films set by the ALD method sometimes contain more elements such as carbon or chlorine. Note that the quantification of these elements can be performed by X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In addition, the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but because one or both of the conditions of high substrate temperature during deposition and impurity removal treatment are used, the carbon and chlorine content in the film is sometimes less than when the ALD method is used without the above conditions.

[0277] Unlike a deposition method that deposits particles released from a target material, the ALD method is a deposition method that forms a film by a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, and is therefore suitable for covering the surface of an opening with a high aspect ratio.

[0278] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since no plasma is used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. In addition, in the thermal CVD method, no plasma damage is generated during formation, so a film with fewer defects can be obtained.

[0279] Examples of the second deposition method include sputtering and pulsed laser deposition (PLD: Pulsed Laser Deposition) methods. The metal oxide formed by the second deposition method tends to have a CAAC structure.

[0280] In addition, as the first layer, a metal oxide having a microcrystalline structure or an amorphous structure, for example, whose crystallinity is lower than that of the CAAC structure, is sometimes formed. By forming a second layer having high crystallinity on the first layer having low crystallinity or forming the layer and heat-treating it, the crystallinity of the first layer is sometimes improved with the second layer as the core. Thus, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the formed surface can be improved.

[0281] In addition, a third layer may be formed on the second layer. Since the second layer has high crystallinity, the third layer may be crystallized with the crystal of the second layer as a nucleus or seed. Thus, even if the deposition method of the third layer does not use a deposition method that is easy to have crystallinity, the third layer may be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, the oxide semiconductor layer as a whole may have both high crystallinity and high coverage.

[0282] As an example, an oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following process: after forming a metal oxide as a first layer using a first deposition method, a metal oxide is formed as a second layer using a second deposition method, and then a metal oxide is formed as a third layer using the first deposition method. Specifically, the ALD method can be used as the first deposition method, and the sputtering method can be used as the second deposition method. The ALD method is a deposition method with excellent coverage compared to the sputtering method. When the ALD method is used as the deposition method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0283] [Method for producing oxide semiconductor layer] The semiconductor layer 230 as an oxide semiconductor layer can be manufactured, for example, by the following process: forming a semiconductor layer 230a on the layer 229 to be formed by the ALD method, forming a semiconductor layer 230b as an oxide semiconductor layer by the sputtering method on the semiconductor layer 230a as an oxide semiconductor layer, and forming a semiconductor layer 230c as an oxide semiconductor layer by the ALD method on the semiconductor layer 230b. In addition, it is preferable to perform a heat treatment after forming the semiconductor layer 230 as an oxide semiconductor layer. By performing the heat treatment, the crystallinity of the semiconductor layer 230 can be improved. The heat treatment described here is not limited to the heat treatment. For example, it can also be the heat received in the manufacturing process.

[0284] The layer 229 corresponds to the insulating layer 235 or the insulating layer 280 described in the above embodiment. The layer 229 does not necessarily have crystallinity. When the layer 229 has crystallinity, the layer 229 may have a crystal structure with low lattice conformity with the metal oxide included in the semiconductor layer 230.

[0285] Reference FIG. 22A to FIG. 22D and FIG. 23A to FIG. 23D An example of a method for manufacturing the semiconductor layer 230 will be described.

[0286] In the case of depositing a metal oxide film by sputtering, alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface sometimes occurs due to damage caused by sputtered particles on the formed surface or energy applied to one side of the substrate by sputtered particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed area even when the heat treatment described later is performed. When an oxide semiconductor layer having an alloyed area is used in a transistor, there is concern that the initial characteristics or reliability of the transistor will be negatively affected. Therefore, it is preferred to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface.

[0287] Thus, first, a semiconductor layer 230a ( Fig.22A Then, a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering. Fig. 22B ).

[0288] In a method for manufacturing an oxide semiconductor layer of one embodiment of the present invention, a semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 using a deposition method that causes less damage to the formed surface, thereby suppressing the alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, and the crystallinity of the semiconductor layer 230 can be further improved.

[0289] By adopting the above structure, the thickness of the alloyed region can be reduced or the alloyed region can be reduced to an unobservable level. For example, the thickness of the alloyed region can be reduced to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Fig.22A and Fig. 22B An example is shown in which no alloyed region is formed between the layer 229 and the semiconductor layer 230 a .

[0290] Note that the thickness of the alloyed region may be calculated by linearly analyzing the composition of the region and its vicinity using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0291] For example, the linear analysis of the above-mentioned region and its vicinity using EDX is performed with the direction perpendicular to the formed surface of the semiconductor layer 230a as the depth direction. Next, in the distribution of the quantitative values ​​of each element in the depth direction obtained relative to the analysis, the depth at which the quantitative value of the metal (In when the semiconductor layer 230a contains In) which is the main component of the semiconductor layer 230a but not the main component of the layer of the formed surface reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the semiconductor layer 230a. In addition, the depth at which the quantitative value of the element (for example, Si) which is the main component of the layer of the formed surface but not the main component of the semiconductor layer 230a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer of the formed surface. Thus, the thickness of the alloyed region can be calculated.

[0292] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, the thickness is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm.

[0293] For example, when a silicon oxide layer is used as the layer 229 and the semiconductor layer 230 formed on the layer 229 is subjected to SIMS analysis, the depth at which the concentration of silicon reaches 50% of the maximum value of the concentration in the layer 229 is regarded as the interface, and the concentration of silicon is reduced to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance from the depth to the interface is regarded as the thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0294] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0295] In addition, by thinning the alloyed region, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm from the formed surface of the semiconductor layer 230 in a substantially vertical direction.

[0296] Note that the CAAC structure may be confirmed near the formed surface during observation using TEM. For example, when observing the cross section of the semiconductor layer 230 using high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface may be confirmed near the formed surface.

[0297] When the semiconductor layer 230a is formed by the ALD method, a microcrystalline structure or an amorphous structure oxide semiconductor layer having lower crystallinity than the CAAC structure may be formed. Fig.22A In the manufacturing stage shown, semiconductor layer 230a sometimes includes regions having lower crystallinity than semiconductor layer 230b.

[0298] The semiconductor layer 230 b preferably has a composition suitable for forming a CAAC structure.

[0299] When the semiconductor layer 230b is formed by sputtering, the mixed layer 231 is formed on the surface or near the surface of the semiconductor layer 230a. In addition, when the semiconductor layer 230b is formed, a tiny crystal region may be formed in the mixed layer 231 due to sputtered particles or energy applied to the substrate side by the sputtered particles. In the subsequent heat treatment process, the mixed layer 231 or the tiny crystal region formed in the mixed layer 231 may serve as a nucleus to crystallize at least a part of the semiconductor layer 230a.

[0300] When the semiconductor layer 230b is deposited by sputtering, the substrate is preferably heated. When forming a metal oxide, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) when forming the metal oxide.

[0301] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by using an ALD method. Fig. 22C When the semiconductor layer 230 c is formed by the ALD method, the formation method of the semiconductor layer 230 a may be referred to.

[0302] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c is sometimes epitaxially grown with the semiconductor layer 230b as the core. Thus, when the semiconductor layer 230c is formed, the semiconductor layer 230c sometimes includes a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed in the entire semiconductor layer 230c.

[0303] Next, a heat treatment process may be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the semiconductor layer 230c is sometimes improved. In addition, when the region is formed only below the semiconductor layer 230c after deposition by the ALD method, the region may be expanded to the upper part of the semiconductor layer 230c by the heat treatment process ( Fig.22D ). That is, by performing this heat treatment, a region having a CAAC structure in the semiconductor layer 230c is sometimes formed in the entire semiconductor layer 230c.

[0304] In addition, it is preferred that at least a portion of the semiconductor layer 230a is converted to CAAC by the heat treatment step ( Fig.22D ). It is expected that the mixed layer 231 formed in the semiconductor layer 230a when the semiconductor layer 230b is deposited is used as a core or seed to facilitate CAAC. In the semiconductor layer 230a, the larger the CAAC area is, the better, and it is preferred that the vicinity of the layer 229 is also CAACized.

[0305] In addition, since CAAC is performed from the upper part of the semiconductor layer 230a to the lower part thereof, it is not limited by the material or crystallinity of the layer 229, and the vicinity of the layer 229 can also be CAAC. For example, even if the layer 229 has an amorphous structure, a semiconductor layer 230a with high crystallinity can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0306] Notice, FIG. 22A to FIG. 22D : is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 22A to FIG. 22D It can also be regarded as a schematic diagram of a deposition model of a metal oxide according to one embodiment of the present invention. FIG. 22A to FIG. 22D As shown, the crystallinity of the semiconductor layer 230a and the semiconductor layer 230c is improved by using the semiconductor layer 230b with high crystallinity as a core or seed. Specifically, the crystallinity of the semiconductor layer 230a is sometimes improved by heat treatment when the semiconductor layer 230b is deposited or after the semiconductor layer 230c is deposited. In addition, the crystallinity of the semiconductor layer 230c is sometimes improved by heat treatment when the semiconductor layer 230c is deposited or after the semiconductor layer 230c is deposited. Note that the above-mentioned heat treatment has the function of assisting in improving the crystallinity.

[0307] Thus, in a metal oxide deposition method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, semiconductor layer 230a and semiconductor layer 230c) can be improved by using the highly crystalline semiconductor layer 230b (that is, CAAC) as a core or seed. Thus, the crystallinity of the oxide semiconductor as a whole can be improved. In other words, the upper and lower oxide semiconductors are solid-phase epitaxially grown using the semiconductor layer 230b as a core or seed, thereby forming an oxide semiconductor with high crystallinity. The oxide semiconductor formed by this deposition method, here the CAAC film, can be called axial growth (Axial Growth) CAAC (AG CAAC). Note that, FIG. 23A to FIG. 23D The structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c is shown, but the present invention is not limited thereto. For example, the structure including the semiconductor layer 230a and the semiconductor layer 230b may also be referred to as AG CAAC.

[0308] In the semiconductor layer 230 , the region having the CAAC structure preferably exists widely throughout the entire layer. Fig.23A The semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are all crystallized. In this case, the boundary between the semiconductor layer 230a and the semiconductor layer 230b is sometimes not observed. In addition, the boundary between the semiconductor layer 230b and the semiconductor layer 230c is sometimes not observed. The semiconductor layer 230 can sometimes be said to be a layer whose interface is not clearly observed. The semiconductor layer 230 can sometimes be said to be a layer of a single-layer structure.

[0309] In addition, part of the semiconductor layer 230 a or the semiconductor layer 230 c may not be crystallized. Fig. 23B The illustrated example shows a state in which the vicinity of the interface between the semiconductor layer 230 a and the layer 229 is not crystallized. Fig.23C The semiconductor layer 230 c is shown in a state where the vicinity of the surface is not crystallized. Fig.23D The semiconductor layer 230 a and the vicinity of the interface with the layer 229 and the vicinity of the surface of the semiconductor layer 230 c are not crystallized.

[0310] By improving the crystallinity of the oxide semiconductor layer, the increase in the resistance of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed and the initial characteristics of the transistor (especially the on-state current) are improved, thereby it can be expected that a transistor suitable for high-speed driving can be realized. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0311] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity in the entire layer. Therefore, the boundary of the stacked film cannot be observed in the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c in the semiconductor layer 230. In particular, after the heat treatment, it is difficult to confirm the boundary of the stacked film. In order to confirm the presence or absence of the boundary of the stacked film, for example, TEM can be used.

[0312] As described above, by using a metal oxide with a high In content in a transistor, the field effect mobility of the transistor can be improved. On the other hand, an oxide semiconductor with a high In content has a tendency to polycrystallize. By using a metal oxide with a polycrystalline structure in a transistor, the initial characteristics or reliability of the transistor is negatively affected. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, a crystal reflecting the orientation of the crystal in the semiconductor layer 230b is formed, thereby suppressing polycrystallization.

[0313] In addition, the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is preferably small. Thus, the semiconductor layer 230a or the semiconductor layer 230c can form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. At this time, for example, when the semiconductor layer 230 is observed in cross section using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0314] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small, there is no particular limitation on the crystal structure of the semiconductor layer 230a or the semiconductor layer 230c. The crystal structure of the semiconductor layer 230a or the semiconductor layer 230c may be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0315] [Composition of Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. When forming the semiconductor layer 230b, for example, a sputtering method can be used. The semiconductor layer 230b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be achieved. In addition, the semiconductor layer 230b preferably contains element M in addition to zinc. When the semiconductor layer 230b contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. As a result, the reliability of the transistor using the oxide semiconductor layer can be improved. As the semiconductor layer 230b, specifically, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition near it, In:M:Zn=1:1:1.2 [atomic ratio] or a composition near it, In:M:Zn=1:1:0.5 [atomic ratio] or a composition near it, In:M:Zn=1:1:2 [atomic ratio] or a composition near it, In:M:Zn=4:2:3 [atomic ratio] or a composition near it, In:M:Zn=1:3:2 [atomic ratio] or a composition near it, or In:M:Zn=1:3:4 [atomic ratio] or a composition near it can be used. In addition, the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, as the element M, one or more of gallium, aluminum, and tin are preferably used.

[0316] The semiconductor layer 230b may also have a structure that does not contain the element M. For example, In-Zn oxide may also be used. Specifically, a composition of In:Zn=1:1 [atomic ratio] or thereabouts, a composition of In:Zn=2:1 [atomic ratio] or thereabouts, or a composition of In:Zn=4:1 [atomic ratio] or thereabouts may be used. Alternatively, indium oxide may also be used. In addition, a structure containing a trace amount of the element M may also be used. For example, a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or thereabouts, or a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or thereabouts may be used. In addition, for example, a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or thereabouts, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or thereabouts may be used.

[0317] The semiconductor layer 230a and the semiconductor layer 230c may use a metal oxide having a high ratio of In. When forming the semiconductor layer 230a and the semiconductor layer 230c, for example, the ALD method may be used. In addition, it is particularly preferred to use a metal oxide having a high ratio of In compared to the element M. By using a metal oxide having a high ratio of In, when the oxide semiconductor layer is used for a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0318] Alternatively, the semiconductor layer 230a and the semiconductor layer 230c may also have a structure that does not contain the element M. For example, In-Zn oxide may also be used. Specifically, a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto. In addition, indium oxide may also be used. In addition, the semiconductor layer 230a and the semiconductor layer 230c may also have a structure that contains a trace amount of the element M. Specifically, a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition close thereto, a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition close thereto.

[0319] In addition, by increasing the zinc composition of the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, it is preferred to adopt a structure in which the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by the ALD method and the semiconductor layer 230b is formed by the sputtering method, the zinc contained in the semiconductor layer 230a sometimes diffuses into the semiconductor layer 230b. Note that this diffusion is caused by heat treatment during or after sputtering. When zinc diffuses from the semiconductor layer 230a to the semiconductor layer 230b, it is expected that the crystallinity will be improved. In addition, when zinc diffuses from the semiconductor layer 230a to the semiconductor layer 230b, it is expected that the crystalline part with c-axis orientation will grow laterally to promote CAAC.

[0320] In addition, the semiconductor layer 230 a and the semiconductor layer 230 c can be said to be metal oxides having a higher In content than the semiconductor layer 230 b .

[0321] In addition, for example, as the semiconductor layer 230a and the semiconductor layer 230c, a metal oxide having a higher Ga ratio than the semiconductor layer 230b may be used. For example, the semiconductor layer 230a and the semiconductor layer 230c preferably use a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the Ga ratio, for example, the band gaps of the semiconductor layer 230a and the semiconductor layer 230c may be made larger than those of the semiconductor layer 230b. Thus, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c having a large band gap, and the semiconductor layer 230b is mainly used as a current path (channel). When the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, the trap levels at the interface of the semiconductor layer 230b and its vicinity may be reduced. Thus, an embedded channel transistor in which the channel is far away from the insulating layer interface can be realized, thereby improving the field effect mobility.

[0322] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the semiconductor layer 230a and the semiconductor layer 230c have a composition that makes it difficult to form a CAAC structure when formed as a single layer, by crystal growth with the semiconductor layer 230b as a core, a structure having a CAAC structure in the entire oxide semiconductor layer including the semiconductor layer 230a and the semiconductor layer 230c can be achieved. Alternatively, a region spanning at least a portion of each of the semiconductor layer 230a and the semiconductor layer 230c and a region of the semiconductor layer 230b can have a CAAC structure.

[0323] In particular, even in the composition of the semiconductor layer 230a and the semiconductor layer 230c with a high ratio of In, the crystallinity of the semiconductor layer suitable for use as a transistor can be achieved. In the oxide semiconductor layer of one embodiment of the present invention, the following effects can be achieved simultaneously: by increasing the ratio of In, the on-state characteristics of the transistor are improved; by adopting a CAAC structure with high crystallinity, the reliability is improved.

[0324] Note that the composition of the semiconductor layer 230 a may be different from the composition of the semiconductor layer 230 c .

[0325] Alternatively, the semiconductor layer 230 a and the semiconductor layer 230 c may use a metal oxide having the same composition as that of the semiconductor layer 230 b .

[0326] By using the oxide semiconductor layer with a CAAC structure formed by the two deposition methods mentioned above in the channel formation region of the transistor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0327] When analyzing the composition of the metal oxide used for the semiconductor layer 230, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a combination of multiple of the above methods can be used for analysis. Note that due to the influence of analysis accuracy, the actual content of an element with a low content is sometimes different from the content obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0328] [c-axis orientation ratio] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The degree of crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated by, for example, crystal orientation.

[0329] The crystal orientation can be obtained by using the FFT pattern obtained by performing fast Fourier transform (FFT) processing on the TEM image. Specifically, the FFT pattern is used to obtain the direction of the crystal axis. The FFT pattern obtained by FFT processing reflects the same reciprocal lattice spatial information as the electron beam diffraction pattern.

[0330] By performing FFT processing on each region of the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area range, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are confirmed in the FFT pattern of the region with the layered crystal part. The direction of the crystal axis of the region can be known from the angle of the line segment connecting the two spots.

[0331] The c-axis orientation ratio can be calculated by calculating the ratio of the region oriented to the c-axis in the diagram showing the crystal orientation. Note that the region oriented to the c-axis here refers to a region whose orientation coincides with the c-axis and a region whose orientation differs from the c-axis by less than 20°.

[0332] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by observing the cross section or plane of the oxide semiconductor layer by TEM. In addition, the region where FFT is performed (also referred to as FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0333] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and further preferably 95% or more.

[0334] In addition, the c-axis orientation ratios of the region deposited as the semiconductor layer 230a, the region deposited as the semiconductor layer 230b, and the region deposited as the semiconductor layer 230c may be respectively Rc1, Rc2, and Rc3. Rc2 and Rc3 are both 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0335] Note that in the semiconductor layer 230 , the boundaries between the semiconductor layers 230 a , 230 b , and 230 c may not be clearly observed after manufacturing.

[0336] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region, in order from the layer 229. Each region is a layered region.

[0337] The first region, the second region, and the third region all have a CAAC structure. In addition, the c-axis orientation ratio of the third region is preferably higher than that of the first region. In addition, the c-axis orientation ratio of the second region is preferably higher than that of the first region. In addition, the c-axis orientation ratios of the second region and the third region are respectively 80% or more, more preferably 90% or more, and further preferably 95% or more.

[0338] The first region is located in a range of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located in a range of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0339] Alternatively, the thickness of the layer in each region may be substantially the same, for example.

[0340] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0341] Implementation 4 In this embodiment, a configuration example of a storage device 300 including a memory string 100 according to one embodiment of the present invention will be described.

[0342] <Storage Device 300> Fig.24A 1 is a block diagram showing a configuration example of a storage device 300 including a memory string 100 according to one embodiment of the present invention. Fig.24A The memory device 300 shown includes a driving circuit 21 and a memory cell array 310 .

[0343] The memory cell array 310 includes a plurality of memory strings 100 arranged in a matrix of p rows and q columns (p and q are integers greater than or equal to 1). By arranging the plurality of memory strings 100 in a matrix, a memory device with a large storage capacity can be realized.

[0344] exist Fig.24A , the memory string 100 in the first row and first column is represented as memory string 100[1, 1], the memory string 100 in the p-th row and q-th column is represented as memory string 100[p, q], the memory string 100 in the p-th row and first column is represented as memory string 100[p, 1], the memory string 100 in the first row and q-th column is represented as memory string 100[1, q], and the memory string 100 in the r-th row and s-th column (r is an integer greater than 1 and less than p representing any row, and s is an integer greater than 1 and less than q representing any column) is represented as memory string 100[r, s].

[0345] In addition, rows and columns extend in directions orthogonal to each other. In this embodiment, the X direction (the direction along the X axis) is called a "row" and the Y direction (the direction along the Y axis) is called a "column", but the X direction may be called a "column" and the Y direction may be called a "row".

[0346] The driving circuit 21 includes a power switch 22, a power switch 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generating circuit 33.

[0347] In the storage device 300, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0348] In addition, the signal BW, the signal CE and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 32.

[0349] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0350] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when a signal of potential H is supplied as the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0351] The peripheral circuit 41 is a circuit for writing data to the memory string 100 and reading data from the memory string 100. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, a sense amplifier 46, and an output circuit 48.

[0352] The row decoder 42 and the column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has a function of selecting the wiring (wiring WWL, wiring WBG, wiring RBG) specified by the row decoder 42. The column driver 45 has a function of supplying the data stored in the memory string 100 to the wiring WBL specified by the column decoder 44. In addition, the column driver 45 has a function of supplying the potential H to the wiring RBL specified by the column decoder 44. The sense amplifier 46 has a function of detecting a change in the potential of the wiring RBL specified by the column decoder 44 and reading out the data stored in the memory string 100.

[0353] The input circuit 47 has a function of holding a signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory string 100. The data (Dout) read from the memory string 100 by the sense amplifier 46 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0354] The power switch 22 has a function of controlling the supply of the potential VDD to the peripheral circuit 31. The power switch 23 has a function of controlling the supply of the potential VHM to the row driver 43. Here, the high power supply potential of the memory device 300 is the potential VDD, and the low power supply potential is the potential GND (ground potential). In addition, the potential VHM is a power supply potential for making the word line (for example, the wiring WWL) become the potential H, and is a potential higher than the potential VDD. The power switch 22 is turned on and off by the signal PON1, and the power switch 23 is turned on and off by the signal PON2. In Fig.24A In the embodiment, the number of power domains to which the potential VDD is supplied in the peripheral circuit 31 is one, but the number of power domains may be plural. In this case, a power switch may be provided for each power domain.

[0355] In addition, if Fig. 24B As shown, the driving circuit 21 may be provided in the layer 50, and the layer 20 including the memory cell array 310 may be provided overlapping with the layer 50. The layer 50 may also use a single crystal semiconductor substrate or an SOI substrate. By separately forming the layer 50 including the driving circuit 21 and the layer 20 including the memory cell array 310, the operation of the driving circuit 21 included in the layer 50 may be confirmed before forming the layer 20 on the layer 50. Thus, good products in the layer 50 may be selected, and the manufacturing yield of the memory device 300 may be improved.

[0356] By overlapping the layer 50 including the driving circuit 21 and the layer 20 including the memory cell array 310, the signal transmission distance between the driving circuit 21 and the memory cell array 310 can be shortened. As a result, the parasitic resistance and parasitic capacitance between the driving circuit 21 and the memory cell array 310 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized. In addition, the storage capacity per unit area can be increased.

[0357] <Stacked Structure Example of Memory Device> Fig.25 An example of a stacked structure of a memory device 300 which is one of semiconductor devices is shown. Fig.25The illustrated memory device 300 includes a layer 20 including a memory cell array 310 above a layer 50 including a driving circuit 21. Fig.25 As an example, the memory cell 10[i] and the memory cell 10[i+1] included in the memory string 100[r, s] are shown. Fig.25 In FIG. 1 , [i] is assigned to a part of the layer constituting the memory cell 10 [i]. Also, [i+1] is assigned to a part of the layer constituting the memory cell 10 [i+1].

[0358] Note that in order to avoid duplication of description, the description of the storage unit 10 is omitted here.

[0359] In addition, Fig.25 , a transistor 400 is shown as a transistor included in the driving circuit 21. The transistor 400 is provided on a substrate 371, and includes a conductive layer 376 used as a gate, an insulating layer 375 used as a gate insulating layer, a semiconductor region 373 formed by a portion of the substrate 371, and a low resistance region 374a and a low resistance region 374b used as a source region or a drain region. The transistor 400 can be any one of a p-channel transistor and an n-channel transistor. As the substrate 371, for example, a single crystal silicon substrate can be used.

[0360] Here, in Fig.25 In the transistor 400 shown, the semiconductor region 373 (a part of the substrate 371) forming the channel has a convex shape. In addition, the conductive layer 376 covers the side and top surfaces of the semiconductor region 373 via the insulating layer 375. In addition, the conductive layer 376 can also use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also called a FIN-type transistor. In addition, an insulating layer used as a mask for forming the convex portion can also be provided in a manner that contacts the upper portion of the convex portion. In addition, although a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI (Silicon on Insulator) substrate can also be processed to form a semiconductor film having a convex shape.

[0361] Notice, Fig.25 The structure of the transistor 400 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0362] A wiring layer including an interlayer film, wiring, and plugs may also be provided in layer 50. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and plugs electrically connected to the wiring may also be one component. That is, a part of the conductive layer may be used as wiring, and a part of the conductive layer may be used as a plug.

[0363] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are sequentially stacked as interlayer films on the transistor 400. In addition, a conductive layer 392 and the like are embedded in the insulating layer 390 and the insulating layer 391. In addition, a conductive layer 395 and the like are embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392 and the conductive layer 395 are used as contact plugs or wirings.

[0364] In addition, the insulating layer used as an interlayer film can also be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like.

[0365] A wiring layer may also be provided on the insulating layer 394 and the conductive layer 395. Fig.25 In the embodiment, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are sequentially stacked on the insulating layer 394 and the conductive layer 395. A conductive layer 386 is formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 is used as a contact plug or wiring. The memory string 100[r, s] is connected to the transistor 400 through the conductive layer 386.

[0366] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0367] Implementation method 5 In this embodiment, an application example of a storage device including a storage element which is one embodiment of the present invention (hereinafter also referred to as “a storage device which is one embodiment of the present invention”) is described.

[0368] Generally speaking, in semiconductor devices such as computers, various storage devices are used depending on their applications. Fig.26A Various storage devices used in semiconductor devices are shown in a hierarchical manner. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the storage density is required. Fig.26A , the memory installed together as registers in a CPU or other arithmetic processing device, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown in order from the top layer.

[0369] Since the memory installed together with the register in the CPU and other processing devices is used for temporary storage of the calculation results, the access frequency from the processing devices is high. Therefore, the operation speed is required to be faster than the storage capacity. In addition, the register has the function of holding the setting information of the processing device.

[0370] SRAM is used, for example, for cache. The cache has the function of copying and retaining a portion of the information stored in the main memory. By copying and retaining frequently used data in the cache, the speed of accessing the data can be increased. The storage capacity required for the cache is less than that of the main memory, while the operating speed required for the cache is higher than that of the main memory. In addition, the data rewritten in the cache is copied and supplied to the main memory.

[0371] DRAM is used, for example, as a main memory. The main memory has the function of retaining programs and data read from storage. The storage density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 .

[0372] 3D NAND memory is used for storage, for example. The storage has the function of maintaining data that needs to be stored for a long time and various programs used in the computing processing device. Therefore, in storage, a large storage capacity and a high storage density are required more than the operating speed. The storage density of the storage device used for storage is about 0.6 to 6.0 Gbit / mm 2 .

[0373] The storage device of one embodiment of the present invention operates at a high speed and can retain data for a long time. The storage device of one embodiment of the present invention is suitable for use as a storage device located in a boundary area 901 between a layer including a cache and a layer including a main memory. In addition, the storage device of one embodiment of the present invention is suitable for use as a storage device located in a boundary area 902 between a layer including a main memory and a layer including a storage.

[0374] Furthermore, the storage device according to one aspect of the present invention is suitable for use in both a hierarchy including a main memory and a hierarchy including a storage. Furthermore, the storage device according to one aspect of the present invention is suitable for use in a hierarchy including a cache. Fig.26B Shown with Fig.26A Different levels of various storage devices.

[0375] exist Fig.26B, a memory installed together with a register in a CPU or other computing device, an SRAM used as a cache, and a storage device 300 of one embodiment of the present invention are shown in order from the top layer. The cache, the main memory, and the storage can use the storage device 300 of one embodiment of the present invention. Note that when a high-speed memory of 1 GHz or more is required as a cache, the cache is installed together with a CPU or other computing device.

[0376] For example, a storage device according to one embodiment of the present invention can be used in electronic components, large computers, space equipment, data centers (DCs), and various electronic devices. By using a storage device according to one embodiment of the present invention, low power consumption and high performance of electronic components, large computers, space equipment, DCs, and various electronic devices can be achieved.

[0377] Electronic devices include, for example, television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like.

[0378] The electronic device of this embodiment may also include a sensor (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0379] The electronic device of this embodiment may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0380] [Electronic components] Fig.27A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig.27A The electronic component 700 shown includes the storage device 300 within a mold 711. Fig.27A700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 300 through a lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the above-mentioned electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0381] In addition, the memory device 300 includes a layer 50 and a layer 20. Note that the layer 50 includes a driving circuit 21, and the layer 20 includes a memory cell array 310. The memory cell array 310 includes a plurality of memory strings 100. In addition, the memory string 100 includes a plurality of memory cells 10. The memory device 300 may have a monolithic stacked structure of the layer 50 and the layer 20. In the monolithic stacked structure, each layer may be connected without using a through-electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. When having a monolithic stacked structure of the layer 50 and the layer 20, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor may be realized. By adopting an on-chip memory structure, high-speed operation of the interface portion between the processor and the memory may be realized.

[0382] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0383] In addition, it is preferred that the memory cell array 310 in the layer 20 is formed using OS transistors, and the plurality of memory cell arrays are stacked in a monolithic manner. When the plurality of memory cell arrays have a monolithic stacked structure, one or both of the bandwidth of the memory and the access delay of the memory can be improved. The bandwidth refers to the amount of data transmitted per unit time, and the access delay refers to the time between accessing and starting the exchange of data. When Si transistors are used in the layer 20, it is more difficult to adopt a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0384] In addition, the storage device 300 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon chip.

[0385] then, Fig.27B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 300 are provided on the interposer 731.

[0386] The electronic component 730 shows an example of using the storage device 300 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0387] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0388] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are arranged in a single layer or in multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit arranged on the interposer 731 to the electrode arranged on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is arranged in the interposer 731, and the through electrode is used to electrically connect the integrated circuit to the package substrate 732. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0389] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0390] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to be poor. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5-dimensional mounting), in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0391] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, there is the problem of the width of the terminal pitch, and it is sometimes difficult to set up more wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0392] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the height of the integrated circuit provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the height of the storage device 300 and the semiconductor device 735 consistent.

[0393] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.27B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0394] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0395] [Mainframe computer] then, Fig.28A A perspective view of a mainframe computer 5600 is shown. Fig.28A In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0396] Computer 5620 may have, for example, Fig.28B The structure of the stereogram is shown. Fig.28B In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0397] Fig.28C The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.28C Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0398] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0399] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. As the specifications of the connection terminals 5623, 5624, and 5625, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. can be cited. In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0400] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0401] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0402] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622, for example, by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0403] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0404] [Space Equipment] A semiconductor device according to one embodiment of the present invention is suitable for use in space equipment.

[0405] A semiconductor device of one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor due to exposure to radiation change little. In other words, the resistance to radiation is high, so the OS transistor is suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space, for example, refers to an altitude of 100 km or more, but the outer space shown in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0406] exist Fig.28D In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.28D An example of a planet 6804 in outer space is shown.

[0407] In addition, although Fig.28D Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided to the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, low power consumption can be achieved, and high reliability can be achieved even in outer space, so it is preferred.

[0408] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0409] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0410] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0411] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change is small. Therefore, OS transistors are preferred because they have high reliability even in an environment where radiation may be incident.

[0412] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0413] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention is suitable for use in space equipment such as a spacecraft, a space capsule, and a space probe.

[0414] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and high resistance to radiation.

[0415] [Data Center] For example, a semiconductor device according to one embodiment of the present invention is suitable for use in a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to increase the size of the facility, such as by installing storage and servers for storing large amounts of data, ensuring a stable power supply to store data, or ensuring cooling equipment required for data storage.

[0416] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required to maintain data and to miniaturize the semiconductor device that maintains data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for maintaining data, and reduce the size of the cooling equipment. As a result, it is possible to save space in the data center.

[0417] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0418] Fig.28E A storage system that may be used in a data center is shown. Fig.28E The storage system 7010 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0419] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0420] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache is generally set in the storage to shorten the time required for data storage and output.

[0421] The above-mentioned cache is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0422] When an OS transistor is used as a transistor for storing the data in the cache to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0423] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0424] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

Claims

1. A storage device, comprising: n storage units, where n is an integer greater than 3; first wiring; n second wirings; n third wirings; as well as n fourth wirings, Each of the n storage units comprises: a first transistor; and The second transistor, The first transistor and the second transistor each include: a first conductive layer; a first insulating layer on the first conductive layer; a fourth conductive layer on the first insulating layer; a second insulating layer on the fourth conductive layer; a second conductive layer on the second insulating layer; a semiconductor layer having a region along a side surface of the fourth conductive layer; and a third conductive layer having a region along a side surface of the fourth conductive layer across the semiconductor layer, The second conductive layer of the first transistor [i] included in the i-th storage unit is electrically connected to the first wiring, i is an integer greater than 2 and less than n-1, The first conductive layer of the first transistor [i] is electrically connected to the third conductive layer of the second transistor [i] included in the i-th storage unit, The third conductive layer of the first transistor [i] is electrically connected to the i-th second wiring, The fourth conductive layer of the first transistor [i] is electrically connected to the i-th third wiring, The fourth conductive layer of the second transistor [i] is electrically connected to the i-th fourth wiring, The first conductive layer of the second transistor [i] is electrically connected to the second conductive layer of the second transistor [i-1] included in the i-1th memory cell, Furthermore, the second conductive layer of the second transistor [i] is electrically connected to the first conductive layer of the second transistor [i+1] included in the (i+1)th memory cell.

2. The storage device according to claim 1, The first transistor [i] and the second transistor [i] have a region where the first transistor [i] and the second transistor [i] overlap each other when viewed from a plane.

3. The storage device according to claim 1, The first conductive layer of the first transistor [i] is used as the third conductive layer of the second transistor [i].

4. The storage device according to claim 1, The semiconductor layer includes an oxide semiconductor.

5. The storage device according to claim 1, wherein each of the n storage cells comprises a capacitive element, And the capacitor included in the i-th storage unit is electrically connected to the third conductive layer of the second transistor [i].

6. The storage device according to claim 2, The first conductive layer of the first transistor [i] is used as the third conductive layer of the second transistor [i].

7. The storage device according to claim 2, The semiconductor layer includes an oxide semiconductor.

8. The storage device according to claim 2, wherein each of the n storage cells comprises a capacitive element, And the capacitor included in the i-th storage unit is electrically connected to the third conductive layer of the second transistor [i].

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