Semiconductor element with protective layer and preparation method thereof

Abstract

The invention discloses a semiconductor element and a preparation method thereof. The semiconductor element comprises a substrate; the first outer filling layer comprises a first concave part and a first flat part, the first concave part is arranged in the substrate and is provided with a U-shaped section profile, and the first flat part is arranged on the substrate and is connected with the first concave part; the first central layer is arranged on the first concave part of the first outer filling layer; and a first protective layer disposed on the first central layer. A top surface of the first recess and a top surface of the first protective layer are substantially coplanar.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 230,183 (i.e., the priority date is "August 4, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a method for preparing the same, and in particular to a semiconductor element having a protective layer and a method for preparing the same. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To meet the growing demand for computing power, the size of semiconductor components continues to shrink. However, various problems arise during the shrinking process, and these problems are increasing. Therefore, there are still challenges in improving the performance, quality, yield, efficiency, and reliability of semiconductor components.

[0004] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a semiconductor element, comprising a substrate; a first outer filling layer, comprising a first concave portion, which is disposed in the substrate and comprises a U-shaped cross-sectional profile; and a first flat portion, which is disposed on the substrate and connected to the first concave portion; a first central layer, which is disposed on the first concave portion of the first outer filling layer; and a first protective layer, which is disposed on the first central layer. A top surface of the first concave portion is substantially coplanar with a top surface of the first protective layer.

[0006] Another aspect of the present disclosure provides a semiconductor element, which includes a substrate, which includes a first region and a second region; a second outer filling layer, which includes a second concave portion, which is disposed in the second region of the substrate and has a U-shaped cross-sectional profile; and a second flat portion, which is disposed on the substrate and connected to the second concave portion; a second center layer, which is conformally disposed on the second concave portion and includes a U-shaped cross-sectional profile; an inner filling layer, which is disposed on the second center layer; and a plurality of second protection layers, which are disposed at both ends of the second center layer and between the second concave portion and the inner filling layer. A top surface of the second concave portion, a top surface of the inner filling layer, and a top surface of the second protection layers are substantially coplanar.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a first groove in the substrate; conformally forming a layer of a first filling material on the substrate and in the first groove to form a first recess in the first groove; forming a layer of a second filling material on the layer of the first filling material and completely filling the first recess; performing a planarization process until the layer of the first filling material is exposed to transform the layer of the first filling material into a first outer filling layer and transform the layer of the second filling material into a first center layer; and performing a surface oxidation process to form a first protective layer on the first center layer.

[0008] Due to the design of the semiconductor element disclosed in the present invention, the surface (i.e., the top surfaces of the first outer filling layer, the second outer filling layer, the first protective layer, and the second protective layer, respectively) is intact and substantially flat for subsequent semiconductor processes, thereby improving the reliability of the semiconductor element.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the disclosure of the present application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which the same reference numerals refer to the same elements.

[0011] Figure 1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure; and

[0012] Figures 2 to 17 is a cross-sectional view illustrating a process of manufacturing a semiconductor device in one embodiment of the present disclosure.

[0013] The reference numerals are described as follows:

[0014] 1: Semiconductor components

[0015] 10: Preparation method

[0016] 101: Base

[0017] 101T: Top

[0018] 201: Repair layer

[0019] 201T: Top

[0020] 203: Character line hard mask layer

[0021] 301: First outer filling layer

[0022] 301C: First recess

[0023] 301CT: Top

[0024] 301F: First flat part

[0025] 301FT: Top

[0026] 303: First Central Floor

[0027] 303T: Top surface

[0028] 401: Second outer filling layer

[0029] 401C: Second recess

[0030] 401CT: Top

[0031] 401F: Second flat part

[0032] 401FT: Top

[0033] 403: Second Central Floor

[0034] 403E: End

[0035] 403T: Top surface

[0036] 405: Second inner filling layer

[0037] 405T: Top surface

[0038] 501: First protection layer

[0039] 501B: Bottom

[0040] 501T: Top

[0041] 503: Second protection layer

[0042] 503B: Bottom

[0043] 503T: Top surface

[0044] 601: First filling material

[0045] 603: Second filling material

[0046] 603T: Top surface

[0047] 605: The third filling material

[0048] 605T: Top surface

[0049] 701: Bottom hard mask layer

[0050] 703: Top hard mask layer

[0051] 801: Sacrificial mask layer

[0052] 901: First mask layer

[0053] P1: First pattern

[0054] P2: Second pattern

[0055] R1: First Area

[0056] R2: Second Area

[0057] RS1: First Sag

[0058] RS2: Second depression

[0059] RS3: The third depression

[0060] S11: Steps

[0061] S13: Steps

[0062] S15: Steps

[0063] S17: Steps

[0064] T1: Thickness

[0065] T2: Thickness

[0066] T3: Thickness

[0067] T4: Thickness

[0068] T5: Thickness

[0069] TR1: First groove

[0070] TR2: Second groove

[0071] VL1: Vertical Level

[0072] VL2: Vertical Level

[0073] W1: Width

[0074] W2: Width

[0075] W3: Width

[0076] W4: Width

[0077] W5: Width

[0078] W6: Width

[0079] W7: Width

[0080] W8: Width

[0081] Z: Direction DETAILED DESCRIPTION

[0082] The following description of the present disclosure is accompanied by the drawings which are incorporated into and constitute a part of the specification, and illustrate embodiments of the present disclosure, but the present disclosure is not limited to the embodiments. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0083] "One embodiment", "an embodiment", "an exemplary embodiment", "another embodiment", "another embodiment", etc. mean that the embodiment described in the present disclosure may include specific features, structures or characteristics, but not every embodiment must include the specific features, structures or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but it can be the same embodiment.

[0084] In order to make the present disclosure fully understood, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, the known structures and steps are no longer described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

[0085] In the present disclosure, a semiconductor element generally refers to a device that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic components all fall into the category of semiconductor elements.

[0086] It should be noted that, in the description of the present invention, the upper side (or upward) corresponds to the direction of the Z-direction arrow, and the lower side (or downward) corresponds to the opposite direction of the Z-direction arrow.

[0087] Figure 1 is a flow chart illustrating a method for preparing a semiconductor element according to an embodiment of the present disclosure; Figures 2 to 17 2 is a cross-sectional view illustrating a process of manufacturing a semiconductor device 1 in one embodiment of the present disclosure.

[0088] Reference Figures 1 to 6 In step S11, a substrate 101 including a first region R1 and a second region R2 is provided, a plurality of first trenches TR1 are formed in the first region R1, and a second trench TR2 is formed in the second region R2.

[0089] Reference Figure 2 The substrate 101 may include a bulk semiconductor substrate. The bulk semiconductor substrate may be formed of elemental semiconductors such as silicon and germanium, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors or combinations thereof.

[0090] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure, which consists of a processing substrate, an insulator layer, and a topmost semiconductor material layer from bottom to top. The processing substrate and the topmost semiconductor material layer are formed of the same material as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. For another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulator layer includes a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer has a thickness between about 10 nanometers (nm) and 200 nm.

[0091] It should be noted that the term "approximately" changes the amount of an ingredient, component, or reactant disclosed herein, and refers to, for example, a change in the value that may occur in a concentrate or solution through typical measurements and liquid handling procedures used for preparation. In addition, changes may also arise from unintentional errors in the measurement procedures, differences in the preparation, source, or purity of the ingredients used in the preparation of the composition or implementation of the method. In some aspects, the term "approximately" refers to a change within 10% of the value shown. In other aspects, the term "approximately" refers to a change within 5% of the value shown. In other aspects, the term "approximately" refers to a change within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the value shown.

[0092] Reference Figure 2, in some embodiments, the first region R1 and the second region R2 are adjacent to each other. In some embodiments, the first region R1 and the second region R2 are separated from each other. It should be noted that the first region R1 may include a portion of the substrate 101 and a space above the portion of the substrate 101. Describing an element as being disposed on the first region R1 means that the element is disposed on a top surface of the portion of the substrate 101. Describing an element as being disposed in the first region R1 means that the element is disposed in the portion of the substrate 101; however, a top surface of the element may be flush with the top surface of the portion of the substrate 101. Describing an element as being disposed above the first region R1 means that the element is disposed above the top surface of the portion of the substrate 101. Therefore, the second region R2 may include another portion of the substrate 101 and a space above the other portion of the substrate 101. In some embodiments, the first region R1 and the second region R2 may have different element densities, which will be described later.

[0093] Reference Figure 3 , a bottom hard mask layer 701 is formed on the substrate 101. The bottom hard mask layer 701 is formed of, for example, silicon oxide. In some embodiments, the bottom hard mask layer 701 may be formed in an oxide / oxynitride atmosphere by Figure 2 The middle semiconductor device is shown to undergo a rapid thermal oxidation to form a bottom hard mask layer 701. In some embodiments, the temperature of the rapid thermal oxidation may be about 1000°C.

[0094] Reference Figure 3 , a top hard mask layer 703 is formed on the bottom hard mask layer 701. In some embodiments, the top hard mask layer 703 is formed of, for example, silicon oxide. In some embodiments, the top hard mask layer 703 can be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition. For example, the top hard mask layer 703 can be deposited by chemical vapor deposition using a silicate or silicon source, a plurality of doping sources, and an ozone source. In some embodiments, the doping source is optional. In some embodiments, the doping source can be, for example, triethyl borate, triethyl phosphate, triethyl phosphite, trimethyl phosphate, or trimethyl phosphite. In some embodiments, the silicate or silicon source can be, for example, tetramethyl orthosilicate. The doping source can produce impurity atoms such as phosphorus or boron in the top hard mask layer 703.

[0095] Reference Figure 3 , a first mask layer 901 is formed on the top hard mask layer 703. In some embodiments, the first mask layer 901 may be a photoresist and include patterns of the first trench TR1 and the second trench TR2.

[0096] Reference Figure 4, a hard mask etching process is performed using the first mask layer 901 as a mask to remove a portion of the top hard mask layer 703 and a portion of the bottom hard mask layer 701. After the hard mask etching process, the pattern of the first mask layer 901 can be transferred to the top hard mask layer 703 and the bottom hard mask layer 701. The patterns transferred from the first mask layer 901 can be referred to as a first pattern P1 and a second pattern P2. The first pattern P1 is formed above the first region R1. The second pattern P2 is formed above the second region R2. A portion of the top surface 101T of the substrate 101 is exposed by the first pattern P1 and the second pattern P2.

[0097] In some embodiments, the etching rate of the top hard mask layer 703 (or the bottom hard mask layer 701) of the hard mask etching process may be faster than the etching rate of the substrate 101 of the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 703 (or the bottom hard mask layer 701) to the substrate 101 may be between about 100:1 and about 2:1. For another example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 703 (or the bottom hard mask layer 701) to the substrate 101 may be between about 100:1 and about 10:1.

[0098] Reference Figure 4 After forming the first pattern P1 and the second pattern P2, the first mask layer 901 is removed. In some embodiments, the first mask layer 901 may be removed by, for example, an ashing process or other applicable semiconductor processes.

[0099] Reference Figure 5 A trench etching process is performed using the bottom hard mask layer 701 and the top hard mask layer 703 as masks to remove a portion of the substrate 101. This process results in the formation of a first trench TR1 in the substrate 101 and a second trench TR2 in the second region R2.

[0100] In some embodiments, the etching rate of the substrate 101 during the trench etching process may be faster than the etching rate of the top hard mask layer 703 (or the bottom hard mask layer 701) during the trench etching process. For example, during the trench etching process, the etching rate ratio of the substrate 101 to the top hard mask layer 703 (or the bottom hard mask layer 701) may be between about 100:1 and about 2:1. For another example, during the trench etching process, the etching rate ratio of the substrate 101 to the top hard mask layer 703 (or the bottom hard mask layer 701) may be between about 100:1 and about 10:1.

[0101] In some embodiments, the first region R1 has a higher element density (or pattern density or feature density) than the element density of the second region R2. The element density is a value determined by dividing the number of elements (e.g., first trenches TR1 or second trenches TR2) formed in the first region R1 (or second region R2) by the surface area of ​​each region at a top view angle. From a cross-sectional perspective, a region with a higher element density contains more elements and a smaller distance between adjacent elements (or features) than a region with a lower element density. Figure 5 The reason why the first trenches TR1 are represented by a larger number is to emphasize that the first region R1 has a higher element density than the second region R2. Figure 5 The number of first trenches TR1 or second trenches TR2 shown is for illustration purposes only.

[0102] In some embodiments, a post-etching cleaning process may be performed after forming the first trench TR1 and the second trench TR2. The post-etching cleaning process includes three stages with inter-stage rinses between each stage. Specifically, in the first stage of the post-etching cleaning process, after forming the first trench TR1 and the second trench TR2, a first cleaning solution is applied to the intermediate semiconductor element. The first cleaning solution may be cleaned by a first inter-stage rinse. In the second stage of the post-etching cleaning process, a second cleaning solution may be applied to the intermediate semiconductor element and then cleaned by a second inter-stage rinse. In the third stage of the cleaning process, a third cleaning solution may be applied to the intermediate semiconductor element and then cleaned by a post-stage rinse.

[0103] In some embodiments, during the first stage of the post-etch cleaning process, the intermediate semiconductor element is rotated at a rate between about 10 revolutions per minute (rpm) and about 2000 rpm or between about 100 rpm and 1000 rpm. The first cleaning solution can be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While the first cleaning solution is applied to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0104] In some embodiments, the first cleaning solution may include dilute hydrofluoric acid. The concentration of the first cleaning solution is about 5 parts of deionized water to one part of hydrofluoric acid and about 1000 parts of deionized water to one part of hydrofluoric acid, about 300 parts of deionized water to one part of hydrofluoric acid, or about 50 parts of deionized water to one part of hydrofluoric acid. Generally speaking, the front side of the intermediate semiconductor element is exposed to the first cleaning solution for a sufficient time to etch a sacrificial oxide (usually about 50 angstroms to 200 angstroms) or a native oxide (usually about 10 angstroms). In some embodiments, the process time of the first stage of the cleaning process is between about 20 seconds and about 50 seconds, about 40 seconds, or about 30 seconds. In some embodiments, the process time of the first stage of the post-etch cleaning process is between about 1 minute and about 5 minutes.

[0105] In some embodiments, the first cleaning solution may further include a fluorine compound, an organic acid salt, and / or glyoxylic acid.

[0106] Fluorine compounds can be included in the first cleaning solution as a component of the etching residue for removing the trench etching process. Examples of fluorine compounds may include hydrofluoric acid and ammonium fluoride salts or amine fluoride salts, such as ammonium fluoride, ammonium bifluoride, hydrofluorinated methylamine, hydrofluorinated ethylamine, hydrofluorinated propylamine, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluorinated ethanolamine, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride and triethylenediamine hydrofluoride. In some embodiments, the concentration of fluorine compounds in the first cleaning solution can be determined according to the composition of the etching residue. For example, the concentration of fluorine compounds can be about 0.1% to about 5% by mass of the total composition of the first cleaning solution, or about 0.2% to about 3% by mass of the total composition of the first cleaning solution.

[0107] The organic acid salt may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. The organic acid salt may act as a pH regulator or buffer in the first cleaning solution. The concentration of the organic acid salt may be about 0.1% to about 10% by mass of the total composition of the first cleaning solution, or about 0.3% to about 5% by mass of the total composition of the first cleaning solution.

[0108] The glyoxylic acid contained in the first cleaning solution may serve as a corrosion inhibitor.

[0109] In some embodiments, the first cleaning solution may further include a resist removal component. The resist removal component may include tetramethylammonium hydroxide and / or monomethanolamine.

[0110] The first interstage cleaning may be performed after the first stage of the post-etch cleaning process. During the first interstage cleaning, the intermediate semiconductor element after the first stage of the post-etch cleaning process may be rotated at between about 10 rpm and about 1000 rpm while being cleaned with deionized water. In some embodiments, the cleaning temperature may be between about 19° C. and about 23° C. In some embodiments, the processing time of the first interstage cleaning may be between about 20 seconds and about 50 seconds, or about 30 seconds.

[0111] In some embodiments, the deionized water used for the first interstage cleaning can be oxidized or ozonated by dissolving oxygen or ozone gas before cleaning the intermediate semiconductor elements. Dissolved oxygen or ozone is added to the deionized water at a concentration greater than 1 parts per million (ppm) to act as an oxidant. For example, the concentration of dissolved oxygen or ozone can be between about 1 ppm and about 200 ppm or between about 2 ppm and about 20 ppm. For another example, the deionized water can be saturated with dissolved oxygen or ozone. Alternatively, hydrogen peroxide at a concentration greater than 100 ppm can be added to the deionized water to act as an oxidant. Whichever oxidant is used, it should have an oxidation potential sufficient to oxidize the most noble metal in the solution. Copper (Cu 2+ ) has a standard reduction potential of 0.3 V and is typically the most noble metal present. Therefore, a standard reduction potential greater than 0.5 V is desired. Oxygen or ozone will solvate the metal ions and prevent precipitation by oxidizing the metal ions in solution. This will make the first interstage cleaning more effective, helping to reduce processing time.

[0112] In some embodiments, the deionized water used for the first interstage cleaning may have carbon dioxide dissolved therein to dissipate static electricity that builds up in the deionized water. Static electricity that builds up in the deionized water originates from the rotation of the intermediate semiconductor elements. The dissolved carbon dioxide may also make the deionized water more acidic, thereby reducing any metal contamination. In some embodiments, the carbon dioxide may be dissolved into the deionized water in an amount sufficient to dissipate static electricity. For example, the amount of carbon dioxide dissolved into the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 megohms cm.

[0113] In some embodiments, the deionized water used for the first interstage cleaning may be supplemented with isopropyl alcohol or any other liquid having a lower surface tension than deionized water. The isopropyl alcohol may help by spreading the deionized water over the front side of the intermediate semiconductor element, thereby removing the chemicals more quickly. The isopropyl alcohol may also help clean the intermediate semiconductor element during the spinning process. Alternatively, isopropyl alcohol vapor may be blown onto the front side of the intermediate semiconductor element during cleaning to assist in the first interstage cleaning.

[0114] In some embodiments, during the second stage of the post-etch cleaning process, the intermediate semiconductor element after the first stage cleaning can be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The second cleaning solution can be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While the second cleaning solution is applied to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0115] In some embodiments, the second cleaning solution can be an alkaline solution, including aqueous solutions of inorganic compounds such as sodium hydroxide, potassium hydroxide, and ammonium hydroxide, and aqueous solutions of organic compounds such as tetramethylammonium hydroxide and choline. The second cleaning solution may also contain hydrogen peroxide. The purpose of the ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic contaminants from the front side of the intermediate semiconductor element.

[0116] For example, in the present embodiment, the second cleaning solution may include ammonium hydroxide, hydrogen peroxide, and water. Ammonium hydroxide, hydrogen peroxide, and water are present in concentrations defined by dilution ratios between 5 / 1 / 1 and 1000 / 1 / 1, respectively. In some embodiments, the ammonium hydroxide / hydrogen peroxide ratio may vary between 0.05 / 1 and 5 / 1. In some embodiments, hydrogen peroxide is not used at all. The ammonium hydroxide in the second cleaning solution comes from a solution of 28-29% w / w ammonia and water. The hydrogen peroxide in the second cleaning solution may come from a solution of 31-32% w / w hydrogen peroxide and water. Due to ammonium hydroxide and hydrogen peroxide, the pH of the second cleaning solution is between about 9 and 12 or between about 10 and 11.

[0117] In some embodiments, the second cleaning solution may also include dissolved hydrogen. The hydrogen dissolved in the second cleaning solution can provide cavitation (cavitation, bubble generation) to the second cleaning solution. Providing cavitation to the second cleaning solution can enhance the post-etching cleaning process. In some embodiments, the concentration of dissolved hydrogen can be between about 0.01 mg / L to about 5 mg / L or between about 0.1 mg / L to about 5 mg / L. In some embodiments, other suitable cavitation gases, such as nitrogen, helium, argon or oxygen, can also be used. For example, dissolved oxygen with a concentration of about 1 mg / L to about 20 mg / L can be used in the second cleaning solution.

[0118] In some embodiments, the second stage of the post-etch cleaning process may have a process time between about 30 seconds and about 100 seconds, between about 30 seconds and 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution may be between about 40° C. and about 85° C.

[0119] The second inter-stage cleaning may be performed after the second stage of the post-etch cleaning process. The second inter-stage cleaning process may be similar to the first inter-stage cleaning process, and will not be described in detail herein.

[0120] In some embodiments, in the third stage of the post-etch cleaning process, the intermediate semiconductor element after the second stage cleaning is rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The third cleaning solution can be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While the third cleaning solution is applied to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0121] In some embodiments, the third cleaning solution can be an acidic solution, including aqueous solutions of inorganic acids such as hydrochloric acid, hydrofluoric acid, sulfuric acid, nitric acid, and aqueous solutions of organic acids such as oxalic acid, citric acid, malonic acid, malic acid, fumaric acid and maleic acid. In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be from about 0.001 wt % to about 10 wt % or from about 0.01 wt % to about 5 wt %. When the concentration is too low, the washing effect may not be fully obtained. When the concentration is too high, metal corrosion of cleaning equipment or other related equipment may occur.

[0122] After the third stage of the post-etch cleaning process, a post-stage cleaning process may be performed. The process of the post-stage cleaning process may be similar to the first stage cleaning process, and will not be described in detail herein.

[0123] In some embodiments, the second and third stages of the post-etch cleaning process are optional. In other words, only the first stage of the post-etch cleaning process may be performed. In some embodiments, the third stage of the post-etch cleaning process is optional. In other words, only the first and second stages of the post-etch cleaning process may be performed.

[0124] Reference Figure 6 , the top hard mask layer 703 and the bottom hard mask layer 701 may be removed by, for example, an etching process such as a wet etching process or a dry etching process. In the present embodiment, a wet etching process may be used to remove the top hard mask layer 703 and the bottom hard mask layer 701. In some embodiments, in the etching process, an etching rate ratio of the top hard mask layer 703 (or the bottom hard mask layer 701) to the substrate 101 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0125] Reference Figures 7 to 12In step S13, a plurality of first outer filling layers 301 are formed in the first trench TR1, a plurality of first center layers 303 are formed on the first outer filling layer 301 and in the first trench TR1, a second outer filling layer 401 is formed in the second trench TR2, a second center layer 403 is conformally formed on the second outer filling layer 401, and a second inner filling layer 405 is formed on the second center layer 403 and in the second trench TR2.

[0126] Reference Figure 7 , a repair layer 201 is conformally formed on the substrate 101, on the first trench TR1 and on the second trench TR2. In some embodiments, the repair layer 201 can be formed of, for example, silicon. In some embodiments, the repair layer 201 can be formed by, for example, atomic layer deposition, chemical vapor deposition or other applicable deposition processes. In some embodiments, the repair layer 201 fills the joint of the first trench TR1 and the second trench TR2. In some embodiments, the repair layer 201 can be used as a buffer layer or a stress reduction layer. The repair layer 201 can be used to relieve mechanical stress caused by the difference in thermal expansion coefficient between the substrate 101 and the insulating material subsequently filled.

[0127] Reference Figure 8 , a layer of a first filling material 601 is conformally formed on the repair layer 201. The first trench TR1 and the second trench TR2 may not be completely filled with the layer of the first filling material 601. Specifically, the layer of the first filling material 601 may be conformally formed in the first trench TR1 and the second trench TR2 along the surface of the repair layer 201, thereby generating a plurality of recesses RS1 (or first recesses RS1) facing upward in the first trench TR1, and generating a recess RS2 (or second recess RS2) facing upward in the second trench TR2. In some embodiments, the top surface of the layer of the first filling material 601 may vary from region to region due to the loading effect of the deposition. In some embodiments, the first filling material 601 may include silicon oxide or other applicable insulating materials.

[0128] In some embodiments, the layer of the first filling material 601 may be formed of, for example, silicon oxide. In some embodiments, the layer of the first filling material 601 may be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes.

[0129] In some embodiments, the layer of the first filler material 601 may be formed by a thermal oxidation and subsequent deposition process. For example, the layer of the first filler material 601 may be first deposited in an oxide / oxynitride atmosphere. Figure 7The intermediate semiconductor element shown performs a rapid thermal oxidation to conformally form a thin layer (not shown for clarity) on the repair layer 201. Subsequently, a flowable layer (not shown for clarity) is conformally formed on the thin layer. Finally, the flowable layer can be transformed into a layer of the first filling material 601.

[0130] In some embodiments, the flowable layer may include compounds with unsaturated bonds such as double bonds and triple bonds. The flowable layer is characterized by a soft jelly-like layer, a gel or liquid layer with liquid flow characteristics, but is not limited thereto. The flowable layer can flow into and fill a small substrate gap without forming a gap or a weak seam. A heat treatment may be performed subsequently to convert the flowable layer into a layer of the first filling material 601 by curing the flowable layer. The heat treatment may break the unsaturated bonds into free radicals, and the compound may be cross-linked by free radicals. Therefore, the flowable layer is cured. In some embodiments, the volume of the flowable layer decreases during the heat treatment. Therefore, compared with the flowable layer, the layer of the first filling material 601 has a greater density. The layer of the first filling material 601 may be located at a position previously occupied by the flowable layer. In other words, the layer of the first filling material 601 may be conformally arranged on the top surface 101T of the substrate 101, on the first groove TR1, and on the second groove TR2.

[0131] Alternatively, in some embodiments, the flowable layer is a flowable silicon and nitrogen containing layer. The flowable silicon and nitrogen containing layer can be formed by mixing a carbon-free silicon containing precursor with a radical nitrogen precursor. The flowable nature of the flowable silicon and nitrogen containing layer can allow the flowable silicon and nitrogen containing layer to flow into a narrow substrate gap or a narrow trench. During the formation of the flowable silicon and nitrogen containing layer, the temperature of the substrate 101 can be less than 120° C., less than 100° C., less than 80° C., or less than 60° C.

[0132] The carbon-free silicon-containing precursor can be, for example, a silicon and nitrogen precursor, a silicon and hydrogen precursor, or a silicon-containing nitrogen and hydrogen precursor. In some embodiments, the carbon-free silicon-containing precursor can also be oxygen-free. The lack of oxygen results in a lower concentration of silanol (Si—OH) groups in the flowable silicon-and-nitrogen-containing layer formed from the carbon-free silicon-containing precursor. Excess silanol moieties in the flowable silicon-and-nitrogen-containing layer may cause increased porosity and shrinkage during subsequent processing to remove hydroxyl (—OH) moieties from the flowable silicon-and-nitrogen-containing layer.

[0133] In some embodiments, the carbon-free silicon-containing precursor may include silylamines, such as H2N(SiH3), HN(SiH3)2, and N(SiH3)3. The flow rate of the silylamines may be greater than or about 200 standard cubic centimeters per minute (sccm), greater than or about 300 sccm, or greater than or about 500 sccm. These silylamines may be mixed with additional gases that may act as carrier gases, reactive gases, or both. Examples of these additional gases may include H2, N2, NH3, He, and Ar.

[0134] In some embodiments, the carbon-free silicon-containing precursor may include silane alone or mixed with other silicon (eg, N(SiH 3 ) 3 ), hydrogen (eg, H 2 ), and / or nitrogen (eg, N 2 , NH 3 ) gases.

[0135] In some embodiments, the carbon-free silicon-containing precursor includes disilane, trisilane, even higher order silanes and chlorinated silanes, alone or in combination with silylamines.

[0136] The radical nitrogen precursor can be generated by delivering ammonia to the plasma region. The radical nitrogen precursor can then be delivered to mix with the carbon-free silicon-containing precursor. The flow rate of ammonia delivered to the plasma region can be greater than or about 300 sccm, greater than or about 500 sccm, or greater than or about 700 sccm. In some embodiments, gases such as nitrogen and hydrogen can be used to adjust the nitrogen:hydrogen atomic flow ratio. In some embodiments, a gas such as helium or argon can be used as a carrier gas to deliver ammonia to the plasma region.

[0137] In some embodiments, the radical-nitrogen precursor is generated without the use of ammonia.A gas including one or more of hydrogen, nitrogen, and hydrazine may be delivered to the plasma region to generate the radical-nitrogen precursor.

[0138] Subsequently, a curing process and an annealing process may be sequentially performed on the flowable silicon-and-nitrogen-containing layer (i.e., the flowable layer) in an oxygen-containing atmosphere to transform the flowable silicon-and-nitrogen-containing layer into a layer of the first filling material 601 formed of silicon oxide. In some embodiments, the substrate temperature of the curing process may be lower than or about 400° C. For example, the substrate temperature of the curing process may be between about 100° C. and about 200° C. In some embodiments, the substrate temperature of the annealing process may be between about 500° C. and about 1100° C. In some embodiments, the oxygen-containing atmosphere may include one or more oxygen-containing gases, such as molecular oxygen, ozone, water vapor, hydrogen peroxide, and nitrogen oxides (e.g., nitric oxide, nitrous oxide, etc.).

[0139] Alternatively, in some embodiments, the flowable layer is formed by reacting a gas phase precursor with a co-reactant. The flowable layer has a flow characteristic that can provide a consistent filling of the substrate gap of substrate 101. Subsequently, a deposition post-processing is carried out, and the flowable layer is physically densified and / or chemically converted to reduce its fluidity. After the deposition post-processing, the flowable layer is transformed into a layer of the first filling material 601. In certain embodiments, the dense flowable layer can be considered to be solidified. In certain embodiments, the physical densification flowable layer can be related to the contraction flowable layer. In certain embodiments, the deposition post-processing can be related to the replacement of the chemical substance in the flowable layer, which can produce a denser, higher volume first filling material 601 layer.

[0140] In some embodiments, the flowable layer may be a flowable silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the flowable layer may be silicon carbide or silicon oxycarbide. In some embodiments, the chamber pressure for forming the flowable layer may be between about 1 Torr and 200 Torr, between 10 Torr and 75 Torr, or about 10 Torr. In some embodiments, the substrate temperature for forming the flowable layer is between about -20°C and about 100°C, between about -20°C and about 30°C, or between about -10°C and about 10°C.

[0141] In some embodiments, the gas-phase precursor may include a silicon-containing precursor or a carbon-containing precursor. The co-reactant may include an oxidant, a catalyst, a surfactant, or an inert carrier gas.

[0142] The silicon-containing precursor may include, but is not limited to, silane, disilane, trisilane, hexasilane, cyclohexasilane, alkoxysilane, aminosilane, alkylsilane, tetraisocyanate silane (TICS), hydrogen silsesquioxane, T8-hydrogenated spherulosic siloxane, or 1,2-dimethoxy-1,1,2,2-tetramethyldisilane.

[0143] The alkoxysilane may include tetraoxymethylcyclotetrasiloxane (TOMCTS), octamethylcyclotetrasiloxane (OMCTS), tetraethoxysilane (TEOS), triethoxysilane (TES), trimethoxysilane (TriMOS), methyltriethoxyorthosilicate (MTEOS), tetramethylorthosilicate (TMOS), methyltrimethoxysilane (MTMOS), dimethyldimethoxysilane (DMDMOS), diethoxysilane. (DES), dimethoxysilane (DMOS), triphenylethoxysilane, 1-(triethoxysilyl)-2-(diethoxymethylsilyl)ethane, tri-tert-butoxysilanol, hexamethoxydisilane (HMODS), hexaethoxydisilane (HEODS) or tert-butoxydisilane. The aminosilane may include bis-tert-butylaminosilane (BTBAS) or tris(dimethylamino)silane.

[0144] The carbon-containing precursor may include, but is not limited to, trimethylsilane (3MS), tetramethylsilane (4MS), diethoxymethylsilane (DEMS), dimethyldimethoxysilane, methyltriethoxysilane (MTES), methyltrimethoxysilane, methyldiethoxysilane, methyldimethoxysilane, trimethoxymethylsilane, dimethoxymethylsilane, or bis(trimethylsilyl)carbodiimide.

[0145] The oxidizing agent may include, but is not limited to, ozone, hydrogen peroxide, oxygen, water, alcohol, nitric oxide, nitrous oxide, nitrous oxide, carbon monoxide, or carbon dioxide. The alcohol may include, for example, methanol, ethanol, or isopropanol.

[0146] Catalyst can include but not limited to proton donor catalyst, halogen-containing compound, inorganic acid, alkali, chlorodiethoxysilane, methanesulfonic acid, trifluoromethanesulfonic acid, chlorodimethoxysilane, pyridine, acetyl chloride, chloroacetic acid, dichloroacetic acid, trichloroacetic acid, oxalic acid, benzoic acid or triethylamine. Proton donor catalyst can include nitric acid, hydrofluoric acid, phosphoric acid, sulfuric acid, hydrochloric acid, bromic acid, carboxylic acid derivatives, ammonia, ammonium hydroxide, hydrazine or hydroxylamine. Halogen-containing compound can include dichlorosilane, trichlorosilane, methylchlorosilane, chlorotriethoxysilane, chlorotrimethoxysilane, chloromethyldiethoxysilane, chloromethyldimethoxysilane, vinyltrichlorosilane, diethoxydichlorosilane or hexachlorodisiloxane. Inorganic acid can include formic acid or acetic acid. Alkali can include phosphine.

[0147] Surfactants may include solvents, alcohols, ethylene glycol, or polyethylene glycol. Surfactants may be used to reduce surface tension and increase wetting of reactants on the substrate surface. Surfactants may also increase the miscibility of gas-phase precursors with other reactants.

[0148] The solvent can be nonpolar or polar and protic or aprotic. The solvent can be matched to the choice of gas phase precursor to improve miscibility in the oxidant. Nonpolar solvents can include alkanes and alkenes; polar aprotic solvents can include acetone and acetates; polar protic solvents can include alcohols and carboxylic acid compounds.

[0149] Solvents include, but are not limited to, methanol, ethanol, isopropanol, acetone, diethyl ether, acetonitrile, dimethylformamide, dimethyl sulfoxide, tetrahydrofuran, dichloromethane, hexane, benzene, toluene, isoheptane, and diethyl ether. In some embodiments, the solvent may be introduced before the other reactants.

[0150] Inert carrier gases may include nitrogen, helium, or argon.

[0151] The post-deposition treatment can crosslink and remove terminal groups in the flowable layer, such as -OH and -H groups, thereby increasing the density and hardness of the flowable layer. The post-deposition treatment can be thermal curing, exposure to downstream or direct plasma, exposure to ultraviolet or microwave radiation, or exposure to another energy source.

[0152] When thermal curing is used as a means of post-deposition treatment, the temperature of the thermal curing can be between about 200°C and 600°C. Post-deposition treatment can be performed in an inert environment, an oxidizing environment, a nitriding environment, or a mixed environment of an oxidizing and nitriding environment. The inert environment can include argon or helium. The oxidizing environment can include oxygen, ozone, water, hydrogen peroxide, nitrous oxide, nitric oxide, nitrogen dioxide, carbon monoxide, carbon dioxide. The nitriding environment can include nitrogen, ammonia, nitrous oxide, nitric oxide, nitrogen dioxide. The pressure of the thermal curing can be between about 0.1 torr and about 10 torr.

[0153] When exposure to a downstream or direct plasma is used as a means of post-deposition treatment, the plasma can be an inert plasma or a reactive plasma. Inert plasmas can be helium plasmas and argon plasmas. Reactive plasmas can be oxidizing plasmas including oxygen and steam, or hydrogen-containing plasmas including hydrogen and a diluent such as an inert gas. In some embodiments, the temperature during plasma exposure can be about 25°C or higher. In some embodiments, the temperature during plasma exposure can be between about -15°C and about 25°C.

[0154] Reference Figure 8 , a width W1 of the first recess RS1 is smaller than a width W2 of the second recess RS2. In some embodiments, a thickness T1 of a layer of the first filling material 601 formed in the first trench TR1 may be greater than a thickness T2 of a layer of the first filling material 601 formed in the first trench TR2.

[0155] Reference Fig. 9 , a layer of a second filling material 603 is conformally formed on the layer of the first filling material 601. Specifically, the layer of the second filling material 603 may completely fill the first recess RS1, and may not completely fill the second recess RS2. Specifically, the layer of the second filling material 603 is conformally formed along the surface of the layer of the first filling material 601 in the second trench TR2 (i.e., the second recess RS2), thereby generating a recess RS3 (or a third recess RS3) facing upward in the second trench TR2.

[0156] In some embodiments, the second filling material 603 is formed of a material having an etching selectivity relative to the first filling material 601. In some embodiments, the second filling material 603 may include silicon nitride or other applicable insulating materials. In some embodiments, the layer of the second filling material 603 serves as a stop layer for a subsequent planarization process or an etching process. In some embodiments, the layer of the second filling material 603 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0157] Reference Fig.10 , a layer of a third filling material 605 is formed on the layer of the second filling material 603. The layer of the third filling material 605 completely fills the third recess RS3. In some embodiments, a pit may be formed above the second trench TR2. In some embodiments, the third filling material 605 may be formed of a material having an etching selectivity relative to the second filling material 603. In some embodiments, the third filling material 605 may include the same material as the first filling material 601. In some embodiments, the third filling material 605 may include silicon oxide or other applicable materials. In some embodiments, the layer of the third filling material 605 may be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes.

[0158] In some embodiments, a high aspect ratio process is performed to deposit a layer of the third filling material 605, ensuring that the third recess RS3 is completely filled and covers the layer of the second filling material 603. The high aspect ratio process may involve two stages. In the first stage, a low deposition rate is used to achieve more uniform trench filling and reduce the possibility of void formation. In the second stage, a fast deposition rate is used to improve overall production efficiency by reducing deposition time. This high aspect ratio process combines slower and higher deposition rate stages, strategically utilizing slower deposition rates when it is beneficial to reduce defects, and using higher deposition rates at shorter deposition times. In addition, in some embodiments, the pressure during the high aspect ratio process can be in a range between about 200 Torr and about 760 Torr, and the temperature can be between about 400°C and about 570°C.

[0159] In some embodiments, a two-stage annealing process may be performed after the high aspect ratio process. During the first stage of the two-stage annealing, a lower temperature environment containing one or more oxygen-containing species (e.g., water, oxygen, nitric oxide, or nitrous oxide) is used. The purpose of the first stage is to rearrange and strengthen the silicon oxide network, thereby preventing the formation of voids and seam openings in the third recess RS3. In addition, the lower temperature in the first stage prevents oxygen from reacting with the trench walls and other parts of the substrate 101, which may result in the formation of an undesirable oxide layer.

[0160] Subsequently, in the second stage of the two-stage annealing, an oxygen-free higher temperature environment is used. The second stage is used to further rearrange the structure of the third filling material 605 and drive out moisture, both of which increase the density of the layer of the third filling material 605. The environment of the second stage can be, for example, substantially pure nitrogen, a mixture of nitrogen and a rare gas (such as helium, neon, argon or xenon), or substantially pure rare gas. It may also contain reducing gases such as hydrogen or ammonia. The second stage is conducive to high temperature densification without causing oxidation of the substrate 101.

[0161] Reference Fig.11 After the two-stage annealing, a planarization process, such as chemical mechanical polishing, is performed until the top surface 603T of the layer of the second filling material 603 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. The layer of the second filling material 603 can serve as a stop layer in the planarization process. At this stage, the top surface 603T of the layer of the second filling material 603 and the top surface 605T of the layer of the third filling material 605 are substantially coplanar.

[0162] Reference Fig.12 , performing an etch-back process. After exposing most of the first filling material 601 layer, removing most of the second filling material 603 above the substrate 101. The etching rate of the third filling material 605 of the etch-back process is substantially the same as the etching rate of the second filling material 603 of the etch-back process. In some embodiments, the etch-back process may be a dry etching process. In some embodiments, a post-etch cleaning process may be performed after the etch-back process. Figure 5 The post-etch cleaning process is performed by a process similar to the process shown in the figure, and will not be repeated here.

[0163] Reference Fig.12 As shown, the remaining first filling material 601 can be regarded as a first outer filling layer 301 and a second outer filling layer 401. The first outer filling layer 301 can be formed in the first region R1 and include a plurality of first recesses 301C and a first flat portion 301F. The first recesses 301C can be formed on the repair layer 201 and in the first trench TR1 respectively. Each first recess 301C includes a U-shaped cross-sectional profile, thereby forming a first recess RS1 facing upward. The end of the first recess 301C protrudes from the top surface 101T of the substrate 101. The first flat portion 301F is formed on the repair layer 201 and is parallel to the top surface 101T of the substrate 101. The first flat portion 301F can connect the ends of the first recess 301C.

[0164] Reference Fig.12, the second outer filling layer 401 is formed in the second region R2 and includes a second recess 401C and a second flat portion 401F. The second recess 401C is formed on the repair layer 201 and in the second groove TR2. The second recess 401C includes a U-shaped cross-sectional profile, thereby producing a second recess RS2 facing upward. The end of the second recess 401C protrudes from the top surface 101T of the substrate 101. The second flat portion 401F is formed on the repair layer 201 and is parallel to the top surface 101T of the substrate 101. The second flat portion 401F connects the ends of the second recess 401C. The first flat portion 301F and the second flat portion 401F can be connected and can be considered as a uniform flat layer formed on the repair layer 201 and parallel to the top surface 101T of the substrate 101.

[0165] Reference Fig.12 , the remaining second filling material 603 can be regarded as the first center layer 303 and the second center layer 403. For the sake of brevity, clarity and convenience of description, only one first center layer 303 is described. The first center layer 303 is formed on the first recess 301C and completely fills the first recess RS1. At this stage, the top surface 303T of the first center layer 303, the top surface 301CT of the first recess 301C, and the top surface 301FT of the first flat portion 301F are substantially coplanar.

[0166] Reference Fig.12 , the second center layer 403 is conformally formed on the second recess 401C and includes a U-shaped cross-sectional profile, thereby generating a third recess RS3 facing upward. The end of the second center layer 403 protrudes from the top surface 101T of the substrate 101. The second inner filling layer 405 is formed on the second center layer 403 and completely fills the third recess RS3. At the current stage, the top surface 405T of the second inner filling layer 405, the top surface 403T of the second center layer 403, the top surface 401CT of the second recess 401C, and the top surface 401FT of the second flat portion 401F are substantially coplanar. In some embodiments, the top surface 401FT of the second flat portion 401F and the top surface 301FT of the first flat portion 301F are substantially coplanar.

[0167] Reference Fig.12In some embodiments, the thickness T1 of the first concave portion 301C and the thickness T3 of the first flat portion 301F are substantially the same. In some embodiments, the thickness T1 of the first concave portion 301C and the thickness T3 of the first flat portion 301F may be different. In some embodiments, the thickness T2 of the second concave portion 401C and the thickness T4 of the second flat portion 401F are substantially the same. In some embodiments, the thickness T2 of the second concave portion 401C and the thickness T4 of the second flat portion 401F may be different. In some embodiments, the thickness T2 of the first flat portion 301F and the thickness T4 of the second flat portion 401F are substantially the same. In some embodiments, the thickness T1 of the first concave portion 301C may be greater than the thickness T2 of the second concave portion 401C.

[0168] Reference Figure 1 and Fig.13 In step S15 , a plurality of first protective layers 501 are formed on the first central layer 303 , and a second protective layer 503 is formed on the second central layer 403 .

[0169] Reference Fig.13 , a surface oxidation process is performed to oxidize the top of the first center layer 303 and the top of the second center layer 403 formed of silicon nitride in this embodiment. The oxidized end of the first center layer 303 and the oxidized end of the second center layer 403 refer to the first protective layer 501 and the second protective layer 503 respectively. The first protective layer 501 is respectively disposed on the first center layer 303. The second protective layer 503 is respectively disposed on the two ends 403E of the second center layer 403.

[0170] In some embodiments, the surface oxidation process can be a low temperature plasma oxidation process. The low temperature plasma oxidation process for converting silicon nitride into silicon oxide involves multiple steps and specific process conditions. First, Fig.12 The intermediate semiconductor element shown is loaded into a plasma enhanced chemical vapor deposition (PECVD) chamber maintained at a low temperature between about 200° C. and about 400° C. Then, a gas mixture of oxygen and an inert gas (e.g., nitrogen or argon) is introduced into the chamber at a controlled flow rate. The flow rate of oxygen can be set in the range of about 10 sccm to about 100 sccm, while the inert gas flow rate can vary between about 50 sccm and about 500 sccm. Radio frequency (RF) power is applied to generate a low temperature plasma with a power level of about 50 watts and about 300 watts. The RF power excites the gas mixture to generate reactive species including oxygen radicals, which play a vital role in the low temperature plasma oxidation process.

[0171] In the low temperature plasma oxidation process, oxygen radicals react with the silicon nitride surface, converting it to silicon oxide without the need for high temperatures. The low temperature plasma oxidation process is self-limiting, meaning that the reaction rate decreases as the silicon nitride layer is converted to silicon oxide. The oxidation time can be carefully controlled to achieve the desired thickness of the silicon oxide layer (i.e., the first protective layer 501 and the second protective layer 503), and the oxidation time is typically in the range of several minutes to tens of minutes, depending on the desired film thickness and properties. After the oxidation step is completed, the plasma is deactivated and a purge gas (usually nitrogen) is introduced into the chamber to remove any residual active species and byproducts.

[0172] For the sake of brevity, clarity and convenience of description, only one first protective layer 501 is described.

[0173] Reference Fig.13 , the bottom surface 501B of the first protective layer 501 is located at a vertical level VL1 higher than the top surface 101T of the substrate 101 or the top surface 201T of the repair layer 201. In some embodiments, the thickness T5 of the first protective layer 501 may be less than the thickness T3 of the first flat portion 301F. In some embodiments, the ratio of the thickness T5 of the first protective layer 501 to the thickness T3 of the first flat portion 301F may be between about 0.1 and about 0.8, or between about 0.3 and about 0.6. In some embodiments, the width W1 of the first central layer 303 is substantially the same as the width W3 of the first protective layer 501. In some embodiments, the ratio of the width W3 of the first protective layer 501 to the width W5 of the first recess 301C may be between about 0.05 and about 0.35, or between about 0.10 and about 0.30.

[0174] Reference Fig.13 , the bottom surface 503B of the second protective layer 503 is located at a vertical level VL2 higher than the top surface 101T of the substrate 101 or the top surface 201T of the repair layer 201. In some embodiments, the thickness T6 of the second protective layer 503 may be less than the thickness T4 of the second flat portion 401F. In some embodiments, the ratio of the thickness T6 of the second protective layer 503 to the thickness T4 of the second flat portion 401F may be between about 0.1 and about 0.8, or between about 0.3 and about 0.6. In some embodiments, the width W4 of the second protective layer 503 is substantially the same as the width W6 of the second center layer 403. In some embodiments, the ratio of the width W7 of the second inner filling layer 405 to the width W8 of the second recess 401C may be between about 0.60 and about 0.95, or between about 0.70 and about 0.90.

[0175] Reference Fig.13In some embodiments, the bottom surface 501B of the first protection layer 501 is substantially coplanar with the bottom surface 503B of the second protection layer 503. In some embodiments, the bottom surface 501B of the first protection layer 501 and the bottom surface 503B of the second protection layer 503 are located at different vertical levels.

[0176] Reference Figures 14 to 17 In step S17 , an implantation process IMP is performed on the substrate 101 , and a word line hard mask layer 203 is formed on the substrate 101 .

[0177] Reference Fig.14 , a sacrificial mask layer 801 may be formed over the substrate 101 to cover the first outer filling layer 301, the first protective layer 501, the second outer filling layer 401, and the second protective layer 503. In some embodiments, the sacrificial mask layer 801 may be formed of a material having a high etching selectivity to the first outer filling layer 301 and the second outer filling layer 401. In some embodiments, the sacrificial mask layer 801 may be formed of a material different from the first outer filling layer 301 and the second outer filling layer 401. In some embodiments, the sacrificial mask layer 801 may be formed of silicon nitride. In some embodiments, the sacrificial mask layer 801 may be formed of a material different from the first outer filling layer 301 and the second outer filling layer 401. Fig. 9 The second filling material 603 is formed by a similar process to the sacrificial mask layer 801 , which will not be described again here.

[0178] The sacrificial mask layer 801 plays a vital role in protecting the first outer fill layer 301 and the second outer fill layer 401 during the subsequent implantation process. As a protective cover, the sacrificial mask layer 801 prevents potential damage to the top surface of the above layers, which may otherwise occur during the implantation process or the post-implantation cleaning process. The presence of the sacrificial mask layer 801 is crucial because it ensures the integrity of the contact area of ​​the semiconductor component 1. Without this protective layer, the active area of ​​the semiconductor component 1 may experience a reduction in contact area, resulting in potential reliability issues and performance degradation. Therefore, the sacrificial mask layer 801 contributes greatly to the overall reliability and functionality of the semiconductor component 1.

[0179] Reference Fig.15 , an implantation process IMP is performed using a p-type dopant or an n-type dopant to form an active region of the semiconductor element 1 in the substrate 101 (not shown for clarity). The p-type dopant can be added to the intrinsic semiconductor to create a defect in valence electrons. In a silicon-containing substrate, the p-type dopant includes, but is not limited to, boron, aluminum, gallium, and indium. The n-type dopant can be added to the intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, the n-type dopant includes, but is not limited to, antimony, arsenic, and phosphorus.

[0180] After the implantation process IMP, a post-implantation cleaning process is performed. The post-implantation cleaning process is a critical step to ensure the integrity and reliability of the semiconductor element 1. After the implantation process IMP, the intermediate semiconductor element is first cleaned with deionized water to remove loose particles and debris. Subsequently, a pre-cleaning step is performed using a dilute acid solution (usually a mixture of sulfuric acid and hydrogen peroxide in a ratio of 3:1) to eliminate metal contaminants and / or surface oxide layers. The intermediate semiconductor element can then undergo multiple washes with deionized water to thoroughly remove any residual cleaning solution and contaminants. Next is the RCA cleaning step, using an RCA-2 solution composed of deionized water, hydrogen peroxide and ammonium hydroxide in a ratio of 5:1:1, heated to about 70°C to about 80°C. This step effectively removes metal ion contaminants, organic residues, and ensures a cleaner surface. The intermediate semiconductor element can then be additionally cleaned to eliminate any residual cleaning chemicals or particles. Finally, the intermediate semiconductor element can be dried using a spin dryer or a nitrogen gas stream to prevent watermarks or contamination.

[0181] Reference Fig.16 , selectively removing the sacrificial mask layer 801. This removal is achieved by an etching process having a high etching selectivity to the sacrificial mask layer 801. During the etching process, the etching rate of the sacrificial mask layer 801, which may be formed of silicon nitride in some embodiments, is greater than the etching rate of the first outer filling layer 301, the second outer filling layer 401, the first protective layer 501, and the second protective layer 503. In some embodiments, the second protective layer 503 may be formed of silicon oxide. For example, the etching process selectively removes silicon nitride while leaving the silicon oxide intact.

[0182] The first protection layer 501 and the second protection layer 503 are used to prevent the first central layer 303 and the second central layer 403 below from being removed during the etching process. Therefore, after removing the sacrificial mask layer 801, the top surface, i.e., the top surface 301FT of the first flat portion 301F, the top surface 301CT of the first concave portion 301C, the top surface 501T of the first protection layer 501, the top surface 401FT of the second flat portion 401F, the top surface 401CT of the second concave portion 401C, the top surface 405T of the second inner filling layer 405, and the top surface 503T of the second protection layer 503 are substantially coplanar. That is, the surface of the semiconductor element 1 can be intact and substantially flat for subsequent semiconductor processes. Therefore, the reliability of the semiconductor device 1 is improved.

[0183] In some comparative embodiments, if the first protective layer 501 and the second protective layer 503 do not exist, the first central layer 303 and the second central layer 403 formed of silicon nitride may also be removed during the removal of the sacrificial mask layer 801, thereby generating a small depression. Therefore, the reliability of the semiconductor element 1 may be affected.

[0184] Reference Fig.17 , a word line hard mask layer 203 is formed on the first outer filling layer 301, the second outer filling layer 401, the first protection layer 501 and the second protection layer 503. In some embodiments, the word line hard mask layer 203 can be formed of the same material as the first central layer 303 or the second central layer 403. In some embodiments, the word line hard mask layer 203 can be formed of, for example, silicon nitride. In some embodiments, the word line hard mask layer 203 can be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition or other applicable deposition processes.

[0185] One aspect of the present disclosure provides a semiconductor element, comprising a substrate; a first outer filling layer, comprising a first concave portion, which is disposed in the substrate and comprises a U-shaped cross-sectional profile; and a first flat portion, which is disposed on the substrate and connected to the first concave portion; a first central layer, which is disposed on the first concave portion of the first outer filling layer; and a first protective layer, which is disposed on the first central layer. A top surface of the first concave portion is substantially coplanar with a top surface of the first protective layer.

[0186] Another aspect of the present disclosure provides a semiconductor element, which includes a substrate, which includes a first region and a second region; a second outer filling layer, which includes a second concave portion, which is disposed in the second region of the substrate and has a U-shaped cross-sectional profile; and a second flat portion, which is disposed on the substrate and connected to the second concave portion; a second center layer, which is conformally disposed on the second concave portion and includes a U-shaped cross-sectional profile; an inner filling layer, which is disposed on the second center layer; and a plurality of second protection layers, which are disposed at both ends of the second center layer and between the second concave portion and the inner filling layer. A top surface of the second concave portion, a top surface of the inner filling layer, and a top surface of the second protection layers are substantially coplanar.

[0187] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a first groove in the substrate; conformally forming a layer of a first filling material on the substrate and in the first groove, thereby forming a first recess in the first groove; forming a layer of a second filling material on the layer of the first filling material and completely filling the first recess; performing a planarization process until the layer of the first filling material is exposed to transform the layer of the first filling material into a first outer filling layer and transform the layer of the second filling material into a first central layer; and performing a surface oxidation process to form a first protective layer on the first central layer.

[0188] Due to the design of the semiconductor device disclosed in the present invention, the surface (i.e., the top surfaces of the first outer filling layer 301, the second outer filling layer 401, the first protective layer 501, and the second protective layer 503, respectively) is intact and substantially flat for subsequent semiconductor processes. Therefore, the reliability of the semiconductor device 1 is improved.

[0189] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0190] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; A first outer filling layer, comprising: a first recessed portion disposed in the base and comprising a U-shaped cross-sectional profile; and a first flat portion, which is disposed on the base and connected to the first concave portion; a first center layer disposed on the first concave portion of the first outer filling layer; and a first protective layer disposed on the first central layer; A top surface of the first concave portion is substantially coplanar with a top surface of the first protection layer. 2 . The semiconductor device as claimed in claim 1 , wherein the first core layer and the first protection layer comprise different materials. 3 . The semiconductor device as claimed in claim 2 , further comprising a repair layer conformally disposed between the first outer filling layer and the substrate. 4 . The semiconductor device as claimed in claim 3 , wherein a bottom surface of the first protection layer is located at a vertical level higher than a top surface of the substrate. 5 . The semiconductor device as claimed in claim 3 , wherein a ratio of a thickness of the first protection layer to a thickness of the first flat portion of the first outer-fill layer is between about 0.1 and about 0.

8. 6 . The semiconductor device as claimed in claim 3 , wherein a width of the first protection layer is substantially the same as a width of the first central layer. 7 . The semiconductor device as claimed in claim 3 , wherein a ratio of a width of the first protection layer to a width of the first recess of the first outer-filling layer is between about 0.05 and about 0.

35. 8 . The semiconductor device as claimed in claim 3 , wherein a bottom surface of the first protection layer is located at a vertical level higher than a top surface of the repair layer. 9 . The semiconductor device as claimed in claim 3 , wherein a thickness of the first recessed portion is substantially the same as a thickness of the first flat portion.

10. A semiconductor element, comprising: a substrate comprising a first region and a second region; a second outer filling layer, comprising: a second recessed portion disposed in the second region of the base and having a U-shaped cross-sectional profile; and a second flat portion, disposed on the base and connected to the second concave portion; a second center layer, which is conformally disposed on the second recess and includes a U-shaped cross-sectional profile; an inner filling layer, which is disposed on the second center layer; and A plurality of second protective layers, which are disposed at both ends of the second central layer and between the second concave portion and the inner filling layer; A top surface of the second concave portion, a top surface of the inner filling layer, and a top surface of the plurality of second protection layers are substantially coplanar.

11. The semiconductor device as claimed in claim 10, further comprising a first outer filling layer, a plurality of first central layers and a plurality of first protective layers; The first outer filling layer comprises: A plurality of first recesses, which are disposed in the first region of the base and are spaced apart from each other and each of which comprises a U-shaped cross-sectional profile; and a first flat portion, disposed on the base and connected to the plurality of first recesses; wherein the plurality of first central layers are respectively disposed on the plurality of first recesses; wherein the plurality of first protective layers are respectively and correspondingly arranged on the plurality of first central layers; A top surface of the plurality of first recesses is substantially coplanar with a top surface of the plurality of first protection layers. 12 . The semiconductor device as claimed in claim 11 , wherein top surfaces of the first recesses, top surfaces of the first protection layers, top surfaces of the second recesses, top surfaces of the underfill layer, and top surfaces of the second protection layers are substantially coplanar. 13 . The semiconductor device as claimed in claim 12 , further comprising a repair layer conformally disposed between the substrate and the first outer filling layer, and between the substrate and the second outer filling layer. 14 . The semiconductor device as claimed in claim 13 , further comprising a word line hard mask layer disposed on the first outer filling layer, the second outer filling layer, the plurality of first protection layers, and the plurality of second protection layers. 15 . The semiconductor element of claim 14 , wherein the plurality of first core layers and the plurality of first protection layers comprise different materials. 16 . The semiconductor device as claimed in claim 15 , wherein the plurality of second protection layers and the second core layer comprise different materials. 17 . The semiconductor device as claimed in claim 16 , wherein a bottom surface of the plurality of first protection layers and a bottom surface of the plurality of second protection layers are located at the same vertical level. 18 . The semiconductor device according to claim 17 , wherein the thickness of the plurality of first recesses is different from the thickness of the second recess. 19 . The semiconductor device as claimed in claim 17 , wherein a bottom surface of the plurality of second protection layers is located at a vertical level higher than a top surface of the substrate. 20 . The semiconductor device as claimed in claim 17 , wherein a ratio of a thickness of the second protection layers to a thickness of the second planar portion is between about 0.1 and about 0.8.

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