IC package with side surface immersed with tin

Abstract

The invention relates to an IC package with a side surface immersed with tin. A method for forming an integrated circuit (IC) package includes mounting a tape on a molding compound (108) of a flat leadless IC package strip (100). The method also includes sawing the molding compound (108) of the flat leadless IC package strip (100) to form a singulated IC package (303) mounted on the tape (202). The method further includes immersing the singulated IC package (304) in a dip tin bath (402) to form a dip tin plating (502) on a side of a lead of the singulated IC package (304).

Description

Technical Field

[0001] The present description relates to forming an integrated circuit (IC) package with immersion tin on the sides of the leads. Background Art

[0002] Different integrated circuit (IC) package types available on the market contain conductive leads on the underside of the IC package for soldering joints. Because the leads are not easily visible or exposed, it is difficult to determine whether the IC package has been successfully soldered to the printed circuit board (PCB). Wettable side designs expose the leads at the sidewalls of the IC package, which enables optical inspection of soldering. However, the exposed leads are susceptible to oxidation and corrosion, making it difficult to wet the sidewall solder and reducing the shelf life of the IC package. Summary of the invention

[0003] A first example relates to a method for forming an integrated circuit (IC) package. The method includes mounting a tape on a molding compound of a strip of flat leadless IC packages. The method also includes sawing the molding compound of the strip of flat leadless IC packages to form singulated IC packages mounted on the tape. The method further includes immersing the singulated IC packages in an immersion tin bath to form an immersion tin plating on the sides of leads of the singulated IC packages.

[0004] A second example relates to an IC package. The IC package includes a die mounted on a flat leadless interconnect and a molding compound encapsulating the die on the top side of the flat leadless interconnect. The sides of the leads of the flat leadless interconnect have an immersion tin plating greater than 2 microns thick. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a strip of flat no-lead integrated circuit (IC) packages is shown.

[0006] Figure 2 An example of a strip of flat no-lead IC packages mounted on tape is shown.

[0007] Figure 3 An example of a singulated IC package mounted on tape is shown.

[0008] Figure 4 An example of a tin immersion bath for singulated IC packages mounted on tape is shown.

[0009] Figure 5 An example of a singulated IC package with immersion tin plating is shown.

[0010] Figure 6 An example process flow for utilizing an immersion tin bath is shown.

[0011] Figure 7 An example of wire bonding between the die and the leads is shown.

[0012] Figure 8 A flow chart illustrating an example method for forming an IC package is shown.

[0013] Fig. 9 A flow chart is shown for an example method utilizing an immersion tin bath. DETAILED DESCRIPTION

[0014] This specification relates to forming integrated circuit (IC) packages. Many IC packages include an interconnect (alternatively referred to as a lead frame) on which one or more dies containing semiconductor devices are mounted and electrically attached. The interconnect and die are encapsulated in a molding compound that forms an enclosure around the interconnect and die. The interconnect includes a plurality of electrical contacts or leads that are exposed to the external environment to enable the device within the enclosure to be electrically coupled to one or more other electrical components outside the enclosure.

[0015] Interconnects with wettable sides for IC packaging (e.g., quad flat no-leads (QFN) and double flat no-leads (DFN)) do not have leads protruding from the housing. Alternatively, the wettable sides refer to non-protruding leads or contact pads of the interconnect. The wettable sides are manufactured in a manner that promotes solder wetting to the leads when mounted to the PCB. The wettable sides enable the formation of solder fillets that can be visually detected (e.g., via automatic optical inspection (AOI)) to verify that an acceptable solder joint is formed between the leads and the PCB. Wetting is achieved by coating or plating the conductive material (e.g., copper) of the interconnect with a solderable metal different from the conductive material, and the wetting provides increased wettability (e.g., exhibiting increased solderability) for the solder. Example metals with high solderability include nickel, palladium, tin, and gold.

[0016] In some examples, flat no-lead IC packages are manufactured in strip form. During the singulation process, individual IC packages are cut from the strip by cutting through the interconnects to expose the internal copper material of the interconnects at the sidewalls of the individual IC packages. At such locations, the exposed copper surfaces of the interconnects are wettable sides that can be visually detected but are subject to corrosion.

[0017] In the apparatus and method described herein, the wettable side is plated with an immersion tin plating that mitigates corrosion and protects the leads of the interconnect. The immersion tin plating is applied in an immersion tin bath that produces an immersion tin plating having a thickness greater than 2 microns on the wettable side. The thickness of the immersion tin plating increases the shelf life and reliability of the flat leadless IC package.

[0018] Figures 1 to 5Stages of a method for forming an IC package including immersion tinning on the sides of the leads are shown. For simplicity purposes, Figures 1 to 5 Like reference numerals are used to refer to like structures. Figure 1 The first stage of a method of forming an IC package is shown. Figure 1 , an example strip 100 of flat no-lead IC packages includes a first flat no-lead IC package 102, a second flat no-lead IC package 104, and a third flat no-lead IC package 106. The unsingulated flat no-lead IC packages 102, 104, 106 each include interconnects electrically connected to a die encapsulated in a mold compound 108. The mold compound 108 encapsulates the die on the top side of the flat no-lead interconnects.

[0019] Components described with respect to one unsingulated flat no-lead IC package (e.g., first unsingulated flat no-lead IC package 102) are present in other unsingulated flat no-lead IC packages (e.g., second unsingulated flat no-lead IC package 104 and third unsingulated flat no-lead IC package 106) of strip 100 and operate in a similar manner. For clarity, reference numbers identify components with respect to one unsingulated flat no-lead IC package. Strip 100 is an array of unsingulated flat no-lead IC packages extending in a longitudinal direction and coupled to each other by mold compound 108. Although a single row of flat no-lead IC packages extending in the longitudinal direction is described for clarity, in other examples, strip 100 includes multiple rows of flat no-lead IC packages.

[0020] The flat no-lead IC packages 102, 104, 106 are formed with interconnects of conductive material and are associated with corresponding leads 110 formed of conductive material. For example, the leads 110 of the flat no-lead interconnects are formed of copper. The first side 112 of the leads 110 is substantially flush with the mold compound 108 at the first surface 114 of the strip 100. The first surface 114 of the strip 100 refers to the surface that faces the PCB when the corresponding no-lead IC package of the strip 100 is mounted (e.g., soldered) to the PCB. In other words, the first side of the leads 110 does not extend beyond the first surface 114 of the strip 100 in a lateral direction that is substantially orthogonal to the longitudinal direction.

[0021] The first side 112 of the lead 110 is coated with a solderable metal layer 116 that extends beyond the first surface 114 of the strip 100 in the lateral direction. The solderable metal layer 116 provides a protective coating that prevents oxidation from occurring at the first side 112 of the lead 110. The solderable metal layer 116 is formed of a solderable metal material. Examples of solderable metal materials include various forms of nickel, palladium, tin, gold, etc. In the illustrated example, the lead 110 is formed of a conductive material, here copper (Cu), and the solderable metal layer 116 is formed of a solderable material, here matte tin (Sn). The solderable metal layer 116 is formed by applying the solderable metal material to the first side 112 of the lead 110 in a deposition process, such as electroplating using an electric current. The solderable metal layer 116 does not extend over the mold compound 108 in the longitudinal direction.

[0022] Figure 2 The second stage of the method of forming an IC package is shown. Figure 2 In the above text about Figure 1 The depicted strip 100 of flat no-lead IC packages 102, 104, 106 is mounted on a tape 202. The tape 202, such as an ultraviolet (UV) tape, is applied to a second surface 204 of the strip 100 opposite the first surface 114 of the strip 100. In some examples, the strip 100 and the tape 202 are positioned on a carrier, frame, or other suitable surface. The tape 202 supports the strip 100 during the singulation process. As an example, the tape 202 includes cut marks that indicate where the strip 100 will be cut during the singulation process.

[0023] Figure 3 The third stage of the method of forming an IC package is shown. Figure 3 , an example of a singulated IC package including a first singulated flat leadless IC package 302, a second singulated flat leadless IC package 304, and a third singulated flat leadless IC package 306 is shown. The singulated flat leadless IC packages 302, 304, 306 mounted on the tape 202 correspond to Figure 1 The non-singulated flat no-lead IC packages 102 , 104 , 106 are shown.

[0024] The singulation process utilizes a cutting tool 308. For example, the cutting tool 308 is a saw including a saw blade 310 that is configured to scribe, saw, or cut through the height of the strip 100 in a lateral direction. The saw blade 310 travels along a path from the first surface 114 to the second surface 204 through the strip 100 to the tape 202 without severing the tape 202. Because the singulation process does not sever the tape 202, the first singulated flat no-lead IC package 302, the second singulated flat no-lead IC package 304, and the third singulated flat no-lead IC package 306 remain supported by the strip 100 due to adhesion to the tape 202. In other examples, the cutting tool 308 is laser-based or plasma-based.

[0025] The first singulated flat no-lead IC package 302, the second singulated flat no-lead IC package 304, and the third singulated flat no-lead IC package 306 are separated from each other by grooves 312. The grooves 312 are gaps extending toward the second surface 204. By means of singulation, the grooves 312 expose the copper leads 110 at the sidewall surfaces 314 that form wettable sides. Therefore, the bottom and sides of the leads 110 are exposed.

[0026] The depth of the groove 312 is defined in the lateral direction and varies depending on whether the solderable metal layer 116 is present on the first surface 114. For example, where the solderable metal layer 116 is present, the depth of the groove 312 extends from the third surface 318 to the second surface 204 of the strip 100. Where the solderable metal layer 116 is not present, the depth of the groove 312 extends from the first surface 114 to the second surface 204. Thus, the depth of the groove 312 varies.

[0027] In some examples, the width of the groove 312 defined in the longitudinal direction is based on a predetermined spacing distance between adjacent individualized flat leadless IC packages. For example, the predetermined distance is set to be greater than ten microns. In another example, the width of the groove 312 is based on the profile of the cutting tool 308 and / or the saw blade 310. In some examples, the width of the groove 312 is variable, having a first width at a first depth and a second width at a second depth. The first width and the second width meet the predetermined distance. Continuing with the above example, the first width may be greater than or less than the second width, but both the first width and the second width are greater than ten microns.

[0028] The groove 312 defines a sidewall surface 314 of the singulated flat leadless IC package 302, 304, 306. The sidewall surface 314 is approximately orthogonal to the first surface 114 and the second surface 204. The singulated flat leadless IC package 302, 304, 306 has corresponding leads 110 and a solderable metal layer 116. Due to the singulation process, the second side 316 of the lead 110 is exposed at the sidewall surface 314 of the singulated flat leadless IC package 302, 304, 306, thereby forming a wettable side. In one example, the second side 316 of the lead 110 is approximately flush with the sidewall surface 314. In the illustrated example, the exposed second side 316 extends approximately orthogonally from the first side 112 of the lead 110. The second side 316 of the lead 110 extends from the first side 112 of the lead 110 to the third side 320. The third side 320 is opposite the first side 112 and is proximate to the second surface 204. As an example, the solderable metal layer 116 is approximately twelve microns thick and extends from the first side 112 to the third surface 318 in a lateral direction.

[0029] Figure 4 The fourth stage of the method of forming an IC package is shown. Figure 4 , the singulated IC packages 302, 304, 306 are immersed in a tin bath 402. The tin bath 402 coats the second side 316 of the lead 110 with an electroplating material using a chemical reaction between the interconnect material and the tin bath 402. In one example, the tin bath 402 is the same as the solderable metal material of the solderable metal layer 116. In another example, the tin bath 402 is different from the solderable metal material of the solderable metal layer 116. The tin bath 402 contains various forms of tin. As an example, the tin bath 402 includes a solution of tin, a tin salt, and an activator. Although the tin bath 402 is described using tin, other suitable materials with similar properties can be used. Because the matte tin plating of solderable metal layer 116 is applied to the bottom of leads 110 of strip 100 of flat no-lead IC packages prior to immersion in immersion tin bath 402 , immersion tin bath 402 is non-reactive to the solderable metal material of solderable metal layer 116 .

[0030] In some examples, the immersion tin bath 402 includes an impact generator and / or a vibrator. The impact generator is configured to apply impact to the immersion tin bath 402 to release bubbles in the immersion material. The vibrator is configured to apply vibration to the immersion tin bath 402 and / or the strip 100 to release byproducts of the chemical reaction.

[0031] Figure 5 The fifth stage of the method of forming an IC package is shown. Figure 5, the singulated IC packages 302, 304, 306 have an immersion tin plating 502 from the immersion tin bath 402. The immersion tin plating 502 coats the second side 316 of the lead 110. The immersion tin plating 502 extends in a lateral direction along the sidewall surface 314 from the third side 320 of the lead 110 to the first side 112 of the lead 110. In some examples, the immersion tin plating 502 further extends in a lateral direction from the third side 320 of the lead 110 beyond the first side 112 of the lead 110 so that the immersion tin plating 502 coats a portion of the sidewall surface 314 formed by the solderable metal layer 116. For example, the solderable metal layer 116 extends from the first surface 114 to the third surface 318 of the strip 100 away from the second surface 204. The immersion tin plating 502 has a height extending along the sidewall surface 314 from the third side 320 of the lead 110 to the third surface 318 of the strip 100. In one example, the immersion tin plating 502 has a height of at least 50 microns in the lateral direction adjacent to the sidewall surface 314. As another example, the immersion tin plating 502 has a height of at least 100 microns.

[0032] Figure 6 Show the above about Figure 4 An example process flow 600 of a bath process is described. At 602, a cleaning process is performed. In the cleaning process, a cleaning agent is applied to the strip 100 to remove contaminants that have been encountered during the manufacturing and / or singulation process from the strip 100. In one example, the cleaning agent is STANNA-Q ETCH. As an example, the cleaning process is performed at 20 to 40 degrees Celsius for thirty seconds to two minutes.

[0033] At 604, a first rinse cycle is performed to remove the cleaning agent from the strip 100. The first rinse cycle includes multiple rinse operations. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation. In one example, the rinse operation is performed at approximately 20 degrees Celsius for one to ten minutes.

[0034] At 606, an etching process is performed to remove oxidation or defects by etching the exposed conductive material (here, the copper interconnect, particularly the second side of the lead 110). For example, the etching process includes applying an etchant to the second side 316 of the lead 110. The etchant removes burrs in the second side 316 of the lead 110 caused by the singulation process or oxidation caused by exposure of the conductive material at the second side 316 to the environment. The etchant is, for example, STANNA-QPROTECT. In one example, the etching process removes approximately 6 microns of the second side 316 of the lead 110. As an example, the etching process is performed at 15 to 35 degrees Celsius for one to eleven minutes.

[0035] At 608, a second rinse cycle is performed to remove the etchant. In some examples, the rinse cycles are standardized. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation that are performed at approximately 20 degrees Celsius for one to ten minutes during a second rinse cycle similar to the first rinse cycle.

[0036] At 610, in an activation process, the strip 100 is dipped into an activation chemistry to prepare the second side 316 of the leads 110 for a tin dip bath. The activation chemistry is, for example, STANNA-Q DIP.

[0037] At 612, immersing the strip 100 in a tin bath 402 is performed. In particular, the second side 316 of the lead 110 is immersed in the tin bath. For example, at a first time in the tin bath 402, the second side 316 of the lead 110 contacts the tin bath at a depth corresponding to the first side 112 of the lead 110. At a second time after the first time in the tin bath 402, the second side 316 of the lead 110 contacts the tin bath at a depth corresponding to the third side 320 of the lead 110. The tin bath is, for example, STANNA-Q2. As an example, the immersion of the strip 100 is performed at a temperature of 50 to 90 degrees Celsius for 150 minutes to 4 hours.

[0038] In one example, the immersion tin bath 402 includes impacting the immersion tin bath in response to immersing the strip 100 in the immersion tin bath. Additionally or alternatively, the immersion tin bath 402 includes vibrating the immersion tin bath when the strip 100 is immersed.

[0039] At 614, a third rinse cycle is performed. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation, which is performed at approximately 20 degrees Celsius for one to ten minutes during the third rinse cycle. The rinse cycles are performed before and after the immersion tin bath.

[0040] At 616, the strip 100 is dipped in the first dip chemistry to prepare the strip 100 for the second dip chemistry in a first post dip process. The first dip chemistry is, for example, IONIX SF 8. As an example, the first post dip process is performed at 40 to 60 degrees Celsius for 30 seconds to 2 minutes.

[0041] A fourth rinse cycle is performed at 618. For example, strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation, which are performed at approximately 20 degrees Celsius for one to ten minutes during the fourth rinse cycle.

[0042] At 620, the strip 100 is dipped in a second dip chemistry to prepare the strip 100 for a third dip chemistry in a second post dip process. The second dip chemistry is, for example, PROTECTOSTAN PLUS 2. As an example, the second post dip process is performed at approximately 20 degrees Celsius for 15 seconds to 1 minute.

[0043] At 622, a fifth rinse cycle is performed. For example, strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation, which are performed at approximately 20 degrees Celsius for one to ten minutes during the fifth rinse cycle.

[0044] At 624, the strip 100 is dipped in a third dip chemistry that forms an anti-tarnish layer on the immersion tin plating 502 in a third post-dip process. In one example, the first dip chemistry is the same as the third dip chemistry. The third dip chemistry is, for example, IONIX SF 8. The anti-tarnish layer protects the immersion tin plating 502. As an example, the third post-dip process is performed at 20 to 60 degrees Celsius for 15 seconds to 1 minute.

[0045] At 626, a sixth rinse cycle is performed. For example, strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation, which are performed at approximately 20 degrees Celsius for one to ten minutes during the sixth rinse cycle.

[0046] At 628, a thermal rinse is performed to rinse the strip 100. For example, the thermal rinse is performed at approximately 60 degrees Celsius for one to ten minutes. At 630, air is applied to the strip 100, and at 632, a drying process is performed.

[0047] Figure 7 An example of an IC package 700 is shown having wirebond connections 702 of a die 704 mounted on a die pad 706 encapsulated in a mold compound 708. The mold compound 708 encapsulates the die 704 on the top side of the flat leadless interconnect. In some examples, the IC package 700 is comprised of Figures 1 to 5 The die pad 706 separates the lead 710 from the wire bond connection 702 , thereby forming an electrical connection between the die 704 and the lead 710 .

[0048] Solderable metal layer 712 is applied to the first side of lead 710. Solderable metal layer 712 can be used to implement Figure 11. The solderable metal layer 116 is applied to the die pad 706. In addition, the solderable metal layer 712 is applied to the die pad 706. In one example, the solderable metal layer 712 is a matte tin plating. Thus, the bottom side of the lead 710 of the IC package 700 has a matte tin plating. The immersion tin plating 714 is applied to a second side of the lead 710, the second side being substantially orthogonal to the first side of the lead 710. The immersion tin plating 714 may be used to implement Figure 5 As an example, the side of the lead has an immersion tin plating greater than 2 microns thick.

[0049] Figure 8 A method for forming an IC package (e.g., Figure 7 700) is a flow chart of an example method 800 of an IC package 700. At 802, a die is mounted on a strip (e.g., Figure 1 In some examples, a single die (e.g., Figure 7 The die 704 of the flat leadless IC package is mounted on the interconnects of the interconnect strip. The first side of the leads formed by the interconnects is exposed at the first surface of the flat leadless IC package.

[0050] At 804, a first side of the lead is coated with a solderable metal material, such as matte tin, to form a solderable material layer (eg, Figure 1 The solderable metal layer 116, Figure 7 As an example, the solderable metal material is applied using an electroplating process that utilizes an electric current to deposit the solderable metal material on the first side of the leads of the first flat no-lead IC package.

[0051] At 806, an annealing process is performed to heat the solderable material layer of the strip to approximately 150 degrees Celsius for approximately one hour. The annealing process reduces fuzzing by relieving residual stress of the solderable material layer.

[0052] At 808, the strip 100 is applied to the tape. At 810, the flat no-lead IC package is attached to the strip (e.g., Figure 5 The singulation process is performed by separating the lead strips 100 from the lead strips 100. The singulation process cuts the molding compound and the interconnects associated with the leads. Due to the singulation process, the second side of the lead is exposed to form a wettable side of the singulated flat leadless IC package. The second side of the lead is substantially orthogonal to the first side of the lead. Because the interconnects are encapsulated by the molding compound when the layer of solderable material is applied to the first side of the lead, the exposed second side of the lead is not coated, and the conductive material of the interconnects is exposed at the sidewall surface of the singulated flat leadless IC package.

[0053] At 812, the immersion material is coated with Figure 4The immersion tin bath 402 is depicted coating the second side of the lead. The immersion tin bath utilizes a chemical reaction between the conductive material of the interconnect and the immersion tin bath to coat the second side of the lead with the immersion tin material to form an immersion tin plating (e.g., Figure 5 Immersion tin plating 502, Figure 7 In some examples, no current is applied to the immersion tin bath used for electroplating. The immersion tin bath does not adhere to the mold compound 708. Therefore, the immersion tin plating coats the second side of the lead but does not extend beyond the lead. In one example, no annealing is performed after the immersion bath.

[0054] At 814, strip testing is performed on the singulated flat no-lead IC packages. For example, the singulated flat no-lead IC packages, such as the first singulated flat no-lead IC package 302, the second singulated flat no-lead IC package 304, and the third singulated flat no-lead IC package 306, are tested in parallel.

[0055] At 816, a curing process is performed to release the singulated flat no-lead IC package from the tape. As an example, the tape is an ultraviolet (UV) curing tape that is exposed to UV radiation during the curing process. At 818, a testing and winding process is performed. In response to curing, the adhesion of the tape is invalidated. Therefore, after the curing process, the singulated flat no-lead IC package is removed from the tape and encapsulated.

[0056] Fig. 9 A flow chart of an example method 900 is shown, which includes an additional sub-process of the method 800 for utilizing a tin immersion bath at 812 .

[0057] At 902, a cleaning process is performed. In the cleaning process, a cleaning agent is applied to the strip. For example, the cleaning process includes applying a cleaning agent to wettable sides formed by exposed leads. As an example, the cleaning agent etches exposed copper of copper interconnects forming exposed leads.

[0058] At 904, a first rinse cycle is performed after etching to remove the cleaning agent from the strip.

[0059] At 906, a protectant is applied to the wettable side to protect exposed copper of the leads at the second side of the IC package from oxidation or defects.

[0060] At 908, a second rinse cycle is performed to remove the protectant from the second side of the leads. At 910, the strip undergoes a preparatory dip and is dipped in an activation chemistry to prepare for a tinning bath (e.g., Figure 4 The activating chemical increases the reactivity between the conductive material and the immersion tin bath.

[0061] At 912, the strip is immersed in an immersion tin bath. In particular, the immersion includes immersing the singulated IC package in the immersion tin bath so that the etched exposed copper is immersed in the immersion tin. The second side of the lead is immersed in the immersion tin bath to form an immersion tin plating layer (e.g., Figure 5 Immersion tin plating 502, Figure 7 The immersion tin plating layer 714 is based on the chemical reaction between the conductive material and the solution of the immersion tin bath and increases by greater reactivity. In one example, the thickness of the immersion tin plating layer in the longitudinal direction is greater than 2 microns. In another example, the thickness of the immersion tin plating layer in the longitudinal direction is greater than 3 microns. As discussed above, the immersion tin plating layer prevents oxidation of the conductive material of the lead for a certain amount of time based on the thickness of the immersion tin plating layer. For example, the immersion tin plating layer is applied to have a thickness sufficient to prevent consumption of the copper leads of the flat leadless IC package for at least one year.

[0062] Due to the redox reaction between the interconnect material and the plating material, the plating material decreases over time until the plating material is no longer able to protect the interconnect material. The thicker the plating material, the longer the plating material protects the interconnect material, thereby increasing the shelf life of the corresponding flat no-lead IC package. The apparatus and method described herein provide a thicker immersion plating layer on the wettable side of the flat no-lead IC package, which increases the shelf life and reliability of the flat no-lead IC package.

[0063] At 914, a third flush cycle is performed.

[0064] At 916, the strip undergoes a first dip process and is dipped in the first dip chemistry to prepare the strip for a second dip chemistry in a first post dip process. At 918, a fourth rinse cycle is performed. At 920, the strip undergoes a second post dip process and is dipped in the second dip chemistry to prepare the strip for a third dip chemistry. At 922, a fifth rinse cycle is performed.

[0065] At 924, the strip undergoes a third immersion process and is immersed in a third immersion chemistry that forms an anti-tarnish layer on the immersion tin plating. At 926, a sixth rinse cycle is performed. At 928, a hot rinse is performed to rinse the strip. At 930, air is applied to the strip, and at 932, a drying process is performed.

[0066] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / -10% range of the parameter. Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A method for forming an integrated circuit (IC) package, the method comprising: Mounting the tape on the molding compound of the flat leadless IC package strip; sawing the molding compound of the strip of flat no-lead IC packages to form singulated IC packages mounted on the tape; as well as The singulated IC packages are immersed in an immersion tin bath to form an immersion tin plating layer on the sides of the leads of the singulated IC packages. 2 . The method of claim 1 , wherein the immersion tin plating layer has a thickness greater than 2 microns.

3. The method of claim 1, wherein the immersion tin plating layer has a thickness greater than 3 microns. The method of claim 1 , wherein the immersion tin plating has a height of at least 50 microns.

5. The method of claim 1, wherein the tin immersion bath is formed from a solution of tin, a tin salt, and an activator. 6 . The method of claim 1 , wherein the singulated IC packages of the strip of flat no-lead IC packages have copper interconnects.

7. The method of claim 6, wherein the immersing comprises: etching exposed copper of the copper interconnect; as well as The singulated IC packages are immersed in the immersion tin bath such that the etched exposed copper is submerged in the immersion tin.

8. The method according to claim 7, further comprising: The singulated IC packages are rinsed before and after the dipping.

9. The method according to claim 8, further comprising: The singulated IC packages are rinsed before and after the etching.

10. The method of claim 7, wherein said immersing further comprises shocking a tin bath in response to said immersing.

11. The method of claim 10, wherein immersing further comprises vibrating the tin bath during the immersing.

12. The method of claim 7, further comprising encapsulating the strip of flat no-lead IC packages in the molding compound with the bottoms and the sides of the leads exposed.

13. The method of claim 12, further comprising applying a matte tin plating to the bottoms of the leads of the strip of flat no-lead IC packages prior to the dipping.

14. The method of claim 13, wherein the immersion tin of the immersion tin bath is non-reactive to the matte tin plating layer.

15. An integrated circuit (IC) package, comprising: a die mounted on a flat leadless interconnect; as well as The die is encapsulated in a molding compound on a top side of the flat no-leads interconnect, wherein sides of the leads of the flat no-leads interconnect have an immersion tin plating greater than 2 microns thick.

16. The IC package of claim 15, wherein the leads of the flat no-lead interconnect are formed of copper.

17. The IC package of claim 16, wherein the immersion tin plating has a thickness greater than 3 microns.

18. The IC package of claim 16, wherein the immersion tin plating has a thickness sufficient to prevent consumption of copper leads of the flat no-lead interconnect for at least 1 year.

19. The IC package of claim 15, wherein the bottom sides of the leads of the IC package have a matte tin plating.

20. The IC package of claim 15, wherein the height of the immersion tin plating is at least 50 microns.

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