Preparation method, structure and circuit of radio frequency power amplifier

Abstract

The invention discloses a radio frequency power amplifier preparation method, a radio frequency power amplifier structure and a radio frequency power amplifier circuit. The preparation method comprises the steps that a first wafer is provided, a multi-stage cascade field effect transistor structure is formed on the first wafer, and the first wafer is a silicon-on-insulator wafer; a second wafer is provided, a silicon-germanium heterojunction bipolar transistor structure is formed on the second wafer, and the second wafer is a bulk silicon wafer; bonding the multi-stage cascade field effect transistor structure with the silicon germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; and forming a metal wiring structure on the initial power amplifier structure, and electrically connecting the metal wiring structure with the radio frequency input end and the radio frequency output end to form the radio frequency power amplifier. The corresponding structure and circuit prepared by the preparation method have good radio frequency performance, the preparation cost is relatively low, and the compatibility with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit is good.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a radio frequency power amplifier, a radio frequency power amplifier structure, and a radio frequency power amplifier circuit. Background Art

[0002] A transmission system is a system used to transmit signals into space. In this transmission system, the transmitter, as the core part of the transmission system, is responsible for processing and amplifying the information signal to be transmitted, and sending it into space through the antenna. The transmitter usually contains a pre-stage circuit, a modulation oscillation circuit, and a radio-frequency power amplifier (RF PA). The pre-stage circuit is mainly responsible for the preparation of the input baseband signal, such as filtering and preliminary amplification. The modulation oscillation circuit is responsible for modulating the input baseband signal (such as audio, video, data, etc.) into a carrier signal. The modulated carrier signal is usually weak, so it needs to be boosted to sufficient signal strength by an RF power amplifier so that it can be effectively transmitted through the antenna. The main technical indicators of the above-mentioned RF power amplifier are output power and efficiency. Therefore, how to improve the output power and efficiency is the core of the design goal of the RF power amplifier and is also a key topic for relevant researchers.

[0003] Traditional linear power amplifiers have high gain and linearity, but low efficiency, while switching power amplifiers have high efficiency and output power, but poor linearity.

[0004] In view of this, improving the device performance of power amplifiers is an urgent issue to be solved at this stage. Summary of the invention

[0005] The purpose of the present application is to provide a method for preparing a radio frequency power amplifier, a radio frequency power amplifier structure and a radio frequency power amplifier circuit, which can not only effectively solve the problems existing in the prior art, but also have good performance (can provide sufficient gain, large output power and high conversion efficiency), relatively low preparation cost, and good compatibility with CMOS circuits.

[0006] According to the first aspect of the present application, an embodiment of the present application provides a method for preparing a radio frequency power amplifier, including: providing a first wafer, on which a multi-stage cascade field effect transistor structure is formed, wherein the first wafer is a silicon-on-insulator wafer; providing a second wafer, on which a silicon-germanium heterojunction bipolar transistor structure is formed, wherein the second wafer is a bulk silicon wafer; bonding the multi-stage cascade field effect transistor structure to the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; forming a metal wiring structure on the initial power amplifier structure, wherein the metal wiring structure is electrically connected to an radio frequency input terminal and an radio frequency output terminal, respectively, to form a radio frequency power amplifier.

[0007] According to a second aspect of the present application, an embodiment of the present application provides a radio frequency power amplifier structure, comprising: a first semiconductor substrate; a first semiconductor layer, located above the first semiconductor substrate, the first semiconductor layer comprising a plurality of device regions, each of the device regions having a well region and a doped region, a first polysilicon layer being located above each of the well regions, and a first metal silicide layer being located above each of the doped regions and each of the first polysilicon layers; a first dielectric layer, located above the first semiconductor layer, the first dielectric layer covering the first metal silicide layer and the first semiconductor layer, the first dielectric layer having a first contact hole penetrating therethrough, the first contact hole being in contact with a surface of the first metal silicide layer to connect a source, a drain and a gate of the field effect transistor device; a second dielectric layer, located above the first dielectric layer, the second dielectric layer having a first metal interconnect structure, the first metal interconnect structure being electrically connected to the first contact hole; a fourth dielectric layer, located above the second dielectric layer The fourth dielectric layer has a second metal silicide layer and a second contact hole passing through the dielectric layer, and the second contact hole is used to electrically connect the second metal silicide layer and the first metal interconnection structure; the second metal silicide layer has a third polysilicon layer and a second polysilicon layer respectively; the third polysilicon layer is used to form the emitter of the silicon-germanium heterojunction bipolar transistor; the second semiconductor layer is located above the fourth dielectric layer, the second semiconductor layer has a stacked silicon-germanium crystal layer and a collector layer, the silicon-germanium crystal layer is used to form the base of the silicon-germanium heterojunction bipolar transistor, and the collector layer is used to form the collector of the silicon-germanium heterojunction bipolar transistor; the fifth dielectric layer is located above the second semiconductor layer, the fifth dielectric layer has a metal wiring structure, the metal wiring structure is electrically connected to the gate terminal and the radio frequency input terminal of the field effect transistor device, and is electrically connected to the collector terminal and the radio frequency output terminal of the silicon-germanium heterojunction bipolar transistor.

[0008] According to the third aspect of the present application, an embodiment of the present application provides a radio frequency power amplifier circuit, which includes: an input unit, the input unit is configured as a field effect transistor common source amplifier, the field effect transistor common source amplifier includes a first field effect transistor device; an intermediate unit, the intermediate unit is coupled to the input unit, the intermediate unit is configured as a field effect transistor common gate amplifier, the field effect transistor common gate amplifier includes a second field effect transistor device; the second field effect transistor device is configured as at least one cascade field effect transistor; a final stage unit, the final stage unit is coupled to the intermediate unit, the final stage unit includes a triode device, and the triode device is a silicon germanium heterojunction bipolar transistor.

[0009] In the RF power amplifier preparation method, RF power amplifier structure and RF power amplifier circuit provided by the embodiments of the present application, the RF power amplifier includes a silicon germanium heterojunction bipolar transistor (SiGe HBT) structure made of silicon germanium (SiGe) material. The silicon germanium (SiGe) material has a high electron mobility, so that the RF power amplifier can operate at a high frequency with a lower power, which can improve the device performance of the RF power amplifier and make the silicon germanium heterojunction bipolar transistor structure show higher reliability and better voltage resistance. In addition, the silicon germanium material has good thermal diffusion and can effectively conduct heat to other areas inside the device structure, thereby reducing local overheating. Furthermore, by introducing a silicon germanium (SiGe) base region into the silicon germanium heterojunction bipolar transistor structure, the silicon germanium heterojunction bipolar transistor structure has a higher current gain and a lower base resistance, which can reduce power consumption and thus reduce the self-effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 This is a flow chart of the steps of a method for preparing a radio frequency power amplifier in one embodiment of the present application.

[0012] Figure 2 for Figure 1 FIG. 1 is a schematic diagram of an embodiment of step S100 shown in FIG.

[0013] Figure 3 for Figure 1 FIG. 1 is a schematic diagram of an embodiment of step S200 shown in FIG.

[0014] Figure 4 for Figure 1FIG. 4 is a schematic diagram of an embodiment of step S300 shown in FIG.

[0015] Figure 5 for Figure 1 FIG. 4 is a schematic diagram of an embodiment of step S400 shown in FIG.

[0016] 6A to 6F for Figure 1 FIG. 1 is a process flow chart of an embodiment of step S100 shown in FIG.

[0017] 7A to 7F for Figure 1 FIG. 1 is a process flow chart of an embodiment of step S200 shown in FIG.

[0018] Figure 8 and Fig. 9 They are Figure 1 FIG. 1 is a process flow chart of an embodiment of step S300 and step S400 shown in FIG.

[0019] Fig.10 It is a schematic diagram of the structure of a radio frequency power amplifier in one embodiment of the present application.

[0020] Fig.11 Schematic diagram of a radio frequency power amplifier circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0022] See also Figure 1 As shown, an embodiment of the present application provides a method for preparing a radio frequency power amplifier, the preparation method comprising: step S100: providing a first wafer, a multi-stage cascade field effect transistor structure is formed on the first wafer, wherein the first wafer is a silicon-on-insulator wafer (i.e., SOI wafer, the same below); step S200: providing a second wafer, a silicon-germanium heterojunction bipolar transistor structure is formed on the second wafer, wherein the second wafer is a bulk silicon wafer (i.e., Bulk wafer); step S300: bonding the multi-stage cascade field effect transistor structure to the silicon-germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; step S400: forming a metal wiring structure on the initial power amplifier structure, the metal wiring structure being electrically connected to the radio frequency input terminal and the radio frequency output terminal, respectively, to form a radio frequency power amplifier.

[0023] Step S100 , step S200 , step S300 and step S400 will be further described below.

[0024] See also Figure 2 and 6A to 6F As shown, a first wafer is provided, and a multi-stage cascade field effect transistor structure is formed on the first wafer (ie, step S100 ), including the following steps S110 to S160 .

[0025] Specifically, step S110: providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a first semiconductor substrate 101 and a first semiconductor layer 102 stacked in layers; the first semiconductor layer 102 comprises a plurality of device regions, wherein the device regions are used to form field effect transistor devices (i.e., MOS transistor devices, the same below), such as Fig. 6A As shown. The semiconductor substrate on insulator is a SOI substrate, which can be specifically a silicon on insulator, a germanium on an insulator, or a germanium on an insulator. The first semiconductor substrate 101 can be undoped or doped (for example, N-type, P-type, or a combination of the two) silicon. The first semiconductor layer 102 can be silicon. In some embodiments, a buried oxide layer (Buried Oxide, referred to as BOX) is stacked between the first semiconductor substrate 101 and the first semiconductor layer 102 (not shown in the figure), and the buried oxide layer is used to strengthen the isolation of the semiconductor device (here, the MOS tube device), so as to reduce parasitic effects and help improve the switching speed of the semiconductor device. The buried oxide layer can be silicon oxide or silicon oxynitride. The MOS tube device is, for example, an NMOS tube or a PMOS tube.

[0026] Step S120: performing ion implantation at the first position and the second position of each device region respectively to form a well region at each first position and a doping region at each second position, wherein the well region and the doping region of the same device region have opposite doping types.

[0027] In this embodiment, the well region 104 includes a first type well region 104A and a second type well region 104B. The doping region 105 includes a first type doping region 105A and a second type doping region 105B. Figure 6B shown.

[0028] Specifically, the first type ion or the second type ion implantation may be performed at the first position of each device region to form the first type well region 104A or the second type well region 104B accordingly. Similarly, the second type ion or the first type ion implantation may be performed at the second position of each device region to form the second type doping region 105B or the first type doping region 105A accordingly. Figure 6BAs shown. Among them, the doping types of the first type well region 104A and the second type well region 104B are opposite, the doping types of the first type well region 104A and the first type doping region 105A are the same, and the doping types of the second type well region 104B and the second type doping region 105B are the same. The positions of the first position and the second position in the device region are different. For example, when the first type ion implantation is performed at the first position of the first device region 1021, and the first type ion is P ion, such as boron (B), gallium (Ga) or indium (In), the first type well region 104A formed is a P-type well region (i.e., PW), and when the second type ion implantation is performed at the second position of the first device region 1021, and the second type ion is N ion, such as phosphorus (P), antimony (Sb) or arsenic (As), the second type doping region 105B formed is an N-type doping region (N+). With such a configuration, the MOS tube device formed in the first device region 1021 is an NMOS tube. For another example, when the second type of ion implantation is performed at the first position of the second device region 1022, and the second type of ions are N ions, such as phosphorus (P), antimony (Sb) or arsenic (As), the second type of well region 104B formed is an N-type well region (i.e., NW); when the first type of ion implantation is performed at the second position of the second device region 1022, and the first type of ions are P ions, such as boron (B), gallium (Ga) or indium (In), the first type of doped region 105A formed is a P-type doped region (P+). With this configuration, the MOS tube device formed in the second device region 1022 is a PMOS tube.

[0029] In the above example, the first type of ions are configured as P ions and the second type of ions are configured as N ions. Of course, the first type of ions can also be configured as N ions and the second type of ions can be configured as P ions, so that the MOS tube device formed in the above-mentioned first device area is a PMOS tube, and the MOS tube device formed in the second device area is an NMOS tube.

[0030] In one embodiment of the present application, before ion implantation is performed at the first position and the second position of each device region to form a well region at each first position and a doped region at each second position (i.e., step S120), the preparation method may further include: forming a first trench isolation region (Shallow Trench Isolation, STI for short) 103 at the periphery of the device region of the first semiconductor layer 102, such as Fig. 6AAs shown. Specifically, at the periphery of the device area on the first semiconductor layer 102, photolithography technology is used to define the areas that need to be isolated on the surface of the SOI wafer, and these areas are etched into grooves by using dry etching (RIE) technology, and oxide (for example, silicon dioxide) material is filled in the etched grooves by using chemical vapor deposition (CVD) technology to form a first trench isolation region 103. Further, a chemical mechanical polishing (CMP) process can be used to remove excess oxide material so that the surface of the SOI wafer is flat, and only the oxide in the trench remains. In this embodiment, the first trench isolation region 103 surrounds the device area and isolates the MOS tube device formed in the device area from other areas, thereby achieving electrical isolation between different devices. Furthermore, the first trench isolation region 103 is also located between the first device region 1021 and the second device region 1022 of the first semiconductor layer 102, and the doping type of the doping region in the first device region 1021 is opposite to that of the doping region in the second device region 1022, as shown in FIG. Figure 6B shown.

[0031] Step S130: forming a first polysilicon layer 107 on a side of each well region away from the first semiconductor substrate, wherein the doping type of each first polysilicon layer is opposite to that of the corresponding well region.

[0032] In this embodiment, the first polysilicon layer 107 may include a first type polysilicon 107A and a second type polysilicon 107B. Figure 6B and Figure 6C As shown, the second type polysilicon 107B and the first type polysilicon 107A may be formed respectively on the side of the first type well region 104A and the second type well region 104B away from the first semiconductor substrate 101 .

[0033] Specifically, if the MOS transistor device to be formed in the first device region is an NMOS transistor, a second type of polysilicon 107B is formed above the first type well region 104A (here, a P-type well region) (i.e., the side away from the first semiconductor substrate 101). Further, the second type of polysilicon 107B is N-type doped (for example, phosphorus or arsenic is doped) to form N-type doped polysilicon, so as to be used as the gate material of the NMOS transistor. In other words, the doping type (N-type) of the second type of polysilicon 107B is opposite to the doping type (P-type) of the first type of well region 104A. If the MOS transistor device to be formed in the second device region is a PMOS transistor, a first type of polysilicon 107A is formed above the second type of well region 104B (here, an N-type well region) (i.e., the side away from the first semiconductor substrate 101). Further, the first type of polysilicon 107A is P-type doped (for example, boron doped) to form P-type doped polysilicon, so as to be used as the gate material of the PMOS transistor. That is, the doping type (P type) of the first type polysilicon 107A is opposite to the doping type (N type) of the second type well region 104B.

[0034] In one embodiment of the present application, before forming a first polysilicon layer on a side of each well region away from the first semiconductor substrate, and each first polysilicon layer has a doping type opposite to that of the corresponding well region (i.e., step S130), the preparation method may further include: forming a gate oxide layer 106 on a side of the first type well region 104A and the second type well region 104B away from the first semiconductor substrate 101, such as Figure 6C As shown. The gate oxide layer 106 can be silicon dioxide (SiO2) or a high-K material, which can be used as an insulating layer for MOS tube devices. Specifically, a thinner silicon dioxide layer is grown on the active silicon layer on the surface of the SOI wafer through a thermal oxidation process as the gate oxide layer 106. The thickness of the gate oxide layer 106 is tens of nanometers, and the smaller the thickness, the more conducive to improving the performance of the device. It should be noted that in the present application, according to actual needs, a stepped gate oxide layer 106 can be achieved by repeatedly using oxidation and etching processes, so as to optimize the electrical performance of different regions.

[0035] Step S140: depositing metal on a side of each doped region and each first polysilicon layer away from the first semiconductor substrate to form a first metal silicide layer.

[0036] In this embodiment, combined with FIG. 6B to FIG. 6D As shown, metal is deposited on the first type doped region 105A, the second type doped region 105B, the second type polysilicon 107B, and the side of the first type polysilicon 107A facing away from the first semiconductor substrate 101 to form a first metal silicide layer 108 .

[0037] Specifically, when the second type doping region 105B is an N-type doping region, the first type doping region 105A is a P-type doping region, the second type polysilicon 107B is N-type doped polysilicon, and the first type polysilicon 107A is P-type doped polysilicon, a layer of nickel is deposited on the N-type doping region, the P-type doping region, the N-type doped polysilicon, and the P-type doped polysilicon by using sputtering or physical vapor deposition (PVD) technology, and rapid thermal annealing (RTA) is performed to make the nickel react with the silicon in the source, drain, and gate regions to form a low-resistance nickel-silicon layer, such as Fig.6D As shown, unreacted nickel is removed by selective etching to ensure that nickel silicon is formed at the desired location.

[0038] Step S150: forming a first dielectric layer 109 covering the first metal silicide layer 108 and the first semiconductor layer 102, wherein the first dielectric layer 109 has a first contact hole (111, 112, 113), the first contact hole penetrates the first dielectric layer 109, and contacts with the surface of the first metal silicide layer 108, so as to connect the source, drain and gate of the field effect transistor device.

[0039] Combination FIG. 6B to FIG. 6E As shown, a first dielectric layer 109 is formed above the first metal silicide layer 108 and the first semiconductor layer 102 (i.e., on the side away from the first semiconductor substrate 101), that is, the first dielectric layer 109 covers the first metal silicide layer 108 and the first semiconductor layer 102. The first dielectric layer 109 has a plurality of first contact holes (111, 112, 113). These first contact holes (111, 112, 113) penetrate the first dielectric layer 109 and contact the surface of the first metal silicide layer 108 to connect the source (Source), drain (Drain) and gate (Gate) of the field effect transistor device. The first metal silicide layer 108 is used to reduce the contact resistance of the source, drain and gate, thereby improving the electrical performance of the device.

[0040] The specific implementation of this step is as follows: a first dielectric layer 109 (for example, silicon dioxide or silicon nitride) is formed above the first metal silicide layer 108 and the first semiconductor layer 102 (i.e., the side away from the first semiconductor substrate 101), and a first contact hole (111, 112, 113) is formed in the first dielectric layer 109 corresponding to the source, gate, and drain regions using photolithography and etching techniques to expose the first metal silicide layer 108 (here, a nickel silicon layer), and then a metal (for example, titanium / titanium nitride, aluminum, or copper) is deposited in the first contact hole using physical vapor deposition or chemical vapor deposition techniques, and then a chemical mechanical polishing (CMP) process is used to remove excess metal deposition, leaving only the metal in the first contact hole. In this way, a first contact hole (for example, a first contact hole) connecting the source, drain, and gate of the MOS tube device can be formed inside the first dielectric layer 109 and on the surface of the first metal silicide layer 108. Fig. 6E Reference numerals 111, 112, 113 are shown).

[0041] Step S160: forming a second dielectric layer 114 on a side of the first dielectric layer 109 away from the first semiconductor substrate, and forming a first metal interconnection structure 115 in the second dielectric layer 114, such as Fig. 6F As shown, the first metal interconnection structure 115 is used to electrically connect the source, drain and gate of the field effect transistor device. In this configuration, the first metal interconnection structure 115 can electrically connect the source, drain and gate of the MOS transistor device to other devices or circuits to achieve signal transmission.

[0042] Specifically, a second dielectric layer 114 (e.g., silicon dioxide or silicon nitride) is deposited above the first dielectric layer 109 (i.e., on the side away from the first semiconductor substrate 101), and a first metal interconnect structure 115 (e.g., a through hole or groove of the metal interconnect structure) is defined using photolithography and etching techniques to expose the area that needs to be connected. Then, a metal (e.g., copper or aluminum) is filled in the through hole of the metal interconnect structure using electroplating or chemical vapor deposition technology to form a metal interconnect path, and then a chemical mechanical polishing process is used to remove excess metal. It should be noted that when executing this step S160, the above steps can be repeated to achieve a metal interconnect structure with a multi-layer arrangement according to the design of the relevant circuit.

[0043] In addition, it is worth noting that when multiple MOS tube devices formed by multiple device regions are configured to be cascaded in a corresponding circuit, for example, the drain of the first cascade MOS tube is electrically connected to the source of the second cascade MOS tube, the drain of the second cascade MOS tube is electrically connected to the source of the third cascade MOS tube, the drain of the third cascade MOS tube is electrically connected to the source of the fourth cascade MOS tube... and so on, the drain of the (N-1)th cascade MOS tube is electrically connected to the source of the Nth cascade MOS tube, in this case, the second type doping region 105B in each device region is configured to be formed integrally with the second type doping region 105B in the adjacent device region. Similarly, according to the corresponding circuit design, the first type doping region 105A in each device region is configured to be formed integrally with the first type doping region 105A in the adjacent device region.

[0044] See also Figure 3 and 7A to 7F As shown, a second wafer is provided, on which a silicon-germanium heterojunction bipolar transistor structure is formed (ie, step S200 ), including the following steps S210 to S260 .

[0045] Step S210: providing a second semiconductor substrate 201 .

[0046] Step S220: forming a second semiconductor layer 202 on the second semiconductor substrate 201, wherein a heavily doped collector layer 204 is formed in the second semiconductor layer 202 to obtain a collector of a silicon germanium heterojunction bipolar transistor, such as Fig. 7A shown.

[0047] Specifically, a second semiconductor substrate 201 is provided on the surface of a second wafer (here, a bulk wafer). On the second semiconductor substrate 201, an epitaxial growth method is used to grow silicon or silicon germanium material on the second semiconductor substrate 201 (for example, a silicon substrate), and during the growth process, high doping is achieved by controlling the concentration of the doping source (for example, N-type dopants such as phosphorus and arsenic), and a highly doped collector layer 204 is formed. It should be noted that the epitaxial growth method refers to depositing a layer of material having the same structure as the substrate on a substrate (usually silicon). The epitaxial layer serves as the second semiconductor layer 202, and its thickness, doping concentration and material composition can be precisely controlled to form the desired electrical properties. High doping means that the collector layer 204 has a higher conductivity by controlling the flow rate of the doping source and the epitaxial growth parameters. The heavy doping of the collector helps to increase the carrier concentration in the collector region, reduce the resistance in the collector region, and speed up the current transmission speed. It is worth noting that excessive doping will lead to current leakage and reduced breakdown voltage, while too low doping will lead to excessive resistance in the collector region, affecting device performance. Therefore, in this embodiment, the heavily doped collector layer 204 ensures that the required doping concentration is obtained in the collector region through precise process control, and by controlling the thickness of the collector layer 204 (for example, making it thinner), the time for carriers to pass through the collector is shortened, while the resistance of the collector region is reduced, thereby achieving the effect of meeting high-frequency performance and low power consumption.

[0048] In some embodiments, by using ion implantation technology, that is, using a high-energy particle accelerator to directly implant dopants (such as phosphorus or arsenic) into the silicon layer on the second semiconductor substrate 201, a heavily doped collector layer 204 is formed. This method can be performed after epitaxial growth to further enhance the doping concentration of the collector region. Furthermore, annealing is performed after ion implantation to diffuse and activate dopant atoms, thereby ensuring that the dopant reaches the desired depth and distribution, thereby optimizing the electrical performance of the device.

[0049] Optionally, in some embodiments, before step S210, the preparation method further comprises the following steps: forming a second trench isolation region 203 around the collector region of the second semiconductor layer 202, such as Fig. 7A The second trench isolation region 203 is formed in the same manner as the first trench isolation region 103, and will not be described in detail herein.

[0050] Step S230: forming a silicon germanium crystal layer 205 covering the collector layer 204 to obtain a base of a silicon germanium heterojunction bipolar transistor, such as Figure 7BAs shown. In a bipolar transistor, the base region is the region that controls the collector and emitter currents. Specifically, after forming a heavily doped collector layer 204, a silicon germanium material can be grown above the collector layer 204 to obtain the base of the silicon germanium heterojunction bipolar transistor. Silicon germanium has higher mobility and better frequency characteristics, which helps to improve the performance of the device. Further, the silicon germanium crystal layer 205 adopts a lower doping concentration to achieve current control between the emitter and the collector.

[0051] Step S240: forming a second polysilicon layer 206 on the second semiconductor layer 202, wherein the second polysilicon layer 206 has a pattern opening, and the pattern opening exposes a portion of the surface of the silicon germanium crystal layer 205, see Figure 7B and Figure 7C Specifically, a second polysilicon layer 206 is formed on the surface of the second wafer (i.e., the bulk wafer) (here, above the second semiconductor layer 202), and the second polysilicon layer 206 is P-doped (e.g., doped with boron) to form a P-type doped polysilicon layer. In this step, a specific pattern of the P-type doped polysilicon layer is defined by using photolithography and etching techniques, such as Figure 7C As shown, the second polysilicon layer 206 (here, a P-type doped polysilicon layer) has a pattern opening, and the pattern opening exposes a portion of the upper surface of the silicon germanium crystal layer 205.

[0052] Step S250: depositing a third dielectric layer 207 on the second polysilicon layer 206 and the silicon germanium crystal layer 205, wherein a contact window is formed through the third dielectric layer 207, and the contact window is filled with a third polysilicon layer 208, and the third polysilicon layer 208 is in contact with the silicon germanium crystal layer 205, so as to obtain an emitter of a silicon germanium heterojunction bipolar transistor, such as Fig.7D shown.

[0053] Specifically, a layer of oxide (for example, silicon dioxide or other dielectric material) is first deposited on the second polysilicon layer 206 and the silicon germanium crystal layer 205 after doping and patterning (i.e., on the side away from the second semiconductor substrate 201) to form a third dielectric layer 207 (or insulating layer), which is used to isolate different functional areas and prevent unnecessary current leakage. Then, a chemical mechanical polishing (CMP) process is used to flatten the surface to provide a flat surface for subsequent process steps. Then, photolithography and etching techniques are used to form a penetrating contact window in the third dielectric layer 207. It should be noted that the contact window serves as a contact area between the base region and the emitter region, so that the emitter can be electrically connected to the base. After a contact window is formed in the third dielectric layer 207, a third polysilicon layer 208 is filled in the contact window, and the third polysilicon layer 208 contacts the silicon germanium crystal layer 205 to obtain the emitter of the silicon germanium heterojunction bipolar transistor, and establishes an electrical connection with the base of the silicon germanium heterojunction bipolar transistor obtained in step S230. It should be noted that after the third polysilicon layer 208 is deposited and formed, the third polysilicon layer 208 is N-type doped (for example, phosphorus or arsenic is doped) to form an N-type doped polysilicon layer. Further, by using photolithography and etching technology, the specific pattern of the N-type doped polysilicon layer is defined again to ensure the precise positioning of the emitter region.

[0054] Step S260: forming a second metal silicide layer 210 in contact with the second polysilicon layer 206 and the third polysilicon layer 208, such as Fig. 7E shown.

[0055] Specifically, firstly, a portion of the third dielectric layer 207 is removed by photolithography and etching techniques to form a metal contact window, thereby exposing the contact areas of the emitter, base and collector. Subsequently, a layer of metal (for example, nickel silicon (NiSi) or cobalt silicon (CoSi)) is deposited to form a second metal silicide layer 210, wherein the metal silicide is used to reduce the contact resistance, thereby improving the device performance. It should be noted that, if Fig. 7E In the illustrated embodiment, a portion of the third dielectric layer 207 and a portion of the third polysilicon layer 208 are removed using photolithography and etching techniques to form a desired contact region, and a layer of metal (specifically nickel Ni) is deposited on the contact region to form a second metal silicide layer 210. If the metal deposited on the contact region is cobalt Co, there is no need to remove a portion of the third polysilicon layer 208, that is, cobalt is deposited on the second polysilicon layer 206 and the third polysilicon layer 208, and cobalt reacts with silicon to form a cobalt-silicon alloy, that is, the second metal silicide layer 210 is formed.

[0056] Step S270: forming a fourth dielectric layer 211 covering the second metal silicide layer 210 and the third dielectric layer 207, and forming a second contact hole 209 penetrating the fourth dielectric layer 211, wherein the second contact hole 209 contacts the second metal silicide layer 210. Figure 7F As shown, a fourth dielectric layer 211 is formed above the second metal silicide layer 210 and the third dielectric layer 207 (i.e., on the side away from the second semiconductor substrate 201), and a second contact hole 209 is formed in the fourth dielectric layer 211. The second contact hole 209 includes a contact hole for forming a conductive column 212 and a contact hole for forming a first metal interconnection layer 213.

[0057] Specifically, a layer of dielectric material (e.g., silicon dioxide SiO2, a material with a low dielectric constant (low-K material) or a fluorosilicate glass FSG material) is deposited on the second metal silicide layer 210 and the third dielectric layer 207 to form a fourth dielectric layer 211, which is used to prevent electrical short circuits and provide support for subsequent metal wiring. Then, a second contact hole 209 is formed in the dielectric layer using photolithography and etching techniques. The second contact hole first portion 209A in the second contact hole 209 can be used to form a conductive column 212, and the second contact hole second portion 209B can be used to form a first metal interconnection layer 213. The conductive column 212 and the first metal interconnection layer 213 will be further described below.

[0058] In this embodiment, in the fourth dielectric layer 211, the photolithography and etching techniques are first used to form the first part 209A of the second contact hole, and the first part 209A of the second contact hole can expose the surface of the emitter, the base and the collector or the previously formed second metal silicide layer 210 (for example, NiSi or CoSi), so as to prepare for the subsequent metal deposition. Optionally, after the second contact hole first part 209A is formed, titanium (Ti), titanium nitride (TiN) or tantalum (Ta), tantalum nitride (TaN) is deposited on the inner wall of the second contact hole first part 209A using physical vapor deposition technology, wherein titanium or tantalum is used as an adhesion layer (Glue Layer) to enhance the adhesion between the subsequent metal (for example, tungsten) and the dielectric material; titanium nitride or tantalum nitride is used as a barrier layer to prevent metal atoms from diffusing into the dielectric layer to avoid performance degradation. Subsequently, a layer of metal (here tungsten, which has low resistance and good thermal stability and maintains performance under high temperature conditions) is deposited by using chemical vapor deposition or physical vapor deposition technology to fill the first part 209A of the second contact hole and cover the surface of the wafer. It should be noted that the tungsten inside the first part 209A of the second contact hole is used to ensure electrical connection with the exposed contact areas of the emitter, base and collector, that is, the first part 209A of the second contact hole is used as a conductive column 212. After that, a chemical mechanical polishing process is used to remove excess tungsten. Further, by using photolithography and etching technology, the precise pattern of tungsten is defined again, and unnecessary tungsten is removed to meet the design requirements of the relevant circuit.

[0059] In this embodiment, after the tungsten filling of the first part 209A of the second contact hole is completed, the second part 209B of the second contact hole can be formed by using photolithography and etching technology, and metal (such as copper or aluminum, which has good conductivity, processability and cost-effectiveness) is deposited on the second part 209B of the second contact hole by using physical vapor deposition or chemical vapor deposition technology, and the deposited metal is converted into a specific interconnection pattern by using photolithography and etching technology to form a first metal interconnection layer 213, so that the key parts (emitter, base and collector) in the silicon germanium heterojunction bipolar transistor structure can be electrically connected to the external circuit through the first metal interconnection layer 213. It should be noted that the first metal interconnection layer 213 generally refers to the first layer in the metal interconnection layer, and other layers in the metal interconnection layer (such as the second metal interconnection layer M2, the third metal interconnection layer M3, etc.) can also be formed by the above process. Further, these metal interconnection layers are separated by dielectric materials and connected to each other through vias.

[0060] See also Figure 4 and Figure 8As shown, bonding the multi-stage cascade field effect transistor structure with the silicon germanium heterojunction bipolar transistor structure to form an initial power amplifier structure (ie, step S300) includes the following steps S310 to S320.

[0061] Specifically, step S310: inverting (or flipping) the silicon-germanium heterojunction bipolar transistor structure formed on the second wafer.

[0062] Step S320: The inverted silicon germanium heterojunction bipolar transistor structure is electrically connected to the multi-stage cascade field effect transistor structure to obtain an initial power amplifier structure. Specifically, the flip-chip technology can be used to electrically connect the inverted silicon germanium heterojunction bipolar transistor structure (i.e., the emitter 208, base 205, and collector 204 in the SiGe HBT structure) to the multi-stage cascade field effect transistor structure (i.e., the source, gate, and drain of the MOS transistor device) through the interconnecting metal (such as the first metal interconnecting structure 115 mentioned above) to perform physical and electrical integration, thereby effectively combining the high-frequency characteristics of the SiGe HBT with the efficient switching characteristics of the MOS transistor device. Of course, in other embodiments, the through silicon via (TSV) technology can also be used to achieve the physical and electrical connection between the above-mentioned silicon germanium heterojunction bipolar transistor structure and the multi-stage cascade field effect transistor structure.

[0063] It should be noted that separate devices (such as RF switches, low noise amplifiers, RF power amplifiers, etc.) are usually combined together through packaging technology, but may be limited by the packaging, interconnection, circuit complexity and size between devices. With the development of 5G technology, the requirements for transmission system performance, power consumption and volume are getting higher and higher. This requires the integration of more discrete devices on the same wafer to improve system efficiency and reduce power consumption and signal loss. Due to the high operating voltage, high power consumption, and efficiency and thermal management requirements of the RF power amplifier, it is difficult to integrate the RF power amplifier with the RF switch and low noise amplifier on the same wafer. In addition, the technologies used for RF power amplifiers in current technology include gallium arsenide (GaAs) or gallium nitride (NAs). These materials can achieve efficient power amplification, but these materials are incompatible with mainstream silicon (Si)-based CMOS processes and cannot be integrated on the same wafer, especially the RF silicon-on-insulator and gallium arsenide processes are incompatible, and the size of RF silicon-on-insulator wafers in current technology is usually 12 inches (300mm), while the size of gallium arsenide wafers is usually 6 inches (150mm), which means that integrating these two different technologies on the same production line faces huge process challenges. In other words, the differences in material properties and wafer size between RF silicon-on-insulator wafers and gallium arsenide wafers further hinder the integration of the two technologies. This solution independently prepares the SiGe HBT structure and the multi-stage cascade field effect tube structure, wherein the multi-stage cascade field effect tube structure is prepared on a silicon-on-insulator wafer, and the SiGe HBT structure is prepared on a bulk wafer, so that they can be completed on different wafers, and then the wafers with the above structures are bonded and integrated, which can improve the preparation efficiency. At the same time, it also solves the problems of the prior art that the power amplifier made by the gallium arsenide process is expensive and has poor process integration, and the power amplifier made by the complementary metal oxide semiconductor (CMOS) process has low electron mobility, relatively poor performance, and is difficult to be applied in high output power occasions.

[0064] Moreover, the SiGe HBT structure formed on the body wafer of the present application is bonded to (i.e., integrated together) the multi-stage cascade field effect transistor structure formed on the silicon-on-insulator wafer, thereby providing better utilization of the silicon-on-insulator wafer and also reducing the preparation cost of the entire device (the cost of silicon-on-insulator wafers is relatively high).

[0065] Furthermore, the heterojunction bipolar transistor (HBT) of the present application scheme uses silicon germanium material. Compared with silicon material, silicon germanium has higher mobility (the introduction of germanium increases the mobility of electrons and holes, making the carrier transmission speed faster), so that the operating frequency of the circuit can be increased while reducing power consumption; the SiGe HBT structure made of silicon germanium material has better electron mobility, so it can work at a lower power at a high frequency, while also providing higher performance indicators (for example, higher conversion efficiency, higher power amplification efficiency (PAE) (can reach more than 40%), and higher power output), and makes the SiGe HBT structure show higher reliability and better voltage resistance. Furthermore, by optimizing the thickness, alloy composition and device structure of silicon germanium material, silicon germanium material can show higher thermal stability and higher breakdown voltage in high-frequency applications.

[0066] In addition, the present application forms a SiGe HBT structure on the bulk wafer and a multi-stage cascade field effect transistor structure on the silicon-on-insulator wafer, so that high-power devices can be kept away from other RF devices (for example, an RF switch, which can be prepared on a silicon-on-insulator wafer, because the silicon-on-insulator wafer can provide better high-frequency performance, isolation, lower parasitic effects and higher switching speeds), thereby improving isolation and achieving less interference in the signals received and transmitted by the RF power amplifier.

[0067] See also Figure 5 and Fig. 9 As shown, a metal wiring structure is formed on the initial power amplifier structure, and the metal wiring structure is electrically connected to the RF input terminal and the RF output terminal respectively to form a RF power amplifier (ie, step S400) including the following steps S410 to S420.

[0068] Step S410: forming a fifth dielectric layer 401 on the side of the initial power amplifier structure away from the first semiconductor substrate 101, and forming a metal wiring structure 402 located within the fifth dielectric layer 401 and the initial power amplifier structure. The metal wiring structure 402 includes a metal contact layer 4021 and a metal wiring layer 4022 described below.

[0069] Specifically, after integrating the above-mentioned SiGe HBT structure and multi-stage cascade field effect transistor structure, a dielectric material (for example, silicon dioxide or other dielectric materials) is deposited thereon to form a fifth dielectric layer 401, which is used to prevent electrical short circuits and provide mechanical support for subsequent photolithography, etching and metal wiring. After depositing the fifth dielectric layer 401, photolithography and etching techniques are used to open contact windows (or contact holes, contact vias) in areas where electrical connections are required to expose the emitter, base, collector in the SiGe HBT structure or the source, drain and gate of the MOS tube device in the multi-stage cascade field effect transistor structure. The formation of these contact areas is to enable the metal contact layer 4021 described below to be directly electrically connected to the functional areas of the SiGe HBT structure and the multi-stage cascade field effect transistor structure. That is to say, this process enables the metal contact layer 4021 to establish electrical connections with various parts (source, gate and drain) of the MOS tube device in the SiGe HBT structure and the multi-stage cascade field effect tube structure, ensuring that the current and signal are transmitted through the metal contact layer 4021, so as to serve as the basis for RF signal transmission (such as RF input and RF output). After the contact window is formed, a low-resistance metal (such as copper or aluminum) is deposited using physical vapor deposition or chemical vapor deposition technology to form a metal contact layer 4021. The metal contact layer 4021 is filled in the contact window (or contact hole) to achieve local electrical connection with the functional area of ​​the SiGe HBT structure and the MOS tube device, thereby forming a partial metal wiring structure. It should be noted that the formation of the above-mentioned metal contact layer 4021 is used to provide an electrical connection point between the SiGe HBT structure and the multi-stage cascade field effect tube structure, and to form a signal transmission path through further metal wiring.

[0070] Step S420: forming a metal wiring structure located in the fifth dielectric layer and the initial power amplifier structure, the metal wiring structure being electrically connected to the gate terminal and the RF input terminal of the multi-stage cascade field effect transistor structure, and being electrically connected to the collector terminal and the RF output terminal of the silicon germanium heterojunction bipolar transistor.

[0071] Specifically, after completing step S410, an electrical connection point between the SiGe HBT structure and the multi-stage cascade field effect tube structure is provided, and a plurality of metal wiring layers 4022 are stacked to realize global signal transmission and device interconnection. In this embodiment, the RF input terminal (RF IN) is connected to the gate terminal of the MOS tube device in the multi-stage cascade field effect tube structure, and the RF output terminal (RF OUT) is connected to the collector terminal of the SiGe HBT structure. It should be noted that an insulating layer is deposited between each metal wiring layer 4022, and a through hole is formed using photolithography and etching technology. These through holes are used to connect the metal wiring layers 4022 of different layers, and the metal in the through hole (for example, copper or aluminum) is used to form the required wiring path to realize complex interconnection and signal transmission. After establishing the RF input and RF output paths, it is possible to achieve electrical connection with the RF input terminal (RF IN) and the RF output terminal (RF OUT), and to be connected to an external circuit.

[0072] See also Fig.10 As shown, the embodiment of the present application provides a radio frequency power amplifier structure, and the radio frequency power amplifier structure is manufactured by the radio frequency power amplifier manufacturing method described in the embodiment of the present application. The manufacturing method has been described in detail above and will not be repeated here.

[0073] In this embodiment, the radio frequency power amplifier structure may at least include:

[0074] A first semiconductor substrate 101;

[0075] The first semiconductor layer 102 is located above the first semiconductor substrate 101. The first semiconductor layer 102 includes a plurality of device regions, each of which has a well region 104 and a doped region 105 (see Figure 6B ), each well region 104 has a first polysilicon layer 107 (see Figure 6C ), each doped region 105 and each first polysilicon layer 107 has a first metal silicide layer 108 (see Fig.6D ); wherein the device region is used to form a field effect transistor device (i.e., a MOS transistor device); a well region 104 is provided at a first position of each device region, the well region 104 includes a first type well region 104A and a second type well region 104B, and a doping region 105 is provided at a second position of each device region, the doping region 105 includes a first type doping region 105A and a second type doping region 105B; a first polysilicon layer 107 is provided above the first type well region 104A and the second type well region 104B, the first polysilicon layer 107 includes a first type polysilicon 107A and a second type polysilicon 107B; a first metal silicide layer 108 is provided above the first type doping region 105A, the second type doping region 105B, the second type polysilicon 107B and the first type polysilicon 107A;

[0076] A first dielectric layer 109 is located above the first semiconductor layer 102. The first dielectric layer 109 covers the first metal silicide layer 108 and the first semiconductor layer 102. The first dielectric layer 109 has a first contact hole (111, 112, 113) penetrating therethrough. The first contact hole contacts the surface of the first metal silicide layer 108 to connect the source, drain and gate of the field effect transistor device.

[0077] A second dielectric layer 114 is located above the first dielectric layer 109. The second dielectric layer 114 has a first metal interconnection structure 115. The first metal interconnection structure 115 is electrically connected to the first contact holes (111, 112, 113).

[0078] The fourth dielectric layer 211 is located above the second dielectric layer 114. The fourth dielectric layer 211 has a second metal silicide layer 210 and a second contact hole 209 extending therethrough. The second contact hole 209 is used to electrically connect the second metal silicide layer 210 and the first metal interconnect structure 115. A third polysilicon layer 208 and a second polysilicon layer 206 are provided above the second metal silicide layer 210, respectively. The third polysilicon layer 208 is used to form an emitter of a silicon-germanium heterojunction bipolar transistor. It should be noted that a third dielectric layer 207 is provided between the third polysilicon layer 208 and the second polysilicon layer 206. For details, please refer to the description of the preparation method above.

[0079] A second semiconductor layer 202 is located above the fourth dielectric layer 211. The second semiconductor layer 202 comprises a stacked silicon germanium crystal layer 205 and a collector layer 204. The collector layer 204 is used to form a collector of a silicon germanium heterojunction bipolar transistor.

[0080] The fifth dielectric layer 401 is located above the second semiconductor layer 202. The fifth dielectric layer 401 has a metal wiring structure 402. The metal wiring structure 402 is electrically connected to the gate terminal of the field effect transistor device and the radio frequency input terminal (RF IN), and is electrically connected to the collector terminal of the silicon germanium heterojunction bipolar transistor and the radio frequency output terminal (RF OUT). Specifically, the gate terminal of the field effect transistor device is electrically connected to the radio frequency input terminal (RF IN) through the first metal interconnection structure 115 and the metal wiring structure 402, and the metal contact layer 4021 of the metal wiring structure 402 is configured in the second dielectric layer 114, the fourth dielectric layer 211 and the fifth dielectric layer 401; the drain terminal of the field effect transistor device is electrically connected to the first metal interconnection layer 213 through the first metal interconnection structure 115; the collector terminal of the silicon germanium heterojunction bipolar transistor is electrically connected to the radio frequency output terminal (RF OUT) through the metal wiring layer 4022 of the metal wiring structure 402.

[0081] In the RF power amplifier structure provided in the embodiment of the present application, the base (i.e., silicon germanium crystal layer) 205 of the silicon germanium heterojunction bipolar transistor is made of silicon germanium material, which helps to realize that the SiGe HBT structure is easy to integrate into the CMOS logic circuit (here, a multi-stage cascade field effect tube structure), thereby achieving the purpose of mixed signals. Further, the germanium content in the SiGe HBT structure is low, the thermal conductivity of the overall structure is high, and good thermal conductivity can be maintained. In addition, the silicon germanium material has good thermal diffusivity, which can more effectively conduct heat to other areas inside the device, reducing local overheating. Compared with traditional silicon-based bipolar transistors, the silicon germanium crystal layer 205 is introduced into the SiGe HBT structure as the base region, which has a higher current gain and a lower base resistance, thereby reducing power consumption and alleviating the self-heating effect. In addition, the thickness of the silicon germanium crystal layer 205 is thin, the heat dissipation speed is fast, and the vertical structure design of the SiGe HBT structure allows the collector to directly dissipate heat. Therefore, the high thermal conductivity material and low thermal resistance design used in the SiGe HBT structure further optimize the heat dissipation path.

[0082] It should be noted that in the RF power amplifier structure provided in the embodiment of the present application, the collector of the silicon-germanium heterojunction bipolar transistor is directly electrically connected using a metal with high conductivity (e.g., copper), and aluminum is not used because the conductivity of aluminum is lower than that of other metals (e.g., copper, tungsten, or other more advanced metals), and the electromigration problem of aluminum will lead to reduced reliability of interconnection at high current density, which is likely to increase power loss in high-frequency applications. Therefore, in the RF power amplifier structure of the embodiment of the present application, the collector of the silicon-germanium heterojunction bipolar transistor is directly made of copper material, which can reduce resistance, parasitic capacitance, and inductance.

[0083] See also Fig.11 As shown, the present embodiment of the present application provides a radio frequency power amplifier circuit, and the radio frequency power amplifier circuit is manufactured by the radio frequency power amplifier manufacturing method described in the present embodiment of the present application. The manufacturing method is described in detail above, and will not be repeated here.

[0084] In this embodiment, the radio frequency power amplifier circuit may include: an input unit 10 , an intermediate unit 20 and a final unit 30 .

[0085] The input unit 10 is configured as a field effect transistor common source amplifier for providing sufficient gain. The field effect transistor common source amplifier may include a first field effect transistor device Q1. The intermediate unit 20 is coupled to the input unit 10, and the intermediate unit 20 is configured as a field effect transistor common gate amplifier for providing sufficient input impedance. The field effect transistor common gate amplifier includes a second field effect transistor device Q2; the second field effect transistor device Q2 is configured as at least one cascade field effect transistor. The final unit 30 is coupled to the intermediate unit 20, and the final unit 30 includes a triode device T1, wherein the triode device T1 is a silicon germanium (SiGe) heterojunction bipolar transistor for providing high power output and high conversion rate.

[0086] like Fig.11 As shown, the source of the first field effect transistor device Q1 is grounded, the drain of the first field effect transistor device Q1 is electrically connected to the source of the second field effect transistor device Q2, and the gate of the first field effect transistor device Q1 is connected to an input resistor R i Electrical connection, input resistance R i The resistance value of the input resistor Ri is greater than a preset resistance value. That is, the resistance value of the input resistor Ri is set to be relatively large (for example, infinite), that is, the input resistor is a high resistance, which helps the first field effect transistor device Q1 to provide a larger gain. i Apply input voltage V i ,like Fig.11 shown.

[0087] The drain of the second field effect transistor device Q2 is electrically connected to the first power supply terminal VDD1 and the base of the transistor device T1 respectively. Fig.11 In the illustrated embodiment, a current source I is provided between the drain of the second field effect transistor device Q2 and the first power supply terminal VDD1.

[0088] The emitter of the transistor device T1 is grounded, and the collector of the transistor device T1 is electrically connected to the second power supply terminal VDD2 and the radio frequency output terminal (RF OUT) respectively.

[0089] In this embodiment, the second field effect transistor device Q2 is configured as a cascade field effect transistor. In other embodiments, the second field effect transistor device Q2 is configured as a plurality of cascade field effect transistors. In this configuration, the following matching operations need to be performed in combination with specific circumstances. For example, impedance matching, specifically using capacitors, inductors and other matching networks to form Π-type, L-type, T-type; another example, gain matching, specifically adjusting the operating voltage and bias voltage of each stage of MOS tube; another example, load matching, specifically using inductors and capacitors for tuning. In addition, noise matching can also be performed, specifically using appropriate source impedance or inductors and capacitors to complete.

[0090] In this embodiment, the RF power amplifier circuit may further include a first capacitor C1, a first inductor L1, and a second capacitor C2. The first end of the first capacitor C1 is electrically connected to the collector of the transistor device T1 and the second power supply terminal VDD2, respectively, the second end of the first capacitor C1 is electrically connected to the first end of the first inductor L1, the second end of the first inductor L1 is electrically connected to the first end of the second capacitor C2 and the RF output terminal (RF OUT), respectively, and the second end of the second capacitor C2 is grounded. The first capacitor C1 is used to isolate direct current, and the second capacitor C2 is used to filter out specific frequency signals (such as noise). Fig.11 As shown, in this embodiment, the first field effect transistor device Q1 is an NMOS transistor, and the second field effect transistor device Q2 is an NMOS transistor. It should be noted that, in this embodiment, the first capacitor C1, the first inductor L1, and the second capacitor C2 are all externally disposed in the final stage unit 30. In other different embodiments, the first capacitor C1, the first inductor L1, and the second capacitor C2 may also be built into the final stage unit 30.

[0091] In other partial implementations, when the second field effect transistor device Q2 is configured as a plurality of cascade field effect transistors, that is, the drain of the second cascade field effect transistor (i.e., the second cascade MOS tube) is electrically connected to the source of the third cascade field effect tube (i.e., the third cascade MOS tube), the drain of the third cascade field effect tube is electrically connected to the source of the fourth cascade field effect tube (i.e., the fourth cascade MOS tube), the drain of the fourth cascade field effect tube is electrically connected to the source of the fifth cascade field effect tube (i.e., the fifth cascade MOS tube), and so on, the drain of the (N-1)th cascade field effect tube (i.e., the (N-1)th cascade MOS tube) is electrically connected to the source of the Nth cascade field effect tube (i.e., the Nth cascade MOS tube), and such a cascade method can be achieved by the following method: Fig. 6F Of course, as in the above embodiment, the drain of the first field effect transistor device Q1 (here the first cascade field effect transistor) is electrically connected to the source of the second field effect transistor device Q2 (here the second cascade field effect transistor), which can also be achieved by Fig. 6F This can be achieved in the manner shown.

[0092] The above is a detailed introduction to a method for preparing an RF power amplifier, an RF power amplifier structure and an RF power amplifier circuit provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing a radio frequency power amplifier, characterized in that: include: Providing a first wafer, on which a multi-stage cascade field effect transistor structure is formed, wherein the first wafer is a silicon-on-insulator wafer; Providing a second wafer, on which a silicon-germanium heterojunction bipolar transistor structure is formed, wherein the second wafer is a bulk silicon wafer; Bonding the multi-stage cascade field effect transistor structure to the silicon germanium heterojunction bipolar transistor structure to form an initial power amplifier structure; A metal wiring structure is formed on the initial power amplifier structure, and the metal wiring structure is electrically connected to the radio frequency input terminal and the radio frequency output terminal respectively to form a radio frequency power amplifier.

2. The preparation method according to claim 1, characterized in that The providing of a first wafer comprises: A semiconductor-on-insulator substrate is provided, wherein the semiconductor-on-insulator substrate comprises a first semiconductor substrate and a first semiconductor layer which are stacked, wherein the first semiconductor layer comprises a plurality of device regions, wherein the device regions are used to form field effect transistor devices; Performing ion implantation at a first position and a second position of each of the device regions, respectively, to form a well region located at each of the first positions and a doping region located at each of the second positions, wherein the well region and the doping region of the same device region have opposite doping types; forming a first polysilicon layer on a side of each well region away from the first semiconductor substrate, wherein the doping type of each first polysilicon layer is opposite to that of the corresponding well region; Depositing metal on the side of each of the doped regions and each of the first polysilicon layers away from the first semiconductor substrate to form a first metal silicide layer; Forming a first dielectric layer covering the first metal silicide layer and the first semiconductor layer, wherein the first dielectric layer has a first contact hole, the first contact hole penetrates the first dielectric layer and contacts the surface of the first metal silicide layer to connect the source, drain and gate of the field effect transistor device; A second dielectric layer is formed on a side of the first dielectric layer away from the first semiconductor substrate, and a first metal interconnection structure is formed in the second dielectric layer, wherein the first metal interconnection structure is used to electrically connect with the source, drain and gate of the field effect transistor device.

3. The preparation method according to claim 2, characterized in that: Before performing ion implantation at the first position and the second position of each of the device regions to form a well region at each of the first positions and a doping region at each of the second positions, the preparation method further includes: forming a first trench isolation region around the device region of the first semiconductor layer.

4. The preparation method according to claim 3, characterized in that: The first trench isolation region is also located between a first device region and a second device region of the first semiconductor layer, and the doping type of the doping region in the first device region is opposite to that of the doping region in the second device region.

5. The preparation method according to claim 2, characterized in that: Before forming the first polysilicon layer on the side of each well region away from the first semiconductor substrate, the preparation method further comprises: forming a gate oxide layer on the side of each well region away from the first semiconductor substrate.

6. The preparation method according to claim 1, characterized in that: The providing of the second wafer comprises: providing a second semiconductor substrate; forming a second semiconductor layer on the second semiconductor substrate, wherein a heavily doped collector layer is formed in the second semiconductor layer to obtain a collector of a silicon-germanium heterojunction bipolar transistor; forming a silicon germanium crystal layer covering the collector layer to obtain a base of the silicon germanium heterojunction bipolar transistor; forming a second polysilicon layer on the second semiconductor layer, wherein the second polysilicon layer has a pattern opening, and the pattern opening exposes a portion of the surface of the silicon germanium crystal layer; Depositing a third dielectric layer on the second polysilicon layer and the silicon germanium crystal layer, wherein a penetrating contact window is formed in the third dielectric layer, the contact window is filled with a third polysilicon layer, and the third polysilicon layer is in contact with the silicon germanium crystal layer, so as to obtain an emitter of the silicon germanium heterojunction bipolar transistor; forming a second metal silicide layer in contact with the second polysilicon layer and the third polysilicon layer; A fourth dielectric layer covering the second metal silicide layer and the third dielectric layer is formed, and a second contact hole penetrating the fourth dielectric layer is formed, wherein the second contact hole contacts the second metal silicide layer.

7. The preparation method according to claim 1, characterized in that: The forming of a metal wiring structure on the initial power amplifier structure comprises: forming a fifth dielectric layer on a side of the initial power amplifier structure facing away from the first semiconductor substrate; A metal wiring structure is formed within the fifth dielectric layer and the initial power amplifier structure, wherein the metal wiring structure is electrically connected to the gate terminal and the RF input terminal of the multi-stage cascade field effect transistor structure, and is electrically connected to the collector terminal and the RF output terminal of the silicon germanium heterojunction bipolar transistor.

8. A radio frequency power amplifier structure, characterized in that: The radio frequency power amplifier structure comprises: a first semiconductor substrate; A first semiconductor layer is located above the first semiconductor substrate, the first semiconductor layer includes a plurality of device regions, each of the device regions has a well region and a doped region, a first polysilicon layer is located above each of the well regions, and a first metal silicide layer is located above each of the doped regions and each of the first polysilicon layers; A first dielectric layer, located above the first semiconductor layer, the first dielectric layer covers the first metal silicide layer and the first semiconductor layer, the first dielectric layer has a first contact hole penetrating therethrough, the first contact hole contacts with a surface of the first metal silicide layer to connect the source, drain and gate of the field effect transistor device; A second dielectric layer, located above the first dielectric layer, the second dielectric layer having a first metal interconnect structure, and the first metal interconnect structure is electrically connected to the first contact hole; a fourth dielectric layer, located above the second dielectric layer, the fourth dielectric layer having a second metal silicide layer and a second contact hole therethrough, the second contact hole being used to electrically connect the second metal silicide layer and the first metal interconnect structure; a third polysilicon layer and a second polysilicon layer being respectively provided above the second metal silicide layer; the third polysilicon layer being used to form an emitter of a silicon-germanium heterojunction bipolar transistor; a second semiconductor layer, located above the fourth dielectric layer, the second semiconductor layer comprising a stacked silicon germanium crystal layer and a collector layer, the silicon germanium crystal layer is used to form a base of the silicon germanium heterojunction bipolar transistor, and the collector layer is used to form a collector of the silicon germanium heterojunction bipolar transistor; A fifth dielectric layer is located above the second semiconductor layer, and the fifth dielectric layer has a metal wiring structure, and the metal wiring structure is electrically connected to the gate terminal and the radio frequency input terminal of the field effect transistor device, and is electrically connected to the collector terminal and the radio frequency output terminal of the silicon germanium heterojunction bipolar transistor.

9. A radio frequency power amplifier circuit, characterized in that: The radio frequency power amplifier circuit comprises: An input unit, wherein the input unit is configured as a field effect tube common source amplifier, and the field effect tube common source amplifier includes a first field effect tube device; An intermediate unit, the intermediate unit is coupled to the input unit, the intermediate unit is configured as a field effect transistor common-gate amplifier, the field effect transistor common-gate amplifier includes a second field effect transistor device; the second field effect transistor device is configured as at least one cascade field effect transistor; A final unit is coupled to the intermediate unit, and includes a triode device, wherein the triode device is a silicon germanium heterojunction bipolar transistor.

10. The radio frequency power amplifier circuit according to claim 9, characterized in that: The source of the first field effect transistor device is grounded, the drain of the first field effect transistor device is electrically connected to the source of the second field effect transistor device, the gate of the first field effect transistor device is electrically connected to an input resistor, and the resistance of the input resistor is greater than a preset resistance; The drain of the second field effect transistor device is electrically connected to the first power supply terminal and the base of the triode device respectively; The emitter of the triode device is grounded, and the collector of the triode device is electrically connected to the second power supply terminal and the radio frequency output terminal respectively.

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