Semiconductor device, manufacturing method thereof and storage system

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof, and a storage system, and the manufacturing method comprises the steps: forming a semiconductor structure in a wafer, including forming a first device and a first cutting channel which is adjacent to the first device in a first direction and extends along a second direction, and the first direction is intersected with the second direction; a blocking structure extending in the second direction is formed in the portion, adjacent to the first device, in the first cutting channel. According to the invention, the fracture probability of the cutting channel is reduced, the chip yield is improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Wafers are the basic raw materials for manufacturing semiconductor devices. Each wafer can be cut into multiple chips, and each chip can be made into a chip after packaging, testing and other processes.

[0003] In the chip manufacturing process, adjacent chips on a wafer are cut to obtain independent bare chips, which are then packaged and tested to obtain independent chips. However, as the area of ​​a single chip decreases, the chip manufacturing process needs to be improved. Summary of the invention

[0004] The present application provides a semiconductor device and a manufacturing method thereof, and a storage system, which can increase chip yield and reduce manufacturing costs.

[0005] The present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Forming a semiconductor structure in a wafer, including forming a first device and a first scribe line adjacent to the first device in a first direction and extending along a second direction, the first direction intersecting the second direction;

[0007] A blocking structure extending along the second direction is formed at a portion of the first scribe line adjacent to the first device.

[0008] In a second aspect, the present application further provides a semiconductor device, comprising:

[0009] A wafer comprising a plurality of semiconductor structures, wherein the semiconductor structures include a first device and a first dicing path adjacent to the first device in a first direction and extending along a second direction, wherein the first direction intersects the second direction; and

[0010] A blocking structure extends along the second direction and is located at a portion of the first cutting street adjacent to the first device.

[0011] In a third aspect, the present application further provides a storage system, comprising: a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory comprises the semiconductor device described in the second aspect.

[0012] The present application utilizes the available space in the first cutting path to form a barrier structure spaced apart between adjacent first devices in the first direction, thereby preventing Cracks (cracks or fractures) from spreading to the first device, effectively blocking the expansion of cracks, and improving the yield and reliability of effective chips, thereby increasing chip production and reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 is a flow chart of a semiconductor device manufacturing method provided in an embodiment of the present application;

[0015] Figures 2 to 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by some embodiments of the present application;

[0016] Figure 4 is a schematic structural diagram of a blocking structure provided in an embodiment of the present application;

[0017] Figure 5 is an enlarged schematic diagram of a blocking structure including a groove provided in an embodiment of the present application;

[0018] Figure 6 is a structural schematic diagram of a first device and a blocking structure provided in an embodiment of the present application;

[0019] Figure 7 is another flow chart of the semiconductor device manufacturing method provided in the embodiment of the present application;

[0020] Figure 8 is another flow chart of the semiconductor device manufacturing method provided in the embodiment of the present application;

[0021] Fig. 9 It is a curve diagram of the cutting road size and the number of effective devices provided in the embodiment of the present application;

[0022] Fig.10 is another curve diagram of the cutting road size and the number of effective devices provided in the embodiment of the present application;

[0023] Fig.11 is another curve diagram of the cutting road size and the number of effective devices provided in the embodiment of the present application;

[0024] Fig.12It is a schematic diagram of the structure of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0029] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0030] Before cutting each wafer, it is necessary to determine the maximum number of complete chips that can be cut from the wafer in order to increase chip production and reduce manufacturing costs. In the chip manufacturing process, a cutting path is formed between two adjacent chips on the wafer so that the wafer can be cut along the cutting path to obtain an independent bare crystal, and then an independent chip is obtained through packaging and testing processes. And all electrical characteristics of TSK (Test-Key, test key area) and process marks (MASK) are placed in the cutting path to achieve testing and positioning of the wafer. However, as the area of ​​a single chip decreases, the density of chips on the wafer increases. At this time, the area loss caused by the cutting path is becoming more and more important. Therefore, reducing the occupied area of ​​the cutting path can increase the number of effective chips obtained by wafer cutting. However, since the cutting path is in the shape of a long strip, the stress effect will inevitably be concentrated on the cutting path when the wafer is cut, resulting in cracks (cracks or breaks) in the cutting path.

[0031] In the embodiments of the present application, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees. For example, in some embodiments of the present application, the first direction is set as the Y direction and the second direction is set as the X direction.

[0032] To improve the above problems, refer to Figures 1 to 7 As shown, some embodiments of the present application provide a semiconductor device 100 and a manufacturing method thereof, and a storage system 300. The present application utilizes the existing free space of the first cutting path 31 to form a barrier structure 20 disposed between adjacent first devices 10 in the first direction Y, so that cracks (cracks or breaks) in the first cutting path 31 can be prevented from spreading or extending to the first device 10, thereby effectively blocking the expansion of cracks, improving the yield and reliability of effective chips, thereby increasing chip production and reducing manufacturing costs.

[0033] See also Figures 1 to 3 As shown, Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device 100 provided in some embodiments of the present application is provided. Figures 2 to 3 The present invention provides a schematic diagram of the structure of a semiconductor device 100 during the manufacturing process. Figure 1 As shown, the production method comprises the steps of:

[0034] S100, forming a semiconductor structure 101 in a wafer 1, including forming a first device 10 and a first dicing street 31 adjacent to the first device 10 in a first direction Y and extending along a second direction X, wherein the first direction Y intersects the second direction X;

[0035] S200 , forming a blocking structure 20 extending along the second direction X at a portion of the first dicing street 31 adjacent to the first device 10 .

[0036] In some specific examples, such as Figure 2 and Figure 3 As shown, the semiconductor device 100 includes a wafer 1 and a semiconductor structure array, a first scribe line 31 and a blocking structure 20 located on the wafer 1. Figure 2 As shown, a semiconductor device array is formed on a wafer 1, each semiconductor device array includes a plurality of semiconductor structures 101 arranged in an array, each semiconductor structure 101 includes a first device 10 and at least one first cutting street 31, and the first cutting street 31 is adjacent to the first device 10 in a first direction Y, that is, the first device 10 is adjacent to and contacted with at least one first cutting street 31 in the first direction Y. In addition, each first cutting street 31 extends along a second direction X.

[0037] In some specific examples, a blocking structure 20 extending along the second direction X is formed in the first cutting street 31, such as Figure 3 As shown, each semiconductor structure 101 further includes at least one blocking structure 20 located in the first scribe line 31 and adjacent to the first device 10 in the first direction Y, and the blocking structure 20 extends along the second direction X. Figure 4 The blocking structure 20 shown is Figure 3 FIG. 2 is an enlarged schematic diagram of the blocking structure 20 .

[0038] In an embodiment of the present application, a plurality of first devices 10 arranged in an array are first formed on a wafer 1, and then a dry etching process is used to remove a portion of the wafer 1 adjacent to the first device 10 in a first direction Y to form a first cutting street 31 adjacent to the first device 10 in the first direction Y, and then, a dielectric material is deposited in the first cutting street 31 to form a blocking structure 20a adjacent to the plurality of first devices 10 in the first direction Y.

[0039] In some embodiments, the dielectric material includes any one of polysilicon, silicon nitride, silicon oxide, aluminum oxide, or any combination thereof.

[0040] In some embodiments, the deposition method can be chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD), etc.

[0041] In some embodiments, since the stresses on the first cutting paths 31 between adjacent semiconductor devices 101 are different when cutting, cracks are easily generated during cutting to extend to the first devices 10 adjacent to the first cutting paths 31. Therefore, the present application interrupts the blocking structures 20a adjacent to the first devices 10 in the first direction Y, that is, Figure 3 The blocking structure 20a shown is etched along the second direction to form multiple blocking structures 20 adjacent to a first device 10 in the first direction Y, and the extension dimension of each blocking structure 20 along the second direction X is greater than or equal to the extension dimension of the first device 10 adjacent to the blocking structure 20 along the second direction X.

[0042] In some specific examples, the existing free space of the first cutting street 31 is utilized to form a barrier structure 20 spaced apart between adjacent first devices 10 in the first direction Y. There is no need to additionally expand the size of the first cutting street 31 to form the barrier structure 20. Since the occupied area of ​​the first cutting street 31 does not increase, compared with the method of increasing the size of the first cutting street 31 to prevent cracks generated during cutting from extending to the first device 10, the barrier structure 20 is formed in the existing free space of the first cutting street 31. This can increase chip yield and reduce manufacturing costs without reducing the density of the first devices 10 on the wafer 1. In addition, the present application sets a blocking structure 20 at a position adjacent to the first device 10 in the first direction Y. Since the blocking structure 20 is located between the first cutting path 31 and the first device 10 in the first direction Y, the blocking structure 20 can prevent the crack (crack or break) in the first cutting path 31 from spreading or extending to the first device 10, thereby effectively blocking the expansion of the crack and reducing the number of first devices 10 damaged due to crack propagation, thereby increasing the number of independent and undamaged first devices 10 obtained by cutting, and improving the yield and reliability of effective chips.

[0043] In some embodiments, the step of forming the blocking structure 20 extending along the second direction X further includes: Figure 4 and Figure 5 As shown, a plurality of annular structures 201 extending along the second direction X are formed in the first cutting path 31 ; a plurality of slots 21 spaced apart along the second direction X are formed in the annular structure 201 , and the slots 21 extend along the first direction Y.

[0044] In some specific examples, Figure 2 The deposited dielectric material in the first cutting street 31 forms a Figure 4 The annular structure 201 is then removed to form a Figure 5The plurality of slots 21 are arranged at intervals along the second direction X and extend along the first direction Y. Figure 5 Before the groove 21 is formed, a patterned first mask layer (not shown) is formed on the surface of the blocking structure 20 along the second direction X, and the first mask layer has a plurality of openings (not shown), and the openings are used to form the groove 21. In this way, an opening corresponding to the groove 21 can be formed in the patterned first mask layer, and the opening exposes the position of the groove 21 formed by the subsequent etching process, that is, the vertical projection of the opening on the surface of the blocking structure 20 along the second direction X can at least substantially overlap with the position of the groove 21. Then, the position of the blocking structure 20 corresponding to the opening of the first mask layer can be etched by photolithography (PH) or dry etching (ET), and the portion of the blocking structure 20 located below the opening is removed to form the groove 21. Therefore, in the embodiment of the present application, by setting the first mask layer, the etching position of the groove 21 can be quickly and accurately determined, which facilitates the etching process of the blocking structure 20, and then a plurality of grooves 21 arranged at intervals along the second direction X and extending along the first direction Y are formed in the blocking structure 20.

[0045] It should be noted that a plurality of grooves 21 can be formed on the blocking structure 20 at the same time, that is, the first mask layer can form a plurality of openings corresponding to the plurality of grooves 21, and the positions of the plurality of openings correspond to the positions of the plurality of grooves 21 formed subsequently. In the embodiments of the present application, there is no specific limitation on the number, size and arrangement of the grooves 21. Figure 5 The slots 21 shown are only examples and are not intended to limit the positions and number of the slots 21 .

[0046] In some specific examples, in some embodiments, the etching size of the groove 21 along the first direction Y can be controlled by etching process parameters (e.g., etching time, gas flow, ratio, pressure, temperature, etc.). For example, under a constant etching rate, the longer the etching time, the deeper the groove 21 formed in the first direction Y. The groove 21 is formed by etching away a portion of the blocking structure 20 along the first direction Y through a plurality of openings in the first mask layer corresponding to the plurality of grooves 21, and the groove 21 formed by etching along the first direction Y does not expose the adjacent first device 10. The etching method can be dry etching or wet etching, for example, an electron beam lithography process, a plasma etching process, or a reactive ion etching process.

[0047] In the present application embodiment Figure 5The multiple slots 21 formed as shown are arranged at intervals along the second direction X, and a partition structure 22 for spacing two adjacent slots 21 is provided between the slots 21 formed in the blocking structure 20. In this way, the present application designs the originally long strip-shaped blocking structure 20 to arrange the slots 21 at intervals along the second direction X, that is, the slots 21 and the partition structure 22 are alternately arranged along the second direction X. Since the slots 21 and the partition structure 22 are arranged in an alternating manner, when stress mismatch occurs in the first cutting path 31, the degree of concentrated stress release can be reduced, and the stress can be effectively released through the multiple slots 21 and the nearby partition structure 22. In this way, the influence of stress release on the first cutting path 31 can be alleviated, and the first cutting path 31 can be prevented from being twisted and deformed, so that the first cutting path 31 is not easy to crack, and the crack (crack or fracture) in the first cutting path 31 can be further prevented from spreading or extending to the first device 10 adjacent to the first cutting path 31, thereby effectively blocking the expansion of cracks and improving the yield and reliability of effective chips.

[0048] In some examples, a semiconductor structure 101 may include a first device 10 and at least one first scribe line 31 and at least one second scribe line 32. If the semiconductor structure 101 is located at a boundary or edge of the wafer 1, the semiconductor structure 101 may include a first device 10 and a first scribe line 31 and a second scribe line 32. Figure 2 and Figure 3 As shown, if the semiconductor structure 101 is located in the middle area of ​​the wafer 1, that is, not at the edge, then the semiconductor structure 101 may include a first device 10 and two first scribe lines 31 and two second scribe lines 32. In the first direction Y, two adjacent semiconductor structures 101 may share one first scribe line 31, such as Figure 2 As shown, a semiconductor structure 101c and a semiconductor structure 101d adjacent to the semiconductor structure 101c in the first direction Y can share a first scribe line 31. Similarly, two adjacent semiconductor structures 101 in the second direction X can share a second scribe line 32. Figure 2 As shown, a semiconductor structure 101 a and a semiconductor structure 101 b adjacent to the semiconductor structure 101 a in the second direction X may share a second scribe line 32 .

[0049] In some embodiments, the step of forming the semiconductor structure 101 includes: forming a second cutting street 32 ​​adjacent to the first device 10 in the second direction X and extending along the first direction Y, and the size of the first cutting street 31 along the first direction Y is larger than the size of the second cutting street 32 ​​along the second direction X.

[0050] In some specific examples, in the embodiments of the present application, a plurality of first devices 10 arranged in an array are first formed on the wafer 1, and then a dry etching process is used to remove the portion of the wafer 1 adjacent to the first device 10 in the first direction Y to form a first scribe line 31 adjacent to the first device 10 in the first direction Y, and then a dielectric material is deposited in the first scribe line 31 to form a blocking structure 20a adjacent to the plurality of first devices 10 in the first direction Y. Figure 2 and Figure 3 As shown, a second dicing street 32 ​​may be formed on the wafer 1, which is adjacent to the first device 10 in the second direction X and extends in the first direction Y. Each semiconductor device array includes a plurality of semiconductor structures 101 arranged in an array, and each semiconductor structure 101 includes a first device 10, at least one first dicing street 31 and at least one second dicing street 32. In addition, the first dicing street 31 is adjacent to the first device 10 in the first direction Y, that is, the first device 10 is adjacent to and in contact with at least one first dicing street 31 in the first direction Y, and the second dicing street 32 ​​is adjacent to the first device 10 in the second direction X, that is, the first device 10 is adjacent to and in contact with at least one second dicing street 32 ​​in the second direction X. In addition, each first dicing street 31 extends along the second direction X, and each second dicing street 32 ​​extends along the first direction Y.

[0051] In some specific examples, TSK and MASK are placed at the first cutting street 31 and the second cutting street 32. It should be noted that Figure 2 and Figure 3 As shown, the size of the first cutting street 31 in the first direction Y is greater than the size of the second cutting street 32 ​​in the second direction X, so that there is a spare space for the size of the first cutting street 31 in the first direction Y, so that the following can be set in the spare space Figure 3 The blocking structure 20 shown is adjacent to the first device 10 in the first direction Y, so as not to increase the occupied area of ​​the first cutting road 31. It is possible to change the floorplan layout of the wafer 1 without reducing DPW (Dies Per Wafer, the number of wafers that can be cut). By adding the blocking structure 20 in the vacant space of the first cutting road 31, the first device 10 can be reinforced and protected to prevent the crack (crack or break) in the first cutting road 31 from spreading or extending to the first device 10 adjacent to the first cutting road 31, thereby effectively blocking the expansion of the crack and improving the yield and reliability of the effective chip.

[0052] In some embodiments, Figure 7 As shown, the step of forming the semiconductor structure 101 includes:

[0053] S010, obtaining a plurality of preselected cutting sizes according to the wafer size and the first device size;

[0054] S020, determining the largest pre-selected cutting size among the plurality of pre-selected cutting sizes as a target cutting size, wherein the target cutting size increases or keeps the number of effective devices after cutting unchanged;

[0055] S030. Adjust the semiconductor layout according to the target cutting size, the wafer size, and the first device size.

[0056] In some specific examples, the shape of the wafer 1 may include a rectangle and a circle, the first device 10 may include a chip or a bare die, and the shape of the first device 10 includes a rectangle. If the shape of the wafer 1 is a circle, the radius of the wafer 1 may be obtained to obtain the wafer size, and if the shape of the wafer 1 is a rectangle, the length and width of the wafer 1 may be obtained to obtain the wafer size. Similarly, the length and width of the first device 10 may be obtained to obtain the size of the first device 10.

[0057] Specifically, the preselected cutting size is actually a cutting size that can meet the wafer size and the first device size, and the preselected cutting size includes a first preset size of the first cutting street 31 along the first direction Y, and a second preset size of the second cutting street 32 ​​along the second direction X. The target cutting size is a maximum preselected cutting size that increases or keeps the number of effective first devices generated by cutting according to a plurality of preselected cutting sizes.

[0058] For example, multiple pre-selected cutting sizes include K1, K2 and K3. The effective numbers of first devices produced by processing according to the pre-selected cutting sizes K1, K2 and K3 are N1, N2 and N3 respectively. If N2>N1>N3, then the pre-selected cutting size K2 can be determined as the target cutting size. Among them, the embodiment of the present application can filter out the pre-selected cutting size that meets the wafer size and the first device size from the historical record data. The historical data record may include information such as wafer size, chip size, and cutting path size. The embodiment of the present application can also be designed and planned by engineers according to the wafer size and the first device size.

[0059] In some examples, the target cut size is a preselected cut size at which the number of effective devices increases the most after cutting or the number of effective devices remains unchanged.

[0060] In some examples, the target cutting size is obtained by first screening out the pre-selected cutting sizes with the largest increase in the number of valid devices after cutting or keeping the number of valid devices unchanged. The largest pre-selected cutting size can be fine-tuned to increase the preset cutting size. If the number of valid devices does not decrease or increases after fine-tuning, the largest pre-selected cutting size after fine-tuning can be used as the target cutting size.

[0061] In some specific examples, such as Figure 8 As shown, it is assumed that a first preset size in the preselected cutting size along the first direction Y is 60um to 80um, and a second preset size in the preselected cutting size along the second direction X is 60um to 80um.

[0062] Assume that the second preset size along the second direction X in the preselected cutting size is 75 um and remains unchanged. Fig.10 As shown, the number of effective devices does not change substantially when the first preset size along the first direction Y in the preselected cutting size ranges from 72.5um to 80um. Then, the second target size in the target cutting size can be selected to be equal to the second preset size, i.e., 75um, and the first target size in the target cutting size can be equal to the maximum value of the first preset size in the first direction Y, i.e., 80um, under the premise that the number of effective devices remains unchanged. When the first target size is 80um and the second target size is 75um, the number of effective devices N(75,80)=1285. Compared with the number of effective devices N(75,75)=1287 when the first target size is 75um and the second target size is 75um, although the number of effective devices is reduced by a small amount, the larger the cutting road size is during cutting, the smaller the probability of cutting to the first device, and the higher the yield of the first device. In addition, because the blocking structure 20 prevents the crack from extending to the first device 10 during cutting, the yield is further improved. Therefore, the newly added area of ​​the cutting road does not cause loss to the number of effective devices, but greatly improves the yield of the bare crystal, thereby indirectly improving the number of effective devices.

[0063] Assume that the first preset size along the first direction Y in the preselected cutting size is 75um and remains unchanged. Fig.11As shown, the number of effective devices does not change substantially when the second preset size along the second direction X in the preselected cutting size is from 72.5um to 80um. Then, the second target size in the target cutting size can be selected to be equal to the second preset size, i.e., 80um, and the first target size in the target cutting size can be equal to the maximum value of the first preset size in the first direction Y, i.e., 80um, under the premise that the number of effective devices remains unchanged. When the first target size is 75um and the second target size is 80um, the number of effective devices N(80,75)=1287. Compared with the number of effective devices N(75,75)=1289 when the first target size is 75um and the second target size is 75um, the number of effective devices does not increase. However, when cutting, the larger the cutting road size, the smaller the probability of cutting to the first device, and the higher the yield of the first device. In addition, because the blocking structure 20 prevents the crack from extending to the first device 10 during cutting, the yield is further improved. Therefore, the newly added area of ​​the cutting road does not cause loss to the number of effective devices, but greatly improves the yield of the bare crystal, thereby indirectly improving the number of effective devices.

[0064] In some embodiments, the target cutting size includes a first target size D1 along the first direction Y and a second target size D2 along the second direction X; Figure 8 As shown, the step of adjusting the semiconductor layout includes:

[0065] S031, setting a size of the first cutting street 31 along the first direction Y according to the first target size, and setting a size of the second cutting street 32 ​​along the second direction X according to the second target size;

[0066] S032. Setting the arrangement position of the first device 10 according to the target cutting size, the wafer size and the first device size; wherein two adjacent first devices 10 along the first direction Y are isolated by the first cutting path 31, and two adjacent first devices 10 along the second direction X are isolated by the second cutting path 32.

[0067] In some specific examples, the target cutting size includes a first target size D1 along the first direction Y and a second target size D2 along the second direction X, such that Figure 2 and Figure 3As shown, the first target size is set as the size of the first cutting street 31 along the first direction Y, and the second target size is set as the size of the second cutting street 32 ​​along the second direction X. Then, the arrangement position of the first device 10 on the wafer 1 is set according to the target cutting size, the wafer size and the first device size, so that two adjacent first devices 10 in the first direction Y are isolated by the first cutting street 31, and two adjacent first devices 10 in the second direction X are isolated by the second cutting street 32.

[0068] By screening the target cutting size, the present application can achieve the situation where the value of DPW (Dies Per Wafer, the number of wafers 1 that can be cut or the number of chips that can be cut) is not changed by adjusting the size of the cutting lanes 30 in the semiconductor layout, that is, increasing the size of all or part of the cutting lanes, for example, increasing the size of part or all of the first cutting lanes 31 in the first direction Y, or increasing the size of part or all of the second cutting lanes 32 in the second direction X. When the wafer 1 is cut, the larger the size of the first cutting lane 31 in the first direction Y and the size of the second cutting lane 32 in the second direction X, the smaller the probability of cutting the first device 10, and the higher the yield of the chips produced by cutting the wafer 1. In this way, the number of effective chips produced by cutting the wafer 1 can be increased, the waste of the wafer 1 can be reduced, and the chip production cost can be saved.

[0069] In some embodiments, the dimension ΔD of the blocking structure 20 along the first direction Y is equal to half of the difference between the first target dimension D1 of the first cutting line 31 along the first direction Y and the preset cutting dimension L1, and the preset cutting dimension L1 is equal to the second target dimension D2 of the second cutting line 32 along the second direction X.

[0070] In some specific examples, such as Figure 3 and Figure 6 As shown, the size of the blocking structure 20 along the first direction Y is Wherein, L1 is a second target size D2 of the second cutting street 32 ​​along the second direction X.

[0071] In some specific examples, continuing with the above embodiment, assuming that the first target size, i.e., the first target size D1 of the first cutting street 31 along the first direction Y is 80 um, and the second target size, i.e., the second target size D2 of the second cutting street 32 ​​along the second direction X is 75 um, the size of the blocking structure along the first direction Y is

[0072] In some embodiments, the wafer 1 includes any one of an array wafer, a CMOS wafer, a carrier wafer, and a device wafer.

[0073] The target cutting size selected in the present application not only maximizes the increase in the number of effective devices after cutting or keeps the number of effective devices unchanged, but is also the largest pre-selected cutting size among multiple pre-selected cutting sizes. In this way, without changing the number of effective devices or even increasing the number of effective devices, chip cutting through the cutting road 30 with an increased size can reduce the probability of cutting the first device 10 during the cutting process, thereby improving the yield. Moreover, a blocking structure 20 can be added to the idle area of ​​the first cutting road 31 after the size is increased. The blocking structure 20 can prevent the crack (crack or break) in the first cutting road 31 from spreading or extending to the first device 10 adjacent to the first cutting road 31, thereby effectively blocking the expansion of the crack and improving the yield and reliability of the effective chip.

[0074] The present application also provides a semiconductor device 100, including:

[0075] A wafer 1, wherein the wafer 1 comprises a plurality of semiconductor structures 101, wherein the semiconductor structure 101 comprises a first device 10 and a first dicing street 31 located in a first direction Y adjacent to the first device 10 and extending along a second direction X, wherein the first direction Y intersects the second direction X; and

[0076] The blocking structure 20 extends along the second direction X and is located at a portion of the first scribe line 31 adjacent to the first device 10 .

[0077] In some embodiments, the blocking structure 20 includes a plurality of slots 21 arranged at intervals along the second direction X and extending along the first direction Y.

[0078] In some embodiments, the semiconductor structure 101 further includes: a second scribe line 32 adjacent to the first device 10 in the second direction X and extending in the first direction Y;

[0079] The dimension of the first cutting street 31 along the first direction Y is greater than the dimension of the second cutting street 32 ​​along the second direction X.

[0080] In some embodiments, the dimension ΔD of the blocking structure 20 along the first direction Y is equal to half of the difference between the first target dimension D1 of the first cutting line 31 along the first direction Y and the preset cutting dimension L1, and the preset cutting dimension L1 is equal to the second target dimension D2 of the second cutting line 32 along the second direction X.

[0081] In some embodiments, the wafer 1 includes any one of an array wafer, a CMOS wafer, a carrier wafer, and a device wafer.

[0082] The semiconductor device 100 in the embodiment of the present application is manufactured by adopting the manufacturing method of the semiconductor device 100 described above. Therefore, the specific description of the structure and effect of the semiconductor device 100 in the embodiment of the present application can be found in the corresponding embodiments S100 to S200 above, which will not be repeated here.

[0083] Based on the above-mentioned semiconductor device 100 and its manufacturing method, refer to Fig.12 As shown, the embodiment of the present application further provides a memory 320, and the memory 320 includes:

[0084] Array storage structure 321, the array storage structure 321 includes: Figures 2 to 6 The semiconductor device 100 of the illustrated embodiment; and

[0085] The peripheral circuit 322 is connected to the array storage structure 321 to control the bias voltage of the array storage structure 321 .

[0086] Based on the above-mentioned semiconductor device 100 and its manufacturing method, refer to Fig.12 As shown, the embodiment of the present application further provides a storage system 300, the storage system 300 includes a memory 320 and a controller coupled to the memory 320, the memory includes Figures 2 to 6 In the semiconductor device 100 described in the corresponding embodiment, the controller is used to control the memory to perform data writing and reading operations.

[0087] Specifically, Fig.12As shown, the storage system 300 includes a controller 310 and one or more memories 320, wherein the memory 320 (3D NAND Flash) includes an array storage structure 321 (Array) and a peripheral circuit 322 (PeripheryCircuit), wherein the array storage structure 321 includes any of the semiconductor devices 100 described above. The storage system 300 can communicate with the host 400 through the controller 310, wherein the controller 310 can be connected to the one or more memories 320 via channels in the one or more memories 320. Each memory 320 can be managed by the controller 310 via channels in the memory 320.

[0088] Specifically, the array storage structure 321 is used to store information, and the peripheral circuit 322 can be located above or below the array storage structure 321, or can be located around the array storage structure 321, and the peripheral circuit 322 is used to control the corresponding array storage structure 321. In addition, the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 100 of the embodiment of the present application can be a memory 320, which can be a part of a peripheral memory, without special limitation.

[0089] The semiconductor device 100 and its manufacturing method, memory and storage system 300 provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Forming a semiconductor structure in a wafer, including forming a first device and a first scribe line adjacent to the first device in a first direction and extending along a second direction, the first direction intersecting the second direction; A blocking structure extending along the second direction is formed at a portion of the first scribe line adjacent to the first device.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a blocking structure extending along the second direction further comprises: forming a plurality of annular structures extending along the second direction in the first cutting path; A plurality of slots spaced apart along the second direction are formed in the annular structure, and the slots extend along the first direction.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a semiconductor structure includes forming a second scribe line adjacent to the first device in the second direction and extending along the first direction, wherein a size of the first scribe line along the first direction is greater than a size of the second scribe line along the second direction.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The step of forming a semiconductor structure includes: Obtaining a plurality of preselected cutting sizes according to the wafer size and the first device size; Determine the largest pre-selected cutting size among the plurality of pre-selected cutting sizes as a target cutting size, wherein the target cutting size increases or keeps the number of effective devices after cutting unchanged; The semiconductor layout is adjusted according to the target cutting size, the wafer size and the first device size.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The target cutting size includes a first target size along the first direction and a second target size along the second direction; The step of adjusting the semiconductor layout comprises: Setting a size of the first cutting path along the first direction according to the first target size, and setting a size of the second cutting path along the second direction according to the second target size; The arrangement position of the first device is set according to the target cutting size, the wafer size and the first device size; wherein two adjacent first devices along the first direction are isolated by the first cutting path, and two adjacent first devices along the second direction are isolated by the second cutting path.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The size of the blocking structure along the first direction is equal to half of the difference between a first target size of the first cutting path along the first direction and a preset cutting size, and the preset cutting size is equal to a second target size of the second cutting path along the second direction.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that: The wafer includes any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer.

8. A semiconductor device, characterized in that: include: A wafer comprising a plurality of semiconductor structures, wherein the semiconductor structures include a first device and a first dicing path adjacent to the first device in a first direction and extending along a second direction, wherein the first direction intersects the second direction; and A blocking structure extends along the second direction and is located at a portion of the first cutting street adjacent to the first device.

9. The semiconductor device according to claim 8, characterized in that The blocking structure includes a plurality of slots spaced apart along the second direction and extending along the first direction.

10. The semiconductor device according to claim 9, characterized in that The semiconductor structure further includes: a second scribe line adjacent to the first device in the second direction and extending along the first direction; Wherein, a size of the first cutting street along the first direction is greater than a size of the second cutting street along the second direction.

11. The semiconductor device according to claim 10, characterized in that The size of the blocking structure along the first direction is equal to half of the difference between a first target size of the first cutting path along the first direction and a preset cutting size, and the preset cutting size is equal to a second target size of the second cutting path along the second direction.

12. The semiconductor device according to any one of claims 8 to 11, characterized in that: The wafer includes any one of an array wafer, a CMOS wafer, a carrier wafer and a device wafer.

13. A storage system, characterized in that: include: A controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes the semiconductor device according to any one of claims 8 to 12.

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