Encapsulated WCSP with thermal pads for efficient heat dissipation

Abstract

The invention relates to an encapsulated WCSP with thermal pads for efficient heat dissipation. In some examples, a wafer chip size package (WCSP) (104) includes a semiconductor die (200) having a device side (204) in which circuitry is formed and a non-device side (206) opposite the device side; a solder bump (212) electrically coupled to the circuitry; and a molding compound (208) in contact with the device side, the solder bump, and four lateral sides of the semiconductor die. The package also includes a thermal pad (216) in contact with the non-device side of the semiconductor die and the molding compound.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor chips are typically housed inside a semiconductor package that protects the chip from harmful environmental influences such as heat, moisture, and debris. The packaged chip communicates with electronic devices outside the package via conductive members (e.g., leads) exposed to the surface of the package. Within the package, the chip can be electrically coupled to the conductive member using any suitable technology. One such technology is flip chip technology, in which the semiconductor chip (also called a "die") is flipped so that the device side of the chip (where the circuit system is formed) faces downward. The device side is coupled to the conductive member using, for example, solder bumps. Another technology is wire bonding technology, in which the device side of the semiconductor chip is oriented upward and coupled to the conductive member using bonding wires. Summary of the invention

[0003] In some examples, a wafer chip scale package (WCSP) includes: a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side; solder bumps electrically coupled to the circuitry; and a molding compound in contact with the device side, the solder bumps, and four lateral sides of the semiconductor die. The package also includes a thermal pad in contact with the non-device side of the semiconductor die and the molding compound.

[0004] In some examples, a method for manufacturing a semiconductor device includes positioning a solder bump on a device side of a semiconductor wafer, the device side having circuitry formed therein. The method also includes cutting through a thickness of the semiconductor wafer to produce portions of first and second grooves, and applying a molding compound to the device side, the solder bump, and the portions of the first and second grooves. The method also includes back grinding the semiconductor wafer to reduce a thickness of the semiconductor wafer, the back grinding producing first and second semiconductor dies. The method includes: coupling a thermal pad to a first non-device side of the first semiconductor die and a second non-device side of the second semiconductor die; separating the first and second semiconductor dies to produce a wafer chip scale package (WCSP); coupling a thermal interface material to the thermal pad of the WCSP; and coupling a heat sink to the thermal interface material. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an electronic device containing an encapsulated wafer chip scale package (EWCSP) according to various examples.

[0006] Figure 2Ais a cross-sectional view of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples.

[0007] Figure 2B is a top-down view of an EWCSP including a thermal pad, thermal interface material (TIM), and heat sink according to various examples.

[0008] Figure 2C is a perspective view of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples.

[0009] Figure 3A is a cross-sectional view of an EWCSP including a thermal interface material (TIM) and a heat sink according to various examples.

[0010] Figure 3B is a top-down view of an EWCSP including a thermal interface material (TIM) and a heat sink according to various examples.

[0011] Figure 3C is a perspective view of an EWCSP including a thermal interface material (TIM) and a heat sink according to various examples.

[0012] Figures 4A1 to 4I is a process flow for fabricating an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples.

[0013] Figure 5 is a flow chart of a process for fabricating an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples.

[0014] Figures 6A1 to 6H is a process flow for fabricating an EWCSP including a thermal interface material (TIM) and a heat sink according to various examples.

[0015] Figure 7 is a flow chart of a process for fabricating an EWCSP including a thermal interface material (TIM) and a heat spreader according to various examples.

[0016] Figure 8 is a graph depicting the relative mechanical stability provided by an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink, according to various examples.

[0017] Fig. 9 is a graph depicting relative die stress experienced by an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat spreader under different environmental conditions according to various examples.

[0018] Fig.10is a graph depicting relative solder bump bridging risk of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples.

[0019] Fig.11 is a graph depicting relative solder bump bridging risk of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. DETAILED DESCRIPTION

[0020] During the chip manufacturing process, circuits are formed on semiconductor (e.g., silicon) wafers in a manufacturing facility. The wafers are then singulated (or "diced") to produce individual dies, each with its own circuitry. In some cases, the dies are then packaged, for example, using a lead frame, wire bonds, and a molding compound. However, in other cases, such as in wafer-level packaging, such packaging elements are applied to the wafer before the wafer is singulated.

[0021] A chip scale package (CSP) is a package with a relatively small package area to die area ratio. By some non-limiting definitions, a CSP has an area no greater than 1.2 times the die, and the package must be a single die, direct surface mountable package. A wafer level chip scale package (WCSP) is a CSP whose package components are applied to the wafer before the wafer is singulated. WCSP is advantageous because it enables enhanced design flexibility, reduced manufacturing costs, and reduced overall size relative to conventional leaded packages such as dual in-line packages (e.g., with gull-wing leads). For at least these reasons, such packages are advantageous and are often used in a variety of industries, including the automotive industry.

[0022] Some WCSPs are encapsulated using molding compounds, and these WCSPs are referred to as encapsulated WCSPs. In an encapsulated WCSP, circuitry is formed in the device side of the die, and the circuitry is coupled to solder bumps or balls through a network of metal members, which may be referred to as a redistribution layer (RDL). All sides of the die and the RDL are encapsulated by the molding compound. The encapsulated WCSP can then be mounted to a surface, such as a printed circuit board (PCB), by connecting the solder bumps to electrical contacts on the PCB.

[0023] During operation, the die within the encapsulated WCSP (hereafter EWCSP) generates heat. The heat follows the path of least resistance, which in the case of the EWCSP is through the RDL, solder bumps, and to the PCB to which the EWCSP is coupled. Heat accumulation on the PCB and in the EWCSP can cause electrical performance and reliability issues due to inefficient heat dissipation.

[0024] The present disclosure describes various examples of EWCSPs that mitigate the heat buildup challenges described above. Specifically, the die within the EWCSP is encapsulated on five sides by a molding compound, but the top surface of the die (i.e., the non-device side opposite the device side) is not covered by the molding compound. Alternatively, the top surface of the die is covered by a thermal pad (e.g., a metal layer) that promotes heat dissipation in a direction away from the PCB. This mitigates heat buildup near the PCB and within the EWCSP. In some instances, the heat sink is indirectly coupled to the thermal pad by means of a thermal interface material (TIM), which promotes heat transfer from the thermal pad to the heat sink. The heat sink may have physical properties that promote efficient heat dissipation, such as a multi-fin structure to increase the surface area exposed to the surrounding environment. Collectively, the thermal pad, TIM, and heat sink improve heat dissipation efficiency, direct heat away from the PCB and the EWCSP, thereby alleviating the challenges associated with heat buildup.

[0025] Figure 1 1 is a block diagram of an electronic device 100 containing an encapsulated WCSP (EWCSP) according to various examples. The electronic device 100 may be a laptop computer, a desktop computer, a notebook computer, a smart phone, a home or commercial appliance, a vehicle (e.g., an automobile, an aircraft, a spacecraft), an entertainment device (e.g., a video game system, an audio device), or any other suitable type of device. The electronic device 100 may include a printed circuit board (PCB) 102, and a semiconductor package 104 may be coupled to the PCB 102. The semiconductor package 104 is an EWCSP, examples of which are described below with reference to the drawings.

[0026] Figure 2A 1 is a cross-sectional view of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. Specifically, package 104 is an EWCSP coupled to PCB 102. Package 104 includes a semiconductor die 200. Semiconductor die 200 has a device side 204 and a non-device side 206 opposite to device side 204. Device side 204 has circuitry formed therein, and the type and / or operation of the circuitry may vary depending on the context in which package 104 is implemented. Device side 204 also includes a network of metal components that interface between the aforementioned circuitry and contact pads 210, and this network of metal components may be referred to as a redistribution layer (RDL) 202. Molding material 208 covers and contacts four lateral surfaces of semiconductor die 200 and device side 204 of semiconductor die 200. Solder bumps 212 are coupled to contact pads 210 and extend through portions of molding material 208 that contact device side 204, as shown.

[0027] The molding compound 208 does not cover or contact the non-device side 206 of the semiconductor die 200. Instead, the semiconductor package 104 includes a thermal pad 216, such as a metal layer (e.g., gold or tin), covering and contacting the non-device side 206 and a portion of the molding compound 208, as shown. The thermal pad 216 is applied to the non-device side 206 and a portion of the molding compound 208 by any suitable technique, such as physical vapor deposition, chemical vapor deposition, and electroless plating. The thermal pad 216 is a strong thermal conductor, wherein the thermal conductivity is at least 24.5 Watts / meter Kelvin, wherein thermal conductivity below this range is disadvantageous because the above-mentioned challenges of inadequate heat dissipation will remain without an adequate thermal conduction path. The thickness of the thermal pad 216 ranges up to 4 microns, wherein thicknesses above this range are disadvantageous due to the formation of metal burr defects encountered during the assembly process.

[0028] Semiconductor package 104 also includes a thermal interface material (TIM) 218 ​​in contact with and coupled to thermal pad 216. TIM 218 may include a thermal interface material (TIM) 218 ​​formed of HI-FLOW 300P manufactured by . TIM 218 includes a phase change compound and a thermally conductive polyimide film. In an example, TIM 218 includes a gap filler pad, such as a silicone compound pad. In an example, TIM 218 includes an acrylic adhesive. TIM 218 has adhesive properties to couple to both heat sink 220 and thermal pad 216, and the adhesion is in a range between 48 MPa and 100 MPa, wherein adhesion below this range is disadvantageous due to an unacceptably high risk of delamination, and wherein adhesion above this range is disadvantageous due to an unacceptable increase in manufacturing costs. TIM 218 is a strong thermal conductor, wherein the thermal conductivity in the package 104 including the thermal pad 216 is at least 1.5 Watts / meter Kelvin, wherein the thermal conductivity below this range is disadvantageous because the above-mentioned challenge of insufficient heat dissipation will remain. The thickness of the TIM 218 in the package 104 including the thermal pad 216 is in the range of 0.09 mm to 1.1 mm, wherein a thickness below this range is disadvantageous because it provides an unacceptably inefficient path for heat transfer, and wherein a thickness above this range is disadvantageous because it occupies an unacceptably large amount of space. The thickness of the TIM 218 in the package 104 not including the thermal pad 216 is between 0.1 mm and 0.5 mm, wherein a thickness below this range is disadvantageous because it provides an unacceptably inefficient path for heat transfer, and wherein a thickness above this range is disadvantageous because it occupies an unacceptable amount of space.

[0029] Package 104 includes heat sink 220. To maximize the efficiency of heat dissipation through heat sink 220, the bottom surface of the heat sink has a thickness of 90 mm. 2 Up to 160,000mm 2The package 104 has a junction-to-ambient thermal resistance value (i.e., a thermal parameter that specifies how difficult it is for heat to flow from one location to another) in the range of up to 50 degrees Celsius per watt, wherein values ​​above this range are disadvantageous because an inadequate thermal path exists for heat dissipation.

[0030] Figure 2B Based on various examples Figure 2A A top-down view of package 104 is shown. Figure 2C Based on various examples Figure 2A 104 is a perspective view of the package 104.

[0031] Figure 3A is a cross-sectional view of an EWCSP including a thermal interface material (TIM) and a heat sink according to various embodiments. Specifically, Figure 3A Another example of package 104 is shown. Figure 3A The package 104 is structurally equivalent to Figure 2A The example package 104 is different from Figure 3A The package 104 of FIG. 2 does not include the thermal pad 216. Instead, the TIM 218 is coupled to and contacts the non-device side 206 of the semiconductor die 200 and a portion of the molding compound 208, as shown. Figure 3B Based on various examples Figure 3A A top-down view of package 104 is shown. Figure 3C Based on various examples Figure 3A 104 is a perspective view of the package 104.

[0032] Figures 4A1 to 4I is a process flow for manufacturing an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. For example, Figures 4A1 to 4I Process flow description Figure 2A 1. The example package 104 is manufactured. Figure 5 is a flow chart of a method 500 for manufacturing a package 104 according to various examples. Figures 4A1 to 4I and Figure 5 .

[0033] Method 500 begins by performing semiconductor wafer fabrication (502). In addition to fabricating circuitry and RDLs 202 in wafer 400, additional components such as solder bumps 212 may be coupled to device side 204 of wafer 400 (eg, to contact pads 210). Fig.4A1 A cross-sectional view of solder bumps 212 coupled to the device side 204 of wafer 400 is shown. Figure 4A2 Based on various examples Fig.4A1 A top-down view of the structure.

[0034] The method 500 includes performing a half cut to form a trench in the wafer 400 (504). A "half cut" is a cut in the wafer 400, formed by any suitable tool such as a mechanical saw or a laser, that extends from the device side 204 to approximately halfway through the thickness of the wafer 400. The half cut does not necessarily extend exactly to the midpoint of the thickness of the wafer 400. Figure 4B1 exhibit Fig.4A1 4. FIG. 4 is a cross-sectional view of a structure having trenches 402 formed therein, and more specifically formed in device side 204. Trench 402 may be formed in scribe streets of wafer 400, where wafer 400 may be later singulated. Figure 4B2 Based on various examples Figure 4B1 A top-down view of the structure.

[0035] The method 500 includes applying a molding compound to a wafer ( 506 ). Fig.4C1 The molding compound 208 is shown applied to the wafer 400, and more specifically to the device side 204 of the wafer 400. The molding compound 208 also fills the trench 402, as shown. The molding compound 208 further surrounds and contacts the solder bumps 212, as shown, such that the solder bumps 212 extend from the contact pads 210, through the molding compound 208, and to the exterior of the molding compound 208. Figure 4C2 Based on various examples Fig.4C1 A top-down view of the structure.

[0036] The method 500 includes back grinding the wafer (508). Fig.4D1 Wafer 400 is shown back ground so that portions of wafer 400 through which trenches 402 do not extend are removed from wafer 400. In other words, wafer 400 is back ground until individual die 200 are formed, as shown. Figure 4D2 Based on various examples Fig.4D1 A top-down view of the structure.

[0037] The method 500 includes applying a backside metallization to a wafer (510). The backside metallization may form a thermal pad, such as the thermal pad 216 described above. Fig.4E1 Thermal pad 216 is shown applied to non-device side 206 of die 200, as well as to portions of molding compound 208, as shown. Thermal pad 216 may be applied by any suitable technique, such as physical vapor deposition, chemical vapor deposition, and electroless plating. Figure 4E2 Based on various examples Fig.4E1 A top-down view of the structure.

[0038] Method 500 includes: Fig.4E1The structure is mounted on a flexible frame (512). Figure 4F1 Thermal pad 216 is shown coupled to flexible frame 404 . Figure 4F2 Based on various examples Figure 4F1 A top-down view of the structure.

[0039] The method 500 includes performing a sawing process and stretching the flexible frame to singulate the die (514). Figure 4G1 The sawing process is shown having been performed in the trench 402 , which includes sawing in the molding compound 208 and the thermal pad 216 . Figure 4G2 Based on various examples Figure 4G1 A top-down view of the structure. Figure 4H1 The resulting structure is shown after the flexible frame 404 is singulated and removed. Figure 4H2 Based on various examples Figure 4H1 A top-down view of the structure.

[0040] The method 500 includes coupling a thermal interface member and a heat sink to the die (516). Fig. 4I A TIM 218 is shown coupled to a thermal pad 216 , and a heat sink 220 coupled to the TIM 218 , as described above and according to various examples.

[0041] In some examples of package 104, for example, Figure 3A In the package 104 of FIG. 1 , the thermal pad 216 is omitted. Instead of including the thermal pad 216, the TIM 218 is directly coupled to the non-device side 206 and to a portion of the molding compound 208. For example, in the example where the thermal pad 216 is included, the TIM 218 is coupled to and contacts the same portion of the non-device side 206 and the molding compound 208 as the thermal pad 216. Figures 6A1 to 6H is a process flow for manufacturing an EWCSP including a thermal interface material (TIM) and a heat sink according to various examples. For example, Figures 6A1 to 6H Process flow description Figure 3A 1. The example package 104 is manufactured. Figure 7 It is used to manufacture according to various examples Figure 3A 104. Therefore, the following description will now be made in parallel. Figures 6A1 to 6H and Figure 7 .

[0042] Method 700 begins by performing semiconductor wafer fabrication 702 . In addition to fabricating circuitry and RDL 202 in wafer 400 , additional components such as solder bumps 212 may be coupled to device side 204 of wafer 400 (eg, to contact pads 210 ). Fig.6A1 A cross-sectional view of solder bumps 212 coupled to the device side 204 of wafer 400 is shown. Fig.6A2 Based on various examples Fig.6A1 A top-down view of the structure.

[0043] The method 700 includes performing a half cut to form a trench in the wafer 400 (704). A "half cut" is a cut in the wafer 400, formed by any suitable tool such as a mechanical saw or a laser, that extends from the device side 204 to approximately halfway through the thickness of the wafer 400. The half cut does not necessarily extend exactly to the midpoint of the thickness of the wafer 400. Fig.6B1 exhibit Fig.6A1 4. FIG. 4 is a cross-sectional view of a structure having trenches 402 formed therein, and more specifically formed in device side 204. Trench 402 may be formed in scribe streets of wafer 400, where wafer 400 may be later singulated. Figure 6B2 Based on various examples Fig.6B1 A top-down view of the structure.

[0044] The method 700 includes applying a molding compound to the wafer ( 706 ). Fig.6C1 The molding compound 208 is shown applied to the wafer 400, and more specifically to the device side 204 of the wafer 400. The molding compound 208 also fills the trench 402, as shown. The molding compound 208 further surrounds and contacts the solder bumps 212, as shown, such that the solder bumps 212 extend from the contact pads 210, through the molding compound 208, and to the exterior of the molding compound 208. Fig.6C2 Based on various examples Fig.6C1 A top-down view of the structure.

[0045] The method 700 includes back grinding the wafer ( 708 ). Fig.6D1 Wafer 400 is shown back ground so that portions of wafer 400 through which trenches 402 do not extend are removed from wafer 400. In other words, wafer 400 is back ground until individual die 200 are formed, as shown. Fig.6D2 Based on various examples Fig.6D1 A top-down view of the structure.

[0046] Method 700 includes: Fig.6D1 The structure is mounted on a flexible frame (710). Fig.6E1 A flexible frame 404 is shown coupled to the die 200 as well as the portion of the molding compound 208 in the trench 402 . Fig.6E2 Based on various examples Fig.6E1 A top-down view of the structure.

[0047] The method 700 includes performing a sawing process and stretching the flexible frame to singulate the dies ( 712 ). Figure 6F1A sawing process is shown having been performed in the trench 402 , which includes sawing in the molding compound 208 . Figure 6F2 Based on various examples Figure 6F1 A top-down view of the structure. Figure 6G1 The resulting structure is shown after the flexible frame 404 is singulated and removed. Figure 6G2 Based on various examples Figure 6G1 A top-down view of the structure.

[0048] The method 700 includes coupling a thermal interface member and a heat sink to the die ( 714 ). Figure 6H A TIM 218 is shown coupled to the non-device side 206 of the die 200 and a portion of the molding compound 208, and a heat sink 220 coupled to the TIM 218, as described above and according to various examples. Figure 2A and 3A In both packages 104, the molding compound 208 does not cover the non-device side 206, thus permitting heat to flow upward toward the heat sink 220 and out of the package 104. Figure 3A In the package 104 of FIG. 1 , the thermal pad 216 is omitted. In some examples, the TIM 218 and the heat sink 220 may be omitted, and only the thermal pad 216 covers the non-device side 206, such as Figure 4H1 and 4H2 The various packages 104 described herein may be coupled to contact pads on a PCB using solder bumps 212.

[0049] Figure 88 is a graph 800 depicting the relative mechanical stability provided by an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. More specifically, graph 800 depicts the relative risk of cracking in or near solder bumps 212 when package 104 includes heat sink 220 compared to when package 104 omits heat sink 220. Graph 800 depicts plastic work density increment (PWDI) under thermal capacitance (TC) loading of package 104 to assess, for example, ball grid array (BGA) damage at or near solder bumps 212. PWDI is a measure of the plastic work or plastic deformation of a structure due to the action of an external force. TC loading refers to the thermal mass or capacitance possessed by a particular region of a device or integrated circuit. TC loading is a measure of how much thermal energy a device or region can store under a given temperature change. The thermal capacitance of a structure is determined by its physical properties, dimensions, and materials. Graph 800 depicts bar 802 indicating the PWDI of package 104 with heat spreader 220, and bar 804 indicating the PWDI of package 104 without heat spreader 220. As shown by bars 802 and 804, there is less than a 5% difference between the PWDI, meaning that heat spreader 220 may be included in package 104 without significantly affecting the mechanical stability of package 104 (as measured by PWDI).

[0050] Fig. 9 900 is a graph depicting relative die stress experienced by an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink under different environmental conditions according to various examples. Such die stress may cause die cracking, thereby compromising the functional integrity of the die. Graph 900 includes a y-axis depicting die stress in megapascals (MPa), a threshold 902 indicating the fracture strength standard of the die (i.e., the maximum allowable die stress), bars 904, 908, and 912 indicating die stress experienced in a package 104 including a heat sink 220, and bars 906, 910, and 914 indicating die stress experienced in a package 104 not including a heat sink 220. As shown, bar 904 indicates a reduction of approximately 10% in die stress under TC loading at -40 degrees Celsius relative to bar 906. Similarly, bar 912 indicates a reduction of approximately 10% in die stress at reflow temperature relative to bar 914. As shown, the die stress experienced under TC loading at 125 degrees Celsius is approximately the same on bars 908 and 910. Thus, graph 900 indicates that the likelihood of die cracking is generally reduced when heat spreader 220 is included in package 104.

[0051] Fig.101 is a graph 1000 depicting the relative solder bump bridging risk of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. More specifically, graph 1000 depicts the possibility that the gap between solder bumps 212 is reduced to the point where they contact each other and form a short circuit. Graph 1000 indicates the number of TC cycles on a logarithmic scale on the x-axis, and graph 1000 indicates the gap between adjacent solder bumps 212 in millimeters. Curve 1004 indicates the performance of a package 104 with a heat sink 220, and curve 1006 indicates the performance of a package 104 without a heat sink 220. As shown, the performance is almost the same until 1000 TC cycles have been passed. The 1000TC mark is a threshold 1002, after which the relative performance of curves 1004 and 1006 is different. Specifically, the gap between adjacent solder bumps 212 is reduced more for curve 1006 than for curve 1004. Therefore, the inclusion of heat spreader 220 reduces the likelihood of shorts between adjacent solder bumps 212 .

[0052] Fig.11 1 is a graph 1100 depicting the relative solder bump bridging risk of an EWCSP including a thermal pad, a thermal interface material (TIM), and a heat sink according to various examples. Specifically, the graph 1100 depicts the relative risk of bridging between adjacent solder bumps 212 in terms of plastic strain in the horizontal direction (i.e., the x-direction). In the graph 1100, the x-axis depicts the number of TC cycles, and the y-axis depicts the plastic strain. The graph 1100 includes curves 1102 and 1104. The curve 1102 indicates the performance of the package 104 with the heat sink 220, and the curve 1104 indicates the performance of the package 104 without the heat sink 220. As shown, as the number of TC cycles increases, the plastic strain experienced by the package 104 including the heat sink 220 becomes less than the plastic strain experienced by the package 104 without the heat sink 220. The package 104 including the heat sink 220 has superior performance after the ~3.5TC cycle mark relative to the package 104 not including the heat sink 220 .

[0053] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B so that device B is controlled by device A via the control signal generated by device A.

[0054] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter. Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A wafer chip scale package WCSP, comprising: a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side; a solder bump electrically coupled to the circuitry; a molding compound in contact with the device side, the solder bumps, and four lateral sides of the semiconductor die; as well as A thermal pad contacts the non-device side of the semiconductor die and the molding compound. 2 . The WCSP of claim 1 , wherein the molding compound is not in contact with the non-device side of the semiconductor die.

3. The WCSP of claim 1, wherein the WCSP has a junction-to-ambient thermal resistance value in the range of up to 50 degrees Celsius per Watt. The WCSP of claim 1 , wherein the thermal pad comprises gold or tin.

5. The WCSP of claim 4, wherein the thermal pad has a thickness in the range up to 4 microns. 6 . The WCSP of claim 1 , further comprising a thermal interface material in contact with the thermal pad, the thermal interface material comprising a phase change compound and a thermally conductive polyimide film. 7 . The WCSP of claim 6 , further comprising a heat sink in contact with the thermal interface material and comprising a fin structure.

8. The WCSP of claim 6, wherein the thermal interface material has a thickness in a range of 0.09 mm to 1.1 mm.

9. The WCSP of claim 6, wherein the thermal interface material has a thermal conductivity of at least 1.5 W / m Kelvin.

10. A wafer chip scale package (WCSP), comprising: a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side; a solder bump coupled to the device side; a molding compound contacting the device side and the solder bumps; a thermal interface material coupled to and supported by the semiconductor die, the thermal interface material having a thickness between 0.1 mm and 0.5 mm and a thermal conductivity of at least 1.5 Watts per meter Kelvin (W / mK); as well as A heat sink is coupled to the thermal interface material. 11 . The WCSP of claim 10 , wherein the molding compound contacts four lateral sides of the semiconductor die and does not contact the non-device side of the semiconductor die.

12. The WCSP of claim 10, wherein the thermal interface material comprises a gap filler pad.

13. The WCSP of claim 12, wherein the gap filler pad comprises a silicone compound.

14. The WCSP of claim 10, wherein the thermal interface material comprises a phase change compound and a polyimide film.

15. The WCSP of claim 10, wherein the thermal interface material comprises an acrylic adhesive.

16. A method for manufacturing a semiconductor device, comprising: positioning solder bumps on a device side of a semiconductor wafer having circuitry formed therein; cutting through the thickness of the semiconductor wafer to create portions of first and second trenches; applying a molding compound to the device side, the solder bumps, and the portions of the first and second trenches; back grinding the semiconductor wafer to reduce a thickness of the semiconductor wafer, the back grinding producing first and second semiconductor dies; coupling a thermal pad to a first non-device side of the first semiconductor die and to a second non-device side of the second semiconductor die; separating the first and second semiconductor dies to produce a wafer chip scale package (WCSP); coupling a thermal interface material to the thermal pad of the WCSP; as well as A heat sink is coupled to the thermal interface material.

17. The method of claim 16, wherein the thermal interface material has a thermal conductivity of at least 1.5 W / m Kelvin.

18. The method of claim 16, wherein the thermal interface material has a thickness in a range of 0.09 mm to 1.1 mm.

19. The method of claim 16, wherein the thermal interface material comprises a phase change compound.

20. The method of claim 16, wherein the thermal interface material comprises a thermally conductive polyimide film.

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