Semiconductor device and manufacturing method

Abstract

The invention relates to a semiconductor device structure and a method of manufacturing a semiconductor device. The semiconductor device may include a semiconductor wafer having a top major surface, an opposing bottom major surface, and a side surface, the top major surface having one or more electrical contacts formed thereon; a molding material encapsulating the top major surface, the bottom major surface, and the side surfaces of the semiconductor wafer, where the molding material defines a package body having a top surface and a side surface; wherein the plurality of electrical contacts are exposed on a top surface of the package body, and a metal layer is disposed on and electrically connected to the electrical contacts, and wherein the metal layer extends to and at least partially covers a side surface of the package body.

Description

[0001] This application is a divisional application of a patent application with application number 2018115103210, application date December 11, 2018, and invention name “Semiconductor device and manufacturing method”. Technical Field

[0002] The present disclosure relates to semiconductor devices and methods of manufacturing. More particularly, the present disclosure relates to wafer-level semiconductor devices with wettable side contacts. Background Art

[0003] Semiconductor devices in the form of wafer-level packages (WLPs) are becoming increasingly important for applications requiring small devices with improved electrical performance. For example, wafer-level packages are often used in portable electronic devices such as mobile communication devices.

[0004] 1 is a cross-sectional side view of a conventional WLP 100. WLP 100 includes a plurality of input or output (I / O) pads 102 exposed on a bottom surface of WLP 100. I / O pads 102 are mounted to contacts 104, such as pads with solder 106, on a printed circuit board (PCB).

[0005] Figure 1b It is the same as WLP 100 Figure 1a 1 is an enlarged schematic bottom plan view of a portion 108 of line AA of WLP 100. The bottom surface of WLP 100 includes: an I / O pad 102 as a metal area; a saw scribe area 110, which is located at the peripheral area of ​​the bottom surface of WLP 100 and serves as a non-passivation area; and a passivation overlap area 112, which is located between I / O pad 102 and saw scribe area 110.

[0006] However, if Figure 1b As shown, either too much solder and a very narrow spacing between the I / O pads 102 and the saw scribe street area 110 may create flux residue or solder flakes 114 that may bridge the active pads 102 and the saw scribe street area 110, which may result in a short circuit between the I / O pads 102 and the wafer of the WLP 100.

[0007] Additionally, because the active pads 102 do not extend all the way to the sides of the WLP 100, once the WLP 100 is mounted to the PCB and the I / O pads 102 are soldered to the corresponding contacts 104, it is difficult to inspect the solder joints to determine if there are any potential solder joint defects. Summary of the invention

[0008] According to an embodiment, a semiconductor device is provided, comprising: a semiconductor wafer having a top main surface, an opposite bottom main surface and a side surface, the top main surface having one or more electrical contacts formed thereon; a molding material encapsulating the top main surface, the bottom main surface and the side surface of the semiconductor wafer, wherein the molding material defines a package body having a top surface and a side surface; wherein the multiple electrical contacts are exposed on the top surface of the package body, and a metal layer is arranged on the electrical contacts and electrically connected to the electrical contacts, and wherein the metal layer extends to the side surface of the package body and at least partially covers the side surface of the package body.

[0009] Alternatively, the metal layer may comprise copper and the metal layer may be coated with a wettable material such as tin.

[0010] Alternatively, the metal layer may extend across a width of the top surface of the package body.

[0011] Alternatively, a molding material may be disposed overall to encapsulate the semiconductor wafer.

[0012] According to an embodiment, a method for assembling semiconductor devices is provided, the method may include: providing a plurality of spaced-apart semiconductor wafers having a top main surface on which one or more electrical contacts are formed, an opposite bottom main surface, and side surfaces, wherein each wafer has a plurality of electrical contacts formed on the top surface; encapsulating the wafers with a molding material, wherein the molding material partially covers a portion of the top surface so that the electrical contacts are exposed and the molding material covers the bottom surface and the side surface of the wafer; cutting a plurality of first grooves to define side walls of a package body of each semiconductor device; forming a metal layer on the top surface of each package body, wherein the metal layer is in electrical contact with the electrical contacts and extends to the side surface of each package body; and separating the semiconductor devices from each other.

[0013] Alternatively, the metal layer may include copper and may be formed by sputtering or electroplating. Alternatively, the metal layer may be coated with a wettable material by electroplating. The metal layer may extend across the width of the top surface of the package body.

[0014] Optionally, molding the semiconductor wafers includes integrally encapsulating each semiconductor wafer with a molding material. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order that the manner in which the features of the present disclosure may be understood in detail, a more specific description will be given with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be considered to limit their scope. The accompanying drawings are intended to facilitate understanding of the present disclosure and are not necessarily drawn to scale. By reading this specification in conjunction with the accompanying drawings, the advantages of the claimed subject matter will become apparent to those skilled in the art, in which the same reference numerals are used to represent the same elements, and in the accompanying drawings:

[0016] Figure 1a shows a cross-sectional side view of a conventional wafer-level semiconductor device;

[0017] Figure 1b Shows Figure 1a The traditional wafer-level semiconductor devices are Figure 1a an enlarged bottom plan view of line AA;

[0018] Figure 2 shows a cross-sectional side view of a wafer-level semiconductor device according to an embodiment;

[0019] Figure 3a shows an isometric view of a wafer-level semiconductor device according to an embodiment;

[0020] Figure 3b shows an isometric view of a wafer-level semiconductor device according to an embodiment;

[0021] Figure 4a The steps of mounting a semiconductor wafer on a carrier tape are shown;

[0022] Figure 4b The steps of encapsulating a semiconductor wafer are shown;

[0023] Figure 4c The steps of removing the carrier tape are shown;

[0024] Figure 4d The steps of mounting the encapsulated semiconductor wafer on a temporary stage are shown;

[0025] Figure 4e The steps of partially singulating a semiconductor wafer are shown;

[0026] Figure 5a The formation of a metallic intermediate layer is shown;

[0027] Figure 5b shows the further formation of a metallic intermediate layer;

[0028] Figure 5c shows the formation of metal I / O pads;

[0029] Figure 5dshows singulation of wafer-level semiconductor devices according to an embodiment; and

[0030] Figure 5e A plan view of an array of wafer-level semiconductor devices after singulation is shown. DETAILED DESCRIPTION

[0031] Reference Figure 2 , shows a cross section of an example wafer-level semiconductor device 200 according to an embodiment. The device 200 includes a semiconductor wafer 202 having a top major surface 204 and an opposite bottom major surface 208. The top major surface 204 of the semiconductor wafer 202 has one or more electrical contacts 206 formed thereon. The semiconductor wafer 202 may include one or more active components (not shown) such as transistors or diodes and one or more electrical contacts 206. The electrical contacts may preferably be formed by depositing a patterned metal layer on the wafer top surface 204 to provide electrical connections to the one or more active components of the semiconductor wafer 202.

[0032] The semiconductor device 200 further includes a molding material 210 covering the bottom surface 208 and each side surface of the semiconductor wafer 202. In addition, the molding material 210 covers at least a portion of the top surface 204 of the semiconductor wafer, wherein the contacts 206 arranged on the top surface 204 will be free of the molding material 210.

[0033] The molding material 210 defines a package body having a top surface 212, corresponding side surfaces 214, and a bottom surface 215. In the absence of the molding material 210 for the electrical contacts 206, openings are defined in the top surface 212 of the package body such that the electrical contacts 206 are at least partially exposed through the openings in the molding material 210. Depending on the molding process used, the tops of the electrical contacts may be substantially flush with the top of the molding material 210. Alternatively, the tops of the contacts may be disposed below the top of the molding material 210. The device 200 also includes a metal layer 218 formed over the electrical contacts 206 and electrically connected to the electrical contacts 206 through the openings 216. The metal layer 218 extends to and at least partially covers the side surfaces 214 of the package body.

[0034] The metal layers 218, which are respectively electrically connected to the electrical contacts 206, are separated and isolated from each other by gaps 220 therebetween. The metal layers 218 form a metal interlayer between the metal electrical contacts 206 and I / O pads 222 (discussed below) of the semiconductor device 200.

[0035] The metal layer 218 may include copper, and the metal layer 218 may be coated with a wettable material (e.g., tin) by, for example, an electroplating process to form an I / O pad 222, so that the device 200 has a wettable side that allows a solder joint to be formed between the I / O pad 222 and the contact pad of the PCB. The metal layer 218 with a wettable material forms an I / O pad that allows solder joint inspection by, for example, automatic optical inspection as required for automotive qualified semiconductor devices. In addition, because the top surface 204 of the semiconductor wafer 202 (except for the location of the electrical contacts as described above) is covered by the molding material, the six sides of the packaged semiconductor wafer are protected by the molding material. As a result, the possibility of a short circuit between the I / O pad 102 and the semiconductor wafer 202 caused by flux residues or solder flakes is reduced when the I / O pad 102 and the semiconductor wafer 202 are mounted to the PCB. In addition, the arrangement as described above can result in a lower package height because no wafer carrier or mounting member is required.

[0036] Reference Figure 3a , which shows an isometric view of a semiconductor device 200 according to an embodiment, the I / O pads 222 may extend across the entire width of the top surface of the package body and also across the entire width of the side surface 214 of the package body. When the semiconductor device 200 is mounted on a carrier such as a PCB, this arrangement of the I / O pads 222 results in improved visibility of the solder joints connecting the I / O pads 222 to the contact pads of the PCB.

[0037] In an alternative arrangement, such as Figure 3b As shown, which illustrates an isometric view of a semiconductor device 200 according to an embodiment, the I / O pad 222 may extend partially across the width of the top surface of the package body and also partially across the width of the side surface 214 of the package body.

[0038] Figure 3a In, with Figure 3b In comparison, with the same body width, the solder pad is larger and the solder is very visible.

[0039] Figures 4a to 4e 2 shows the steps of molding a wafer-level semiconductor device according to an embodiment. The semiconductor wafer 202 is initially singulated (not shown) from a wafer containing an array of such semiconductor wafers 202. Figure 4a As shown, semiconductor wafer 202 is mounted on carrier tape 402. Semiconductor wafer 202 is mounted by electrical contacts 206 secured to carrier tape 402.

[0040] In an alternative process, a die containing an array of such semiconductor wafers 202 may be mounted on a carrier tape 402. The semiconductor wafers 202 may then be singulated without cutting the carrier tape 402 so that they remain on the carrier tape 402 ready for molding.

[0041] After the semiconductor wafer 202 is mounted on the carrier tape 402, the Figure 4b The semiconductor wafer 202 is molded as shown. The molding process can be a film assisted molding process, whereby the carrier tape 402 prevents the molding material 212 from covering the top surface of the electrical contact 206. As described above, this results in the top surface of the electrical contact 206 being substantially flush with the top surface of the molding material 212. The use of the carrier tape 402 also prevents the molding material 212 from covering the electrical contact 206, so that the electrical contact 206 is free of the molding material 212, as described above. In addition, the use of this molding method ensures that all six sides of the semiconductor wafer (except for the locations of the electrical contacts) are covered in a single step by a single integrally formed molding material 212.

[0042] In such Figure 4c After the carrier tape 402 is removed as shown, the molded array of semiconductor wafers 202 is then mounted on a carrier 404, as shown. Figure 4d As shown, the electrical contacts 206 are directed upwards away from the carrier. The carrier 404 may be any suitable temporary carrier (eg, a film frame carrier (FFC)) to hold the individual semiconductor devices 202 in place during singulation (described below).

[0043] After the semiconductor wafer 202 is mounted on the FFC 404, the molding material 212 is partially cut in a direction toward the FFC 404, such as Figure 4e As shown. In an array of such wafers, a cut is made between adjacent sidewalls of adjacent semiconductor wafers 202. The cut is a partial cut in that it does not extend completely through the molding material 212 and terminates before the FFC 404, thus forming a trench in the molding material 212 and partially defining the sidewalls of the semiconductor device 200. The cut may be made using any suitable means, such as a laser or a saw blade with appropriate cuts.

[0044] After the above molding and cutting steps, then as reference Figures 5a to 5d I / O pads 222 are formed as shown. Figure 5a As shown, a metal layer 406 is formed on the top surface (i.e., the surface of each package body having the electrical contact 206) so that the metal layer is electrically connected to the electrical contact 206. The metal layer 406 also extends to the side surface of each package body and the bottom surface formed by the groove cut in the molding material. Optionally, the metal layer 406 is formed by sputtering or electroplating, and the metal layer 406 may include copper.

[0045] like Figure 5bAs shown, the metal layer intermediate layer 406 can be removed from the top of the package between the contacts 206 to prevent short circuits between them. The metal layer 406 can be removed by etching or cutting. The step of removing the metal layer intermediate layer 406 can expose the molding material on the top of the package. After the metal intermediate layer 406 is formed and as shown in FIG. Figure 5c As shown, the metal interlayer is coated with a wettable material 408 by electroplating to complete the formation of the I / O pad 222. The wettable material 440 may include tin. Optionally, the electroplating is performed before removing the metal interlayer 406 between the contacts 206.

[0046] like Figure 5d As shown, singulation is performed along the trenches and between the remaining adjacent sidewalls to separate the semiconductor devices 200 from each other. Figure 5e The singulation process is described in more detail above. Figure 4e As discussed, a partial cut through the molding material 212 is made before forming the I / O pad 222. After forming the I / O pad 222, a first cut through the molding material 212 is made in the y direction. A second cut is then made in the x direction after the partial cut described above. This second cut may optionally be made with a saw having a kerf that is smaller than the kerf of the saw used to make the partial cut. This results in a stepped feature of the sidewall of the molding material.

[0047] Although the above example shows two I / O pads 222, the skilled person will understand that, based on the above discussion, any number or arrangement can be implemented without departing from the scope of the present disclosure. In this way, the skilled person will understand that the above example can be applied to, for example, a dual silicon no-lead (DSN) arrangement.

[0048] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or the independent claim may be combined as appropriate and not just as set out in the claims.

[0049] The scope of the present disclosure includes any novel feature or combination of features disclosed explicitly or implicitly, or any generalization thereof, whether or not it relates to the claimed invention or mitigates any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from separate independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.

[0050] Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0051] The term "comprising" does not exclude other elements or steps and the term "a" or "an" does not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A semiconductor device, comprising: a semiconductor wafer having a top major surface, an opposing bottom major surface, and side surfaces, the top major surface having one or more electrical contacts formed thereon; a molding material encapsulating the top major surface, the bottom major surface, and the side surfaces of the semiconductor wafer, wherein the molding material defines a package body having a top surface and side surfaces, and the molding material is disposed solely and integrally to encapsulate the semiconductor wafer; wherein the plurality of electrical contacts are exposed on the top surface of the package body, and the metal layer is arranged on the top surface of the plurality of electrical contacts and is electrically connected to the electrical contacts, and The metal layer extends to the side surface of the package body and at least partially covers the side surface of the package body, and does not extend to the bottom main surface of the package body.

2. The semiconductor device according to claim 1, wherein The metal layer includes copper.

3. The semiconductor device according to claim 1, wherein The metal layer is coated with a wettable material.

4. The semiconductor device according to claim 3, wherein: The wettable material includes tin.

5. The semiconductor device according to claim 1, wherein The metal layer extends across a width of the top surface of the package body.

6. The semiconductor device according to claim 1, wherein The metal layer extends to and at least partially covers the side surfaces along which the package body is in contact.

7. A method for assembling a semiconductor device, the method comprising: providing a plurality of spaced apart semiconductor wafers, each semiconductor wafer having a top major surface having one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces, wherein each semiconductor wafer has a plurality of electrical contacts formed on the top surface; encapsulating the semiconductor wafers with a molding material, wherein the molding material partially covers a portion of a top surface of each of the semiconductor wafers such that the electrical contacts are exposed, and the molding material covers a bottom surface and side surfaces of each of the semiconductor wafers; cutting a plurality of first grooves to define a plurality of package body sidewalls of the plurality of package bodies; forming a metal layer on a top surface of each of the package bodies, wherein the metal layer is in electrical contact with the electrical contacts and extends to a side surface of each package body; as well as The package bodies are separated from each other to form a plurality of semiconductor devices.

8. The method according to claim 7, wherein: The metal layer includes copper.

9. The method according to claim 7, wherein: The metal layer is formed by sputtering or electroplating.

10. The method of claim 7, further comprising coating the metal layer with a wettable material by electroplating.

11. The method according to claim 7, wherein: The metal layer extends across a width of the top surface of each package body.

12. The method according to claim 7, wherein: Encapsulating the semiconductor wafers with a molding material includes entirely encapsulating each semiconductor wafer with the molding material.

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