Semiconductor device

Abstract

The invention relates to a semiconductor device. The performance of a semiconductor device may be improved. The plurality of protruding electrodes of the semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of the insulating layer; a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer; and a plurality of third protruding electrodes arranged at positions overlapping the third region of the insulating layer. The plurality of first protruding electrodes are arranged at a first pitch, the plurality of second protruding electrodes are arranged at a second pitch, and the plurality of third protruding electrodes are arranged at a third pitch different from each of the first pitch and the second pitch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-125203 filed on August 1, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-75442

[0006] There is a semiconductor device in which a semiconductor chip is mounted on a wiring substrate including a plurality of wiring layers by a flip chip connection method. For example, Patent Document 1 discloses a structure in which a semiconductor chip and a wiring substrate are electrically connected to each other via a plurality of protruding electrodes arranged on the surface of the semiconductor chip. Summary of the invention

[0007] According to the development of semiconductor devices, there is a trend that the number of protruding electrodes of a semiconductor chip increases. On the other hand, due to the demand for miniaturization of semiconductor chips, the arrangement density of the protruding electrodes is high. Therefore, it is necessary to arrange the protruding electrodes so that no electrical short circuit occurs between adjacent protruding electrodes. The inventors have found that from the viewpoint of improving the reliability of semiconductor devices or improving electrical characteristics, the reliability can be improved or the electrical characteristics can be improved by designing the arrangement of the protruding electrodes, compared with the case where the protruding electrodes are simply arranged at a minimum pitch.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] A semiconductor chip of a semiconductor device according to an embodiment includes: a first wiring layer formed on a semiconductor substrate; a second insulating layer arranged to cover the first wiring layer; and a plurality of protruding electrodes electrically connected to the first wiring layer. The plurality of protruding electrodes include: a plurality of first protruding electrodes arranged at a position overlapping with a first region of the second insulating layer; a plurality of second protruding electrodes arranged at a position overlapping with a second region of the second insulating layer; and a plurality of third protruding electrodes arranged at a position overlapping with a third region of the second insulating layer. The plurality of first protruding electrodes are arranged at a first pitch, the plurality of second protruding electrodes are arranged at a second pitch, and the plurality of third protruding electrodes are arranged at a third pitch different from each of the first pitch and the second pitch. The component of the second pitch in the second direction is greater than the component of the first pitch in the second direction.

[0010] According to the embodiments, the performance of a semiconductor device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a plan view of an upper surface of a semiconductor device according to an embodiment.

[0012] Figure 2 yes Figure 1 A plan view of the bottom surface of the semiconductor device shown.

[0013] Figure 3 It is along Figure 1 A cross-sectional view along line AA is shown.

[0014] Figure 4 It shows that Figures 1 to 3 An explanatory diagram of a configuration example of a circuit provided in the semiconductor device shown.

[0015] Figure 5 yes Figure 3 A plan view of the electrode arrangement surface of a semiconductor chip is shown.

[0016] Figure 6 yes Figure 5 An enlarged plan view of portion A is shown.

[0017] Figure 7 is shown with Figure 5 A plan view of an inspection example related to the layout of the protruding electrodes is shown.

[0018] Figure 8 is shown with Figure 5 A plan view of another inspection example related to the layout of the protruding electrodes is shown.

[0019] Fig. 9 It is along Figure 6 An enlarged cross-sectional view of line BB is shown.

[0020] Fig.10 yes Figure 5 An enlarged plan view of portion B is shown.

[0021] Fig.11 It is a plan view of the electrode arrangement surface of a semiconductor chip. Figure 5 's modified example.

[0022] Fig.12 yes Fig.11 An enlarged plan view of portion C is shown.

[0023] Fig.13 is an enlarged plan view showing an example of the layout of a wiring layer located on the top layer of a wiring substrate, Fig.11 and12 The semiconductor chip shown is mounted on the wiring substrate.

[0024] Fig.14 It is a plan view of the electrode arrangement surface of a semiconductor chip. Figure 5 Another modified example of .

[0025] Fig.15 yes Fig.14 An enlarged plan view of portion D is shown.

[0026] Fig.16 It shows the manufacturing Figure 3 An explanatory diagram of an example of a flow chart of a method for implementing a semiconductor device shown in FIG.

[0027] Fig.17 It is schematically shown Fig.16 A plan view showing the direction of air supply during the drying process. DETAILED DESCRIPTION

[0028] (Explanation of description format, basic terms and usage in this application)

[0029] In this application, for the sake of convenience, the description of the embodiment is divided into a plurality of parts, etc., when necessary, unless otherwise explicitly stated, these parts are not independent of each other, and each part of a single example, one of which is a detailed part of another or a part or all of a modified example, regardless of the order of description. In principle, the description of similar parts is omitted. Moreover, each component in the embodiment is not indispensable, unless otherwise explicitly stated, and is theoretically limited to the number, and it is obviously not the case from the context.

[0030] Similarly, in the description of the embodiments, etc., "X consisting of A" etc. with respect to materials, compositions, etc. does not exclude those including elements other than A, unless otherwise explicitly stated and it is obvious from the context that this is not the case. For example, with respect to a component, it means "X including A as a main component" etc. For example, even if referred to as a "silicon member" etc., it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys with silicon as the main component and other additives. Moreover, when referred to as gold plating, Cu layer, nickel plating, etc., unless otherwise explicitly stated, it includes not only pure but also members with gold, Cu, nickel, etc. as the main component.

[0031] Furthermore, when a specific value or amount is mentioned, unless expressly stated otherwise, it is theoretically limited to that amount and it is obvious from the context that this is not the case, otherwise the value may be greater or less than the specific value.

[0032] In the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description is not repeated in principle.

[0033] In the attached drawings, even in a cross section, hatching or the like may be omitted when it becomes complicated or when it is clearly distinguished from a gap. In view of this, even if a hole is closed in a plane, the outline of the background may be omitted when it is obvious from the description, etc. In addition, even if it is not a cross section, hatching or a dot pattern may be added to indicate that it is not a gap or to indicate the boundary of an area.

[0034] In the following description, the semiconductor chip electrode refers to a component used as an external terminal of the semiconductor chip. In the electrode, a plate-like component with a smaller area is called an "electrode pad". In the electrode, a component formed to protrude locally from the substrate is called a "bump electrode" or a "protruding electrode". Moreover, an "electrode pad" or a "bump electrode (or protruding electrode)" may be referred to as an "electrode" for short. Moreover, a structure in which a bump electrode (or a protruding electrode) is formed on an electrode pad may be referred to as an "electrode".

[0035] In the following description, the directions of X, Y, and Z may be used. Figure 1 In the description, the X direction and the Y direction are shown. The X direction and the Y direction intersect each other. In the example described below, the X direction is orthogonal to the Y direction. Hereinafter, the XY plane including the X direction and the Y direction will be described as a plane parallel to the main surface of the semiconductor device and the main surface of the mounting substrate.

[0036] The surface intersecting the XY plane (e.g., the surface parallel to the XZ plane including the X direction and the Z direction and the surface parallel to the YZ plane including the Y direction and the Z direction) is referred to as the side surface. In the following description, unless otherwise explicitly stated, the term "plan view" refers to a view of a plane parallel to the XY plane. Moreover, the normal direction of the XY plane is described as the "Z direction" or the thickness direction. Unless otherwise explicitly stated, the terms "thickness" and "height" refer to the length in the "Z direction". The X, Y, and Z directions intersect with each other, and more specifically, they are orthogonal to each other.

[0037] <Semiconductor devices>

[0038] Figure 1 is a plan view of the upper surface of the semiconductor device of this embodiment. Figure 2 yes Figure 1 FIG. 1 is a plan view of the lower surface of the semiconductor device shown. In addition, Figure 3 It is along Figure 1 The cross-sectional view of the line AA is shown. Figure 3, for ease of viewing, the number of electrodes 1PD and the number of protruding electrodes 1BP are shown to be smaller than those in a plan view of a semiconductor chip described later.

[0039] The semiconductor device PKG1 of the present embodiment includes a wiring substrate 20 and a semiconductor chip 10 mounted on the wiring substrate 20 (see FIG. Figure 1 and 3 ). The semiconductor device PKG1 also has an underfill layer (insulating layer, insulating material) UF (see Figure 1 and 3 ), which is arranged between the semiconductor chip 10 and the wiring substrate 20, and seals the plurality of protruding electrodes 1BP (see Figure 3 ).

[0040] like Figure 3 As shown, the wiring substrate 20 has an upper surface (surface, main surface, chip mounting surface) 20t on which the semiconductor chip 10 is mounted and a lower surface (surface, main surface, mounting surface) 20b on the opposite side of the upper surface 20t. The wiring substrate 20 also has a plurality of side surfaces 20s (see Figure 1 and 2 ), these side surfaces form the peripheries of the upper surface 20t and the lower surface 20b in a plan view. Figure 1 ) and the lower surface 20b (see Figure 2 ) are respectively rectangular, and the wiring substrate 20 has four sides 20s in a plan view.

[0041] The wiring substrate 20 also has a plurality of wiring layers (in Figure 3 In the example shown, there are 8 layers) WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8. The plurality of wiring layers include a wiring layer WL1, which is the layer closest to the upper surface 20t of the wiring substrate 20 among the wiring layers and has a terminal (terminal 2PD). The plurality of wiring layers also include a wiring layer WL8, which is the layer closest to the lower surface 20b of the wiring substrate 20 among the wiring layers and has a terminal (pad 2LD).

[0042] Each wiring layer has a conductor pattern such as wiring 2D, which is used as a path for supplying electrical signals and power. An insulating layer 2E is arranged between each wiring layer. Each wiring layer is electrically connected to each other by a via 2V or a through-hole wiring 2THW as an interlayer conductive path penetrating the insulating layer 2E. In the present embodiment, a wiring substrate having 8 wiring layers is illustrated as an example of a wiring substrate 20, but the number of wiring layers provided by the wiring substrate 20 is not limited to 8. For example, a wiring substrate having 7 or fewer layers, or 9 or more layers can be used as a modified example.

[0043] Among the plurality of wiring layers, the wiring layer WL1 as the layer closest to the upper surface 20t (top layer) is covered with the insulating film SR1. Openings are provided in the insulating film SR1, and the plurality of terminals 2PD provided on the wiring layer WL1 are exposed from the insulating film SR1 at the openings.

[0044] Among the plurality of wiring layers, the wiring layer WL8, which is the layer (bottom layer) closest to the lower surface 20b of the wiring substrate 20, has a plurality of pads 2LD. The wiring layer WL8 is covered by the insulating film SR2. An opening is provided in the insulating film SR2, and a plurality of pads 2LD provided on the wiring layer WL8 are exposed from the insulating film SR2 at the opening.

[0045] Each of the insulating films SR1 and SR2 is a solder resist film. A plurality of terminals 2PD provided in the wiring layer WL1 are electrically connected to a plurality of pads (pad patterns) 2LD provided in the wiring layer WL8 and conductor patterns (wiring 2D and large-area conductor patterns) formed in each wiring layer provided in the wiring substrate 20 via 2V and through-hole wiring 2THW.

[0046] The wiring substrate 20 is formed by laminating a plurality of wiring layers on the upper surface 2Ct and the lower surface 2Cb of an insulating layer (core material, core insulating layer) 2CR made of a prepreg impregnated with a resin, for example, using a build-up method. The wiring layer WL4 on the upper surface 2Ct side of the insulating layer 2CR and the wiring layer WL5 on the lower surface 2Cb side are electrically connected via a plurality of through-hole wirings 2THW embedded in a plurality of through-hole wirings 2THW provided to penetrate from one of the upper surface 2Ct and the lower surface 2Cb to the other.

[0047] exist Figure 3 In the example shown, the wiring substrate 20 shows a wiring substrate in which a plurality of wiring layers are laminated on the upper surface 2Ct side and the lower surface 2Cb side of the insulating layer 2CR as a core material. Figure 3In a modified example, there is a case where a coreless substrate is used, which is formed by sequentially laminating an insulating layer 2E and a conductor pattern (such as wiring 2D) without an insulating layer 2CR made of a hard material (such as prepreg). In the case of using a coreless substrate, a through-hole wiring 2THW is not formed, and each wiring layer is electrically connected via a via 2V.

[0048] exist Figure 3 In the example shown, a solder ball (solder material, external terminal, electrode, external electrode) SB is connected to each of the plurality of pads 2LD. The solder ball SB is a conductive member that electrically connects a plurality of terminals (not shown) on the motherboard side and the plurality of pads 2LD when the semiconductor device PKG1 is mounted on a motherboard (not shown).

[0049] The solder ball SB is, for example, a solder material made of Sn-Pb solder including lead (Pb) or a so-called lead-free solder that does not substantially include Pb. Examples of lead-free solder include, for example, only tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder means that the content of lead (Pb) is 0.1wt% or less, and the content is defined as the standard of the RoHS (Restriction of Hazardous Substances) directive.

[0050] like Figure 2 As shown, a plurality of solder balls SB are arranged in a matrix (array, matrix) form. Figure 2 Although not shown, a plurality of pads 2LD (see Figure 3 ) are also arranged in a matrix (matrix). Therefore, a semiconductor device in which a plurality of external terminals (solder balls SB, pads 2LD) are arranged in a matrix on the mounting surface side of the wiring substrate 20 is called an area array type semiconductor device.

[0051] The area array type semiconductor device is preferred because it can effectively utilize the mounting surface (lower surface 20b) side of the wiring substrate 20 as a placement space for external terminals, and even if the number of external terminals increases, the increase in the mounting area of ​​the semiconductor device can be suppressed. In other words, due to high functionality and high integration, a semiconductor device with an increased number of external terminals can be installed in a space-saving manner.

[0052] The semiconductor device PKG1 includes a semiconductor chip 10 mounted on a wiring substrate 20. Figure 3 As shown, each of the semiconductor chips 10 has a front surface (front surface, main surface, upper surface) 1t and a back surface (front surface, main surface, rear surface, lower surface) 1b opposite to the front surface 1t. The semiconductor chip 10 has a plurality of side surfaces 1s (see Figure 1), these side surfaces constitute the outer edges of each of the front surface 1t and the back surface 1b in a plan view. Figure 1 As shown in FIG. 1 , the semiconductor chip 10 has a rectangular shape in a plan view, and its planar area is smaller than that of the wiring substrate 20. Therefore, the semiconductor chip 10 has four side surfaces 1s in a plan view. Figure 1 In the example shown, the semiconductor chip 10 is mounted at the center of the upper surface 20 t of the wiring substrate 20 , and each of the four side surfaces 1 s of the semiconductor chip 10 extends along each of the four side surfaces 20 s of the wiring substrate 20 .

[0053] On the front surface 1t of the semiconductor chip 10, a plurality of electrodes (pads, electrode pads, bonding pads) 1PD are formed. Figure 3 In the example shown, the semiconductor chip 10 is mounted on the wiring substrate 20 with the front surface 1t facing the upper surface 20t of the wiring substrate 20. This mounting method is called a down mounting method or a flip chip connection method.

[0054] A plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip 10 (specifically, a semiconductor element forming region provided on the element forming surface of a semiconductor substrate as a base material of the semiconductor chip 10). A plurality of electrodes 1PD are electrically connected to these semiconductor elements via wiring (not shown) formed in a wiring layer located inside the semiconductor chip 10 (specifically, between the front surface 1t and the semiconductor element forming region not shown).

[0055] The semiconductor substrate provided in the semiconductor chip 10 is made of, for example, silicon (Si). On the front surface 1t of the semiconductor chip 10, an insulating film covering the semiconductor substrate and wiring is formed, and a portion of each of the plurality of electrodes 1PD (see Figure 3 ) is exposed from the insulating film at an opening formed in the insulating film. Moreover, each of the plurality of electrodes 1PD is made of a metal film. The detailed structure of the semiconductor chip 10 will be described later.

[0056] like Figure 3 As shown, each of the plurality of electrodes 1PD is connected to a protruding electrode 1BP, and the plurality of electrodes 1PD of the semiconductor chip 10 and the plurality of terminals 2PD of the wiring substrate 20 are electrically connected to each other via the plurality of protruding electrodes 1BP. The protruding electrode (bump electrode) 1BP is a metal member (conductive member) formed to protrude on the front surface 1t of the semiconductor chip 10.

[0057] In the present embodiment, the protruding electrode 1BP is made of a solder material. The protruding electrode 1BP made of a solder material is called a solder bump. The electrode 1PD is electrically connected to the protruding electrode 1BP via an under bump metal (UBM) (see the solder bump described later). Fig. 9 ), the under bump metal is a base metal film of a solder bump as the protruding electrode 1BP. As a solder material constituting the protruding electrode 1BP, a lead-containing solder material or a lead-free solder can be used, as in the case of the above-mentioned solder ball SB.

[0058] When the semiconductor chip 10 is mounted on the wiring substrate 20, solder bumps are formed on the plurality of electrodes 1PD and the plurality of terminals 2PD in advance, and by applying heat treatment (reflow process) in a state where the solder bumps are in contact with each other, the solder bumps are integrated to form the protruding electrodes 1BP.

[0059] like Figure 3 As shown, an underfill (insulating layer, insulating resin, insulating material) UF is arranged between the semiconductor chip 10 and the wiring substrate 20. The underfill layer UF is arranged to block the space between the front surface 1t of the semiconductor chip 10 and the upper surface 20t of the wiring substrate 20. Each of the plurality of protruding electrodes 1BP is sealed by the underfill layer UF. The underfill layer UF is made of an insulating (non-conductive) material (e.g., a resin material) and is arranged to seal the electrical connection portion (bonding portion of the plurality of protruding electrodes 1BP) between the semiconductor chip 10 and the wiring substrate 20.

[0060] In this way, by sealing the joint portions between the plurality of protruding electrodes 1BP and the plurality of terminals 2PD with the underfill layer UF, it is possible to relieve stress generated in the electrical connection portion between the semiconductor chip 10 and the wiring substrate 20. The underfill layer UF can relieve stress generated at the joint portions between the plurality of electrodes 1PD and the plurality of protruding electrodes 1BP of the semiconductor chip 10. The underfill layer UF can protect the main surface of the semiconductor device (circuit element) forming the semiconductor chip 10.

[0061] exist Figures 1 to 3 Various modification examples of semiconductor devices are shown in FIG. Figure 3 In the example shown, a single semiconductor chip 10 is mounted on the wiring substrate 20. The number of semiconductor chips 10 mounted on the wiring substrate 20 is not limited to one, and there may be two or more. Figure 1 and 3 In the example shown, the back surface 1b of the semiconductor chip 10 is exposed. Figure 1 and 3As a modified example, there may be a case where a cover member serving as a heat dissipation member is attached to the back surface 1b of the semiconductor chip 10. In this case, the heat dissipation characteristics of the semiconductor device PKG1 can be improved. If the semiconductor chip 10 is covered with the cover member, the semiconductor chip 10 can be protected.

[0062] <Example of circuit configuration>

[0063] Next, we will describe Figures 1 to 3 An example of a circuit configuration provided in the semiconductor device PKG1 shown. Figure 4 It shows that Figures 1 to 3 1 is an explanatory diagram of a configuration example of a circuit provided in a semiconductor device shown in FIG. Figure 4 , a plurality of circuits, a plurality of signal transmission paths, and a plurality of power supply paths provided in the semiconductor device PKG1 are partially schematically shown.

[0064] like Figure 4 As shown in FIG. 1 , the semiconductor chip 10 of the semiconductor device PKG1 of the present embodiment has an input / output circuit IO1. Figure 4 In the illustrated example, the semiconductor chip 10 has an input / output circuit IO1 and a core circuit CC1 electrically coupled to the input / output circuit IO1 .

[0065] The input / output circuit IO1 includes, for example, a SerDes (Serializer Deserializer) circuit, which is equipped with a function of converting parallel signals and serial signals into each other. In other words, the SerDes circuit included in the input / output circuit IO1 is a circuit capable of converting from a serial signal to a parallel signal and from a parallel signal to a serial signal.

[0066] exist Figure 4 In the example shown, the signal SG1 input to the input / output circuit IO1 from the outside through the wiring substrate 20 is, for example, a serial signal. Moreover, the signal SG2 output from the input / output circuit IO1 to the outside through the wiring substrate 20 is, for example, a serial signal. On the other hand, the signals SG3 and SG4 transmitted between the input / output circuit IO1 and the core circuit CC1 are, for example, parallel signals. Since the semiconductor chip 10 is equipped with the input / output circuit IO1 including the SerDes circuit, it can adopt different transmission methods in signal transmission inside the semiconductor chip 10 and signal transmission between the semiconductor chip 10 and external devices.

[0067] Moreover, in Figure 4In the example shown, the semiconductor chip 10 has an input / output circuit IO2. The input / output circuit IO2 and the core circuit CC1 are electrically connected. The input / output circuit IO2 is, for example, an interface circuit for a DDR (double data rate) memory. A signal SG5 is input from the outside to the input / output circuit IO2 through the wiring substrate 20. Moreover, the input / output circuit IO2 outputs a signal SG6, and the signal SG5 is transmitted to an external memory (not shown) through the wiring substrate 20.

[0068] The core circuit CC1 performs data processing (e.g., arithmetic processing) on ​​the signal SG3 transmitted from the input / output circuit IO1, and outputs a signal SG4. The signal SG4 is converted into a signal SG2 in the input / output circuit IO1, and is transmitted to an external device. Similarly, the core circuit CC1 performs data processing (e.g., arithmetic processing) on ​​the signal SG7 transmitted from the input / output circuit IO2, and outputs a signal SG8. The signal SG8 is transmitted to the input / output circuit IO2. Figure 4 , a signal SG6 outputted by the input / output circuit IO2 and a signal SG8 outputted by the core circuit CC1 are distinguished. However, the signal SG6 and the signal SG8 may be the same signal.

[0069] exist Figure 4 In the example shown, each of the input / output circuits IO1 and IO2 is coupled to the same core circuit CC1. However, the number of core circuits CC1 provided in the semiconductor chip 10 is not limited to one, and there may be a plurality of core circuits CC1. Moreover, the input / output circuits IO1 and IO2 may be coupled to different core circuits CC1, respectively.

[0070] The semiconductor device PKG1 has a path for supplying a voltage to drive a plurality of circuits (the input / output circuit IO1 , the input / output circuit IO2 , and the core circuit CC1 ) provided in the semiconductor chip 10 .

[0071] Specifically, the semiconductor device PKG1 has a power supply potential supply path PVD1 for supplying the power supply potential VD1 to the input / output circuit IO1 and a reference potential supply path PVS1 for supplying the reference potential VS1 to the input / output circuit IO1 .

[0072] The semiconductor device PKG1 has a power supply potential supply path PVD2 for supplying the power supply potential VD2 to the input / output circuit IO2 and a reference potential supply path PVS2 for supplying the reference potential VS2 to the input / output circuit IO2.

[0073] The semiconductor device PKG1 has a power supply potential supply path PVD3 for supplying a power supply potential VD3 to the core circuit CC1 and a reference potential supply path PVS3 for supplying a reference potential VS3 to the core circuit CC1 .

[0074] exist Figure 4 In the case of , an example is shown in which different potentials are supplied to the input / output circuit IO1, the input / output circuit IO2, and the core circuit CC1. However, it is not limited to the case where the potentials to be supplied to the plurality of circuits are different from each other. For example, some or all of the power supply potentials VD1, VD2, and VD3 may be the same potential. Similarly, some or all of the reference potentials VS1, VS2, and VS3 may be the same potential.

[0075] Note that each of the reference potentials VS1 , VS2 , and VS3 is a potential different from the power supply potentials VD1 , VD2 , and VD3 , but may be a potential different from the ground potential.

[0076] <Electrode layout of semiconductor chips>

[0077] Next, the electrode layout of the semiconductor chip will be described. Figure 5 yes Figure 3 A plan view of the electrode arrangement surface of a semiconductor chip is shown. Figure 6 yes Figure 5 An enlarged plan view of portion A is shown. Figure 7 and 8 is shown with Figure 5 A plan view of an inspection example related to the layout of multiple protruding electrodes is shown. Fig. 9 It is along Figure 6 An enlarged cross-sectional view of line BB is shown.

[0078] Generally, the electrodes of a semiconductor chip are not arranged in the central region (including the center) of the semiconductor chip in a plan view, but are arranged in a peripheral region surrounding the central region. With the demand for miniaturization (reducing the plane size) of semiconductor chips, when electrodes are arranged only in the peripheral region, there is a tendency that there is insufficient space for electrode arrangement.

[0079] Therefore, if Figures 5 to 8 As shown, an area array method is being considered in which electrodes are regularly arranged on the entire main surface of a semiconductor chip, including a central area and a peripheral area. The central area of ​​a semiconductor chip is an area where main circuits such as a core circuit are arranged, and is called an active area. Therefore, the electrode arrangement method by the area array method can be called PAA (pad on active area).

[0080] From the viewpoint of maximizing the arrangement density of the electrodes, it is preferred that Figure 7 As in the semiconductor chip 10C1 shown in FIG. 1 , all the protruding electrodes 1BP are arranged at the minimum allowable pitch. However, due to various circumstances, there may be a case where it is difficult to arrange all the protruding electrodes 1BP at the same pitch as each other.

[0081] For example, when a component such as a coil or a capacitor is arranged in a portion of the semiconductor chip 10 , there may be an area where it is difficult to arrange the protruding electrodes 1BP around the component, and the pitch of some protruding electrodes 1BP may be different from that of other protruding electrodes 1BP.

[0082] Alternatively, if some of the plurality of circuits included in the semiconductor chip 10 are Figure 4 If the input / output circuit IO1, input / output circuit IO2 and core circuit CC1 shown are standardized circuits, the layout of the protruding electrode 1BP can be defined by the standard. A standardized circuit refers to a circuit block whose specifications and the specifications of the circuit components constituting the circuit have been standardized to enhance the versatility of circuits with specific functions. Such a circuit block can be called an IP (intellectual property) circuit. For example, Figure 4 The input / output circuit IO1 shown is standardized including the arrangement method of the protruding electrodes in the circuit block specification.

[0083] Since the circuit scale of an integrated circuit is large, it takes a considerable amount of time to design all circuit blocks from the beginning. By including standardized circuit blocks such as IP circuits in a part of an integrated circuit, the efficiency of the design can be improved.

[0084] A standardized circuit (such as an input / output circuit IO1 or an input / output circuit IO2) is generally an interface circuit that transmits signals between other circuits. The interface circuit is generally located in a peripheral area of ​​a semiconductor chip. By placing the interface circuit in the peripheral area, the signal transmission path can be shortened.

[0085] On the other hand, in the central region, the protruding electrode 1BP is often arranged, which mainly contacts the core circuit CC1 (reference Figure 4 )Supply power supply potential VD3 (reference Figure 4 ) or reference potential VS3 (reference Figure 4 ). The core circuit CC1 formed in the central area transmits a signal to an external device via the input / output circuit IO1 or the input / output circuit IO2.

[0086] In the case of a semiconductor chip 10 including a standardized circuit, it is difficult to arrange all the protruding electrodes 1BP at the same pitch as each other. Figure 8In the case of the semiconductor chip 10C2 shown, the pitch of some of the protruding electrodes BP3 arranged in the peripheral region is wider than the pitch of the protruding electrodes BP1 arranged in the central region.

[0087] <Definition of terms related to electrode arrangement>

[0088] Hereinafter, the pitch at which the plurality of protruding electrodes 1BP are arranged is explained. In this specification, terms such as "staggered arrangement", "pitch", "component along the X direction of the pitch", and "component along the Y direction of the pitch" may be used. Each term is defined as follows.

[0089] First, "staggered arrangement" is like Figure 5 The arrangement is shown enlarged in Figure 5 In FIG. 1 , if the X direction is defined as a row direction and the Y direction is defined as a column direction, the plurality of protruding electrodes 1BP are arranged as follows.

[0090] That is, the plurality of protruding electrodes 1BP are arranged in a plurality of columns in the Y direction. Figure 5 , there are shown a plurality of protruding electrodes 51 arranged in column RW1, a plurality of protruding electrodes 52 arranged in column RW2 adjacent to column RW1, a plurality of protruding electrodes 53 arranged in column RW3 adjacent to column RW2, and a plurality of protruding electrodes 54 arranged in column RW4 adjacent to column RW3.

[0091] Figure 5 The plurality of protruding electrodes 1BP shown are arranged in a staggered manner. Therefore, in the row direction (ie, the X direction), the center of each of the plurality of protruding electrodes 52 is located between adjacent protruding electrodes 51 (in the X direction). Figure 5 Similarly, in the X direction, the center of each of the plurality of protruding electrodes 53 is located between adjacent protruding electrodes 52 (in the middle of Figure 5 In the X direction, the center of each of the plurality of protruding electrodes 54 is located between adjacent protruding electrodes 53 (in the middle of Figure 5 in the middle).

[0092] On the other hand, in the X direction, the center of each of the plurality of protruding electrodes 53 is located at the same position as the center of each of the plurality of protruding electrodes 51. Similarly, in the X direction, the center of each of the plurality of protruding electrodes 54 is located at the same position as the center of each of the plurality of protruding electrodes 52.

[0093] This type of arrangement is called a "staggered arrangement". Figure 2As shown, an arrangement method in which a plurality of solder balls SB are arranged in rows and columns along the X and Y directions is referred to as a "matrix arrangement".

[0094] In the case of the staggered arrangement, the interval between the protruding electrodes arranged in a row and the protruding electrodes arranged in the row next to it can be widened compared to the matrix arrangement, which can increase the arrangement density of the objects to be arranged. Therefore, in the present embodiment, each of the plurality of protruding electrodes 1BP is arranged in a staggered manner to increase the arrangement density of the plurality of protruding electrodes 1BP.

[0095] However, the arrangement method of the plurality of protruding electrodes 1BP is not limited to the staggered arrangement, and as a modification example, some or all of the plurality of protruding electrodes 1BP may be arranged by a matrix arrangement.

[0096] The "pitch" of the protruding electrode 1BP refers to the center-to-center distance between one protruding electrode 1BP and the protruding electrode 1BP closest to the protruding electrode among the plurality of protruding electrodes 1BP. Figure 5 In the illustrated example, the center-to-center distance between the protruding electrode 51 and the protruding electrode 52 closest to the protruding electrode 51 is illustrated as a pitch PXY.

[0097] The "component of the pitch in the X direction" of the protruding electrode 1BP refers to the component of the pitch PXY in the X direction. Figure 5 In the illustrated example, the pitch component between the protruding electrode 51 and the protruding electrode 52 along the X direction is illustrated as a distance PX.

[0098] The "component of the pitch in the Y direction" of the protruding electrode 1BP refers to the component of the pitch PXY in the Y direction. Figure 5 In the illustrated example, the pitch component between the protruding electrode 51 and the protruding electrode 52 along the Y direction is illustrated as a distance PY.

[0099] <Differences between the Inspection Example and the Present Embodiment>

[0100] Next, we will explain Figure 5 and 6 The semiconductor chip 10 and Figure 8 The similarities and differences between the semiconductor chips 10C2 shown.

[0101] like Fig. 9 As shown, the semiconductor chip 10 includes a semiconductor substrate 11, a wiring portion DP, a wiring layer RDL, an insulating layer 12, and a protruding electrode 1BP. The semiconductor substrate 11 has a surface (main surface) 11t. On the surface 11t, a semiconductor element such as a transistor or a diode (not shown) is formed.

[0102] The wiring portion DP of the semiconductor chip 10 has a plurality of stacked wiring layers. Except for the wiring layer in the top layer (the wiring layer farthest from the surface 11t) among the plurality of wiring layers and the plug connected to the semiconductor element, the wiring layer is made of, for example, copper or a copper alloy. Between the plurality of wiring layers, an inorganic insulating layer such as silicon oxide is inserted. A pad (not shown) made of, for example, aluminum is formed on the wiring layer in the top layer of the wiring portion DP.

[0103] The wiring layer RDL is formed on the surface 11t of the semiconductor substrate 11 (specifically, formed on the wiring portion DP located on the surface 11t). The wiring layer RDL is electrically connected to the semiconductor element formed on the surface 11t of the semiconductor substrate 11 through the wiring portion DP. Fig. 9 , an example of a conductor pattern formed on the wiring layer RDL is illustrated as an electrode 1PD. In addition to the electrode 1PD, the wiring layer RDL also has a wiring pattern connected to the electrode 1PD and the like.

[0104] When a distinction is made between the wiring portion DP and the wiring layer RDL, the wiring layer RDL may be referred to as a rewiring layer. The wiring layer RDL is made of, for example, copper or a copper alloy. The pad formed on the topmost layer of the wiring portion DP and the electrode 1PD are electrically connected through wiring formed on the wiring layer RDL.

[0105] The insulating layer 12 has a surface 12b facing the surface 11t of the semiconductor substrate 11 and a surface 12t on the opposite side of the surface 12b, and is arranged to cover the wiring layer RDL. The insulating layer 12 has a function of ensuring electrical insulation of the plurality of protruding electrodes 1BP and a function as a protective film for protecting the wiring layer RDL. From the viewpoint of improving the flatness of the surface 12t of the insulating layer 12, the insulating layer 12 is an organic insulating layer made of, for example, a polyimide resin. However, as a modified example, there may be a case where the insulating layer 12 is an inorganic insulating layer.

[0106] A plurality of openings are formed in the insulating layer 12. Each of the plurality of electrodes 1PD provided on the wiring layer RDL is located at a position overlapping any one of the plurality of openings formed in the insulating layer 12. Each of the plurality of electrodes 1PD is exposed from the insulating layer 12 at a position overlapping with the opening. In the opening, an under bump metal (UBM) of a base metal film as a protruding electrode 1BP, which is a solder bump, is formed. The plurality of protruding electrodes 1BP and the plurality of electrodes 1PD are electrically connected through the base metal film UBM.

[0107] use Fig. 9 The structure of the semiconductor chip 10 explained is also similar to Figure 8 The semiconductor chips 10C2 shown are identical.

[0108] like Figure 5 and 8 As shown in each of the figures, the surface 12t of the insulating layer 12 has a side 1s1 extending along the X direction, a side 1s2 located on the opposite side of the side 1s1, a side 1s3 extending along the Y direction intersecting the X direction, and a side 1s4 located on the opposite side of the side 1s3.

[0109] exist Figure 5 In the case of the semiconductor chip 10 shown, the surface 12t of the insulating layer 12 includes a region R1 located between the side 1s1 and the side 1s2, a region R2 located between the side 1s1 and the region R1 and next to the region R1, and a region R3 located between the side 1s1 and the region R2 and next to the region R2.

[0110] like Figure 6 As shown, the plurality of protruding electrodes 1BP include a plurality of protruding electrodes BP1 arranged at positions overlapping with the region R1, a plurality of protruding electrodes BP2 arranged at positions overlapping with the region R2, and a plurality of protruding electrodes BP3 arranged at positions overlapping with the region R3.

[0111] Each of the plurality of protruding electrodes BP3 is connected to Figure 4 The input / output circuit IO1 of the semiconductor chip 10 is shown to be electrically connected. Figure 6 Each of the plurality of protruding electrodes BP1 and BP2 shown has a different Figure 4 The circuits of the input / output circuit IO1 (eg, core circuit CC1 ) are shown to be electrically connected.

[0112] like Figure 6 As shown, a plurality of protruding electrodes BP1 are arranged at a pitch P11. A plurality of protruding electrodes BP2 are arranged at a pitch P22 wider than the pitch P11. A plurality of protruding electrodes BP3 are arranged at a pitch different from each of the pitches P11 and P22. In the Y direction perpendicular to the X direction, the component of the pitch P22 in the Y direction (distance P2Y) is greater than the component of the pitch P11 in the Y direction (distance P1Y).

[0113] On the other hand, Figure 8 In the case of the semiconductor chip 10C2 shown, a blank region RBL where no protruding electrode 1BP is arranged is provided between the region R1 and the region R3. Figure 5 The semiconductor chip 10 shown is Figure 8 The semiconductor chip 10C2 shown is different.

[0114] According to the research of the present inventor, it has been found that when using Figure 8 In the case of the semiconductor device of the semiconductor chip 10C2 shown in FIG. Fig. 9The insulating layer 12 and the bottom fill layer UF are shown to form gaps. It has been found that gaps are likely to appear Figure 8 The blank area RBL is shown nearby.

[0115] According to the research of the present inventors, the cause of the void is presumed to be as follows. The manufacturing process of the semiconductor device includes a cleaning process for cleaning residues remaining around the plurality of protruding electrodes 1BP after mounting the semiconductor chip 10 on the wiring substrate 20 with a cleaning liquid, and a drying process for removing the cleaning liquid. In the drying process, it is preferred to remove all moisture, but it has been found that in the drying process, the voids are Figure 8 Near the blank area RBL shown, some moisture is difficult to remove and cleaning residues are likely to appear. Fig. 9 As shown, cleaning residues may appear in the gap between the protruding electrode 1BP and the insulating layer 12.

[0116] The voids are caused by such cleaning residues, and it is considered that the cleaning residues (ie, voids) generated in the gap between the protruding electrode 1BP and the insulating layer 12 reduce the underfill layer UF (see Figure 3 ) and the adhesion between the insulating layer 12. Figure 8 In the blank region RBL of the semiconductor chip 10C2 shown, the distance between the region R1 where the plurality of protruding electrodes BP1 are arranged and the region R3 where the plurality of protruding electrodes BP3 are arranged is wider than the pitch of the plurality of protruding electrodes BP1 and the pitch of the plurality of protruding electrodes BP3.

[0117] There is no particular problem when the volume of the void is small, but when the volume of the void is large, there is a possibility that the adjacent protruding electrodes 1BP may be short-circuited. Therefore, if residual moisture causing the void can be suppressed, the reliability of the semiconductor device can be improved.

[0118] exist Figure 6 In the case of the semiconductor chip 10 according to the present embodiment shown in FIG. 1 , a region R2 where a plurality of protruding electrodes BP2 are arranged is provided between a region R1 where a plurality of protruding electrodes BP1 are arranged and a region R3 where a plurality of protruding electrodes BP3 are arranged. In the case of the semiconductor chip 10, by adjusting the pitch P22 of the plurality of protruding electrodes BP2 arranged in the region R2, the area of ​​the gap where the protruding electrodes BP2 are not arranged can be reduced. Therefore, in the semiconductor device PKG1 (see FIG. 1 ) using the semiconductor chip 10, Figure 3 ), the occurrence of voids can be suppressed, thereby improving reliability.

[0119] In the following description, like the protruding electrode BP2 , the protruding electrode 1BP arranged to reduce a wide gap occurring between the protruding electrode BP3 arranged in the region R3 and the protruding electrode BP1 arranged in the region R1 may be referred to as an array adjustment protruding electrode 1BP.

[0120] like Figure 5 and 6 As shown, the plurality of protruding electrodes BP3 are arranged in the peripheral region of the semiconductor chip 10. In other words, among the plurality of protruding electrodes 1BP, the plurality of protruding electrodes BP3 include the protruding electrode 1BP arranged at a position closest to the side surface 1s1. Since the plurality of protruding electrodes BP3 are arranged in the peripheral region of the semiconductor chip 10, even if moisture accumulates between the protruding electrodes BP3 and the insulating layer 12, the moisture can be easily removed by a drying process.

[0121] Figure 6 The pitch P33 shown is different from the pitch P11 and the pitch P22. Figure 6 In the example shown, the pitch P33 is even wider than the pitch P22. However, as a modified example, there may be a case where the pitch P33 is narrower than the pitch P22.

[0122] As described above, the circuit to which each of the plurality of protruding electrodes BP3 is electrically connected is the input / output circuit IO1 (see Figure 4 ). Therefore, by arranging a plurality of protruding electrodes BP3 in the peripheral region of the semiconductor chip 10, the path length of the signal transmission path can be shortened.

[0123] exist Figure 6 In the example shown, the plurality of protruding electrodes BP2 are arranged in three rows in the Y direction. The number of rows of the plurality of protruding electrodes BP2 in the Y direction is not limited to three. Fig.11 In the case of the semiconductor chip 10A shown (to be described later as a modified example), the plurality of protruding electrodes BP2 arranged in the region R2 are arranged in two rows in the Y direction. Moreover, the plurality of protruding electrodes BP5 arranged in the region R5 are arranged in four rows in the Y direction. Although not shown, as a further modified example, there may be a case where the plurality of protruding electrodes BP2 or the plurality of protruding electrodes BP5 are arranged in five or more rows in the Y direction.

[0124] However, in the case of the present embodiment, the area of ​​the gap is reduced by adjusting the component of the pitch P22 in the Y direction. Therefore, it is preferred that the number of rows of the plurality of protruding electrodes BP2 in the Y direction is two or more. Moreover, if the number of rows of the plurality of protruding electrodes BP2 in the Y direction becomes very large, the area of ​​the region R1 where the plurality of protruding electrodes BP1 are arranged is reduced. From the viewpoint of increasing the arrangement density of the protruding electrodes 1BP, it is preferred that the area of ​​the region R1 is large. Therefore, it is preferred that the number of rows of the plurality of protruding electrodes BP2 in the Y direction is, for example, five or less.

[0125] Moreover, in the case of the present embodiment, strictly speaking, the area of ​​the gap is reduced by adjusting the component of the pitch P22 in the Y direction. Therefore, at least, if the component of the pitch P22 in the Y direction (distance P2Y) is longer than the component of the pitch P11 in the Y direction (distance P1Y), the value of the component of the pitch P22 in the X direction (distance P1X) can be set arbitrarily. Figure 6 In the example shown, pitch P22 is wider than pitch P11. However, as a modified example, depending on the value of the component of pitch P22 in the X direction (distance P2X), there may be a case where pitch P22 is the same as pitch P11 or pitch P22 is narrower than pitch P11. From the perspective of easy adjustment for filling the gap area, it is preferred that the component of pitch P22 in the X direction (distance P2X) is wide. Therefore, as Figure 6 As shown, when the pitch P22 is wider than the pitch P11, it is easier to adjust to fill the gap.

[0126] like Figure 6 As shown, each of the plurality of protruding electrodes BP1 and the plurality of protruding electrodes BP2 is arranged in a staggered manner. From the viewpoint of increasing the arrangement density of the protruding electrodes 1BP, it is preferable that they are arranged in a staggered manner as in the present embodiment.

[0127] exist Figure 6 In the example shown, the component of pitch P11 in the X direction (distance P1X) and the component of pitch P11 in the Y direction (distance P1Y) are equal to each other. The component of pitch P22 in the X direction (distance P2X) and the component of pitch P22 in the Y direction (distance P2Y) are equal to each other. The component of pitch P33 in the X direction (distance P3X) and the component of pitch P33 in the Y direction (distance P3Y) are equal to each other.

[0128] exist Figure 6In the example shown, the minimum pitch (pitch P12min) between one protruding electrode BP1 among the plurality of protruding electrodes BP1 and one protruding electrode BP2 among the plurality of protruding electrodes BP2 is equal to or greater than the pitch P11. Moreover, the minimum pitch (pitch P23min) between one protruding electrode BP3 among the plurality of protruding electrodes BP3 and one protruding electrode BP2 among the plurality of protruding electrodes BP2 is equal to or greater than the pitch P11. Figure 6 The pitch P12min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP1 and one of the plurality of protruding electrodes BP2, which is located next to one of the plurality of protruding electrodes BP1. Similarly, Figure 6 The pitch P23min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP3 and one of the plurality of protruding electrodes BP2, which is located next to one of the plurality of protruding electrodes BP3.

[0129] In the case of the present embodiment, the pitch P11 of the plurality of protruding electrodes BP1 is set to an acceptable value from the perspective of preventing a short circuit between adjacent protruding electrodes BP1. Therefore, by making each of the pitches P12 and P23 equal to or greater than the pitch P11, a short circuit between the protruding electrode BP1 and the protruding electrode BP2 or between the protruding electrode BP3 and the protruding electrode BP2 can be prevented.

[0130] exist Figure 6 In the illustrated example, the ball diameter (the maximum value of the diameter in a plan view) of each of the plurality of protruding electrodes 1BP is approximately 100 μm.

[0131] Figure 6 Each of the distances P1X and P1Y shown is 92 μm. Therefore, the pitch P11 is 130 μm. Figure 6 Each of the distances P2X and P2Y shown is 104 μm. Therefore, the pitch P22 is 147 μm. Moreover, Figure 6 The pitch P12min shown is equal to the pitch P11. The pitch P23min is wider than the pitch P11 and is 134 μm.

[0132] On the other hand, it is preferable that the pitch ( Figure 6 The maximum value of the pitch P12max in the protrusion BP3 is equal to or smaller than the pitch P22. Furthermore, it is preferable that the pitch ( Figure 6 The maximum value of the pitch P23max) in is equal to or less than the pitch P22.

[0133] Figure 6 The pitch P12max shown is 135 μm, and the pitch P23max is 144 μm. Figure 6 In the modified example, there may be a case where one or both of pitch P12max and pitch P23max are narrower than pitch P22. Even in this case, if the average value of the center-to-center distance between protruding electrode BP1 and protruding electrode BP2 is equal to or smaller than pitch P22, residual moisture can be suppressed.

[0134] From the perspective of easy adjustment of the values ​​of pitch P12min, pitch P12max, pitch P23min, and pitch P23max, it is preferred that the value of pitch P22 is larger within a range where residual moisture is not generated. Therefore, by making each of pitch P12 and pitch P23 equal to or smaller than pitch P22, it is possible to prevent moisture from being left between region R1 and region R2 and between region R2 and region R3.

[0135] By the way, using Figure 6 , explains Figure 5 FIG. 1 is a diagram showing a layout of the protruding electrodes 1BP around the side surface 1s1 of the semiconductor chip 10. In the case of the semiconductor chip 10, as shown in FIG. Figure 5 As shown, the layout around the side 1s2 of the semiconductor chip 10 is the same as the layout around the side 1s1. Fig.10 yes Figure 5 An enlarged plan view of portion B is shown.

[0136] like Fig.10 As shown, in a plan view, the plurality of protruding electrodes 1BP include a plurality of protruding electrodes BP1 arranged at positions overlapping with the region R1, a plurality of protruding electrodes BP5 arranged at positions overlapping with the region R5, and a plurality of protruding electrodes BP6 arranged at positions overlapping with the region R6.

[0137] Each of the plurality of protruding electrodes BP6 is connected to Figure 4 The input / output circuit IO1 of the semiconductor chip 10 is shown to be electrically connected. Fig.10 Each of the plurality of protruding electrodes BP1 and BP5 shown has a different Figure 4 The circuits of the input / output circuit IO1 (eg, core circuit CC1 ) are shown to be electrically connected.

[0138] like Fig.10As shown, a plurality of protruding electrodes BP1 are arranged at a pitch P11. A plurality of protruding electrodes BP5 are arranged at a pitch P55 wider than the pitch P11. A plurality of protruding electrodes BP6 are arranged at a pitch different from both the pitch P11 and the pitch P55. In the Y direction perpendicular to the X direction, the component of the pitch P55 in the Y direction (distance P5Y) is greater than the component of the pitch P11 in the Y direction (distance P1Y).

[0139] As reference Figure 6 Explain the relationship between pitch P11 and pitch P22, if Fig.10 If the component of pitch P55 in the Y direction (distance P5Y) is longer than the component of pitch P11 in the Y direction (distance P1Y), the value of the component of pitch P55 in the X direction (distance P5X) can be set arbitrarily. Fig.10 In the example shown, pitch P55 is wider than pitch P11. However, as a modified example, pitch P55 may be the same as pitch P11 or pitch P55 may be narrower than pitch P11, depending on the value of the component of pitch P55 in the X direction (distance P5X). Fig.10 As shown, when pitch P55 is wider than pitch P11, it is easier to adjust to fill the gap.

[0140] According to the research of the present inventors, it was found that the degree of residual moisture in the drying process varies depending on the drying method. That is, in the drying process, there may be a case where drying is performed by blowing air in one direction. In this case, the degree of moisture removal varies depending on the direction of the wind used for drying.

[0141] For example, in Figure 8 In the case of the semiconductor chip 10C2 shown, when air is blown from the side 1s2 toward the side 1s1 along the Y direction, moisture tends to remain around the blank area RBL1 relatively close to the edge 1s1 of the two blank areas RBL. On the other hand, moisture is less likely to remain around the blank area RBL2 relatively close to the side 1s2. Therefore, voids are less likely to occur around the blank area RBL2.

[0142] Considering this finding, as Figure 5 As a modified example of the semiconductor chip 10 shown, it is conceivable that the structure around the side 1s2 is different from Figure 8 The structure of the semiconductor chip 10C2 shown in FIG. 1 is the same as that of the semiconductor chip 10C2 shown in FIG. Figure 8 The area corresponding to the blank area RBL2 shown is also less likely to have voids due to residual moisture by blowing air from the side 1s2 to the side 1s1 along the Y direction during the drying process.

[0143] On the other hand, Figure 5In the case of the semiconductor chip 10 shown, as described above, the structure around the side 1s2 and the structure around the side 1s1 are similar to each other. Therefore, in the case of the semiconductor chip 10, the void can be suppressed regardless of the drying method.

[0144] Preferably, Fig.10 The layout and use of the protruding electrodes BP5 and BP6 shown Figure 6 The layouts of the explained protruding electrodes BP2 and BP3 are the same.

[0145] like Figure 5 and 10 As shown, the plurality of protruding electrodes BP6 arranged in the region R6 are arranged in the peripheral region of the semiconductor chip 10. In other words, among the plurality of protruding electrodes 1BP, the plurality of protruding electrodes BP6 include the protruding electrode 1BP arranged at a position closest to the side surface 1s2.

[0146] Fig.10 The pitch P66 shown is different from the pitch P11 and the pitch P55. Fig.10 In the example shown, pitch P66 is even wider than pitch P55. However, as a modified example, there may be a case where pitch P66 is narrower than pitch P55.

[0147] The circuit to which each of the plurality of protruding electrodes BP6 is electrically connected is an input / output circuit IO1 (reference Figure 4 ). Therefore, by arranging a plurality of protruding electrodes BP6 in the peripheral region of the semiconductor chip 10, the path length of the signal transmission path can be shortened.

[0148] exist Fig.10 In the example shown, the plurality of protruding electrodes BP5 are arranged in three rows in the Y direction. The number of rows of the plurality of protruding electrodes BP5 in the Y direction is not limited to three rows, and there may be two rows or four or more rows, for example.

[0149] like Fig.10 As shown, each of the plurality of protruding electrodes BP1 and the plurality of protruding electrodes BP5 is arranged in a staggered manner. Fig.10 In the example shown, the component of pitch P55 in the X direction (distance P5X) and the component of pitch P55 in the Y direction (distance P5Y) are equal to each other. The component of pitch P66 in the X direction (distance P6X) and the component of pitch P66 in the Y direction (distance P6Y) are equal to each other.

[0150] exist Fig.10In the example shown, the minimum pitch (pitch P15min) between one protruding electrode BP1 among the plurality of protruding electrodes BP1 and one protruding electrode BP5 among the plurality of protruding electrodes BP5 is equal to or greater than the pitch P11. Moreover, the minimum pitch (pitch P56min) between one protruding electrode BP6 among the plurality of protruding electrodes BP6 and one protruding electrode BP5 among the plurality of protruding electrodes BP5 is equal to or greater than the pitch P11. Fig.10 The pitch P15min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP1 and one of the plurality of protruding electrodes BP5, which is located next to one of the plurality of protruding electrodes BP1. Similarly, Fig.10 The pitch P56min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP6 and one of the plurality of protruding electrodes BP5 , which is located next to one of the plurality of protruding electrodes BP6 .

[0151] On the other hand, the pitch ( Fig.10 The maximum value of the pitch P15max in the protruding electrode BP5 is equal to or less than the pitch P55, and the protruding electrode BP5 is located next to one of the protruding electrodes BP1 in the plurality of protruding electrodes BP1. Moreover, the pitch ( Fig.10 The maximum value of the pitch P56max) in the protruding electrode BP5 is equal to or smaller than the pitch P55, and the protruding electrode BP5 is located next to a protruding electrode BP6 among multiple protruding electrodes BP6.

[0152] <First Modification Example>

[0153] Next, we will describe Figure 5 A modified example of the semiconductor chip 10 is shown. Fig.11 It is a plan view of the electrode arrangement surface of a semiconductor chip. Figure 5 's modified example. Fig.12 yes Fig.11 An enlarged plan view of portion C is shown.

[0154] exist Fig.11 and 12 As about Figure 5 and 6 As a modified example of the semiconductor device PKG1 having the semiconductor chip 10 shown, a semiconductor device PKG2 having the semiconductor chip 10A is shown. Fig.11 and 12The surface 12t of the insulating layer 12 of the semiconductor chip 10A shown includes a side surface 1s3 extending in the Y direction and a region R4 located between the side surface 1s3 and the region R1. Figure 5 The semiconductor chips 10 shown are identical.

[0155] The plurality of protruding electrodes 1BP include a protruding electrode BP4 arranged at a position overlapping with the region R4 in a plan view. Each of the plurality of protruding electrodes BP4 is connected to a circuit (eg, Figure 4 The input / output circuit IO2 shown in FIG. 1 is electrically connected to the plurality of protruding electrodes BP1 and each of the plurality of protruding electrodes BP2 (reference Fig.11 ) are all connected to circuits other than the input / output circuit IO2 (e.g. Figure 4 The core circuit CC1) shown is electrically connected.

[0156] The plurality of protruding electrodes BP4 are arranged at a pitch P44. The value of the pitch P44 and the value of the pitch P11 are the same as each other. That is, they are arranged at the same pitch P11 as the plurality of protruding electrodes BP1. Moreover, in both the X direction and the Y direction, the plurality of protruding electrodes BP4 are arranged at the same pitch as the plurality of protruding electrodes BP1.

[0157] In detail, Fig.12 As shown, each of the plurality of protruding electrodes BP4 is arranged at a pitch P44. Moreover, each of the plurality of protruding electrodes BP1 is arranged at a pitch P11. In the case of the semiconductor chip 10A, the distance P4X as a component of the pitch P44 in the X direction is equal to the distance P1X as a component of the pitch P11 in the X direction, and the distance P4Y as a component of the pitch P44 in the Y direction is equal to the distance P1Y as a component of the pitch P11 in the Y direction. Moreover, the pitch P14 between the protruding electrode BP1 and the protruding electrode BP4 adjacent to each other is equal to each of the pitch P11 and the pitch P44.

[0158] If used Figure 8 Explained, as we all know, in Figure 8 A gap that reduces the reliability of the semiconductor device is easily formed around the blank area RBL shown. In this modified example, since the plurality of protruding electrodes BP4 are arranged at the same pitch as the plurality of protruding electrodes BP1 in the X direction and the Y direction, it is possible to prevent gaps where no protruding electrodes are arranged, such as Figure 8 The blank area RBL is shown.

[0159] At the same time, Figure 5In the case of the semiconductor chip 10 shown, the circuit connected to the plurality of protruding electrodes BP4 is not an IP circuit, for example, but a circuit newly designed with a layout of at least one protruding electrode 1BP according to the specification of the semiconductor chip 10. Figure 5 In the case of the semiconductor chip 10 shown in FIG. 1 , the plurality of protruding electrodes BP4 are arranged at the same pitch P1 (see FIG. 1 ) as the plurality of protruding electrodes BP1 in the X direction and the Y direction. Figure 6 ) arrangement.

[0160] On the other hand, Fig.11 and 12 In the case of the semiconductor chip 10A shown in FIG. 1 , the input / output circuit IO2 (see FIG. 1 ) connected to the plurality of protruding electrodes BP4 is Figure 4 ) is, for example, the interface circuit for DDR memory mentioned above. Memory interface circuits are usually IP circuits because they are often incorporated into various integrated circuits. In this modified example, the input / output circuit IO2 is a standardized IP circuit.

[0161] Therefore, in this modification example, in order to arrange the plurality of protruding electrodes BP4 at the same pitch as the plurality of protruding electrodes BP1 , it is necessary to align the layout of the plurality of protruding electrodes BP1 with the layout of the plurality of protruding electrodes BP4 .

[0162] The semiconductor chip 10A of this modification example is designed so that the layout of the plurality of protruding electrodes BP1 is the same as the layout of the plurality of protruding electrodes BP4. Figure 6 Unlike the illustrated case, in this modified example, the values ​​of the distance P1X and the distance P1Y are different.

[0163] exist Fig.12 In the example shown, the component of pitch P11 along the Y direction (distance P1Y) is longer than the component of pitch P11 along the X direction (distance P1X). Also, the component of pitch P44 along the Y direction (distance P4Y) is longer than the component of pitch P44 along the X direction (distance P4X).

[0164] exist Fig.12 In the example shown, each of the distances P1X and P4X is, for example, 75 μm. On the other hand, each of the distances P1Y and P4Y is, for example, 110 μm.

[0165] In the case of a memory interface circuit, there are many signal transmission lines (hereinafter referred to as signal lines). Fig.12 As shown, in the wiring portion DP of the semiconductor chip (see Fig. 9 ) and the wiring layer of the wiring substrate 20 (see Fig. 9), there may be a case where one of the values ​​of the distance P1X and the distance P1Y is larger than the other in order to ensure a space for arranging a large number of signal lines.

[0166] On the other hand, a plurality of protruding electrodes BP1 are provided for Figure 4 The core circuit CC1 shown is connected to a power supply potential supply path PVD3 for supplying a power supply potential VD3 or to a reference potential supply path PVS3 for supplying a reference potential VS3 to the core circuit CC1.

[0167] In the case of a terminal for power supply, such as the protruding electrode BP1, unlike the signal transmission protruding electrode BP4, such as Figure 6 As shown, the values ​​of the distance P1X and the distance P1Y are usually equal. In the case of this modification example, in which the values ​​of the distance P1X and the distance P1Y are different, there are the following advantages.

[0168] Fig.13 It shows that the installation Fig.11 and 12 FIG. 1 is an enlarged plan view of an example of a layout of a topmost wiring layer of a wiring substrate of a semiconductor chip shown.

[0169] Fig.11 and 12 Each of the plurality of protruding electrodes BP1 shown is connected to the Figure 4 The core circuit CC1 is connected to a power supply potential supply path PVD3 for supplying a power supply potential, or a reference potential supply path PVS3 for supplying a reference potential to the core circuit CC1.

[0170] exist Figure 3 and 13 On the wiring layer WL1 of the wiring substrate 20 shown in FIG. Fig.11 A plurality of terminals 2PD of any one of the plurality of protruding electrodes BP1, BP2 and BP3 are shown.

[0171] exist Fig.13 In the example shown, the wiring layer WL1 includes a plurality of power supply potential terminals PDD electrically connected to a power supply potential supply path PVD3 among a plurality of terminals 2PD and a plurality of reference potential terminals PDS electrically connected to a reference potential supply path PVS3 among a plurality of terminals 2PD. The wiring layer WL1 is connected to each of the plurality of power supply potential terminals PDD arranged along the X direction and includes a power supply potential wiring 2DD extending along the X direction. The wiring layer WL1 is connected to each of the plurality of reference potential terminals PDS arranged along the X direction and includes a reference potential wiring 2DS extending along the X direction.

[0172] In the Y direction, a plurality of power potential wirings 2DD and a plurality of reference potential wirings 2DS are alternately arranged. A plurality of power potential terminals PDD are electrically connected via the power potential wiring 2DD, thereby stabilizing the potential of the power potential supply path PVD3. Similarly, a plurality of reference potential terminals PDS are electrically connected via the reference potential wiring 2DS, thereby stabilizing the potential of the reference potential supply path PVS3.

[0173] If used Figure 6 As explained in the semiconductor chip 10 shown, the above configuration can be realized even when the value of the distance P1X is equal to the value of the distance P1X.

[0174] However, in this modified example, as Fig.12 As shown, the value of distance P1Y is greater than the value of distance P1X, so Fig.13 The layout of the plurality of terminals 2PD in the wiring layer WL1 shown is as follows. That is, in the Y direction (column direction), the component of the pitch PPD between adjacent terminals 2PD in the Y direction (distance PPDY) is longer than the component of the pitch PPD in the X direction (distance PPDX). Fig.13 In the example shown, the distance PPDX is, for example, 75 μm. On the other hand, the distance PPDY is, for example, 110 μm.

[0175] if Fig.13 If the distance PPDX and the distance PPDY shown in FIG. 1 are the same value, it is necessary to design the widths of the power supply potential wiring 2DD and the reference potential wiring 2DS to be narrow in order to prevent a short circuit between the power supply potential supply path VDD3 and the reference potential supply path VDS3. On the other hand, as in this modified example, if the distance PPDY is long, the short circuit problem between the power supply potential supply path VDD3 and the reference potential supply path VDS3 becomes smaller, so it is possible to widen the distance PPDY. Fig.13 The power supply potential wiring 2DD has a width W2DD and the reference potential wiring 2DS has a width W2DS.

[0176] For example, in Fig.13 In the example shown, each outer edge of the plurality of power potential terminals PDD forms an arc. The width W2DD of the power potential wiring 2DD in the Y direction is equal to or greater than the radius RPDD of the arc of the power potential terminal PDD. By widening the width W2DD of the power potential wiring 2DD, the potential of the power potential supply path PVD3 can be further stabilized.

[0177] exist Fig.13In the example shown, each outer edge of the plurality of reference potential terminals PDS forms an arc. The width W2DS of the reference potential wiring 2DS in the Y direction is equal to or greater than the radius RPDS of the arc of the reference potential terminal PDS. By widening the width W2DS of the reference potential wiring 2DS, the potential of the reference potential supply path PVS3 can be further stabilized.

[0178] In addition to the above differences, Fig.11 The semiconductor chip 10A shown is Figure 5 The semiconductor chip 10 shown is also different in the following points: That is, the plurality of protruding electrodes BP2 arranged in the region R2 are arranged in two rows in the Y direction. Also, the plurality of protruding electrodes BP5 arranged in the region R5 are arranged in four rows in the Y direction.

[0179] However, the positional relationship between the plurality of protruding electrodes BP2 and the plurality of protruding electrodes BP1 and the positional relationship between the plurality of protruding electrodes BP2 and the plurality of protruding electrodes BP3 are different from those using Figure 5 and 6 The positional relationship of the semiconductor chip 10 explained is the same as that of the semiconductor chip 10, so redundant explanation will be omitted. Similarly, the positional relationship between the plurality of protruding electrodes BP5 and the plurality of protruding electrodes BP1 and the positional relationship between the plurality of protruding electrodes BP5 and the plurality of protruding electrodes BP6 are the same as those of the semiconductor chip 10 explained using FIG. Figure 5 and 10 The positional relationship of the semiconductor chip 10 explained is the same, and thus redundant explanation will be omitted.

[0180] Furthermore, in addition to the differences mentioned above, using Fig.11 and 12 Explanation of semiconductor device PKG2 and Figure 5 and 6 The semiconductor device PKG1 shown is the same. Therefore, redundant explanation will be omitted.

[0181] <Second Modification Example>

[0182] Next, we will explain Figure 5 Other modified examples of the semiconductor chip 10 are shown.

[0183] Fig.14 yes Figure 5 FIG. 1 is a plan view of an electrode arrangement side of a semiconductor chip according to another modified example of FIG. 1 .

[0184] Fig.15 yes Fig.14 An enlarged plan view of portion D is shown.

[0185] exist Figure 5 The semiconductor device PKG1 and Fig.11In the case of the semiconductor device PKG2 shown in FIG. 1 , when the pitches between the plurality of protruding electrodes BP3 arranged in the region R3 as the peripheral region and the plurality of protruding electrodes BP1 arranged in the region R1 as the central region are different, the following method is used to prevent the occurrence of gaps. That is, in the case of the semiconductor device PKG1 and the semiconductor device PKG2, as shown in FIG. Figure 6 As shown, region R2 is provided between region R3 and region R1, and the component of the pitch P22 of the multiple protruding electrodes BP2 arranged in region R2 in the Y direction (distance P2Y) is longer than the component of the pitch P11 of the multiple protruding electrodes BP1 arranged in region R1 in the Y direction (distance P1Y).

[0186] On the other hand, Fig.14 In the case of the semiconductor device PKG3 shown in FIG. 1 , it is different from the semiconductor device PKG1 and the semiconductor device PKG2 in that Figure 5 The region R8 corresponding to the region R1 shown is adjacent to the region R3. Also, in the case of the semiconductor device PKG3, it is different from the semiconductor devices PKG1 and PKG2 in the following points. That is, the region R7 is provided in the region corresponding to the region R1. Figure 5 The region R1 shown in FIG. 1 is between the region R8 and the region R9 corresponding to the region R1. Fig.15 As shown, the component of the pitch P77 of the plurality of protruding electrodes BP7 arranged in the region R7 in the Y direction (distance P7Y) is longer than the component of the pitch P88 of the plurality of protruding electrodes BP8 arranged in the region R8 in the Y direction (distance P8Y). The plurality of protruding electrodes BP7 arranged in the region R7 are protruding electrodes 1BP for adjusting the arrangement to prevent a gap causing a void from occurring between the region R8 and the region R3.

[0187] Hereinafter, the configuration of the semiconductor device PKG3 will be described in detail. Figure 3 As shown, the semiconductor device PKG3 has a wiring substrate 20, a semiconductor chip 10B mounted on the wiring substrate 20 via a plurality of protruding electrodes 1BP, and an underfill layer UF arranged between the semiconductor chip 10B and the wiring substrate 20 and sealing the plurality of protruding electrodes 1BP.

[0188] like Fig. 9 As shown, the semiconductor chip 10B includes a semiconductor substrate 11 having a surface 11t and a wiring layer RDL formed on the surface 11t. In addition, the semiconductor chip 10B has an insulating layer 12, which is arranged to cover the wiring layer RDL and has a surface 12b facing the surface 11t of the semiconductor substrate 11, a surface 12t opposite to the surface 12b, and a plurality of protruding electrodes 1BP electrically connected to the wiring layer RDL.

[0189] like Fig.14 As shown, the surface 12t of the insulating layer 12 includes a side 1s1 extending in the X direction, a side 1s2 located on the opposite side of the side 1s1, a region R7 located between the side 1s1 and the side 1s2, a region R8 located between the side 1s1 and the region R7, and a region R3 located between the side 1s1 and the region R8.

[0190] The plurality of protruding electrodes 1BP include a protruding electrode BP7 arranged at a position overlapping with the region R7 in plan view, a protruding electrode BP8 arranged at a position overlapping with the region R8 in plan view, and a protruding electrode BP3 arranged at a position overlapping with the region R3 in plan view.

[0191] Each of the plurality of protruding electrodes BP3 is electrically connected to the input / output circuit IO1 (reference number 114) of the semiconductor chip 10B. Figure 4 Each of the plurality of protruding electrodes BP7 and the plurality of protruding electrodes BP8 is electrically connected to a circuit (eg, Figure 4 The core circuit CC1 shown).

[0192] like Fig.15 As shown, the plurality of protruding electrodes BP7 are arranged at a pitch P77. The plurality of protruding electrodes BP8 are arranged at a pitch P88 narrower than the pitch P77. Fig.14 ) with pitch P33 (reference Figure 6 ) is arranged, and the pitch P33 is different from each of the pitches P77 and P88. In the Y direction perpendicular to the X direction, the component of the pitch P88 in the Y direction (distance P8Y) is smaller than the component of the pitch P77 in the Y direction (distance P7Y).

[0193] exist Fig.15 In the example shown, the minimum pitch (pitch P78min) between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP8 is equal to or greater than the pitch P88. Fig.14 The minimum pitch (pitch P38min) between one of the plurality of protruding electrodes BP3 and one of the plurality of protruding electrodes BP8 is equal to or greater than Fig.15 Pitch P88 shown. Fig.15 The pitch P78min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP8, which is located next to one of the plurality of protruding electrodes BP7. Fig.14The pitch P38min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP3 and one of the plurality of protruding electrodes BP8 , which is located next to one of the plurality of protruding electrodes BP3 .

[0194] Fig.15 Each of the distances P8X and P8Y shown is 92 μm. Therefore, the pitch P88 is 130 μm. Fig.15 The distance P7X shown is 92 μm, and the distance P7Y is 108 μm. Therefore, the pitch P77 is 142 μm. Moreover, Fig.14 The pitch P38min shown is equal to the pitch P88. Fig.15 The pitch P78min shown is wider than the pitch P11 and is 124 μm.

[0195] In this way, in the case of the semiconductor device PKG3, a plurality of protruding electrodes BP7 are provided in the region R7 to easily adjust the distance between the plurality of protruding electrodes BP8 and the plurality of protruding electrodes BP3. Fig.14 The distance between the plurality of protruding electrodes BP3 and the plurality of protruding electrodes BP8 shown is controlled to be an appropriate distance, so the occurrence of the above-mentioned gaps can be suppressed.

[0196] like Figure 6 The relationship between pitch P11 and pitch P22 is explained in Fig.15 If the Y-direction component of pitch P88 (distance P8Y) is shorter than the Y-direction component of pitch P77 (distance P7Y), the value of the X-direction component of pitch P77 (distance P7X) can be set arbitrarily. Fig.15 In the example shown, pitch P88 is narrower than pitch P77. However, as a modified example, depending on the value of the component of pitch P77 in the X direction (distance P7X), there may be a case where pitch P77 is the same as pitch P88 or pitch P88 is wider than pitch P77. Fig.15 As shown, when pitch P77 is wider than pitch P88, it is easier to adjust to fill the gap.

[0197] In this modified example, Fig.14 As shown, the surface 12 t of the insulating layer 12 further includes a region R9 located between the side surface 1 s2 and the region R7 and a region R6 located between the side surface 1 s1 and the region R9 .

[0198] The plurality of protruding electrodes 1BP also include a protruding electrode BP7 arranged at a position overlapping with the region R7 in plan view, a protruding electrode BP9 arranged at a position overlapping with the region R9 in plan view, and a protruding electrode BP6 arranged at a position overlapping with the region R6 in plan view.

[0199] Each of the plurality of protruding electrodes BP6 is electrically connected to the input / output circuit IO1 (reference Figure 4 Each of the plurality of protruding electrodes BP7 and the plurality of protruding electrodes BP9 is electrically connected to a circuit (eg, Figure 4 The core circuit CC1 shown).

[0200] like Fig.15 As shown, the plurality of protruding electrodes BP9 are arranged at a pitch P99 which is narrower than the pitch P77. The plurality of protruding electrodes BP6 are arranged at a pitch P66 (reference Fig.10 In the Y direction perpendicular to the X direction, the component of the pitch P99 along the Y direction (distance P9Y) is smaller than the component of the pitch P77 along the Y direction (distance P7Y).

[0201] Note that with Figure 6 The relationship between pitch P11 and pitch P22 explained in Fig.15 If the component of pitch P99 in the Y direction (distance P9Y) is shorter than the component of pitch P77 in the Y direction (distance P7Y), the value of the component of pitch P77 in the X direction (distance P7X) can be set arbitrarily. Fig.15 In the example shown, pitch P99 is narrower than pitch P77. However, as a modified example, depending on the value of the component of pitch P77 in the X direction (distance P7X), there may be a case where pitch P99 is the same as pitch P77 or pitch P99 is wider than pitch P77. Fig.15 As shown, when pitch P77 is wider than pitch P99, it is easier to adjust to fill the gap.

[0202] Moreover, in Fig.15 In the example shown, the minimum pitch (pitch P79min) between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP9 is equal to or greater than the pitch P99. Fig.14 The minimum pitch (pitch P69min) between one protruding electrode BP6 among the plurality of protruding electrodes BP6 and one protruding electrode BP9 among the plurality of protruding electrodes BP9 is equal to or greater than Fig.15 Pitch P99 shown. Fig.15The pitch P79min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP9, which is located next to one of the plurality of protruding electrodes BP7. Fig.14 The pitch P69min shown is the minimum value of the pitch between one of the plurality of protruding electrodes BP6 and one of the plurality of protruding electrodes BP9 , which is located next to one of the plurality of protruding electrodes BP6 .

[0203] Fig.15 Each of the distances P9X and P9Y shown is 92 μm. Therefore, the pitch P99 is 130 μm. Fig.15 The distance P7X shown is 92 μm, and the distance P7Y is 108 μm. Therefore, the pitch P77 is 142 μm. Moreover, Fig.14 The pitch P69min shown is equal to the pitch P99. Fig.15 The pitch P79min shown is wider than the pitch P11 and is 124 μm.

[0204] The semiconductor device PKG3 of this modification example has a region R7 for array adjustment arranged between regions R8 and R9. Also, in the case of the semiconductor device PKG3, regions R8 and R3 are adjacent to each other, and regions R9 and R6 are adjacent to each other. Figure 5 The semiconductor device PKG1 or Fig.11 Compared with the semiconductor device PKG2 shown in the figure, it has the advantage that the arrangement space of the protruding electrode BP7 used for array adjustment can be reduced.

[0205] On the other hand, in terms of the ease of adjusting the interval between the protruding electrodes, Figure 5 The semiconductor device PKG1 or Fig.11 The semiconductor device PKG2 shown is advantageous.

[0206] <Method of Manufacturing Semiconductor Device>

[0207] Next, a brief explanation of a method for manufacturing the above-mentioned semiconductor device will be given. Here, as a representative example, Figure 5 The manufacturing method of the semiconductor device PKG1 shown in FIG. 1 will focus on the drying process related to the cause of the void mentioned above, and the explanation of other processes will be brief. Fig.16 It shows the manufacturing Figure 3 An explanatory diagram of an example of a flow chart of a method for implementing a semiconductor device shown in FIG.

[0208] like Fig.16As shown, the method for manufacturing a semiconductor device of the present embodiment includes a wiring substrate preparation process, a semiconductor chip preparation process, a semiconductor chip mounting process, an underfill filling process, a ball mounting process and a singulation process.

[0209] exist Fig.16 In the wiring substrate preparation process shown in FIG. Figure 3 The wiring substrate 20 shown. Note that the wiring substrate prepared in this process is a so-called multi-piece substrate in which a plurality of wiring substrates 20 are integrally formed.

[0210] exist Fig.16 In the semiconductor chip preparation process shown in FIG. Figure 1 , 3 , 4, 5, 6, 9 and 10. As a modified example, in this process, it is possible to prepare Fig.11 and 12 The semiconductor chip 10A shown in FIG. 10A is shown in FIG. 10A. In addition, as another modification example, there may be a case where Fig.14 and 15 The case of the semiconductor chip 10B is shown.

[0211] Fig.16 The semiconductor chip mounting process shown includes a chip placement process, a reflow process, a cleaning process, and a drying process.

[0212] In the chip placement process, such as Figure 3 As shown, the semiconductor chip 10 is placed on the upper surface 20t of the wiring substrate 20. In this process, a plurality of terminals 2PD and a plurality of protruding electrodes 1BP formed on the wiring substrate 20 are positioned to face each other. Moreover, for example, flux or a paste material mixed with solder may be applied in advance to each exposed surface of the plurality of terminals 2PD. Flux is a material including an activator that promotes bonding of solder and the terminal 2PD.

[0213] In the reflow process performed after the chip placement process, the temperature of the protruding electrode 1BP is heated to a temperature at which the solder included in the protruding electrode 1BP melts, and after the solder and the terminal 2PD have been wetted, the temperature is lowered. Through this process, a plurality of protruding electrodes 1BP and a plurality of terminals 2PD are bonded, respectively. At this time, residues such as flux, for example, may adhere to the periphery of the protruding electrode 1BP.

[0214] In order to prevent residues such as flux from being left in the product, a cleaning process is performed after the reflow process. In the cleaning process, water or a cleaning solution with a drug added thereto is continuously supplied to the gap between the semiconductor chip 10 and the wiring substrate 20, such as Figure 3 If moisture supplied during this process is left in the product, this may result in the voids mentioned above.

[0215] Next, in a drying process, moisture is removed by continuously supplying air (eg, warm air) to the gap between the semiconductor chip 10 and the wiring substrate 20, as shown in FIG. Figure 3 shown. Fig.17 It is schematically shown Fig.16 A plan view showing the direction of air supply during the drying process.

[0216] In the case of this embodiment, if Fig.17 As schematically shown by arrows in FIG. 1 , air VT is continuously sent in a direction from the side 1s2 to the side 1s1 of the semiconductor chip 10. In this case, drying is performed from a position closer to the side 1s2, and when drying is completed up to the side 1s1, the drying process ends.

[0217] The moisture left around the protruding electrode 1BP can be removed by evaporation, but can also be removed by being pushed out in the direction of the wind. Fig.17 In the case of the drying method shown, not only the area near the side 1s2 (corresponding to Figure 8 The blank area RBL2 shown in FIG. 1 and the area close to the side 1s1 (corresponding to Figure 8 The blank area RBL1 shown in FIG. 1 can suppress the occurrence of gaps. More specifically, in Fig.17 In the case of the semiconductor chip 10 shown, the occurrence of voids can be suppressed not only at the boundary between the region R6 and the region R5 and the boundary between the region R5 and the region R1 but also at the boundary between the region R1 and the region R2 and the boundary between the region R2 and the region R3 .

[0218] The same applies to Fig.11 The semiconductor chip 10A shown in FIG. Fig.15 In the case of the semiconductor chip 10B shown, the occurrence of voids can be suppressed at each of the boundaries between the region R6 and the region R9 , the region R9 and the region R7 , the region R7 and the region R8 , and the region R8 and the region R3 .

[0219] Through these results, when applying Fig.17 In the drying method shown in FIG. 1 , air VT is continuously sent from the side 1s2 to the side 1s1. Figure 5 , Fig.11 or Fig.15 The structure shown can particularly suppress the occurrence of voids.

[0220] Next, in the underfill filling process, a paste or liquid resin is supplied to the Figure 3The gap between the semiconductor chip 10 and the wiring substrate 20 shown in FIG. 1 and the plurality of protruding electrodes 1BP are sealed. In the case of this embodiment, since the drying process is completed before the underfill filling process and the remaining moisture is removed, the occurrence of voids after the underfill filling process can be prevented.

[0221] Next, in a singulation process, the wiring substrate (multi-piece substrate) is divided to obtain a plurality of semiconductor devices PKG1.

[0222] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: Wiring substrate; a semiconductor chip mounted on the wiring substrate via a plurality of protruding electrodes; as well as a first insulating material arranged between the semiconductor chip and the wiring substrate and sealing the plurality of protruding electrodes, The semiconductor chip comprises: A semiconductor substrate having a first surface; a first wiring layer formed on the first surface; a second insulating layer arranged to cover the first wiring layer, the second insulating layer having a second surface facing the first surface of the semiconductor substrate and a third surface opposite to the second surface; and The plurality of protruding electrodes are electrically connected to the first wiring layer, Wherein, in a plan view, the third surface of the second insulating layer includes: a first side extending in a first direction; a second side, opposite to the first side; a first region located between the first side and the second side; a second region located between the first side and the first region and beside the first region; and a third area located between the first side and the second area and beside the second area, Wherein, in a plan view, the plurality of protruding electrodes include: a plurality of first protruding electrodes arranged at positions overlapping the first region; a plurality of second protruding electrodes arranged at positions overlapping the second region; and a plurality of third protruding electrodes arranged at positions overlapping the third region, wherein each of the plurality of third protruding electrodes is electrically connected to the first circuit of the semiconductor chip, wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected to a circuit different from the first circuit, wherein the plurality of first protruding electrodes are arranged at a first pitch, wherein the plurality of second protruding electrodes are arranged at a second pitch, wherein the plurality of third protruding electrodes are arranged at a third pitch different from each of the first pitch and the second pitch, and The component of the second pitch in a second direction perpendicular to the first direction is greater than the component of the first pitch in the second direction. 2 . The semiconductor device according to claim 1 , wherein the plurality of third protruding electrodes among the plurality of protruding electrodes include a protruding electrode arranged at a position closest to the first side.

3. The semiconductor device according to claim 2, wherein the first circuit is an input / output circuit for electric signals. 4 . The semiconductor device according to claim 1 , wherein the plurality of second protruding electrodes are arranged in three or more rows in the second direction. 5 . The semiconductor device according to claim 1 , wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is arranged in a staggered manner.

6. The semiconductor device according to claim 1, wherein a minimum pitch between one of the plurality of first protruding electrodes and one of the plurality of second protruding electrodes is equal to or greater than the first pitch, the one of the plurality of second protruding electrodes is located next to the one of the plurality of first protruding electrodes, and Wherein a minimum pitch between one of the plurality of third protruding electrodes and one of the plurality of second protruding electrodes is equal to or greater than the first pitch, and the one of the plurality of second protruding electrodes is located next to the one of the plurality of third protruding electrodes.

7. A semiconductor device according to claim 6, wherein the maximum pitch between one of the plurality of first protruding electrodes and one of the plurality of second protruding electrodes is equal to or less than the second pitch, and the one of the plurality of second protruding electrodes is located next to the one of the plurality of first protruding electrodes.

8. A semiconductor device according to claim 6, wherein the maximum pitch between one of the plurality of third protruding electrodes and one of the plurality of second protruding electrodes is equal to or less than the second pitch, and the one of the plurality of second protruding electrodes is located next to the one of the plurality of third protruding electrodes.

9. The semiconductor device according to claim 1, in, In a plan view, the third surface of the second insulating layer further includes: a third side extending in the second direction; and a fourth area, located between the third side and the first area, wherein, in a plan view, the plurality of protruding electrodes include a plurality of fourth protruding electrodes arranged at positions overlapping the fourth region, wherein each of the plurality of fourth protruding electrodes is electrically connected to the second circuit of the semiconductor chip, wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected to the circuit different from the second circuit, and wherein the plurality of fourth protruding electrodes are arranged at the first pitch. 10 . The semiconductor device according to claim 9 , wherein the component of the first pitch in the second direction is longer than the component of the first pitch in the first direction.

11. The semiconductor device according to claim 10, wherein each of the plurality of first protruding electrodes is connected to a power supply potential supply path for supplying a power supply potential to the circuit, or is connected to a reference potential supply path for supplying a reference potential to the circuit, and wherein the wiring substrate includes a second wiring layer, wherein the second wiring layer is arranged with a plurality of terminals connected to any one of the plurality of first protruding electrodes, the plurality of second protruding electrodes, and the plurality of third protruding electrodes, The plurality of terminals include: a plurality of power potential terminals electrically connected to the power potential supply path; as well as a plurality of reference potential terminals electrically connected to the reference potential supply path, and The second wiring layer comprises: a power supply potential wiring connected to each of the plurality of power supply potential terminals arranged in the first direction and extending in the first direction; as well as A reference potential wiring is connected to each of the plurality of reference potential terminals arranged in the first direction and extends in the first direction.

12. The semiconductor device according to claim 11, wherein an outer edge of each of the plurality of power supply potential terminals forms an arc shape, and wherein a width of the power supply potential wiring in the second direction is equal to or larger than a radius of each of the plurality of power supply potential terminals.

13. The semiconductor device according to claim 11, wherein an outer edge of each of the plurality of reference potential terminals forms an arc shape, and wherein a width of the reference potential wiring in the second direction is equal to or greater than a radius of each of the plurality of reference potential terminals.

14. A semiconductor device comprising: Wiring substrate; a semiconductor chip mounted on the wiring substrate via a plurality of protruding electrodes; as well as a first insulating material arranged between the semiconductor chip and the wiring substrate and sealing the plurality of protruding electrodes, The semiconductor chip comprises: A semiconductor substrate having a first surface; a first wiring layer formed on the first surface; a second insulating layer arranged to cover the first wiring layer, the second insulating layer having a second surface facing the first surface of the semiconductor substrate and a third surface opposite to the second surface; and The plurality of protruding electrodes are electrically connected to the first wiring layer. Wherein, in a plan view, the third surface of the second insulating layer includes: a first side extending in a first direction; a second side, opposite to the first side; a first region located between the first side and the second side; a second region located between the first side and the first region; and a third region located between the first side and the second region, Wherein, in a plan view, the plurality of protruding electrodes include: a plurality of first protruding electrodes arranged at positions overlapping the first region; a plurality of second protruding electrodes arranged at positions overlapping the second region; and a plurality of third protruding electrodes arranged at positions overlapping the third region, wherein each of the plurality of third protruding electrodes is electrically connected to a first circuit of the semiconductor chip, wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected to a circuit different from the first circuit, wherein the plurality of first protruding electrodes are arranged at a first pitch, wherein the plurality of second protruding electrodes are arranged at a second pitch, wherein the plurality of third protruding electrodes are arranged at a third pitch different from each of the first pitch and the second pitch, and The component of the second pitch in a second direction perpendicular to the first direction is smaller than the component of the first pitch in the second direction.

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