Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a substrate and a shielding metal layer located on the substrate; the dummy metal layer is located on the substrate and located above the shielding metal layer; the grounding ring is located on the substrate and surrounds the pseudo metal layer, the grounding ring is provided with an opening, the grounding ring is electrically connected with the shielding metal layer, and the grounding ring is used for grounding; and the capacitor is positioned above the dummy metal layer and is positioned right above the shielding metal layer. The invention is beneficial to improving the quality factor of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Capacitors are usually made of two isolated metal sheets. Capacitors are widely used in analog circuits and mixed-signal integrated circuits. Metal-Oxdie-Metal (MOM) capacitors are widely used due to their large capacitance.

[0003] Metal-Oxdie-Metal (MOM) capacitors are critical components in many mixed-signal radio frequency integrated circuits (RFICs), such as analog frequency tuning circuits, switched capacitor circuits, filters, resonators, up-conversion and down-conversion mixers, and analog / digital converters (A / D Converters). They play an inter-matching role and can greatly optimize the performance of RFICs.

[0004] However, it is difficult to obtain a high quality factor (Q factor) in the semiconductor structure of the current MOM capacitor. Summary of the invention

[0005] The problem solved by the implementation of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the quality factor of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a base, including a substrate and a shielding metal layer located on the substrate; a dummy metal layer located on the base and above the shielding metal layer; a grounding ring located on the base and surrounding the dummy metal layer, the grounding ring having an opening, the grounding ring being electrically connected to the shielding metal layer, and the grounding ring being used for grounding; and a capacitor located above the dummy metal layer and directly above the shielding metal layer.

[0007] Optionally, the shielding metal layer includes a plurality of first metal layers extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

[0008] Optionally, the first metal layer includes a plurality of first metal wires extending along the first direction and arranged in parallel along the second direction, and a plurality of second metal wires extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact the plurality of first metal wires. The plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

[0009] Optionally, the semiconductor structure further includes: a through-hole interconnect structure, located between an end of the first metal layer along the first direction and the grounding ring, and in contact with the first metal layer and the grounding ring.

[0010] Optionally, a plurality of through-hole interconnect structures are arranged at ends on the same side of the plurality of first metal layers.

[0011] Optionally, the dummy metal layer includes a plurality of second metal lines extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

[0012] Optionally, the dummy metal layer includes a plurality of metal rows extending along a first direction and arranged in parallel along a second direction, the metal rows include a plurality of metal blocks arranged in parallel along the first direction, and the first direction is perpendicular to the second direction.

[0013] Optionally, the plurality of metal blocks are distributed in an array.

[0014] Optionally, the ground ring is on the same layer as the dummy metal layer.

[0015] Optionally, the shielding metal layer is a middle metal layer; and the dummy metal layer is a rear metal layer.

[0016] Optionally, the material of the shielding metal layer includes tungsten; and the material of the dummy metal layer includes copper.

[0017] Optionally, the capacitor includes a plurality of device metal layers stacked from bottom to top, each device metal layer includes a first electrode for serving as a first signal loading end, and a second electrode for serving as a second signal loading end, the first electrode and the second electrode both include a comb handle portion and a plurality of comb teeth portions connected to the comb handle portion, the comb handle portions of the first electrode and the second electrode extend along a second direction and are arranged opposite to each other in the first direction, the plurality of comb teeth portions extend along the first direction and are arranged side by side along the second direction, the comb teeth portions of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

[0018] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a base, including a substrate and a shielding metal layer located on the substrate; forming a pseudo-metal layer on the base, the pseudo-metal layer being located above the shielding metal layer; forming a grounding ring surrounding the pseudo-metal layer on the base, the grounding ring having an opening, the grounding ring being electrically connected to the shielding metal layer, and the grounding ring being used for grounding; forming a capacitor above the pseudo-metal layer, the capacitor being located directly above the shielding metal layer.

[0019] Optionally, in the step of providing the substrate, the shielding metal layer includes a plurality of first metal layers extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

[0020] Optionally, in the step of providing a substrate, the first metal layer includes a plurality of first metal wires extending along a first direction and arranged in parallel along a second direction, and a plurality of second metal wires extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact the plurality of first metal wires. The plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

[0021] Optionally, before forming the pseudo metal layer on the substrate, the formation method also includes: forming a through-hole interconnection structure in contact with the first metal layer at one end of the first metal layer along the first direction; in the step of forming a grounding ring surrounding the pseudo metal layer on the substrate, the grounding ring is in contact with the through-hole interconnection structure.

[0022] Optionally, in the step of forming a dummy metal layer on the substrate, the dummy metal layer includes a plurality of second metal lines extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

[0023] Optionally, in the step of forming a dummy metal layer on the substrate, the dummy metal layer includes a plurality of metal rows extending along a first direction and arranged in parallel along a second direction, the metal rows include a plurality of metal blocks arranged in parallel along the first direction, and the first direction is perpendicular to the second direction.

[0024] Optionally, in the same step, a dummy metal layer is formed on the substrate, and a grounding ring surrounding the dummy metal layer is formed on the substrate, wherein the grounding ring and the dummy metal layer are in the same layer.

[0025] Optionally, in the step of forming a capacitor above the pseudo-metal layer, the capacitor includes a plurality of device metal layers stacked from bottom to top, each device metal layer includes a first electrode for serving as a first signal loading end, and a second electrode for serving as a second signal loading end, the first electrode and the second electrode both include a comb handle portion and a plurality of comb teeth portions connected to the comb handle portion, the comb handle portions of the first electrode and the second electrode extend along the second direction and are arranged opposite to each other in the first direction, the plurality of comb teeth portions extend along the first direction and are arranged side by side in the second direction, the comb teeth portions of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the semiconductor structure provided by the embodiment of the present invention, the substrate includes a substrate and a shielding metal layer located on the substrate, a pseudo-metal layer located on the substrate and above the shielding metal layer, a grounding ring located on the substrate and surrounding the pseudo-metal layer, the grounding ring has an opening, the grounding ring is electrically connected to the shielding metal layer, and the grounding ring is used for grounding, and the capacitor is located above the pseudo-metal layer and directly above the shielding metal layer; the shielding metal layer in the embodiment of the present invention is grounded through the grounding ring and is used as a shielding structure between the capacitor and the substrate, and there is a pseudo-metal layer that is not electrically connected between the shielding metal layer and the capacitor. Compared with the solution of using the pseudo-metal layer as the first shielding structure, this solution increases the spacing between the capacitor and the shielding structure, which is beneficial to reducing the coupling capacitance between the capacitor and the shielding structure, and is beneficial to reducing the electrical loss between the capacitor and the substrate, thereby facilitating improving the quality factor (Q factor) of the semiconductor structure.

[0028] In the semiconductor structure provided by the embodiment of the present invention, a substrate is provided, including a substrate and a shielding metal layer located on the substrate, a pseudo-metal layer is formed on the substrate, the pseudo-metal layer is located above the shielding metal layer, a grounding ring surrounding the pseudo-metal layer is formed on the substrate, the grounding ring has an opening, the grounding ring is electrically connected to the shielding metal layer, the grounding ring is used for grounding, a capacitor is formed above the pseudo-metal layer, and the capacitor is located directly above the shielding metal layer; the shielding metal layer in the embodiment of the present invention is grounded through the grounding ring and is used as a shielding structure between the capacitor and the substrate, and a pseudo-metal layer that is not electrically connected is provided between the shielding metal layer and the capacitor. Compared with the solution of using the pseudo-metal layer as the first shielding structure, this solution increases the spacing between the capacitor and the shielding structure, which is beneficial to reducing the coupling capacitance between the capacitor and the shielding structure, and is beneficial to reducing the electrical loss between the capacitor and the substrate, thereby being beneficial to improving the quality factor (Q factor) of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0030] Figures 4 to 8 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0031] Figures 9 to 16 It is a schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] At present, as the technology nodes continue to shrink, how to improve the quality factor of semiconductor structures has become a challenge. This paper analyzes the reasons why the quality factor of a semiconductor structure needs to be improved.

[0033] Figures 1 to 3 It is a schematic diagram of the structure corresponding to a semiconductor structure. Figure 1 is a cross-sectional view of a semiconductor structure. Figure 2 This is a top view of the semiconductor structure. For clarity, Figure 3 Only the top view of the ground ring, shielding metal layer and front metal layer is shown.

[0034] Combined with reference Figures 1 to 3 The semiconductor structure includes: a substrate 10, including a substrate 11 and a front metal layer 12 located on the substrate 11; a shielding metal layer 22 located on the substrate 10; a grounding ring 21 located on the substrate 10 and surrounding the shielding metal layer 22, the grounding ring 21 has an opening, the grounding ring 2122 is electrically connected to the shielding metal layer, and the grounding ring 21 is used for grounding; a capacitor 30, located directly above the shielding metal layer 22.

[0035] The shielding metal layer 22 is grounded through the grounding ring 21 and is used as a shielding structure between the capacitor 30 and the substrate 11. However, since the distance between the capacitor 30 and the shielding metal layer 22 is small, it is easy to cause a large coupling capacitance between the capacitor 30 and the shielding metal layer 22, which is easy to increase the electrical loss between the capacitor 30 and the substrate 11, making it difficult to improve the quality factor (Q factor) of the semiconductor structure.

[0036] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a base, including a substrate and a shielding metal layer located on the substrate; a dummy metal layer located on the base and above the shielding metal layer; a grounding ring located on the base and surrounding the dummy metal layer, the grounding ring having an opening, the grounding ring being electrically connected to the shielding metal layer, and the grounding ring being used for grounding; a capacitor located above the dummy metal layer and directly above the shielding metal layer.

[0037] In the embodiment of the present invention, the shielding metal layer is grounded through a grounding ring and is used as a shielding structure between the capacitor and the substrate. A pseudo metal layer that is not electrically connected is provided between the shielding metal layer and the capacitor. Compared with a solution that uses the pseudo metal layer as the first shielding structure, this solution increases the spacing between the capacitor and the shielding structure, is beneficial to reducing the coupling capacitance between the capacitor and the shielding structure, is beneficial to reducing the electrical loss between the capacitor and the substrate, and is beneficial to improving the quality factor (Q factor) of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 8 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein: Figure 4 is a cross-sectional view of a semiconductor structure. Figure 5 This is a top view of the semiconductor structure. For clarity, Figure 6Only the top view of the ground ring, dummy metal layer and shielding metal layer is shown. Figure 7 is a Q value curve diagram of this embodiment, Figure 8 FIG. 4 is a coupling capacitance curve diagram between the capacitor and the substrate in this embodiment.

[0040] The semiconductor structure includes: a substrate 100, including a substrate 110 and a shielding metal layer 120 located on the substrate 110; a dummy metal layer 220, located on the substrate 100 and above the shielding metal layer 120; a grounding ring 210, located on the substrate 100 and surrounding the dummy metal layer 220, the grounding ring 210 having an opening, the grounding ring 210 being electrically connected to the shielding metal layer 120, and the grounding ring 210 being used for grounding; and a capacitor 300, located above the dummy metal layer 220 and directly above the shielding metal layer 120.

[0041] Substrate 100 is used to provide a process platform for forming a MOM capacitor. In the present embodiment, substrate 100 includes substrate 110, and substrate 110 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as silicon substrate on insulator or germanium substrate on insulator.

[0042] The shielding metal layer 120 is grounded through the grounding ring 210 and is used as a shielding structure between the capacitor 300 and the substrate 110 .

[0043] In the present embodiment, a dummy metal layer 220 which is not electrically connected is provided between the shielding metal layer 120 and the capacitor 300. Compared with the scheme of using the dummy metal layer as the first shielding structure, the present scheme increases the spacing between the capacitor 300 and the shielding structure, which is beneficial to reduce the coupling capacitance between the capacitor 300 and the shielding structure, and is beneficial to reduce the electrical loss between the capacitor 300 and the substrate 110, thereby being beneficial to improving the quality factor (Q factor) of the semiconductor structure.

[0044] In this embodiment, the shielding metal layer 120 includes a plurality of metal layers along a first direction (eg Figure 6 X direction) and extends along the second direction (as shown in Figure 6 A plurality of first metal layers (not labeled) are arranged in parallel (as shown in the Y direction), and the first direction is perpendicular to the second direction.

[0045] The shielding metal layer 120 is composed of multiple first metal layers extending along the first direction and arranged in parallel along the second direction. The first metal layers can occupy a relatively sufficient area at the bottom of the capacitor 300 and are arranged regularly, which is conducive to making the shielding metal layer 120 have a better shielding effect on the capacitor 300.

[0046] In this embodiment, the shielding metal layer 120 is a middle metal layer.

[0047] Adopting the middle metal layer as the shielding metal layer 120 and utilizing the original middle metal layer without adding an additional metal layer as the shielding metal layer 120 is beneficial for improving the performance of the semiconductor structure while reducing the changes to the original semiconductor structure, saving process costs, and improving the integration of the semiconductor structure.

[0048] In this embodiment, the middle metal layer is a metal layer for realizing electrical connection of the transistor below, specifically, including a gate interconnection metal line extending along a first direction, and a source-drain interconnection metal line extending along a second direction, and the gate interconnection metal line of the gate structure is connected to the source-drain interconnection metal line of the source-drain doping layer on both sides of the same gate structure to form an integrated structure.

[0049] Therefore, in this embodiment, the first metal layer includes a plurality of first metal wires (not labeled) extending along the first direction and arranged in parallel along the second direction, and a plurality of second metal wires (not labeled) extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact the plurality of first metal wires. The plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

[0050] The shielding metal layer 120 is composed of a plurality of first metal wires and second metal wires in a mesh structure. The mesh structure can further occupy a sufficient area at the bottom of the capacitor 300 and is arranged regularly, which is conducive to further improving the shielding effect of the shielding metal layer 120 on the capacitor 300.

[0051] In this embodiment, the material of the shielding metal layer 120 includes tungsten.

[0052] In this embodiment, the shielding metal layer 120 is a middle metal layer, which is usually made of tungsten metal material. Compared with the rear metal layer, the tungsten metal material has a larger resistance. Compared with the solution of using the rear metal layer as the shielding structure, this solution is beneficial to increasing the resistance of the shielding structure, thereby being more beneficial to reducing the loss of the substrate 110.

[0053] The dummy metal layer 220 is the original metal layer of the semiconductor structure. The dummy metal layer 220 is not electrically connected, so it does not affect other structures of the semiconductor structure. Retaining the original metal layer as the dummy metal layer 220 is beneficial to reducing changes to the original structure.

[0054] In this embodiment, the dummy metal layer 220 is a back-end metal layer.

[0055] The back-end metal layer also has other metal structures in the same layer. Although the dummy metal layer 220 is not electrically connected, the dummy metal layer 220 is still retained, which is beneficial to ensure the structural density of the semiconductor structure and provide a better platform for the subsequent process of the semiconductor structure.

[0056] In this embodiment, the dummy metal layer 220 includes a plurality of metal rows (not shown) extending along a first direction and arranged in parallel along a second direction. The metal rows include a plurality of metal blocks 221 arranged in parallel along the first direction. The first direction is perpendicular to the second direction.

[0057] Using multiple metal blocks 221 to form a metal row, and multiple metal rows to form a dummy metal layer 220 is beneficial to making the density distribution uniformity of the dummy metal layer 220 better, and the metal blocks 221 are easy to form and have a smaller morphology, which is beneficial to saving process costs.

[0058] In this embodiment, the plurality of metal blocks 221 are distributed in an array.

[0059] The multiple metal blocks 221 are arranged regularly, further improving the density uniformity of the dummy metal layer 220 .

[0060] In other embodiments, the dummy metal layer may further include a plurality of second metal lines extending along the first direction and arranged in parallel along the second direction.

[0061] In this embodiment, the material of the dummy metal layer 220 includes copper.

[0062] The dummy metal layer 220 uses the same material as the metal layer, which reduces the change to the original material and improves the process efficiency.

[0063] The grounding ring 210 is used for grounding, and is electrically connected to the shielding metal layer 120 to achieve grounding of the shielding metal layer 120 .

[0064] In this embodiment, the grounding ring 210 surrounds the dummy metal layer 220, which is beneficial for making the grounding ring 210 suppress the signal more uniformly. The grounding ring 210 has an opening to prevent the grounding ring 210 from generating eddy currents and affecting the semiconductor structure.

[0065] In this embodiment, the ground ring 210 and the dummy metal layer 220 are in the same layer.

[0066] The ground ring 210 and the dummy metal layer 220 are in the same layer, which reduces the modification to the original semiconductor structure.

[0067] Accordingly, in this embodiment, the material of the grounding ring 210 includes copper.

[0068] In this embodiment, the semiconductor structure further includes: a through-hole interconnection structure 400 , which is located between an end of the first metal layer along the first direction and the grounding ring 210 , and contacts the first metal layer and the grounding ring 210 .

[0069] The through-hole interconnect structure 400 is used to realize the electrical connection between the first metal layer and the ground ring 210 , and correspondingly realize the electrical connection between the shielding metal layer 120 and the ground ring 210 .

[0070] Specifically, in this embodiment, for a first metal layer, only one end is formed with a through-hole interconnection structure 400, which is electrically connected to the grounding ring 210 to prevent the first metal layer and the grounding ring 210 from forming a closed ring, causing eddy currents to affect the semiconductor structure.

[0071] In this embodiment, a plurality of through-hole interconnect structures 400 are arranged at ends on the same side of a plurality of first metal layers.

[0072] The plurality of through-hole interconnect structures 400 are arranged at the ends of the same side of the plurality of first metal layers, which improves the arrangement regularity of the semiconductor structure, makes the structure layout neat, and is easy to form.

[0073] In this embodiment, the capacitor 300 is a Metal-Oxdie-Metal (MOM) capacitor.

[0074] Specifically, in this embodiment, the capacitor 300 includes a plurality of device metal layers (not labeled) stacked from bottom to top, each device metal layer includes a first electrode (not labeled) used as a first signal loading end, and a second electrode (not labeled) used as a second signal loading end, the first electrode and the second electrode both include a comb handle portion 310 and a plurality of comb tooth portions 320 connected to the comb handle portion 310, the comb handle portions 310 of the first electrode and the second electrode extend along the second direction and are arranged opposite to each other in the first direction, the plurality of comb tooth portions 320 extend along the first direction and are arranged in parallel along the second direction, the comb tooth portions 320 of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

[0075] Accordingly, in this embodiment, the comb-tooth portion 320 of the first electrode and the comb-tooth portion 320 of the second electrode constitute a MOM capacitor.

[0076] refer to Figure 7 , shows a Q value curve of the semiconductor structure of this embodiment, where the horizontal axis is frequency and the vertical axis is Q value. Curve 1 is the Q value curve of the semiconductor structure in the prior art, and curve 2 is the Q value curve of the semiconductor structure of this embodiment. It can be seen from measurement that the Q value of the semiconductor structure of this embodiment is improved by 48.2%.

[0077] refer to Figure 8, shows a coupling capacitance curve graph between the capacitor and the substrate in this embodiment, where the horizontal axis is frequency and the vertical axis is coupling capacitance. Curve 1 is the coupling capacitance curve between the capacitor and the substrate in the prior art, and curve 2 is the coupling capacitance curve between the capacitor and the substrate in this embodiment. It can be seen from measurement that the coupling capacitance between the capacitor and the substrate in the semiconductor structure of this embodiment is reduced by 63.6%.

[0078] Figures 9 to 16 1 is a schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention, wherein: Fig.15 is a Q value curve diagram of the semiconductor structure of this embodiment, Fig.16 FIG. 4 is a coupling capacitance curve diagram between the capacitor and the substrate in this embodiment.

[0079] Combined with reference Fig. 9 and Fig.10 , Fig.10 for Fig. 9 A top view of a substrate 100 is provided, including a substrate 110 and a shielding metal layer 120 located on the substrate 110.

[0080] Substrate 100 is used to provide a process platform for forming a MOM capacitor. In the present embodiment, substrate 100 includes substrate 110, and substrate 110 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as silicon substrate on insulator or germanium substrate on insulator.

[0081] The shielding metal layer 120 is subsequently grounded through a grounding ring to serve as a shielding structure between a capacitor formed subsequently and the substrate 110 .

[0082] In the step of providing the substrate 100 in this embodiment, the shielding metal layer 120 includes a first direction (eg Fig.10 X direction) and extends along the second direction (as shown in Fig.10 A plurality of first metal layers (not labeled) are arranged in parallel (as shown in the Y direction), and the first direction is perpendicular to the second direction.

[0083] The shielding metal layer 120 is composed of multiple first metal layers extending along the first direction and arranged in parallel along the second direction. The first metal layer can occupy a sufficient area at the bottom of the capacitor to be formed subsequently, and the arrangement is regular, which is conducive to making the shielding metal layer 120 have a better shielding effect on the capacitor.

[0084] In this embodiment, the shielding metal layer 120 is a middle metal layer.

[0085] Adopting the middle metal layer as the shielding metal layer 120 and utilizing the original middle metal layer without adding an additional metal layer as the shielding metal layer 120 is beneficial for improving the performance of the semiconductor structure while reducing the changes to the original semiconductor structure, saving process costs, and improving the integration of the semiconductor structure.

[0086] In this embodiment, the middle metal layer is a metal layer for realizing electrical connection of the transistor below, specifically, including a gate interconnection metal line extending along a first direction, and a source-drain interconnection metal line extending along a second direction, and the gate interconnection metal line of the gate structure is connected to the source-drain interconnection metal line of the source-drain doping layer on both sides of the same gate structure to form an integrated structure.

[0087] Therefore, in this embodiment, in the step of providing the substrate 100, the first metal layer includes a plurality of first metal wires (not labeled) extending along the first direction and arranged in parallel along the second direction, and a plurality of second metal wires (not labeled) extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact with the plurality of first metal wires, and the plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

[0088] The shielding metal layer 120 is composed of a plurality of first metal wires and second metal wires in a mesh structure. The mesh structure can further occupy a sufficient area at the bottom of the capacitor and is arranged regularly, which is conducive to further improving the shielding effect of the shielding metal layer 120 on the capacitor.

[0089] In this embodiment, in the step of providing the substrate 100 , the material of the shielding metal layer 120 includes tungsten.

[0090] In this embodiment, the shielding metal layer 120 is a middle metal layer, which is usually made of tungsten metal material. Compared with the rear metal layer, the tungsten metal material has a larger resistance. Compared with the solution of using the rear metal layer as the shielding structure, this solution is beneficial to increasing the resistance of the shielding structure, thereby being more beneficial to reducing the loss of the substrate 110.

[0091] Continue to combine references Fig. 9 and Fig.10 Before subsequently forming the dummy metal layer on the substrate 100 , the forming method further includes: forming a through-hole interconnection structure 400 in contact with the first metal layer at one end of the first metal layer along the first direction.

[0092] The through-hole interconnect structure 400 is used to realize the electrical connection between the first metal layer and the subsequently formed grounding ring, and correspondingly realize the electrical connection between the shielding metal layer 120 and the grounding ring.

[0093] Specifically, in this embodiment, for a first metal layer, only one end is formed with a through-hole interconnection structure 400, and is subsequently electrically connected to the ground ring to prevent the first metal layer and the ground ring from forming a closed ring, causing eddy currents to affect the semiconductor structure.

[0094] In this embodiment, in the step of forming the through-hole interconnection structure 400 , a plurality of through-hole interconnection structures 400 are arranged at the ends of the same side of the plurality of first metal layers.

[0095] The plurality of through-hole interconnect structures 400 are arranged at the ends of the same side of the plurality of first metal layers, which improves the arrangement regularity of the semiconductor structure, makes the structure layout neat, and is easy to form.

[0096] Combined with reference Fig.11 and Fig.12 , Fig.12 for Fig.11 In the top view, a dummy metal layer 220 is formed on the substrate 100, and the dummy metal layer 220 is located above the shielding metal layer 120.

[0097] The dummy metal layer 220 is the original metal layer of the semiconductor structure. The dummy metal layer 220 is not electrically connected, so it does not affect other structures of the semiconductor structure. Retaining the original metal layer as the dummy metal layer 220 is beneficial to reducing changes to the original structure.

[0098] In this embodiment, the dummy metal layer 220 is a back-end metal layer.

[0099] The back-end metal layer also has other metal structures in the same layer. Although the dummy metal layer 220 is not electrically connected, the dummy metal layer 220 is still retained, which is beneficial to ensure the structural density of the semiconductor structure and provide a better platform for the subsequent process of the semiconductor structure.

[0100] In this embodiment, in the step of forming a dummy metal layer 220 on the substrate 100, the dummy metal layer 220 includes a plurality of metal rows (not marked) extending along a first direction and arranged in parallel along a second direction, and the metal rows include a plurality of metal blocks 221 arranged in parallel along the first direction, and the first direction is perpendicular to the second direction.

[0101] Using multiple metal blocks 221 to form a metal row, and multiple metal rows to form a dummy metal layer 220 is beneficial to making the density distribution uniformity of the dummy metal layer 220 better, and the metal blocks 221 are easy to form and have a smaller morphology, which is beneficial to saving process costs.

[0102] In this embodiment, in the step of forming the dummy metal layer 220 on the substrate 100 , a plurality of metal blocks 221 are distributed in an array.

[0103] The multiple metal blocks 221 are arranged regularly, further improving the density uniformity of the dummy metal layer 220 .

[0104] In other embodiments, in the step of forming the dummy metal layer on the substrate, the dummy metal layer may further include a plurality of second metal lines extending along the first direction and arranged in parallel along the second direction.

[0105] In this embodiment, in the step of forming the dummy metal layer 220 on the substrate 100 , the material of the dummy metal layer 220 includes copper.

[0106] The dummy metal layer 220 uses the same material as the metal layer, which reduces the change to the original material and improves the process efficiency.

[0107] Continue to combine references Fig.11 and Fig.12 A grounding ring 210 surrounding the dummy metal layer 220 is formed on the substrate 100 . The grounding ring 210 has an opening. The grounding ring 210 is electrically connected to the shielding metal layer 120 . The grounding ring 210 is used for grounding.

[0108] The grounding ring 210 is used for grounding, and is electrically connected to the shielding metal layer 120 to achieve grounding of the shielding metal layer 120 .

[0109] Accordingly, in this embodiment, in the step of forming the grounding ring 210 surrounding the dummy metal layer 220 on the substrate 100 , the grounding ring 210 contacts the through-hole interconnection structure 400 to achieve electrical connection with the through-hole interconnection structure 400 .

[0110] In this embodiment, the grounding ring 210 surrounds the dummy metal layer 220, which is beneficial for making the grounding ring 210 suppress the signal more uniformly. The grounding ring 210 has an opening to prevent the grounding ring 210 from generating eddy currents and affecting the semiconductor structure.

[0111] In this embodiment, in the same step, a dummy metal layer 220 is formed on the substrate 100 , and a grounding ring 210 surrounding the dummy metal layer 220 is formed on the substrate 100 . The grounding ring 210 and the dummy metal layer 220 are in the same layer.

[0112] The ground ring 210 and the dummy metal layer 220 are in the same layer, which reduces the modification to the original semiconductor structure.

[0113] Accordingly, in this embodiment, the material of the grounding ring 210 includes copper.

[0114] Combined with reference Fig.13 and Fig.14 , Fig.14 for Fig.13 In the top view, a capacitor 300 is formed above the dummy metal layer 220 , and the capacitor 300 is located directly above the shielding metal layer 120 .

[0115] In the present embodiment, a dummy metal layer 220 which is not electrically connected is provided between the shielding metal layer 120 and the capacitor 300. Compared with the scheme of using the dummy metal layer as the first shielding structure, the present scheme increases the spacing between the capacitor 300 and the shielding structure, which is beneficial to reduce the coupling capacitance between the capacitor 300 and the shielding structure, and is beneficial to reduce the electrical loss between the capacitor 300 and the substrate 110, thereby being beneficial to improving the quality factor (Q factor) of the semiconductor structure.

[0116] In this embodiment, the capacitor 300 is a Metal-Oxdie-Metal (MOM) capacitor.

[0117] Specifically, in this embodiment, the capacitor 300 includes a plurality of device metal layers (not labeled) stacked from bottom to top, each device metal layer includes a first electrode (not labeled) used as a first signal loading end, and a second electrode (not labeled) used as a second signal loading end, the first electrode and the second electrode both include a comb handle portion 310 and a plurality of comb tooth portions 320 connected to the comb handle portion 310, the comb handle portions 310 of the first electrode and the second electrode extend along the second direction and are arranged opposite to each other in the first direction, the plurality of comb tooth portions 320 extend along the first direction and are arranged in parallel along the second direction, the comb tooth portions 320 of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

[0118] Accordingly, in this embodiment, the comb-tooth portion 320 of the first electrode and the comb-tooth portion 320 of the second electrode constitute a MOM capacitor.

[0119] refer to Fig.15 , shows a Q value curve of the semiconductor structure of this embodiment, where the horizontal axis is frequency and the vertical axis is Q value. Curve 1 is the Q value curve of the semiconductor structure in the prior art, and curve 2 is the Q value curve of the semiconductor structure of this embodiment. It can be seen from measurement that the Q value of the semiconductor structure of this embodiment is improved by 48.2%.

[0120] refer to Fig.16 , shows a coupling capacitance curve graph between the capacitor and the substrate in this embodiment, where the horizontal axis is frequency and the vertical axis is coupling capacitance. Curve 1 is the coupling capacitance curve between the capacitor and the substrate in the prior art, and curve 2 is the coupling capacitance curve between the capacitor and the substrate in this embodiment. It can be seen from measurement that the coupling capacitance between the capacitor and the substrate in the semiconductor structure of this embodiment is reduced by 63.6%.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A base, comprising a substrate and a shielding metal layer located on the substrate; a dummy metal layer, located on the substrate and above the shielding metal layer; A grounding ring, located on the substrate and surrounding the dummy metal layer, the grounding ring having an opening, the grounding ring being electrically connected to the shielding metal layer, and being used for grounding; The capacitor is located above the dummy metal layer and directly above the shielding metal layer.

2. The semiconductor structure according to claim 1, wherein: The shielding metal layer includes a plurality of first metal layers extending along a first direction and arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction.

3. The semiconductor structure according to claim 2, wherein: The first metal layer includes a plurality of first metal wires extending along the first direction and arranged in parallel along the second direction, and a plurality of second metal wires extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact with the plurality of first metal wires. The plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

4. The semiconductor structure according to claim 2, characterized in that The semiconductor structure further includes: a through-hole interconnection structure located between an end of the first metal layer along the first direction and the grounding ring, and in contact with the first metal layer and the grounding ring.

5. The semiconductor structure according to claim 4, characterized in that The plurality of through-hole interconnection structures are arranged at ends on the same side of the plurality of first metal layers.

6. The semiconductor structure according to claim 1, wherein: The dummy metal layer includes a plurality of second metal lines extending along a first direction and arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction.

7. The semiconductor structure according to claim 1, wherein: The dummy metal layer includes a plurality of metal rows extending along a first direction and arranged in parallel along a second direction, and the metal rows include a plurality of metal blocks arranged in parallel along the first direction, wherein the first direction is perpendicular to the second direction.

8. The semiconductor structure according to claim 7, wherein: The plurality of metal blocks are distributed in an array.

9. The semiconductor structure according to claim 1, wherein: The ground ring is in the same layer as the dummy metal layer.

10. The semiconductor structure according to claim 1, wherein: The shielding metal layer is a middle metal layer; the dummy metal layer is a rear metal layer.

11. The semiconductor structure according to claim 1, wherein: The material of the shielding metal layer includes tungsten; the material of the dummy metal layer includes copper.

12. The semiconductor structure according to claim 1, wherein: The capacitor includes a plurality of device metal layers stacked from bottom to top, each device metal layer includes a first electrode used as a first signal loading end, and a second electrode used as a second signal loading end, the first electrode and the second electrode both include a comb handle portion and a plurality of comb teeth portions connected to the comb handle portion, the comb handle portions of the first electrode and the second electrode extend along the second direction and are arranged opposite to each other in the first direction, the plurality of comb teeth portions extend along the first direction and are arranged in parallel along the second direction, the comb teeth portions of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

13. A method for forming a semiconductor structure, characterized in that: include: Providing a base, including a substrate and a shielding metal layer located on the substrate; forming a dummy metal layer on the substrate, wherein the dummy metal layer is located above the shielding metal layer; forming a grounding ring surrounding the dummy metal layer on the substrate, wherein the grounding ring has an opening, is electrically connected to the shielding metal layer, and is used for grounding; A capacitor is formed over the dummy metal layer, the capacitor being located directly over the shielding metal layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of providing the substrate, the shielding metal layer includes a plurality of first metal layers extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

15. The method for forming a semiconductor structure according to claim 14, wherein: In the step of providing the substrate, the first metal layer includes a plurality of first metal wires extending along the first direction and arranged in parallel along the second direction, and a plurality of second metal wires extending along the second direction. The plurality of second metal wires are arranged in parallel along the first direction and cross-contact with the plurality of first metal wires. The plurality of first metal wires and the second metal wires form a mesh structure extending along the first direction.

16. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the dummy metal layer on the substrate, the forming method further comprises: forming a through-hole interconnection structure in contact with the first metal layer on an end portion of the first metal layer along the first direction; In the step of forming a grounding ring surrounding the dummy metal layer on the substrate, the grounding ring is in contact with the through-hole interconnection structure.

17. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a dummy metal layer on the substrate, the dummy metal layer includes a plurality of second metal lines extending along a first direction and arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

18. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a dummy metal layer on the substrate, the dummy metal layer includes a plurality of metal rows extending along a first direction and arranged in parallel along a second direction, and the metal rows include a plurality of metal blocks arranged in parallel along the first direction, and the first direction is perpendicular to the second direction.

19. The method for forming a semiconductor structure according to claim 13, wherein: In the same step, a dummy metal layer is formed on the substrate, and a grounding ring surrounding the dummy metal layer is formed on the substrate, wherein the grounding ring and the dummy metal layer are in the same layer.

20. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a capacitor above the pseudo-metal layer, the capacitor includes a plurality of device metal layers stacked from bottom to top, each device metal layer includes a first electrode used as a first signal loading end, and a second electrode used as a second signal loading end, the first electrode and the second electrode both include a comb handle portion and a plurality of comb teeth portions connected to the comb handle portion, the comb handle portions of the first electrode and the second electrode extend along the second direction and are arranged opposite to each other in the first direction, the plurality of comb teeth portions extend along the first direction and are arranged in parallel along the second direction, the comb teeth portions of the first electrode and the second electrode are arranged crosswise and in parallel, and the first direction is perpendicular to the second direction.

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