Hybrid bonding structure based on interlocking structure and bonding method

Abstract

The invention provides a hybrid bonding structure and bonding method based on an interlocking structure, and the structure comprises a first chip to be bonded, which is provided with a silicon oxide layer and a first connecting piece protruding out of the silicon oxide layer; the second chip to be bonded is provided with a polyimide layer, a recess arranged in the polyimide layer and a second connecting piece arranged at the bottom of the recess, the surface of the second connecting piece is provided with a first adhesion layer, and the first connecting piece and the second connecting piece are made of copper and / or aluminum; the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connecting piece protruding out of the oxide layer is greater than the height difference of the top surface of the first adhesion layer and the top surface of the silicon oxide layer; the silicon oxide layer is connected with the polyimide layer, and the first connecting piece extends into the recess and is connected with the second connecting piece through the first adhesion layer to form an interlocking structure. The method is used for optimizing the performance of the hybrid bonding process and the bonding structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a hybrid bonding structure and a bonding method based on an interlocking structure. Background Art

[0002] As people's requirements for electronic products develop towards miniaturization, multi-function, and environmental protection, many new technologies, new materials, and new designs have emerged. Planar semiconductor devices are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches the physical limit, planar processes and manufacturing technologies become challenging and expensive. Three-dimensional stacked semiconductor device architectures can solve the density limitations in some planar semiconductor devices.

[0003] Among the various technologies used to stack semiconductor substrates, hybrid bonding (heterogeneous bonding) has become the focus of current three-dimensional integration technology research and development because it simultaneously connects circuit leads during the bonding process. For the hybrid bonding process, since the electrical connection between wafers must be achieved while completing wafer bonding, extremely high requirements are placed on the surface morphology of the bonded wafers, especially on the uniformity and consistency of the bonding interface process.

[0004] Taking the heterogeneous bonding process involving copper as an example, after preparing the Cu Pad for bonding, the surface Cu needs to be polished using the CMP process. However, according to the current industry requirements, the surface roughness of the dielectric layer after the CMP process polishing needs to be less than 0.5nm to facilitate the bonding of the dielectric layer, and there are also high requirements for the degree of concavity of the Cu Pad. Therefore, the above bonding method not only requires CMP equipment, but also has extremely high requirements for CMP equipment, which will greatly increase the difficulty of the entire preparation process. If the conditions of the above CMP process are not met, it will seriously affect the bonding yield, the performance and reliability of the bonded product. Summary of the invention

[0005] The object of the present invention is to provide a hybrid bonding structure and a bonding method based on an interlocking structure, so as to optimize the performance of the hybrid bonding process and the bonding structure.

[0006] In order to solve the above technical problems, the present invention provides a hybrid bonding structure based on an interlocking structure, comprising:

[0007] A first chip to be bonded, having a silicon oxide layer and a first connecting member protruding from the silicon oxide layer;

[0008] A second chip to be bonded, having a polyimide layer, a recess in the polyimide layer, and a second connector at the bottom of the recess, wherein a first adhesive layer is disposed on the surface of the second connector, and the first connector and the second connector are made of copper and / or aluminum;

[0009] The first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connecting member protruding from the oxide layer is greater than the height difference between the top surface of the first adhesion layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer is connected to the polyimide layer and the first connecting member extends into the recess and is connected to the second connecting member using the first adhesion layer to form an interlocking structure.

[0010] Optionally, the recess matches the cross-sectional shape of the first connecting member, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first connecting member.

[0011] Optionally, the material of the first connecting member includes aluminum, and the surface of the first connecting member is further covered with a second adhesion layer.

[0012] Optionally, the material of the first adhesion layer and the second adhesion layer includes titanium.

[0013] According to another aspect of the present invention, a hybrid bonding method based on an interlocking structure is also provided, comprising:

[0014] Providing a first chip to be bonded, with a silicon oxide layer on the surface of the first chip;

[0015] forming a plurality of protruding first connecting members on the silicon oxide layer;

[0016] providing a second chip to be bonded;

[0017] A polyimide layer having a recess is formed on the second chip to be bonded, and a second connector and a first adhesive layer are formed at the bottom of the recess, wherein the first adhesive layer covers the surface of the second connector, wherein the first connector and the second connector are made of copper and / or aluminum, and a height difference of the first connector protruding from the silicon oxide layer is greater than a height difference between a top surface of the first adhesive layer and a top surface of the polyimide layer;

[0018] The first chip to be bonded and the second chip to be bonded are subjected to surface treatment, and hot pressing bonding is performed on the first chip to be bonded and the second chip to be bonded at a first hot pressing temperature and a first hot pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connecting member extends into the recess and is connected to the second connecting member using the first adhesion layer to form an interlocking structure.

[0019] Optionally, the material of the first connecting member includes aluminum, and the steps of forming the first connecting member include:

[0020] forming a first patterned mask layer on the silicon oxide layer, the mask layer having a first opening exposing a partial area of ​​the silicon oxide layer;

[0021] Depositing metal aluminum in the first opening to form the first connecting member;

[0022] forming a second adhesive layer to cover the first connecting member;

[0023] The first patterned mask layer is removed.

[0024] Optionally, the material of the first connecting member includes copper, and the step of forming the first connecting member includes:

[0025] forming a third adhesion layer and a copper seed layer in sequence on the silicon oxide layer;

[0026] forming a first patterned mask layer on the copper seed layer, the mask layer having a first opening exposing a portion of the copper seed layer;

[0027] Performing a chemical electroplating process to fill the first opening with a copper layer;

[0028] The first patterned mask layer is removed, and a dry etching process is performed to remove the exposed copper seed layer and the third adhesion layer thereunder, with the remaining third adhesion layer, the copper seed layer and the copper layer serving as the first connector.

[0029] Optionally, the step of forming the polyimide layer, the second connecting member and the first adhesion layer includes:

[0030] forming a polyimide layer on the surface of the second chip to be bonded;

[0031] Forming a plurality of second openings in the polyimide layer to expose a portion of the second chip surface, wherein the width of the second openings is greater than the width of the first openings, and the second openings are used as the recesses;

[0032] Forming a second patterned mask layer on the surface of the polyimide layer, the second patterned mask layer having a third opening exposing a portion of the second chip surface, the third opening facing the second opening and having a width smaller than that of the second opening;

[0033] The second connecting member and the first adhesion layer are sequentially formed at the bottom of the second opening, wherein the material of the second connecting member includes copper and / or aluminum, and the height difference of the first connecting member protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesion layer and the top surface of the polyimide layer;

[0034] The second patterned mask layer is removed.

[0035] Optionally, the process parameters of the hot pressing bonding include: the first hot pressing temperature is 200° C. to 350° C., the hot pressing time is 50 minutes to 90 minutes, and the hot pressing pressure is 100 Newtons to 1000 Newtons.

[0036] Optionally, after surface treatment of the first chip to be bonded and the second chip to be bonded, hot pressing bonding is performed on the first chip to be bonded and the second chip to be bonded at a second hot pressing temperature and a second hot pressing time, and then the first chip to be bonded and the second chip to be bonded are annealed, the second hot pressing temperature is lower than the first hot pressing temperature, and the second hot pressing time is lower than the first hot pressing time.

[0037] In summary, the present invention provides a hybrid bonding structure and bonding method based on an interlocking structure, wherein the hybrid bonding structure includes a first chip to be bonded, on which there is a silicon oxide layer and a first connector protruding from the silicon oxide layer; a second chip to be bonded, on which there is a polyimide layer, a recess provided in the polyimide layer, and a second connector provided at the bottom of the recess, and a first adhesive layer is provided on the surface of the second connector, and the materials of the first connector and the second connector include copper and / or aluminum; the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer, and after bonding, the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector using the first adhesive layer to form an interlocking structure. In the present invention, the first connector of the first chip is extended into the corresponding recess of the second chip to conveniently achieve non-misaligned alignment of the first chip and the second chip. Compared with direct copper-to-copper bonding, the present invention uses the first adhesive layer to connect the first connector and the second connector, which can reduce the bonding temperature and the requirements for the flatness of the copper surface. Considering that the thermal expansion coefficient of polyimide is greater than the expansion coefficient of the first connector, the first connector extends into the recess and contacts the first adhesive layer before bonding, and a gap is reserved between the polyimide layer and the silicon oxide layer (i.e., the difference between the height difference of the first connector protruding from the silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer). During hot pressing bonding, the first adhesive layer connects the first connector and the second connector, and the polyimide layer gradually expands to contact the silicon oxide layer and the first connector, and basically fills the reserved gaps between the polyimide and the silicon oxide layer before bonding, and between the first connector and the side wall of the recess to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding annealing, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip and the second chip after bonding. Moreover, no CMP step is required when preparing the connecting parts for bonding on the first chip and the second chip, completely avoiding the need for high-precision CMP equipment and CMP process. In addition, compared with the silicon oxide layer, the polyimide layer has a higher dielectric constant and insulation performance, which can further reduce the signal interference between the bonded connecting parts (between the pads) and prevent leakage, which is conducive to further improving the interconnection density. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0039] Figure 1 is a flow chart of a hybrid bonding method based on an interlocking structure provided by an embodiment of the present invention;

[0040] Figure 2a to Figure 2lA schematic structural diagram corresponding to corresponding steps of a hybrid bonding method based on an interlocking structure provided in one embodiment of the present invention;

[0041] Figure 3a to Figure 3d It is a schematic diagram of forming a first connecting member provided by another embodiment of the present invention.

[0042] In the accompanying drawings: 10-first chip; 11-silicon oxide layer; 12-third adhesion layer; 13-copper seed layer; 14-first patterned mask layer; 15-first opening; 16-first copper layer; 17-first connecting piece; H1-first height difference; 21-second chip; 22-polyimide layer; 23-recess; 24-second patterned mask layer; 25-third opening; 26-second connecting piece; 27-first adhesion layer; H2-second height difference; 18-second adhesion layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0044] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0045] An embodiment of the present invention provides a hybrid bonding method based on an interlocking structure.

[0046] Figure 1 It is a flow chart of the hybrid bonding method based on the interlocking structure provided in this embodiment.

[0047] like Figure 1 As shown, the hybrid bonding method based on the interlocking structure provided in this embodiment includes:

[0048] S01: providing a first chip to be bonded, with a silicon oxide layer on the surface of the first chip;

[0049] S02: forming a plurality of protruding first connecting members on the silicon oxide layer;

[0050] S03: providing a second chip to be bonded;

[0051] S04: forming a polyimide layer having a recess on the second chip to be bonded, and forming a second connector and a first adhesive layer at the bottom of the recess, wherein the first adhesive layer covers the surface of the second connector, wherein the first connector and the second connector are made of copper and / or aluminum, and a height difference of the first connector protruding from the silicon oxide layer is greater than a height difference between a top surface of the first adhesive layer and a top surface of the polyimide layer;

[0052] S05: Surface treatment is performed on the first chip to be bonded and the second chip to be bonded, and hot pressing bonding is performed on the first chip to be bonded and the second chip to be bonded at a first hot pressing temperature and a first hot pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connecting member extends into the recess and is connected to the second connecting member using the first adhesion layer to form an interlocking structure.

[0053] Figure 2a to Figure 2i The schematic diagram of the structure corresponding to the corresponding steps of the hybrid bonding method based on the interlocking structure provided in this embodiment, and then Figure 2a to Figure 2i The hybrid bonding method based on the interlocking structure is described in detail.

[0054] First, please refer to Figure 2a , perform step S01, provide a first chip 10 to be bonded, and a silicon oxide layer 11 is provided on the surface of the first chip 10.

[0055] The first chip 10 to be bonded can be a semiconductor structure to be bonded in a broad sense, such as a wafer to be bonded, an interposer with through-silicon vias, a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 has an area to be bonded (an area for bonding), the surface of which is a silicon oxide layer 11, and the interconnection structure to be bonded (such as a plug or an interconnection line) is exposed in the silicon oxide layer 11. Of course, if the material of the surface of the bonding area of ​​the first chip 10 is not silicon oxide, a silicon oxide layer 11 can be formed on its surface by a vapor deposition process, and the interconnection structure to be bonded is exposed.

[0056] Next, step S02 is performed to form a plurality of protruding first connecting members 17 on the silicon oxide layer 11. The material of the first connecting members 17 includes copper.

[0057] Please refer to Figure 2b, a third adhesion layer 12 and a copper seed layer 13 are sequentially formed on the silicon oxide layer 11. The third adhesion layer 12 and the copper seed layer 13 can be sequentially formed on the surface of the silicon oxide layer 11 by a physical vapor deposition process, the material of the third adhesion layer 12 can be metal titanium, and a second barrier layer can be preferably formed between the third adhesion layer 12 and the copper seed layer 13, and the material of the second barrier layer can include titanium nitride and / or titanium tungsten.

[0058] Please refer to Figure 2c , a first patterned mask layer 14 is formed on the copper seed layer 13, and the first opening 15 exposes a portion of the copper seed layer 13. The first patterned mask layer 14 may be a patterned photoresist layer, and the first opening 15 exposes the copper seed layer 13 in the region corresponding to the interconnect structure to be bonded. The thickness of the first patterned mask layer 14 may be determined according to the height of the subsequent first connector 17, and the thickness of the first patterned mask layer 14 = the height of the first connector (preset height) - the thickness of the third adhesion layer 12 - the thickness of the copper seed layer 13.

[0059] Please refer to Figure 2d , a chemical plating process is performed to fill the first opening 15 with a first copper layer 16. The top surface of the first copper layer 16 may be substantially flush with or slightly exceed the thickness of the first patterned mask layer 14.

[0060] Please refer to Figure 2e , remove the first patterned mask layer 14, and perform a dry etching process to remove the exposed copper seed layer 13 and the third adhesion layer 12 thereunder, exposing the surface of the silicon oxide layer 11, and use the remaining third adhesion layer 12, copper seed layer 13 and first copper layer 16 as the first connector 17, which electrically leads to the interconnection structure to be bonded to the first chip 10. The height difference of the first connector 17 protruding from the silicon oxide layer 11 can be a first height difference H1.

[0061] Next, please refer to Figure 2f , execute step S03 to provide a second chip 21 to be bonded.

[0062] The second chip 21 may be a semiconductor structure that matches and is bonded to the first chip 10. The second chip 21 has a region to be bonded (region for bonding), the surface of which is an insulating dielectric layer, and an interconnection structure to be bonded (such as a plug or an interconnection line) is exposed in the insulating dielectric layer.

[0063] Next, execute step S04 to form a polyimide layer 22 having a recess 23 on the second chip 21 to be bonded, and form a second connector 26 and a first adhesion layer 27 at the bottom of the recess 23, wherein the first adhesion layer 27 covers the surface of the second connector 26, wherein the height difference of the first connector 17 protruding from the first oxide layer is smaller than the height difference between the top surface of the first adhesion layer 27 and the top surface of the polyimide layer 22.

[0064] Please refer to Figure 2g , a polyimide layer 22 is formed on the surface of the second chip 21 to be bonded. The polyimide layer 22 can be formed on the surface of the area to be bonded of the second chip 21 by, for example, spin coating, and the polyimide layer 22 is subjected to photolithography patterning and curing (for example, heat curing) to form a plurality of second openings in the polyimide layer 22 to expose a portion of the surface of the second chip 21. The second opening is a recess 23, the bottom of which exposes the interconnection structure of the second chip 21 to be bonded, and the cross-sectional shape of the second opening is the same as the cross-sectional shape of the first opening 15, but the size (width) of the recess 23 is slightly larger than the size (width) of the first opening 15, and the depth of the recess 23 is the thickness of the polyimide layer 22, and can match the protruding height of the first connector 17. In addition, in some examples, before forming the polyimide layer 22, a silicon oxide layer (or other dielectric layer) of a certain thickness may be formed on the surface of the second chip 21, and after forming a second opening in the polyimide layer 22, the silicon oxide layer may be etched to expose a portion of the surface of the second chip 21 to compress the thickness of the polyimide layer 22.

[0065] It can be understood that the polyimide layer 22 in this embodiment is not limited to polyimide, but can also be polyimide or other organic materials including polyimide. Compared with inorganic dielectric layers such as silicon oxide, the organic material of the polyimide layer 22 in this embodiment has better dielectric constant and insulation performance, is easier to prepare and is directly compatible with photolithography processes.

[0066] Please refer to Figure 2h , a second patterned mask layer 24 is formed on the surface of the polyimide layer 22, which has a third opening 25 facing the second opening (recess 23) to expose a portion of the surface of the second chip 21 (the bottom of the recess 23). The cross-sectional shape of the third opening 25 is the same as or similar to the cross-sectional shape of the recess 23, but the width of the third opening 25 is slightly smaller than the width of the second opening, for example, 50 nanometers to 200 nanometers smaller. In some examples, the size and shape of the third opening 25 may be the same as the size and shape of the first opening 15.

[0067] Please refer to Figure 2i, a second connector 26 and a first adhesive layer 27 are sequentially formed at the bottom of the recess 23, which are used to electrically lead out the interconnection structure to be bonded and connected to the second chip 21. The second connector 26 and the first adhesive layer 27 can be sequentially formed by a physical vapor deposition process. The material of the second connector 26 may include copper and / or aluminum, and the material of the first adhesive layer 27 may be metal titanium. When the material of the second connector 26 is copper, a first barrier layer may be preferably formed between it and the first adhesive layer 27. The material of the first barrier layer may include titanium nitride and / or titanium tungsten. Of course, it is also feasible to form a very small amount of metal material on the side wall of the recess 23. It should be noted here that since the size of the third opening 25 is smaller than the size of the second opening, the second connector 26 and the first adhesive layer 27 only cover part of the bottom of the recess 23. In other words, a first gap is reserved between the second connector 26 and the first adhesive layer 27 and the side wall of the recess 23.

[0068] Please refer to Figure 2j , remove the second patterned mask layer 24 to expose the surface of the polyimide layer 22. Among them, the height difference of the first connector 17 protruding from the silicon oxide layer 11 is greater than the height difference between the top surface of the first adhesion layer 27 and the top surface of the polyimide layer 22. The second connector 26 and the first adhesion layer 27 electrically lead out the interconnection structure to be bonded to the second chip 21. In other words, the height difference between the top surface of the first adhesion layer 27 and the top surface of the polyimide layer 22 can be a second height difference H2, and the second height difference H2 is slightly smaller than the first height difference H1, for example, 50 nanometers to 500 nanometers smaller. Of course, the second connector 26 and the first adhesion layer 27 formed by the above-mentioned physical vapor deposition process also cover the surface of the second patterned mask layer 24 (at Figure 2i and Figure 2j (not shown), when removing the second patterned mask layer 24, the redundant second connectors 26 and the first adhesive layer 27 on the surface thereof are also removed, leaving only the second connectors 26 and the first adhesive layer 27 in the recess 23.

[0069] Next, please refer to Figure 2k , execute step S05, perform surface treatment on the first chip 10 to be bonded and the second chip 21 to be bonded, and perform hot pressing bonding on the first chip 10 to be bonded and the second chip 21 to be bonded at a first hot pressing temperature and a first hot pressing time, so that the silicon oxide layer 11 is connected to the polyimide layer 22 and the first connecting member 17 extends into the recess 23 and is connected to the second connecting member 26 using the first adhesive layer 27 to form an interlocking structure.

[0070] Among them, the step of surface treatment of the first chip 10 to be bonded and the second chip 21 to be bonded includes: using weak acid to clean the first chip 10 to be bonded and the second chip 21 to be bonded to improve their hydrophilicity; using plasma bombardment on the first chip 10 to be bonded and the second chip 21 to be bonded to remove the surface oxide of the first connector 17 and the first adhesion layer 27 and improve the surface activity of the silicon oxide layer 11 and the polyimide layer 22. In specific implementation, at least part of the above surface treatment steps can be selected according to actual needs. When the first chip 10 to be bonded is subjected to surface treatment, low concentration citric acid cleaning can be tried first to reduce the contact angle and improve the hydrophilicity, and then a mixed gas of argon / nitrogen / hydrogen can be used for bombardment to remove the oxide layer on the surface of the first connector 17. When the second chip 21 to be bonded is subjected to surface treatment, a mixed gas of argon / nitrogen / hydrogen may be used to bombard the polyimide layer 22 and the first adhesion layer 27 to increase the surface activity of the polyimide layer 22 and reduce the oxide content on the surface of the first adhesion layer 27 in the recess 23 .

[0071] Before bonding, the first connector 17 of the first chip 10 is inserted into the corresponding recess 23 of the second chip 21 (similar to interlocking) to conveniently achieve the non-misaligned alignment of the first chip 10 and the second chip 21. Then, the first chip 10 and the second chip 21 are heat-pressed and bonded. The process parameters include: the first heat-pressing temperature is 200℃~350℃, the heat-pressing time is 50 minutes~90 minutes, and the heat-pressing pressure is 100 Newtons~1000 Newtons. It should be noted here that please refer to Figure 2k After alignment, the first connector 17 extends into the recess 23 and contacts the surface of the first adhesive layer 27, but a gap (i.e., a second gap) is maintained between the sidewall of the first connector 17 and the sidewall of the recess 23. On the other hand, the silicon oxide layer 11 of the first chip 10 and the polyimide layer 22 of the second chip 21 are not in contact, but a preset gap (i.e., a third gap is reserved). Next, please refer to Figure 2l During the thermocompression bonding process, the silicon oxide layer 11, the polyimide layer 22 and the first connector 17 are thermally expanded, the first adhesive layer 27 connects the first connector 17 and the second connector 26 under high temperature and external pressure, and the polyimide layer 22 is thermally expanded, gradually filling the second gap and the third gap, until it contacts and connects with the silicon oxide layer 11. Therefore, the gaps (the first gap, the second gap and the third gap) can be determined by the thickness of the polyimide layer 22, the size (height and width) of the first connector 17, and the difference in thermal expansion coefficient between the first connector 17 and the polyimide layer 22.

[0072] Compared with direct bonding between copper and copper (or aluminum), the bonding temperature and the requirements for the surface flatness of the first connector 17 (second connector 26) can be reduced by connecting the first adhesive layer 27 to the first connector 17 (second connector 26). In the above-mentioned hot pressing bonding process, considering that the thermal expansion coefficient of the polyimide layer 22 is greater than the thermal expansion coefficient of the first connector 17 (copper) and the silicon oxide layer 11, the polyimide layer 22 gradually expands to contact and connect with the silicon oxide layer 11, and basically fills the first gap, the second gap and the third gap reserved after alignment to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip 10 and the second chip 21 after bonding annealing.

[0073] It is worth mentioning that when preparing the connection parts for bonding on the first chip 10 and the second chip 21, no CMP step is required at all, which completely avoids the need for high-precision CMP equipment and CMP process, and thereby simplifies the process flow and reduces the process complexity, thereby facilitating stable, reliable and high-performance interconnection. It can be seen from the above connection process that even if the top surface morphology of the first connection part 17 and / or the top morphology of the first adhesive layer 27 are uneven, the first connection part 17 and the first adhesive layer 27 can be confined in the corresponding recess 23 and contact and connect under high temperature expansion and external pressure. In other words, the top surface morphology of the first connection part 17 and / or the top morphology of the first adhesive layer 27 does not affect the bonding connection between the two in the recess 23.

[0074] In addition, compared with the silicon oxide layer 11, the polyimide layer 22 has a higher dielectric constant and insulation performance, which can further reduce the signal interference between the bonded connectors (between pads) and prevent leakage, which is beneficial to further improve the interconnection density.

[0075] Another embodiment of the present invention further provides a hybrid bonding method based on an interlocking structure. The hybrid bonding method of this embodiment is basically the same as the hybrid bonding method of other embodiments, and the main difference is that the material of the first connector 17 on the first chip 10 of this embodiment includes aluminum or copper-aluminum alloy, and the method of forming the first connector 17 on the silicon oxide layer 11 of the first chip 10 to be bonded is different.

[0076] Specifically, the steps of forming the first connecting member 17 mainly made of aluminum include:

[0077] Please refer to Figure 3a A first patterned mask layer 14 is formed on the silicon oxide layer 11 of the first chip 10 to be bonded, wherein the first patterned mask layer 14 has a first opening 15 exposing a portion of the silicon oxide layer 11, that is, exposing the interconnection structure of the first chip 10 to be bonded.

[0078] Please refer to Figure 3b , a physical vapor deposition process is performed to deposit metal aluminum (or copper-aluminum alloy) in the first opening 15 to form a first connecting member 17 .

[0079] Please refer to Figure 3c , a physical vapor deposition process is performed to deposit a second adhesion layer 18 on the first connector 17 in the first opening 15 to cover the first connector 17 . The material of the second adhesion layer 18 may include one or at least two of titanium, gold, tin, niobium or chromium.

[0080] Please refer to Figure 3d , remove the first patterned mask layer 14, and expose the surface of the silicon oxide layer 11. It should be noted that the second adhesion layer 18 also has the function of protecting the first connector 17, and it is also feasible to regard the second adhesion layer 18 as (called) a passivation layer or a protective layer. Of course, the first connector 17 and the second adhesion layer 18 formed by the above-mentioned physical vapor deposition process also cover the surface of the first patterned mask layer 14. When removing the first patterned mask layer 14, the redundant first connector 17 and the second adhesion layer 18 on its surface are also removed, and only the first connector 17 on the silicon oxide layer 11 and the second adhesion layer 18 thereon are retained.

[0081] Another embodiment of the present invention also provides another hybrid bonding method based on an interlocking structure. The hybrid bonding method of this embodiment is basically the same as the hybrid bonding method of other embodiments, and the main difference is that the process parameters and process steps for bonding the first chip 10 and the second chip 21 in this embodiment are slightly different. After the thermocompression bonding, this example also adds an annealing step to shorten the thermocompression bonding time and improve the efficiency of the thermocompression bonding.

[0082] Specifically, the bonding step after surface treatment and alignment of the first chip 10 to be bonded and the second chip 21 to be bonded includes: performing hot pressing bonding at a second hot pressing temperature and a second hot pressing time on the first chip 10 to be bonded and the second chip 21 to be bonded, the second hot pressing temperature is less than the first hot pressing temperature, and the second hot pressing time is less than the first hot pressing time, and then annealing the hot pressed first chip 10 and the second chip 21 to be bonded, and the annealing temperature may be greater than or equal to the first hot pressing temperature. In one example, the second hot pressing temperature may be 100°C to 200°C, the second hot pressing time may be 20 minutes to 40 minutes, the hot pressing pressure may be 100 Newtons to 1000 Newtons, the annealing temperature may be 250°C to 400°C, and the annealing time may be 30 minutes to 90 minutes.

[0083] The present invention also provides a hybrid bonding structure based on an interlocking structure.

[0084] Figure 2e is a schematic diagram of the structure of the first chip to be bonded, Figure 2j FIG. 4 is a schematic diagram of the structure of the second chip to be bonded.

[0085] like Figure 2e and Figure 2j As shown, the hybrid bonding structure based on the interlocking structure provided in this embodiment includes a first chip 10 to be bonded and a second chip 21 to be bonded, both of which are semiconductor structures to be bonded in a broad sense, and may include, for example, a wafer to be bonded, an interposer with through-silicon vias, a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 and the second chip 21 each have a region to be bonded, in which an interconnection structure to be bonded (such as a plug or an interconnection line, not shown in the figure) is exposed.

[0086] like Figure 2e As shown, the surface of the area to be bonded of the first chip 10 is a first silicon oxide layer 11, and there are a number of protruding and spaced first connectors 17 on the first silicon oxide layer 11, each of which is connected to each interconnection structure to be bonded in the first chip 10. Among them, the main material of the first connector 17 is copper, and the first connector 17 may include a third adhesion layer 12, a copper seed layer 13 and a first copper layer 16 stacked in sequence from bottom to top. A second barrier layer may also be provided between the third adhesion layer 12 and the copper seed layer 13. The material of the third adhesion layer 12 may be metal titanium, and the material of the second barrier layer may include titanium nitride and / or titanium tungsten. Among them, the height of the first connector 17 protruding from the surface of the first silicon oxide layer 11, that is, the height difference between the top surface of the first connector 17 and the surface of the first silicon oxide layer 11 may be a first height difference H1.

[0087] In other examples of this embodiment, as shown in FIG3 , the main material of the first connector 17 may also be aluminum (i.e., an aluminum layer or a copper-aluminum alloy layer), and a second adhesion layer 18 is further provided on the surface of the first connector 17, and the height difference between the top surface of the first adhesion layer 27 and the surface of the first silicon oxide layer 11 may be a first height difference H1. The second adhesion layer 18 is used to protect the first connector 17, and therefore, it is also feasible to regard the second adhesion layer 18 as (called) a passivation layer or a protective layer, and the material of the second adhesion layer 18 may include one or at least two of titanium, gold, tin, niobium or chromium.

[0088] like Figure 2jAs shown, the surface of the area to be bonded of the second chip 21 is a polyimide layer 22, and the polyimide layer 22 has a number of recesses 23 exposing the interconnection structure to be bonded and connected to the second chip 21, and the positions of these recesses 23 match the corresponding first connectors 17 on the first chip 10. The bottom of the recess 23, that is, the interconnection structure to be bonded and connected to the second chip 21, is sequentially provided with a second connector 26 and a first adhesive layer 27, and the material of the second connector 26 may include copper and / or aluminum, and the material of the first adhesive layer 27 may include titanium. In a preferred example, the area of ​​the second connector 26 and the first adhesive layer 27 thereon is smaller than the bottom area of ​​the recess 23, that is, there is a gap between the second connector 26 and the first adhesive layer 27 and the side wall of the recess 23.

[0089] When the material of the second connector 26 mainly includes copper, a first barrier layer may be provided between the first adhesive layer 27 and the second connector 26, and the material of the first barrier layer may include titanium nitride and / or titanium tungsten. When the material of the second connector 26 mainly includes aluminum, the first adhesive layer 27 may serve as an adhesive layer between the first connector 17 and the second connector 26, and may also serve as a protective layer for the second connector 26.

[0090] The cross-sectional shape of the recess 23 matches (is the same as) the cross-sectional shape of the first connector 17, but the cross-sectional size (width) of the recess 23 is slightly larger than the cross-sectional size (width) of the first connector 17, and the height difference between the top surface of the first adhesive layer 27 in the recess 23 and the surface of the polyimide layer 22 may be a second height difference H2. The second height difference H2 is smaller than the first height difference H1, and the difference between the second height difference H2 and the first height difference H1 is the reserved gap between the silicon oxide layer 11 and the polyimide layer 22 after the first connector 17 extends into the recess 23 and contacts the first adhesive layer 27, which may be determined by the size (height and width) of the first connector 17, the thickness of the polyimide layer 22, and the difference in thermal expansion coefficient between the first connector 17 and the polyimide layer 22. In other words, after aligning the first chip 10 and the second chip 21, the first connector 17 contacts the first adhesion layer 27, while the silicon oxide layer 11 around the first connector 17 does not contact the polyimide layer 22 around the recess 23. The polyimide layer 22 gradually expands during the thermocompression bonding process to contact and connect with the silicon oxide layer 11, and the first adhesion layer 27 connects the first connector 17 and the second connector 26, thereby filling the reserved gap between the polyimide layer 22 and the silicon oxide layer 11 and the gap between the first connector 17 and the side wall of the recess 23, thereby forming an interlocking structure.

[0091] In a specific example, the height of the first connection member 17 (the first height difference H1 ) may be 1500 nanometers to 3000 nanometers, and the second height difference H2 may be 100 nanometers to 300 nanometers smaller than the first height difference H1 .

[0092] In summary, the present invention provides a hybrid bonding structure and bonding method based on an interlocking structure, wherein the hybrid bonding structure includes a first chip to be bonded, on which there is a silicon oxide layer and a first connector protruding from the silicon oxide layer; a second chip to be bonded, on which there is a polyimide layer, a recess provided in the polyimide layer, and a second connector provided at the bottom of the recess, and a first adhesive layer is provided on the surface of the second connector, and the materials of the first connector and the second connector include copper and / or aluminum; the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connector protruding from the oxide layer is greater than the height difference between the top surface of the first adhesive layer and the top surface of the silicon oxide layer, and after bonding, the silicon oxide layer is connected to the polyimide layer and the first connector extends into the recess and is connected to the second connector using the first adhesive layer to form an interlocking structure. In the present invention, the first connector of the first chip is extended into the corresponding recess of the second chip to conveniently achieve non-misaligned alignment of the first chip and the second chip. Compared with direct copper-to-copper bonding, the present invention uses the first adhesive layer to connect the first connector and the second connector, which can reduce the bonding temperature and the requirements for the flatness of the copper surface. Considering that the thermal expansion coefficient of polyimide is greater than the expansion coefficient of the first connector, the first connector extends into the recess and contacts the first adhesive layer before bonding, and a gap is reserved between the polyimide layer and the silicon oxide layer (i.e., the difference between the height difference of the first connector protruding from the silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the polyimide layer). During hot pressing bonding, the first adhesive layer connects the first connector and the second connector, and the polyimide layer gradually expands to contact the silicon oxide layer and the first connector, and basically fills the reserved gaps between the polyimide and the silicon oxide layer before bonding, and between the first connector and the side wall of the recess to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding annealing, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip and the second chip after bonding. Moreover, no CMP step is required when preparing the connecting parts for bonding on the first chip and the second chip, completely avoiding the need for high-precision CMP equipment and CMP process. In addition, compared with the silicon oxide layer, the polyimide layer has a higher dielectric constant and insulation performance, which can further reduce the signal interference between the bonded connecting parts (between the pads) and prevent leakage, which is conducive to further improving the interconnection density.

[0093] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A hybrid bonding structure based on an interlocking structure, characterized in that: include: A first chip to be bonded, having a silicon oxide layer and a first connecting member protruding from the silicon oxide layer; A second chip to be bonded, having a polyimide layer, a recess in the polyimide layer, and a second connector at the bottom of the recess, wherein a first adhesive layer is disposed on the surface of the second connector, and the first connector and the second connector are made of copper and / or aluminum; The first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first connecting member protruding from the oxide layer is greater than the height difference between the top surface of the first adhesion layer and the top surface of the silicon oxide layer; after bonding, the silicon oxide layer is connected to the polyimide layer and the first connecting member extends into the recess and is connected to the second connecting member using the first adhesion layer to form an interlocking structure.

2. The hybrid bonding structure based on the interlocking structure according to claim 1, characterized in that: The recess matches the cross-sectional shape of the first connecting member, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first connecting member.

3. The hybrid bonding structure based on the interlocking structure according to claim 1, characterized in that: The material of the first connecting member includes aluminum, and the surface of the first connecting member is further covered with a second adhesive layer.

4. The hybrid bonding structure based on the interlocking structure according to claim 2, characterized in that: The material of the first adhesion layer and the second adhesion layer includes titanium.

5. A hybrid bonding method based on an interlocking structure, characterized in that: include: Providing a first chip to be bonded, with a silicon oxide layer on the surface of the first chip; forming a plurality of protruding first connecting members on the silicon oxide layer; providing a second chip to be bonded; A polyimide layer having a recess is formed on the second chip to be bonded, and a second connector and a first adhesive layer are formed at the bottom of the recess, wherein the first adhesive layer covers the surface of the second connector, wherein the first connector and the second connector are made of copper and / or aluminum, and a height difference of the first connector protruding from the silicon oxide layer is greater than a height difference between a top surface of the first adhesive layer and a top surface of the polyimide layer; The first chip to be bonded and the second chip to be bonded are subjected to surface treatment, and hot pressing bonding is performed on the first chip to be bonded and the second chip to be bonded at a first hot pressing temperature and a first hot pressing time, so that the silicon oxide layer is connected to the polyimide layer and the first connecting member extends into the recess and is connected to the second connecting member using the first adhesion layer to form an interlocking structure.

6. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The material of the first connecting member includes aluminum, and the steps of forming the first connecting member include: forming a first patterned mask layer on the silicon oxide layer, the mask layer having a first opening exposing a partial area of ​​the silicon oxide layer; Depositing metal aluminum in the first opening to form the first connecting member; forming a second adhesive layer to cover the first connecting member; The first patterned mask layer is removed.

7. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The material of the first connecting member includes copper, and the steps of forming the first connecting member include: forming a third adhesion layer and a copper seed layer in sequence on the silicon oxide layer; forming a first patterned mask layer on the copper seed layer, the mask layer having a first opening exposing a portion of the copper seed layer; Performing a chemical electroplating process to fill the first opening with a copper layer; The first patterned mask layer is removed, and a dry etching process is performed to remove the exposed copper seed layer and the third adhesion layer thereunder, with the remaining third adhesion layer, the copper seed layer and the copper layer serving as the first connector.

8. The hybrid bonding method based on interlocking structure according to claim 6 or 7, characterized in that: The steps of forming the polyimide layer, the second connecting member and the first adhesive layer include: forming a polyimide layer on the surface of the second chip to be bonded; Forming a plurality of second openings in the polyimide layer to expose a portion of the second chip surface, wherein the width of the second openings is greater than the width of the first openings, and the second openings are used as the recesses; Forming a second patterned mask layer on the surface of the polyimide layer, the second patterned mask layer having a third opening exposing a portion of the second chip surface, the third opening facing the second opening and having a width smaller than that of the second opening; The second connecting member and the first adhesion layer are sequentially formed at the bottom of the second opening, wherein the material of the second connecting member includes copper and / or aluminum, and the height difference of the first connecting member protruding from the silicon oxide layer is greater than the height difference between the top surface of the first adhesion layer and the top surface of the polyimide layer; The second patterned mask layer is removed.

9. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The process parameters of the hot pressing bonding include: the first hot pressing temperature is 200° C. to 350° C., the hot pressing time is 50 minutes to 90 minutes, and the hot pressing pressure is 100 Newtons to 1000 Newtons.

10. The hybrid bonding method based on interlocking structure according to claim 5 or 9, characterized in that: After surface treatment is performed on the first chip to be bonded and the second chip to be bonded, hot pressing bonding is performed on the first chip to be bonded and the second chip to be bonded at a second hot pressing temperature and a second hot pressing time, and then annealing treatment is performed on the first chip to be bonded and the second chip to be bonded, wherein the second hot pressing temperature is lower than the first hot pressing temperature, and the second hot pressing time is lower than the first hot pressing time.

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