Packaging chip and manufacturing method thereof

Abstract

The invention provides a packaging chip and a manufacturing method thereof, the packaging chip comprises a first adapter plate and a second adapter plate, and the second adapter plate is bonded with the first adapter plate; the working chip is arranged on one side, far away from the second adapter plate, of the first adapter plate; the at least one concave part is arranged on the surface, close to the second adapter plate, of the first adapter plate; the at least one concave part is arranged on the surface, close to the first adapter plate, of the second adapter plate, and the convex part and the concave part are nested in an aligned manner; the first metal layer is laid on the surface, close to the second adapter plate, of the first adapter plate, and the first metal layer covers the concave part; the second metal layer is laid on the surface, close to the first adapter plate, of the second adapter plate, and the second metal layer covers the convex part; and an insulating layer disposed between the first metal layer and the second metal layer, the first metal layer, the insulating layer, and the second metal layer forming a capacitor device. According to the packaging chip and the manufacturing method thereof provided by the invention, the requirement of a system on chip on the capacity and the position of a capacitor can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a packaged chip and a manufacturing method thereof. Background Art

[0002] When packaging the chip, each module chip is packaged independently, and the packaged multiple chips are laid flat on a circuit board and connected to form a system on chip through the circuit board. For capacitors, which are large electrical devices, they are laid on the circuit board together with the packaged chips.

[0003] However, as the integration of the system on chip increases, two-dimensional packaging can no longer meet the volume requirements of the system on chip. Furthermore, the system on chip with increased integration requires larger current support, which in turn requires larger capacitors. And as the voltage switching frequency of the power chip continues to increase, the capacitor needs to be as close to the power network as possible. However, the capacitor set on the circuit board cannot meet the system on chip's requirements for the capacity and location of the capacitor. Summary of the invention

[0004] The object of the present invention is to provide a packaged chip and a manufacturing method thereof, which can solve the problem that the capacitor on the circuit board cannot meet the requirements of the system on chip for the capacity and position of the capacitor.

[0005] To achieve the above object, the present invention provides a packaged chip, comprising at least:

[0006] A first adapter plate and a second adapter plate, wherein the second adapter plate is bonded to the first adapter plate;

[0007] A working chip is arranged on a side of the first adapter board away from the second adapter board;

[0008] At least one recessed portion is disposed on a surface of the first adapter plate close to the second adapter plate;

[0009] At least one concave portion is provided on a surface of the second adapter plate close to the first adapter plate, and the convex portion is aligned and nested with the concave portion;

[0010] A first metal layer is laid on a surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the concave portion;

[0011] a second metal layer, laid on a surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the convex portion; and

[0012] The insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0013] In an embodiment of the present invention, a through silicon via structure is provided in the first adapter plate and the second adapter plate.

[0014] In one embodiment of the present invention, a recess is provided on a surface of the first adapter plate close to the second adapter plate and between two adjacent through-silicon via structures; and a protrusion is provided on a surface of the second adapter plate close to the first adapter plate and between two adjacent through-silicon via structures.

[0015] In one embodiment of the present invention, two or more recesses are provided on a surface of the first adapter plate close to the second adapter plate, between two adjacent through-silicon via structures; and two or more protrusions are provided on a surface of the second adapter plate close to the first adapter plate, between two adjacent through-silicon via structures.

[0016] In one embodiment of the present invention, the concave portion and the convex portion are in the shape of a rectangle, a pentagon, a hexagon, or a rectangle, a pentagon, or a hexagon with rounded corners.

[0017] In one embodiment of the present invention, the first metal layer includes a first capacitor metal layer, which covers the concave portion; the second metal layer includes a second capacitor metal layer, which covers the convex portion, and the second capacitor metal layer and the first capacitor metal layer are arranged in alignment.

[0018] In one embodiment of the present invention, the first metal layer includes a first contact metal layer, and the first contact metal layer is arranged on both sides of the first capacitor metal layer; the second metal layer includes a second contact metal layer, and the second contact metal layer is arranged on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are arranged in alignment.

[0019] In one embodiment of the present invention, the sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal layer, the second capacitor metal layer and the insulating layer.

[0020] In an embodiment of the present invention, the first metal layer includes one first capacitor metal layer and two first contact metal layers, and the second metal layer includes one second capacitor metal layer and two second contact metal layers.

[0021] In one embodiment of the present invention, the first metal layer includes at least two first capacitor metal layers, at least two first capacitor metal layers are laid on the surface of the first adapter plate, and each of the first capacitor metal layers covers one of the recessed portions, and a gap is provided between two adjacent first capacitor metal layers; the second metal layer includes at least two second capacitor metal layers, at least two second capacitor metal layers are laid on the surface of the second adapter plate, and each of the second capacitor metal layers covers one of the protruding portions, and a gap is provided between two adjacent second capacitor metal layers.

[0022] The present invention also provides a method for manufacturing a packaged chip, which comprises at least the following steps:

[0023] Providing a first adapter plate and a second adapter plate;

[0024] Etching a surface of the first adapter plate close to the second adapter plate to form at least one concave portion;

[0025] Etching the surface of the second adapter plate close to the first adapter plate to form at least one convex portion, wherein the convex portion is aligned and nested with the concave portion;

[0026] Laying a first metal layer on a surface of the first adapter plate close to the second adapter plate, wherein the first metal layer covers the concave portion;

[0027] Laying a second metal layer on the surface of the second adapter plate close to the first adapter plate, wherein the second metal layer covers the protrusion;

[0028] The second transfer plate is bonded to the first transfer plate, and an insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0029] In summary, the present invention provides a packaged chip and a manufacturing method thereof, which adopts a system-level packaging structure, and chips with multiple functions are packaged in one package, so that the system is more integrated and smaller in size. And the capacitor device is integrated in the three-dimensional direction to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. By bonding the chips between the adapter plates, a large capacitor device is formed, and the entire system is the same size as the chip, with a smaller size and a lower thickness. Compared with the surface-mounted capacitor, the capacitor structure provided by the present application is closer to the device itself, which can better improve the performance of the device. At the same time, the electrode sheet of the capacitor device is formed on the bonding surface of the two passive silicon-based adapter plates, which greatly increases the area of ​​the capacitor device and improves the capacitance of the capacitor device. Further, the capacitor is designed to be tooth-shaped, which effectively increases the capacitor area and further improves the capacitance value, thereby greatly improving the system performance. Moreover, relative to the SIP package, this package structure is reduced in size and has a better market prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0031] Figure 1 It is a structural schematic diagram of the first adapter board in one embodiment of the present application.

[0032] Figure 2 It is a schematic diagram of the structure of the second adapter board in one embodiment of the present application.

[0033] Figure 3 It is a structural schematic diagram of forming a recess on the first adapter plate in one embodiment of the present application.

[0034] Figure 4 It is a structural schematic diagram of a protrusion formed on the second adapter plate in one embodiment of the present application.

[0035] Figure 5 It is a structural schematic diagram of forming a first metal layer on the concave portion of the first adapter plate in one embodiment of the present application.

[0036] Figure 6 It is a structural schematic diagram of forming a second metal layer on the protrusion of the second adapter plate in one embodiment of the present application.

[0037] Figure 7 It is a schematic diagram of the structure of the bonding between the first adapter plate and the second adapter plate in one embodiment of the present application.

[0038] Figure 8 This is a schematic diagram of the structure in which a working chip is arranged on the first adapter board in one embodiment of the present application.

[0039] Description of labels:

[0040] 100, first adapter board; 101, through silicon via structure; 102, first solder pad; 103, recess; 104, first metal layer; 1041, first capacitor metal layer; 1042, first contact metal layer; 105, insulating layer; 106, connecting metal layer; 107, protective layer; 1071, first protective layer; 1072, second protective layer; 200, second adapter board; 201, second solder pad; 202, protrusion; 203, second metal layer; 2031, second capacitor metal layer; 2032, second contact metal layer; 204, solder ball; 300, first chip; 400, second chip. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0044] In some embodiments, when forming an integrated circuit, working modules of various functions are independently packaged to form independent working chips, and then the working chips and capacitor devices are laid flat on the circuit board, and the working chips and capacitors are connected to each other through the circuit board to form a two-dimensional system on chip. As the integration of the system on chip continues to increase, more and more working chips need to be integrated on the circuit board, and the circuit board can no longer meet the line connection between chips. Therefore, in one embodiment of the present invention, a packaged chip is provided, and the working chip is set on a transfer board with a through silicon via structure to achieve 2.5D packaging of the working chip, which can ensure that the connection between the packaged working chips is shorter.

[0045] See also Figure 8 As shown, in one embodiment of the present invention, the packaged chip provided by the present application includes an adapter board, a capacitive device arranged between the adapter boards, and a working chip arranged on the adapter board. The adapter board includes a first adapter board 100 and a second adapter board 200, the first adapter board 100 and the second adapter board 200 are stacked in the thickness direction thereof, and the capacitive device is integrated between the two adapter boards stacked in the thickness direction.

[0046] It should be noted that if Figure 8As shown, the purpose of distinguishing the first adapter plate 100 from the second adapter plate 200 is to integrate the capacitive device between the adapter plates. In some embodiments, a complete adapter plate may be divided in the thickness direction to form the first adapter plate 100 and the second adapter plate 200.

[0047] See also Figure 8 As shown, in one embodiment of the present invention, the number of working chips arranged on the first adapter board 100 is set according to demand. That is, the present application does not limit the specific number of working chips in the packaged chip and the function of the working chip. The role of each working chip can be the same or different, and the specific function of the packaged chip can be realized. Similarly, the present application does not limit the number of capacitors formed between adjacent adapter boards. One capacitor can be formed between two working chips, or two or more capacitors can be formed between two working chips. It can be determined based on the capacitance of the required capacitor and the area occupied by the capacitor between the two working chips.

[0048] See also Figure 8 As shown, in one embodiment of the present invention, the capacitor device is arranged close to the power supply network, that is, when the working chip arranged on the adapter board has a power chip, the capacitor device is arranged in the adapter board at the position of the power chip. In one embodiment of the present invention, two working chips, a first chip 300 and a second chip 400, are arranged on the adapter board as an example for explanation. The first chip 300 is a storage chip, the second chip 400 is a power chip, and the first chip 300 and the second chip 400 form a complete system. In other embodiments, a third chip, a fourth chip or a fifth chip may also be arranged on the adapter board. The third chip, the fourth chip or the fifth chip are arranged side by side with the first chip 300 and the second chip 400 on the first adapter board 100, and the third chip, the fourth chip or the fifth chip may be any type of chip such as a central processing unit chip, a communication chip, a sensor, etc.

[0049] For details, please refer to Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a through silicon via (TSV) structure 101 is provided in the first adapter board 100 and the second adapter board 200, and the through silicon via structure 101 extends from the first surface of the first adapter board 100 and the second adapter board 200 to the inside of the first adapter board 100 and the second adapter board 200. The first surface and the second surface of the first adapter board 100 and the second adapter board 200 are two opposite surfaces of the first adapter board 100 and the second adapter board 200 in the thickness direction, and pads are provided on the first surfaces of the first adapter board 100 and the second adapter board 200, and the pads are connected to the through silicon via structure 101, which are external connection points of the first adapter board 100 and the second adapter board 200.

[0050] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the through silicon via structure 101 extends from the first surface of the first adapter plate 100 and the second adapter plate 200 to the inside of the first adapter plate 100 and the second adapter plate 200. When the through silicon via structure 101 is formed in the first adapter plate 100 and the second adapter plate 200, a through silicon via can be formed in the first adapter plate 100 and the second adapter plate 200 from the first surface of the first adapter plate 100 and the second adapter plate 200 by etching process and other means, and the through silicon via extends through the first adapter plate 100 and the second adapter plate 200. After the through silicon via is formed, a conductive material, such as a metal material such as copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited in the through silicon via to form the through silicon via structure 101.

[0051] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after forming the through silicon via structure 101, a conductive metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, may be deposited at the location of the through silicon via structure 101 to form a pad. The pad formed on the first surface of the first adapter board 100 is the first pad 102, and the pad formed on the first surface of the second adapter board 200 is the second pad 201.

[0052] See also Figures 1 to 4 As shown, in one embodiment of the present invention, after forming a first pad 102 on the first surface of the first adapter board 100 and forming a second pad 201 on the first surface of the second adapter board 200, the second surfaces of the first adapter board 100 and the second adapter board 200 are thinned until the through silicon via structure 101 is exposed from the second surfaces of the first adapter board 100 and the second adapter board 200. Specifically, the second surfaces of the first adapter board 100 and the second adapter board 200 can be polished by a chemical mechanical polishing (CMP) method to thin the first adapter board 100 and the second adapter board 200.

[0053] See also Figures 1 to 4 As shown, in one embodiment of the present invention, after the second surfaces of the first adapter plate 100 and the second adapter plate 200 are thinned, the second surfaces of the first adapter plate 100 and the second adapter plate 200 are etched to form a recess 103 on the second surface of the first adapter plate 100, and a protrusion 202 on the second surface of the second adapter plate 200, and the recess 103 on the second surface of the first adapter plate 100 and the protrusion 202 on the second surface of the second adapter plate 200 are correspondingly nested.

[0054] See also Figures 1 to 4As shown, in one embodiment of the present invention, when etching the second surface of the first adapter plate 100 and the second adapter plate 200, the first adapter plate 100 and the second adapter plate 200 can be etched according to the materials of the first adapter plate 100 and the second adapter plate 200. In some embodiments, the second surfaces of the first adapter plate 100 and the second adapter plate 200 are made of silicon, for example, and hydrogen fluoride (HF) can be used to dry-etch the first adapter plate 100 and the second adapter plate 200. Solutions such as hydrofluoric acid (HF) or nitric acid (HNO3) can also be used to wet-etch the first adapter plate 100 and the second adapter plate 200. In other embodiments, the substrates of the first adapter plate 100 and the second adapter plate 200 can also be organic material substrates, and the corresponding etching materials can be selected according to the organic materials of the first adapter plate 100 and the second adapter plate 200 for etching.

[0055] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, on the second surface of the first adapter plate 100, the recess 103 formed is located between adjacent through-silicon via structures 101, and the recess 103 between the multiple through-silicon via structures 101 forms a tooth-like structure. On the second surface of the second adapter plate 200, the protrusion 202 formed is located between adjacent through-silicon via structures 101, and the protrusion 202 between the multiple through-silicon vias forms a tooth-like structure. The present application does not specifically limit the positions of the recess 103 on the second surface of the first adapter plate 100 and the protrusion 202 on the second surface of the second adapter plate 200, so that the recess 103 on the second surface of the first adapter plate 100 and the protrusion 202 on the second surface of the second adapter plate 200 can be arranged in a nested manner, that is, when the first adapter plate 100 and the second adapter plate 200 are bonded, the protrusion 202 on the second surface of the second adapter plate 200 is nested in the recess 103 on the second surface of the first adapter plate 100.

[0056] It should be noted that if Figure 3 to Figure 4 As shown, the concave portion 103 and the convex portion 202 do not need to be disposed between every two adjacent TSV structures 101. The concave portion 103 or the convex portion 202 may be disposed between the TSV structures 101 according to specific requirements, so that there is a spacing between the concave portion 103 or the convex portion 202 and the TSV structure 101.

[0057] Combination Figures 5 and 6As shown, in the subsequent process of the present invention, a metal layer will be deposited on the concave portion 103 on the second surface of the first adapter plate 100 and the convex portion 202 on the second surface of the second adapter plate 200, thereby forming two electrode plates of the capacitor device. Therefore, the surface area of ​​the concave portion 103 on the second surface of the first adapter plate 100 and the convex portion 202 on the second surface of the second adapter plate 200 is related to the capacitance value of the capacitor device formed. In order to match the capacitance value of the capacitor device formed, the number of the concave portion 103 on the second surface of the first adapter plate 100 and the convex portion 202 on the second surface of the second adapter plate 200 can be adaptively adjusted. In some embodiments, a concave portion 103 is set between two adjacent through-silicon via structures 101 on the second surface of the first adapter plate 100, and a convex portion 202 is set between two adjacent through-silicon via structures 101 on the second surface of the second adapter plate 200. In other embodiments, two, three or more recesses 103 are provided between two adjacent through silicon via structures 101 on the second surface of the first adapter plate 100, and two, three or more convex portions 202 are provided between two adjacent through silicon via structures 101 on the second surface of the second adapter plate 200. By increasing the number of recesses 103 and convex portions 202 between two adjacent through silicon via structures 101, the surface area of ​​the second surface of the first adapter plate 100 and the second adapter plate 200 can be increased, thereby increasing the area size of the two electrode plates of the capacitor device and changing the capacitance of the capacitor device.

[0058] See also Figure 3 to Figure 4 As shown, the present application does not limit the shape of the concave portion 103 on the second surface of the first adapter plate 100 and the convex portion 202 on the second surface of the second adapter plate 200. In some embodiments, the concave portion 103 on the second surface of the first adapter plate 100 and the convex portion 202 on the second surface of the second adapter plate 200 are arranged in a rectangular shape. In other embodiments, the concave portion 103 on the second surface of the first adapter plate 100 can be arranged in a pentagon, hexagon, or a rectangle with rounded corners, a pentagon, a hexagon, etc., and the convex portion 202 on the second surface of the second adapter plate 200 is correspondingly arranged in a pentagon, a hexagon, or a rectangle with rounded corners, a pentagon, a hexagon, etc. After the metal layer and the insulating layer 105 are deposited on the second surface of the first adapter plate 100 and the second surface of the second adapter plate 200, the second surface of the first adapter plate 100 and the second surface of the second adapter plate 200 can be seamlessly bonded.

[0059] See also Figures 3 to 6As shown, in one embodiment of the present invention, after a concave portion 103 is formed on the second surface of the first adapter board 100 and a convex portion 202 is formed on the second surface of the second adapter board 200, a conductive metal material is deposited on the second surface of the first adapter board 100 to form a first metal layer 104. A conductive metal material is deposited on the second surface of the second adapter board 200 to form a second metal layer 203. The first metal layer 104 covers the concave portion 103 on the second surface of the first adapter board 100, and the second metal layer 203 covers the convex portion 202 on the second surface of the second adapter board 200. The conductive metal material is, for example, a metal material such as copper, aluminum, gold, or an alloy of two or three of these metal materials.

[0060] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the first metal layer 104 includes a first capacitor metal layer 1041 and a first contact metal layer 1042. The second metal layer 203 includes a second capacitor metal layer 2031 and a second contact metal layer 2032. The first capacitor metal layer 1041 covers the concave portion 103 of the second surface of the first adapter plate 100, and the second capacitor metal layer 2031 covers the convex portion 202 of the second surface of the second adapter plate 200. The first contact metal layer 1042 is arranged on both sides of the first capacitor metal layer 1041, and has a spacing with the first capacitor metal layer 1041. The second contact metal layer 2032 is arranged on both sides of the second capacitor metal layer 2031, and has a spacing with the second capacitor metal layer 2031. The first contact metal layer 1042 is connected to the silicon through hole structure 101 in the first adapter plate 100, and the second contact metal layer 2032 is connected to the silicon through hole structure 101 in the second adapter plate 200, and the signal transmission is realized after the first adapter plate 100 and the second adapter plate 200 are bonded.

[0061] See also Figure 5 and Figure 6As shown, in one embodiment of the present invention, the first capacitor metal layer 1041 and the second capacitor metal layer 2031 are arranged in alignment, and the first contact metal layer 1042 and the second contact metal layer 2032 are arranged in alignment. And the thickness of the first contact metal layer 1042 is greater than the thickness of the first capacitor metal layer 1041, and the thickness of the second contact metal layer 2032 is greater than the thickness of the second capacitor metal layer 2031. More specifically, the sum of the thickness of the first contact metal layer 1042 and the second contact metal layer 2032 is equal to the sum of the thickness of the first capacitor metal layer 1041, the second capacitor metal layer 2031, and the subsequent filling of the insulating layer 105 between the first capacitor metal layer 1041 and the second capacitor metal layer 2031. The thickness of the insulating layer 105 is determined by the capacity of the capacitor device to be formed. In one embodiment of the present invention, the thickness of the first capacitor metal layer 1041 and the second capacitor metal layer 2031 is, for example, 2um to 5um, specifically, for example, 3um, 4um or 5um. The thickness of the first contact metal layer 1042 and the second contact metal layer 2032 is, for example, 8 um to 15 um, specifically, 10 um, 11 um, or 13 um.

[0062] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after the first adapter plate 100 and the second adapter plate 200 are bonded, the first contact metal layer 1042 and the second contact metal layer 2032 are connected, and the first capacitor metal layer 1041 and the second capacitor metal layer 2031 correspond in position. That is, after the first adapter plate 100 and the second adapter plate 200 are bonded, in the thickness direction of the first adapter plate 100 and the second adapter plate 200, the first contact metal layer 1042 and the second contact metal layer 2032 are aligned, and the first capacitor metal layer 1041 and the second capacitor metal layer 2031 are aligned. After the first adapter plate 100 and the second adapter plate 200 are bonded, the connection of the first contact metal layer 1042 and the second contact metal layer 2032 realizes the bonding and signal transmission between the first adapter plate 100 and the second adapter plate 200. The first capacitor metal layer 1041 forms one electrode plate of the capacitor device, and the second capacitor metal layer 2031 forms the other electrode plate of the capacitor device.

[0063] See also Figure 5 and Figure 6As shown, in one embodiment of the present invention, the first metal layer 104 includes a first capacitor metal layer 1041 and two first contact metal layers 1042 arranged on both sides of the first capacitor metal layer 1041. The second metal layer 203 includes a second capacitor metal layer 2031 and two second contact metal layers 2032 arranged on both sides of the second capacitor metal layer 2031. At this time, a capacitor device can be formed in a subsequent process. In some other embodiments of the present invention, the first metal layer 104 includes at least two first capacitor metal layers 1041, at least two first capacitor metal layers 1041 are flat on the second surface of the first adapter plate 100, each first capacitor metal layer 1041 covers at least one recess 103, and two adjacent first capacitor metal layers 1041 are provided with a gap. Correspondingly, the second metal layer 203 includes at least two second capacitor metal layers 2031, at least two second capacitor metal layers 2031 are tiled on the second surface of the second adapter plate 200, at least two second capacitor metal layers 2031 are tiled on the second surface of the second adapter plate 200, each second capacitor metal layer 2031 covers at least one convex portion 202, and two adjacent second capacitor metal layers 2031 are provided with a gap. In other embodiments of the present invention, the first metal layer 104 includes a plurality of first contact metal layers 1042, and the second metal layer 203 includes a plurality of second contact metal layers 2032. A plurality of first contact metal layers 1042 are distributed on the second surface of the first adapter plate 100, and a plurality of second metal layers 203 are distributed on the second surface of the second adapter plate 200. After the first adapter plate 100 and the second adapter plate 200 are bonded, each first contact metal layer 1042 is connected to a second contact metal layer 2032. At this time, the number of capacitor devices formed is equal to the number of capacitor metal layers. Every two first capacitor metal layers 1041 and second capacitor metal layers 1042 arranged in opposite positions and the insulating layer 107 arranged between the first capacitor metal layer 1041 and the second capacitor metal layer 1042 form a capacitor device.

[0064] See also Figures 5 to 7As shown, in one embodiment of the present invention, after forming a first metal layer 104 on the second surface of the first adapter board 100 and forming a second metal layer 203 on the second surface of the second adapter board 200, the first adapter board 100 and the second adapter board 200 are bonded. When bonding the first adapter board 100 and the second adapter board 200, an insulating material is filled between the first metal layer 104 and the second metal layer 203, and between the gaps between the first adapter board 100 and the second adapter board 200 to form an insulating layer 105. Among them, the material of the insulating layer 105 is a thermoplastic profile with a high dielectric constant, such as ABF (Ajinomoto Build-up Film) material, chip low filling glue, etc. The insulating layer 105 with a high dielectric constant can isolate the two electrode sheets of the capacitor device, and then cooperate with the first metal layer 104 and the second metal layer 203 to form a capacitor device. When the insulating layer 105 is disposed between the first adapter plate 100 and the second adapter plate 200, the thermoplastic profile with a high dielectric constant may be heated first to make it fluid, and then the thermoplastic profile may be used to fill the gap between the first adapter plate 100 and the second adapter plate 200. After the gap between the first adapter plate 100 and the second adapter plate 200 is filled, the thermoplastic profile is cooled and solidified to form the insulating layer 105.

[0065] See also Figure 7 As shown, in one embodiment of the present invention, after the first adapter plate 100 and the second adapter plate 200 are bonded, the tooth-like structure formed by the concave portion 103 on the second surface of the first adapter plate 100 and the tooth-like structure formed by the convex portion 202 on the second surface of the second adapter plate 200 are aligned and nested. The insulating layer 105 fills the gap between the first capacitor metal layer 1041 and the second capacitor metal layer 2031 to form a capacitor device. At the same time, the first contact metal layer 1042 and the second contact metal layer 2032 are connected, and the insulating layer 105 fills the gap on both sides of the first contact metal layer 1042 and the second contact metal layer 2032, playing a supporting role between the first adapter plate 100 and the second adapter plate 200.

[0066] See also Figures 7 and 8 As shown, in one embodiment of the present invention, after forming the capacitor device, a conductive metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, is deposited on the first surface of the first adapter board 100 to form a connecting metal layer 106. The connecting metal layer 106 realizes the connection between the working chips.

[0067] See also Figures 7 and 8As shown, in one embodiment of the present invention, after forming the connection metal layer, the first chip 300 and the second chip 400 are welded on the connection metal layer 106, and an insulating material is deposited on the first chip 300 and the second chip 400 to form a protective layer 107. A solder ball 204 is formed on the second pad 201 on the first surface of the second adapter board 200 by reflow soldering. Then the packaging of the first adapter board 100, the second adapter board 200, the first chip 300 and the second chip 400 is completed. In this embodiment, the protective layer 107 includes a first protective layer 1071 and a second protective layer 1072. The first protective layer 1071 is arranged between the first chip 300 and the first adapter board 100, and between the second chip 400 and the first adapter board 100, filling the gap between the first chip 300, the second chip 400 and the first adapter board 100. The second protective layer 1072 is arranged on the first chip 300 and the second chip 400, covering the first chip 300 and the second chip 400. In this embodiment, the particle size of the first protective layer 1071 is smaller than that of the second protective layer 1072. The first protective layer 1071 is made of, for example, a resin material with a smaller particle size, and the second protective layer 1072 is made of, for example, an organic plastic material with a larger particle size.

[0068] In summary, the present invention provides a packaged chip and a method for manufacturing the same, wherein a capacitor device is integrated between a first adapter plate and a second adapter plate, a working chip is arranged on the first adapter plate, and at least one recess is formed on the surface of the first adapter plate close to the second adapter plate, and at least one recess is formed on the surface of the second adapter plate close to the first adapter plate, and the protrusions are aligned and nested with the recesses. Afterwards, a first metal layer is laid on the surface of the first adapter plate close to the second adapter plate, the first metal layer covers the recesses, and a second metal layer is laid on the surface of the second adapter plate close to the first adapter plate, the second metal layer covers the protrusions. Finally, the first adapter plate and the second adapter plate are bonded, and an insulating layer is arranged between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device. The capacitor device is integrated in the packaged chip, and the capacitor structure is placed close to the power supply network.

[0069] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A packaged chip, characterized in that: At least: A first adapter plate and a second adapter plate, wherein the second adapter plate is bonded to the first adapter plate; A working chip is arranged on a side of the first adapter board away from the second adapter board; At least one recessed portion is disposed on a surface of the first adapter plate close to the second adapter plate; At least one concave portion is provided on a surface of the second adapter plate close to the first adapter plate, and the convex portion is aligned and nested with the concave portion; A first metal layer is laid on a surface of the first adapter plate close to the second adapter plate, and the first metal layer covers the concave portion; a second metal layer, laid on a surface of the second adapter plate close to the first adapter plate, and the second metal layer covers the convex portion; as well as The insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

2. A packaged chip according to claim 1, characterized in that: A through silicon via structure is provided in the first adapter plate and the second adapter plate.

3. A packaged chip according to claim 2, characterized in that: A recess is provided on a surface of the first adapter plate close to the second adapter plate and between two adjacent through silicon via structures; a protrusion is provided on a surface of the second adapter plate close to the first adapter plate and between two adjacent through silicon via structures.

4. The packaged chip according to claim 2, characterized in that: Two or more recesses are provided on a surface of the first adapter plate close to the second adapter plate and between two adjacent through silicon via structures; two or more protrusions are provided on a surface of the second adapter plate close to the first adapter plate and between two adjacent through silicon via structures.

5. The packaged chip according to claim 1, characterized in that: The concave portion and the convex portion are arranged in a rectangular, pentagonal, hexagonal shape or in a rectangular, pentagonal, or hexagonal shape with rounded corners.

6. The packaged chip according to claim 1, characterized in that: The first metal layer includes a first capacitor metal layer, which covers the concave portion; the second metal layer includes a second capacitor metal layer, which covers the convex portion, and the second capacitor metal layer and the first capacitor metal layer are arranged in alignment.

7. The packaged chip according to claim 6, characterized in that: The first metal layer includes a first contact metal layer, which is arranged on both sides of the first capacitor metal layer; the second metal layer includes a second contact metal layer, which is arranged on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are arranged in alignment.

8. The packaged chip according to claim 7, characterized in that: The sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal, the second capacitor metal layer and the insulating layer.

9. The packaged chip according to claim 7, characterized in that: The first metal layer includes one first capacitor metal layer and two first contact metal layers, and the second metal layer includes one second capacitor metal layer and two second contact metal layers.

10. The packaged chip according to claim 7, characterized in that: The first metal layer includes at least two first capacitor metal layers, at least two of the first capacitor metal layers are laid on the surface of the first adapter board, and each of the first capacitor metal layers covers one of the recessed portions, and a gap is set between two adjacent first capacitor metal layers; the second metal layer includes at least two second capacitor metal layers, at least two of the second capacitor metal layers are laid on the surface of the second adapter board, and each of the second capacitor metal layers covers one of the protruding portions, and a gap is set between two adjacent second capacitor metal layers.

11. A method for manufacturing a packaged chip, characterized in that: At least the following steps are included: Providing a first adapter plate and a second adapter plate; Etching a surface of the first adapter plate close to the second adapter plate to form at least one concave portion; Etching the surface of the second adapter plate close to the first adapter plate to form at least one convex portion, wherein the convex portion is aligned and nested with the concave portion; Laying a first metal layer on a surface of the first adapter plate close to the second adapter plate, wherein the first metal layer covers the concave portion; Laying a second metal layer on the surface of the second adapter plate close to the first adapter plate, wherein the second metal layer covers the protrusion; The second transfer plate is bonded to the first transfer plate, and an insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer, the insulating layer and the second metal layer form a capacitor device.

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