A high voltage modulation circuit supporting continuous and high repetition rate pulse operation

Abstract

The present invention provides a high-voltage modulation circuit supporting continuous and high-repetition-rate pulse operation, relates to the technical field of microwave millimeter-wave phased array radar, and solves the defect problem that the prior art cannot simultaneously support continuous operation and high-repetition-rate pulse operation under high-voltage input; in the high-voltage modulation circuit, the input signal driving circuit is used to control the integrated gate driver through a first complementary driving signal; the gate voltage control power supply circuit is used to control the power supply of the input signal driving circuit according to the gate voltage of the final power amplifier chip; the integrated gate driver is used to control the conduction and shutdown of the modulation switch tube and the discharge tube respectively according to the first complementary driving signal; the dead zone adjustment circuit is used to adjust the switching speed of the modulation switch tube and the discharge tube; the isolation power supply circuit is used to power the integrated gate driver to maintain the conduction of the modulation switch tube under high-voltage input; the present invention has the advantages of high design adjustment freedom, safe circuit logic, adaptation to various working scenarios and multi-platform multi-purpose applications.

Description

Technical Field

[0001] The invention relates to the field of modulation and power supply of a final-stage power amplifier chip of a microwave and millimeter-wave phased array radar, and in particular to a high-voltage modulation circuit supporting continuous and high-repetition-rate pulse operation. Background Art

[0002] A power amplifier chip is a radio frequency device that amplifies radio frequency signals and outputs them to the antenna. It is one of the core components of microwave millimeter wave radars, and it determines important parameters such as the radar's transmission power, operating frequency, and signal quality. A power amplifier chip is usually made of semiconductor materials. Depending on the semiconductor material, the power amplifier chip can be divided into several types, such as silicon-based, gallium arsenide, and gallium nitride. Gallium nitride belongs to the third generation of semiconductor materials (also known as wide bandgap semiconductor materials). Its bandgap width, electron saturation migration velocity, breakdown field strength, and operating temperature are much greater than those of silicon and gallium arsenide, and it has inherent advantages as a radio frequency device. Gallium nitride power amplifier chips are considered to be the most advanced type at present. They have the advantages of high power density, high efficiency, high frequency, and high temperature stability, and can achieve the goals of miniaturization, low cost, and low heat dissipation. Its advantages in power, heat dissipation, and reliability, with a smaller volume at the same or even higher output power, are more conducive to the miniaturization and lightness of the radar system, making it more suitable for radar applications with various functions.

[0003] In the design of electronic jamming radar, the modulation methods of GaN power amplifier chips are divided into gate modulation and drain modulation. Gate modulation is to change the conduction and pinch-off between the drain D and source S by modulating the gate voltage VG of the power amplifier chip to achieve the working state switching of the power amplifier chip; because the gate voltage VG is low when the drain D and source S are pinched off, the working state of the power amplifier chip can easily enter the breakdown region, causing damage to the power amplifier chip, so the working stability is poor. Drain modulation is to change the power supply state of the drain D to achieve the modulation switching between the working state and the non-working state of the power amplifier chip. Compared with gate modulation, drain modulation has obvious advantages in working stability and long-term reliability, but it is necessary to design a reasonable drain power supply modulation circuit to meet the requirements of the power amplifier for the rising and falling edges of the rapid changes in the power supply voltage.

[0004] The drain operating voltage of the GaN power amplifier chip is generally at a relatively high voltage of 20~50V. Therefore, the circuit design usually adopts the high-voltage modulation drive of the enhancement MOS tube to power the drain modulation of the GaN power amplifier chip. Based on the type of enhancement MOS tube, there are high-voltage drive solutions based on PMOS modulation switch tubes and high-voltage drive solutions based on NMOS modulation switch tubes. The patent with publication number CN104796098A proposes a GaN power device drain modulation circuit, such as Figure 1As shown, it uses PMOS as the modulation switch tube. The advantage is that the high-voltage drive of PMOS is simple, and the disadvantage is that the carriers of PMOS are holes, while the carriers of NMOS are electrons. The electron mobility is 5 to 10 times that of the hole mobility. The semiconductor material with high carrier mobility has a lower resistivity. When the same current passes through it, the loss is smaller. This leads to the on-resistance Rdson of PMOS being several times larger than that of NMOS under the same volume and doping conditions, and the loss is also several times larger. At the same time, the carriers also affect the operating frequency and response speed of the device. The operating frequency and response speed of PMOS devices are significantly lower than those of NMOS. Therefore, due to the influence of process differences, PMOS has greater switching loss and conduction loss than NMOS, smaller current capacity, and lower withstand voltage. It is not suitable for high-voltage, high-current, and high-repetition-rate application scenarios with edge requirements of less than 50ns and about 800kHz.

[0005] For the NMOS high-voltage drive solution, its drive circuit is more complicated than that of PMOS. The main problem to be solved is that after the high-voltage NMOS is turned on, the source S is approximately equal to the high voltage of the drain D. The patent with publication number CN104917467A proposes a drain modulation circuit for GaN microwave power amplifiers, such as Figure 2 As shown, it adopts the bootstrap method to drive NMOS high voltage. One end of the bootstrap capacitor Cboot is connected to the source S of the NMOS tube, and the other end is connected to the BOOST power supply end of the integrated driver. After the NMOS tube is turned on, the source voltage is raised to close to the drain voltage Vdd2. Based on the principle that the voltage across the bootstrap capacitor Cboot cannot change suddenly, the voltage of the bootstrap capacitor Cboot connected to the BOOST end is raised to Vdd2+Vgs, maintaining the voltage difference between the gate and source voltage Vgs of the NMOS tube, which can maintain the conduction of the NMOS tube; this driving method adds devices such as bootstrap diodes and bootstrap capacitors. If the circuit design is reasonable, it can quickly drive the NMOS tube to turn on and off, so that the NMOS works in a high repetition rate switching state. However, the Cboot capacitor needs to have charging time during the switching operation to charge both ends of the capacitor to supplement the charge at both ends of the bootstrap capacitor. Otherwise, the Cboot charge will gradually decrease in the process of driving the NMOS. When it decreases to a certain level, the voltage at both ends of Cboot cannot support the NMOS tube to be fully turned on, which will cause the on-resistance Rdson of the NMOS to gradually increase due to insufficient driving capability, increase heat consumption, and eventually damage due to excessive heat. Therefore, due to the objective necessity of charging time, the duty cycle cannot reach 100%, that is, the bootstrap drive cannot be used in continuous working scenarios.

[0006] Another NMOS high-voltage drive solution, such as the patent with publication number CN117424572A, proposes a high-voltage and high-current driven GaN power amplifier drain modulation circuit, such as Figure 3As shown, it uses a high-voltage floating charge pump to drive NMOS high voltage. This driving method designs a high-voltage floating charge pump circuit U5 to charge the flying capacitor C1, so that there is a 5V voltage difference across C1, so that there can be a 5V gate-source drive voltage difference Vgs when the NMOS tube is turned on, ensuring the normal conduction and shutdown of NMOS. This driving method can realize the application scenarios of continuous operation and pulse operation. The disadvantage is that because the internal resistance of the flying capacitor C1 of the floating charge pump circuit as a source is large, the output driving capability is weak, and the peak driving capability can usually only reach the level of hundreds of mA, while the peak driving capability required for the high repetition rate switching of the high-voltage NMOS is at the level of several A, which causes the output edge of the driving NMOS of the high-voltage floating charge pump to be relatively slow, often around 100ns~200ns. Therefore, under pulse operation, the effective pulse width will be reduced by about 300ns~400ns, which is only suitable for application scenarios with a repetition rate pulse of tens of kHz and a large duty cycle, but cannot be used in application scenarios with high repetition rate switching above hundreds of kHz, especially small duty cycle application scenarios. In addition, since the energy storage of the capacitor is limited and the driving discharge speed is greater than the charging speed, the 5V voltage across the capacitor gradually drops during the discharge process. Soon, the NMOS tube will not be fully turned on due to the large drop in Vgs, and Rdson will increase accordingly. The NMOS tube will be damaged by overheating. Therefore, it is often not used for pulse work or continuous work with a pulse width exceeding ms. Summary of the invention

[0007] Based on the current status of the background technology, the purpose of the present invention is to solve the limitation problem of the existing driving scheme in the application scenario, and therefore a high-voltage modulation circuit supporting continuous and high repetition rate pulse operation is proposed. The present invention has the advantages of high design adjustment freedom, safe circuit logic, adaptation to various working scenarios and multi-platform multi-purpose applications.

[0008] The present invention adopts the following technical solutions to achieve the purpose:

[0009] The invention discloses a high-voltage modulation circuit which supports continuous and high-repetition-rate pulse operation and drives and modulates a final-stage power amplifier chip in a radar by controlling the supply voltage.

[0010] The high-voltage modulation circuit includes an input signal driving circuit, a gate voltage control power supply circuit, an integrated gate driver, a dead zone adjustment circuit, a modulation switch tube, a discharge tube and an isolation power supply circuit; the input signal driving circuit is respectively connected to the gate voltage control power supply circuit and the integrated gate driver, the integrated gate driver is respectively connected to the dead zone adjustment circuit and the isolation power supply circuit, the dead zone adjustment circuit is respectively connected to the modulation switch tube and the discharge tube; the isolation power supply circuit is also connected to the modulation switch tube; the gate voltage control power supply circuit, the modulation switch tube and the discharge tube are all connected to the final power amplifier chip.

[0011] The input signal driving circuit is used to control the integrated gate driver through the first complementary driving signal; the gate voltage control power supply circuit is used to control the power supply of the input signal driving circuit according to the gate voltage of the final power amplifier chip; the integrated gate driver is used to control the conduction and shutdown of the modulation switch tube and the discharge tube respectively according to the first complementary driving signal; the dead zone adjustment circuit is used to adjust the switching speed of the modulation switch tube and the discharge tube; the isolation power supply circuit is used to power the integrated gate driver to maintain the conduction of the modulation switch tube under high voltage input.

[0012] Furthermore, the input signal driving circuit is also connected to the main control chip (such as FPGA, etc.), and receives the modulation control input signal SWITCH and the power-on enable signal EN given by the main control chip, thereby outputting the first complementary driving signal to control the integrated gate driver through the two control signals SWITCH and EN. The modulation control input signal SWITCH is a normally high control signal for realizing continuous operation, or a high repetition rate pulse control signal for realizing high repetition rate pulse operation.

[0013] Furthermore, both the modulation switch tube and the discharge tube use NMOS tubes. Both use high-voltage NMOS tubes, and the maximum value of their on-resistance Rdson is 10mΩ. At the same time, the current carrying capacity Id value is large, which can ensure that the drain-source voltage drop is very small when switching high voltage and high current. Compared with high-voltage PMOS with similar on-resistance and current carrying capacity, the Ciss, Crss, and Coss capacitances of NMOS tubes are very small, ensuring that they are suitable for high-repetition switching scenarios, and NMOS has greater advantages over PMOS in terms of package size, cost, and process quality.

[0014] Furthermore, the integrated gate driver is used to output a high-side MOS tube gate drive signal and a low-side MOS tube gate drive signal after receiving a first complementary drive signal output by the input signal drive circuit. The high-side MOS tube gate drive signal is used to drive the on and off of the modulation switch tube, and the low-side MOS tube gate drive signal is used to drive the on and off of the discharge tube. The pull-out and injection capabilities of the gate drive signals of these two driving MOS tubes are both at the A level, and the driving capability is large, so the modulation switch tube and the discharge tube can be quickly turned on and off.

[0015] Furthermore, the gate voltage control power supply circuit is used to cut off the VCC power supply of the input signal driving circuit and prohibit it from outputting the first complementary driving signal when the gate voltage of the final stage power amplifier chip is abnormal; conversely, when the gate voltage of the final stage power amplifier chip is normal, the input signal driving circuit is powered to output the first complementary driving signal.

[0016] Furthermore, the dead zone adjustment circuit includes a first debugging circuit and a second debugging circuit respectively arranged in the gate drive loops of the modulation switch tube and the discharge tube; the first debugging circuit is used to adjust the gate drive current size and the drive voltage edge of the modulation switch tube, and the second debugging circuit is used to adjust the gate drive current size and the drive voltage edge of the discharge tube; the purpose of the two debugging circuits is to adjust the speed of conduction and shutdown of the modulation switch tube and the discharge tube when driving different loads, so as to achieve the problem that the modulation switch tube and the discharge tube can switch between the on and off states quickly without being turned on at the same time, causing the power rail to short-circuit to the ground and damage related components.

[0017] Furthermore, since the input current of the integrated gate driver reaches several A level and the current is relatively large, the dead zone adjustment circuit also includes a PNP transistor current discharge loop, and the PNP transistor current discharge loop corresponds to the source setting of the modulation switch tube and / or the discharge tube; the PNP transistor current discharge loop is used for the gate-source charge discharge of the modulation switch tube and / or the discharge tube on the one hand, so that the modulation switch tube and / or the discharge tube are quickly turned off, and on the other hand, it limits the discharge current from flowing back to the integrated gate driver to achieve the purpose of protecting the driver.

[0018] Furthermore, the positive electrode of the isolated power supply circuit is connected to the BST pin of the integrated gate driver, and the negative electrode is connected to the source of the modulation switch tube; the isolated power supply circuit is used to maintain the gate drive voltage of the modulation switch tube through the isolated power supply voltage after the modulation switch tube is turned on, and the isolated power supply voltage is greater than the turn-on threshold voltage of the modulation switch tube, so that the modulation switch tube is continuously in the on state. The main function of the isolated power supply circuit is to realize the conduction of the modulation switch tube under high voltage input; because the high voltage input is different from the low voltage input, after the modulation switch tube is turned on, its source voltage rises to the high voltage input voltage close to the drain, and the gate drive voltage needs to be higher than the source voltage at this time, otherwise the modulation switch tube will not be able to maintain the on state at the moment of turning on because the gate-source voltage difference is lower than the turn-on threshold voltage Vgs(th), resulting in shutdown.

[0019] Furthermore, the isolated power supply circuit is also connected to the main control chip, receives the pulse switching control signal sent by the main control chip, and outputs the second complementary drive signal according to the pulse switching control signal; the second complementary drive signal is connected to both ends of the primary winding of the pulse transformer, and the energy can be converted through electricity, magnetism and electricity by switching between the second complementary drive signals, thereby achieving the purpose of energy isolation and transmission between the primary winding and the secondary winding of the pulse transformer. Among them, the turns ratio of the primary winding to the secondary winding of the pulse transformer is 1:1, so the primary voltage difference and the secondary voltage difference are nearly equal after removing the loss. The secondary winding of the pulse transformer is respectively connected to the integrated gate driver and the modulation switch tube.

[0020] Usually, the turn-on threshold voltage of high-voltage NMOS is between 1V and 4V, but to be fully turned on it must reach about 6V to 8V. Combined with the fact that the maximum gate-source voltage difference of NMOS is usually ±20V, the primary voltage difference can be set to 12V in the design, so that the secondary voltage difference is close to 12V; even in the continuous working state, the modulation switch tube must continuously maintain the on state. At this time, the gate voltage will drop due to continuous discharge, but it can also ensure that the NMOS is fully turned on.

[0021] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:

[0022] The present invention supplies power to the integrated gate driver BST through the designed isolated power supply circuit, provides continuous large current to drive the conduction of the modulation switch tube, realizes the rapid conduction of the modulation switch tube under high voltage input, and ensures that the modulation switch tube can work in both a continuous conduction state and a high repetition rate pulse switching working state.

[0023] The present invention adjusts the gate drive of the modulation switch tube and the discharge tube respectively through the designed dead zone adjustment circuit, realizes the alternating on and off of the modulation switch tube and the discharge tube, and avoids the risk of the input high voltage power supply directly passing to the ground due to the simultaneous on of the modulation switch tube and the discharge tube. When working with high repetition rate pulse switching, the powerful driving ability of the integrated gate driver and the large current discharge ability of the transistor in the dead zone adjustment circuit ensure the rapid on and off of the modulation switch tube and the discharge tube, realizes the effect of short rising and falling edge time of the drain power supply of the final power amplifier chip, and ensures the effective application of high voltage power supply and working pulse width.

[0024] The present invention introduces the gate voltage of the final power amplifier chip into the power supply control method, thereby ensuring the power-on timing requirement that the gate voltage of the final power amplifier chip is powered on first and the drain voltage is powered on later. Combined with the overall circuit structure solution of the present invention, the present invention solves the defect that the prior art cannot support continuous operation and high repetition rate pulse operation at the same time under high voltage input, and has the advantages of high design and adjustment freedom, safe circuit logic, adaptation to various working scenarios, and multi-platform and multi-purpose application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a conventional GaN power device drain modulation circuit;

[0026] Figure 2 A schematic diagram of a drain modulation circuit for an existing GaN microwave power amplifier;

[0027] Figure 3 A schematic diagram of a drain modulation circuit of an existing high-voltage and high-current driven GaN power amplifier;

[0028] Figure 4It is a structural schematic diagram of the high voltage modulation circuit of the present invention;

[0029] Figure 5 It is a partial electrical principle example diagram of the high voltage modulation circuit of the present invention;

[0030] Figure 6 This is an example diagram of the electrical principle of the gate voltage control power supply circuit in the high voltage modulation circuit of the present invention;

[0031] Figure 7 This is an example diagram of the electrical principle of the isolated power supply circuit in the high-voltage modulation circuit of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Example 1

[0035] A high-voltage modulation circuit that supports continuous and high-repetition-rate pulse operation, the high-voltage modulation circuit drives and modulates the final power amplifier chip in the radar by controlling the supply voltage. In this embodiment, Figure 4 As shown, the high-voltage modulation circuit includes an input signal driving circuit, a gate voltage control power supply circuit, an integrated gate driver, a dead zone adjustment circuit, a modulation switch tube, a discharge tube and an isolation power supply circuit; the input signal driving circuit is respectively connected to the gate voltage control power supply circuit and the integrated gate driver, the integrated gate driver is respectively connected to the dead zone adjustment circuit and the isolation power supply circuit, the dead zone adjustment circuit is respectively connected to the modulation switch tube and the discharge tube; the isolation power supply circuit is also connected to the modulation switch tube; the gate voltage control power supply circuit, the modulation switch tube and the discharge tube are all connected to the final power amplifier chip.

[0036] In this embodiment, the input signal driving circuit is used to control the integrated gate driver through the first complementary driving signal; the gate voltage control power supply circuit is used to control the power supply of the input signal driving circuit according to the gate voltage of the final power amplifier chip; the integrated gate driver is used to control the conduction and shutdown of the modulation switch tube and the discharge tube respectively according to the first complementary driving signal; the dead zone adjustment circuit is used to adjust the switching speed of the modulation switch tube and the discharge tube; the isolation power supply circuit is used to power the integrated gate driver to maintain the conduction of the modulation switch tube under high voltage input.

[0037] like Figure 5 As shown, this embodiment provides a specific circuit example and introduces the input signal driving circuit, integrated gate driver, dead zone adjustment circuit, modulation switch tube, and discharge tube in the high-voltage modulation circuit. Figure 5 The model of chip U1 is LTC4449, and the model of chip U2 is LTC4446.

[0038] First, the input signal driving circuit receives the modulation control input signal SWITCH and the power-on enable signal EN given by the main control chip such as FPGA; when continuous operation is required, SWITCH is a normally high level signal; when pulse operation is required, SWITCH is a pulse signal with a corresponding switching frequency of f and a duty cycle of D.

[0039] When the drain modulation of the final power amplifier chip needs to be powered, the EN signal is pulled high, and the TG and BG pins of chip U1 output the corresponding control signal, that is, the first complementary drive signal; when the drain modulation of the final power amplifier chip does not need to be powered, the EN signal is pulled low, and the TG and BG pins of chip U1 are both normally low, and the entire circuit does not work. Through the two control signals SWITCH and EN from the main control chip, the input signal drive circuit, that is, the output of chip U1, is controlled to obtain the complementary drive signals TG and BG, thereby controlling the integrated gate driver.

[0040] In this embodiment, the chip U1 has a dead zone protection function inside, which can ensure that its TG and BG pins will not be high at the same time in hardware, and the output drive signal is a complementary state. Among them, TG is a signal in phase with the input SWITCH, and BG is a signal in phase with the input SWITCH. When working continuously, SWITCH is a normally high VCC1 level signal; when working in pulses, SWITCH is a pulse signal switching between 0V / VCC1 consistent with the pulse switching repetition frequency.

[0041] The VCC and BST pins of chip U1 are connected to the VCC1 power rail. The VCC1 level is usually 5V, and its power supply is controlled by the gate voltage of the final amplifier chip. Figure 6The circuit example shows that the power supply circuit of the final power amplifier chip is controlled by the gate voltage of the final power amplifier chip to realize the power-on of the chip U1; specifically, when the gate voltage PA_VG of the final power amplifier chip exists, the transistor Q3 is turned on, the voltage across the resistor R13 exceeds the turn-on threshold voltage of the PMOS, the PMOS is turned on, and the VCC power supply rail is connected to VCC1, so that the VCC1 of the chip U1 is powered on, and at the same time, the safety timing requirement that the gate voltage PA_VG of the final power amplifier chip is powered on first is realized.

[0042] The TG and BG signals output by chip U1 are connected to the TINP and BINP pins of the integrated gate driver, i.e., chip U2; among them, TINP is the input control signal of the modulation switch tube, and BINP is the input control signal of the discharge tube. Correspondingly, the output TG of chip U2 is the modulation switch tube gate drive signal in phase with TINP, and the output BG is the discharge tube gate drive signal in phase with BINP. The TG level changes between BST and TS of chip U2, that is, the signal that changes between VDD and VGND here; the BG level changes between VCC and GND, that is, the signal that changes between VCC2 and GND here.

[0043] In this embodiment Figure 5 , Figure 6 In the example circuit, the push-pull outputs TG and BG inside the chip U2 have a pull-sink capacity of 4A, which can ensure the rapid on and off of the modulation switch tube and the discharge tube. In this embodiment, a dead zone adjustment circuit is added between TG and the modulation switch tube, and between BG and the discharge tube, in order to avoid the modulation switch tube and the discharge tube being turned on at the same time, causing the VB high-voltage power rail to be short-circuited to the ground.

[0044] Specifically, when the TG output is high, the driving current passes through the resistor R1 and the diode D1, and controls the modulation switch tube NMOS1 to turn on; when the TG output is low, the gate-source voltage Vgs charge of the modulation switch tube NMOS1 passes through the transistor Q1 and the resistor R2 to form the base current loop of the transistor Q1. After the transistor Q1 is turned on, the Vgs charge of the modulation switch tube NMOS1 is directly discharged to the source of the modulation switch tube through the ec pole of the transistor Q1; because the transistor Ic=β*Ib, β is usually between 100 and 300, so the Vgs charge of the modulation switch tube NMOS1 can be quickly discharged through the transistor Q1, realizing the relatively slow opening and fast closing function of the modulation switch tube NMOS1. At the same time, by discharging the current to the source of the modulation switch tube through the transistor Q1, it can also avoid the discharge peak current from impacting the TG pin of the chip U2, and avoid its TG pin from being subjected to large transient electrical stress.

[0045] When the BG output is high, the driving current passes through the resistor R4 and the diode D2, and controls the discharge tube NMOS2 to turn on; when the BG output is low, the Vgs charge of the discharge tube NMOS2 passes through the transistor Q2 and the resistor R5 to form the base current loop of the transistor Q2, and the Vgs charge of the discharge tube NMOS2 is directly discharged to the ground through the ec pole of the transistor Q2; because the transistor Ic=β*Ib, β is usually between 100 and 300, the Vgs charge of the discharge tube NMOS2 can be quickly discharged through the transistor Q2, and the relatively slow opening and fast closing function of the discharge tube NMOS2 is also realized. At the same time, by discharging the current to the ground by the transistor Q2, it can also avoid the discharge peak current from impacting the BG pin of the chip U2, and avoid its BG pin from being subjected to large transient electrical stress. The alternating on / off of the modulation switch tube NMOS1 and the discharge tube NMOS2 realizes the modulation power supply of the drain of the final power amplifier chip.

[0046] In this embodiment, due to the different number of final power amplifier chips, pin junction capacitance, etc. in different applications, the total capacitance of the modulation drain power supply network is different, which will cause the turn-on and turn-off edges of the modulation switch tube NMOS1 and the discharge tube NMOS2 to change, which may cause the phenomenon that one NMOS tube has not been completely turned off, and the other NMOS tube starts to turn on; in order to avoid device damage caused by the simultaneous conduction of two NMOS tubes, the dead zone adjustment circuit adjusts the edge timing through the four resistors R1, R2, R3 and R4 designed therein. The above-mentioned example circuit of this embodiment can be combined with Figure 5 and Figure 6 Synchronous view.

[0047] Example 2

[0048] Based on Example 1, this example introduces a high voltage modulation circuit, such as Figure 7 A specific example of the isolated power supply circuit shown in FIG. Figure 5 and Figure 6 The circuit diagram of the common description, Figure 7 The model of chip U3 in the circuit is LTC4444.

[0049] In this embodiment, since the BST pin of the chip U2 is connected to the VDD power rail of the isolated power supply circuit, and the TS pin is connected to the VGND of the isolated power supply circuit, when the modulation switch tube NMOS1 is turned on, its source voltage is close to the VB high voltage, which is equivalent to raising the VGND to the VB voltage. The isolated power supply circuit can maintain the voltage difference between VDD and VGND, so the absolute voltage of VDD becomes VB+VDD, that is, the high level of TG output reaches VB+VDD. At this time, the gate-source voltage Vgs=VB+VDD-VB=VDD of the modulation switch tube NMOS1, thereby ensuring that the high-voltage drive of the modulation switch tube NMOS1 is turned on.

[0050] In this embodiment, VDD and VGND are the outputs of the isolated power supply circuit, and the two constitute a group of isolated power supplies, which are isolated from other level networks such as VCC1 / VCC2. VDD and VGND are obtained through the isolated power supply circuit. Specifically, the control signals of the two pulse switches sent by the main control chip are sent to the TINP and BINP pins of the chip U3. Usually, the TTL pulse switching control signal input by TINP is a pulse signal with f=200kHz and D=40%; the TTL pulse switching control signal input by BINP is a pulse signal with f=200kHz and D=40%, but it is delayed by 2.5us compared with TINP. After passing through the chip U3, these two pulse signals obtain a group of complementary drive signals, namely the second complementary drive signal. The TG and BG of the chip U3 respectively obtain drive signals in phase with their TINP and BINP, and the complementary drive signals are respectively connected to the two ends of the primary winding of the pulse transformer T1. Through the switching of the complementary drive signals, the energy is converted from electric to magnetic to electric, and the purpose of energy isolation transmission is achieved between the primary winding and the secondary winding. In this embodiment, the turns ratio of the pulse transformer T1 is 1:1, so excluding the loss, the primary voltage difference and the secondary voltage difference are nearly equal. After the two pulse signals are switched from high to low, the secondary output VDD and VGND are obtained through the pulse transformer T1.

[0051] Usually, the turn-on threshold voltage of high-voltage NMOS is between 1V and 4V, but to be fully turned on, it needs to reach about 6V to 8V. Combined with the fact that the maximum gate-source voltage difference of NMOS is usually ±20V, the voltage difference of the primary winding is set to 12V in the design of this embodiment. The voltage difference between VDD and VGND corresponding to the secondary winding obtained in this way is also close to 12V, so that in the continuous working state, the modulation switch tube must continuously maintain the on state. Even if the gate voltage at this time drops due to continuous discharge, it can ensure that NMOS is fully turned on. The turns ratio of the primary winding and the secondary winding of the pulse transformer T1 is 1:1, so the voltage difference between VDD and VGND is also approximately 1:1 with the voltage difference between VCC2 and GND. In addition, Figure 7 The role of the resistor R9 is to suppress the LC oscillation formed by the parasitic inductance of the circuit traces on the PCB board and the capacitor C6. The role of the capacitor C6 is to block direct current and pass alternating current to prevent the core saturation of the pulse transformer T1.

Claims

1. A high voltage modulation circuit supporting continuous and high repetition rate pulse operation, characterized in that: The high-voltage modulation circuit drives and modulates the final power amplifier chip in the radar by controlling the supply voltage; The high voltage modulation circuit includes an input signal driving circuit, a gate voltage control power supply circuit, an integrated gate driver, a dead zone adjustment circuit, a modulation switch tube, a discharge tube and an isolation power supply circuit; The input signal driving circuit is respectively connected to the gate voltage control power supply circuit and the integrated gate driver, the integrated gate driver is respectively connected to the dead zone adjustment circuit and the isolation power supply circuit, the dead zone adjustment circuit is respectively connected to the modulation switch tube and the discharge tube; the isolation power supply circuit is also connected to the modulation switch tube; the gate voltage control power supply circuit, the modulation switch tube and the discharge tube are all connected to the final power amplifier chip; The input signal driving circuit is used to control the integrated gate driver through the first complementary driving signal; the gate voltage control power supply circuit is used to control the power supply of the input signal driving circuit according to the gate voltage of the final power amplifier chip; the integrated gate driver is used to control the on and off of the modulation switch tube and the discharge tube respectively according to the first complementary driving signal; the dead zone adjustment circuit is used to adjust the switching speed of the modulation switch tube and the discharge tube; the isolation power supply circuit is used to supply power to the integrated gate driver to maintain the conduction of the modulation switch tube under high voltage input; The gate voltage control power supply circuit is used to cut off the VCC power supply of the input signal driving circuit and prohibit it from outputting the first complementary driving signal when the gate voltage of the final stage power amplifier chip is abnormal; The dead zone adjustment circuit includes a first debugging circuit and a second debugging circuit respectively arranged in the gate drive loops of the modulation switch tube and the discharge tube; The first debugging circuit is used to adjust the gate drive current and drive voltage edge of the modulation switch tube, and the second debugging circuit is used to adjust the gate drive current and drive voltage edge of the discharge tube; The positive electrode of the isolated power supply circuit is connected to the BST pin of the integrated gate driver, and the negative electrode is connected to the source of the modulation switch tube; the isolated power supply circuit is used to maintain the gate drive voltage of the modulation switch tube through the isolated power supply voltage after the modulation switch tube is turned on, and the isolated power supply voltage is greater than the turn-on threshold voltage of the modulation switch tube, so that the modulation switch tube is continuously in the on state; The isolated power supply circuit is also connected to the main control chip, receives the pulse switching control signal issued by the main control chip, and outputs a second complementary drive signal based on the pulse switching control signal; the second complementary drive signal is connected to both ends of the primary winding of the pulse transformer, and the secondary winding of the pulse transformer is respectively connected to the integrated gate driver and the modulation switch tube.

2. The high voltage modulation circuit according to claim 1, characterized in that: The input signal driving circuit is also connected to the main control chip, receives the modulation control input signal and the power-on enable signal given by the main control chip, and outputs a first complementary driving signal to control the integrated gate driver according to the modulation control input signal and the power-on enable signal.

3. The high voltage modulation circuit according to claim 1, characterized in that: Both the modulation switch tube and the discharge tube adopt NMOS tube.

4. The high voltage modulation circuit according to claim 3, characterized in that: The integrated gate driver is used to output a high-side MOS transistor gate drive signal and a low-side MOS transistor gate drive signal after receiving a first complementary drive signal output by an input signal drive circuit.

5. The high voltage modulation circuit according to claim 4, characterized in that: The high-side MOS tube gate drive signal is used to drive the modulation switch tube to be turned on and off, and the low-side MOS tube gate drive signal is used to drive the discharge tube to be turned on and off; the maximum value of the on-resistance Rdson of the modulation switch tube and the discharge tube is 10mΩ.

6. The high voltage modulation circuit according to claim 1, characterized in that: The gate voltage control power supply circuit is also used to supply power to the input signal driving circuit when the gate voltage of the final stage power amplifier chip is normal, so that the input signal driving circuit outputs the first complementary driving signal.

7. The high voltage modulation circuit according to claim 1, characterized in that: The dead zone adjustment circuit also includes a PNP transistor current discharge loop, which corresponds to the source setting of the modulation switch tube and / or the discharge tube; the PNP transistor current discharge loop is used to discharge the gate-source charge of the modulation switch tube and / or the discharge tube, so that the modulation switch tube and / or the discharge tube are quickly turned off, and at the same time, the discharge current is limited to flow back to the integrated gate driver.

8. The high voltage modulation circuit according to claim 1, characterized in that: The turns ratio of the primary winding to the secondary winding of the pulse transformer is 1:1.

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