Clock control circuit and method

Abstract

The present disclosure provides a clock control circuit and method for circuitry. The circuitry includes a scan flip-flop circuit, a full speed domain and a time sequence exception domain. The scan flip-flop circuit is configured to output data to a full speed domain and a time sequence exception domain. The clock control circuit comprises a first gating control circuit, a first gating circuit, a second gating control circuit and a second gating circuit. The first gating circuit is used for being controlled by a first control signal, a scanning enable signal and a scanning mode signal output by the first gating control circuit so as to block or output a clock signal to the scanning flip-flop circuit. The second gating circuit is used for being controlled by a second control signal output by the second gating control circuit so as to block or output an output signal of the scanning flip-flop circuit to the timing exception domain.

Description

Technical Field

[0001] The present disclosure relates to a clock control circuit and method, and in particular to a clock control circuit and method for scanning a flip-flop circuit. Background Art

[0002] In the existing scan chain test technology, the circuit under test often generates unknown data values ​​(unknown source) due to some timing exception paths (e.g., false paths, multicycle paths, etc.) during the test, so that the number of test patterns required for the transition delay fault test of the circuit under test increases. The increase in the number of test patterns further leads to an increase in the test time and cost of the circuit under test. Therefore, it is necessary to solve this problem. Summary of the invention

[0003] One aspect of the present disclosure is a clock control circuit. The clock control circuit is used to control a circuit system, wherein the circuit system includes one or more scan flip-flop circuits, a full-speed domain, and a timing exception domain, and the scan flip-flop circuit is used to output data to the full-speed domain and the timing exception domain. The clock control circuit includes a first gating control circuit, a first gating circuit, a second gating control circuit, and a second gating circuit. The first gating control circuit is used to output a first control signal. The first gating circuit is coupled between the first gating control circuit and the scan flip-flop circuit, and is controlled by the first control signal, the scan enable signal, and the scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gating control circuit is coupled to the first gating control circuit, and is controlled by the first control signal, the scan mode signal, and the test switching signal to determine a second control signal. The second gating circuit is coupled to the scan flip-flop circuit, the second gating control circuit and the timing exception domain, and is used to receive the second control signal and the output signal of the scan flip-flop circuit, and is used to be controlled by the second control signal to block or output the output signal to the timing exception domain.

[0004] One aspect of the present disclosure is a clock control method for a circuit system. The circuit system includes one or more scan flip-flop circuits, a full-speed domain, and a timing exception domain, and the scan flip-flop circuit is used to output data to the full-speed domain and the timing exception domain. The clock control method includes: when the circuit system operates in a capture phase in a scan test (e.g., a transition delay fault test), a clock signal is provided to the scan flip-flop circuit according to a first control signal having a first logic value by a first gating circuit coupled to a clock input terminal of the scan flip-flop circuit; and when the circuit system operates in the capture phase, the clock signal is blocked from being transmitted to the scan flip-flop circuit according to the first control signal having a second logic value different from the first logic value by the first gating circuit, wherein the logic value of the first control signal is determined by a test pattern used to test the circuit system.

[0005] In some embodiments, the clock control method includes: by coupling a second selection circuit between the data output end of the scan flip-flop circuit and the timing exception domain, selectively transmitting the output signal of the scan flip-flop circuit to the timing exception domain according to the logic value of a second control signal.

[0006] In summary, by means of the clock control circuit of the present disclosure, the full-speed domain in the circuit system can avoid receiving unknown data values ​​under the transition delay fault test. In this way, the number of test patterns used for the circuit system and the test time and cost of the circuit system can be greatly reduced. In addition, the clock control circuit of the present disclosure can also avoid affecting the operation of the circuit system when the circuit system is operated under the fixed-type fault test or in the functional mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a simplified functional block diagram of a circuit system drawn according to the related art.

[0008] Figure 2 The application is illustrated according to some embodiments of the present disclosure. Figure 1 Block diagram of a clock control circuit in a circuit system.

[0009] Figure 3 is a circuit diagram of a clock control circuit according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of a clock control method according to some embodiments of the present disclosure.

[0011] Figure 5A and Figure 5B They are respectively schematic diagrams of operations of a clock control circuit according to some embodiments of the present disclosure when the circuit system operates in a capture phase under a transition delay fault test.

[0012] Figure 6 FIG. 4 is a schematic diagram illustrating the operation of a clock control circuit when a circuit system operates in a capture phase under a stuck-at fault test according to some embodiments of the present disclosure.

[0013] Figure 7 FIG. 4 is a schematic diagram illustrating the operation of a clock control circuit when the circuit system operates in a functional mode according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the components to produce a device with equal efficacy is within the scope of the present disclosure.

[0015] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure and in the specific context, unless otherwise specified.

[0016] As used herein, “coupled” or “connected” may refer to two or more components being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more components operating or moving with each other.

[0017] See also Figure 1 , Figure 1 is a simplified functional block diagram of a circuit system 1 according to the related art. Figure 1 As shown, the circuit system 1 includes a scan flip-flop circuit 10, a scan flip-flop circuit 12, a full-speed domain 14, and a timing exception domain 16. The circuit system 1 can be configured on a chip 3, and the automatic test equipment ATE can test the circuit system 1 through the chip 3. Specifically, the full-speed domain 14 and the timing exception domain 16 are each a combinational logic circuit composed of various logic gates, and the scan flip-flop circuit 10 and the scan flip-flop circuit 12 are each a sequential logic circuit different from the combinational logic circuit. It should be understood that the number of the scan flip-flop circuit 10 can be one or more, and the number of the scan flip-flop circuit 12 can also be one or more.

[0018] exist Figure 1In the related art, the scanning flip-flop circuit 10 and the scanning flip-flop circuit 12 each have a first data input terminal D, a second data input terminal SI, an input enable terminal SE and a data output terminal Q, wherein the input enable terminal SE is used to receive a scanning enable signal sen. In addition, the scanning flip-flop circuit 10 and the scanning flip-flop circuit 12 are each used to receive a clock signal CLK via a clock input terminal. Accordingly, the scanning flip-flop circuit 10 and the scanning flip-flop circuit 12 are each used to temporarily store data received at the first data input terminal D or the second data input terminal SI according to the scanning enable signal sen and the clock signal CLK. For example, when the scanning enable signal sen has a first logic value (e.g., logic "1"), the scanning flip-flop circuit 10 and the scanning flip-flop circuit 12 each temporarily store data received at the second data input terminal SI in response to the triggering of at least one pulse in the clock signal CLK. For another example, the scan flip-flop circuit 10 and the scan flip-flop circuit 12 each temporarily stores the data received at the first data input terminal D in response to at least one pulse of the clock signal CLK when the scan enable signal sen has a second logic value (eg, logic “0”).

[0019] As described above, the data output terminal Q of the scan flip-flop circuit 10 is coupled to the full-speed domain 14 to output the temporarily stored data to the full-speed domain 14. The data output terminal Q of the scan flip-flop circuit 12 is coupled to the full-speed domain 14 and the timing exception domain 16 to output the temporarily stored data to the full-speed domain 14 and the timing exception domain 16. The timing exception domain 16 receives the data output by the scan flip-flop circuit 12 to generate data to output to the full-speed domain 14. Furthermore, the full-speed domain 14 receives the data output by the scan flip-flop circuit 10, the data output by the scan flip-flop circuit 12, and the data output by the timing exception domain 16 to generate data.

[0020] It should be understood that Figure 1 The connection structure of the circuit system 1 shown is only illustrated for illustrative purposes, but is not intended to be limiting. For example, the first data input terminal D is usually coupled to the data output terminal of at least one combinational logic circuit in the circuit system 1. The second data input terminal SI is usually coupled to the data output terminal of at least one scan flip-flop circuit in the circuit system 1. The data output terminal Q is usually coupled to the data input terminal of at least one combinational logic circuit in the circuit system 1 and / or the second data input terminal of at least one scan flip-flop circuit. Accordingly, a plurality of serially connected sequential logic circuits will form a scan chain path in the circuit system 1. In addition, the data output terminal of the full-speed domain 14 can also be coupled to the first data input terminal of at least one scan flip-flop circuit in the circuit system 1.

[0021] Another example Figure 1As shown, the automatic test equipment ATE is used to generate a preset test pattern STP. In the related art, the test pattern STP is used to test the circuit system 1 and can be a data sequence. Specifically, the test pattern STP can be composed of a default number of data values ​​(e.g., logic "0", logic "1", etc.), and the arrangement of the data values ​​can be predetermined by the automatic test equipment ATE according to the test to be performed on the circuit system 1.

[0022] In the related art, the automatic test equipment ATE can input the test pattern STP to the circuit system 1 via the scan input terminal IO1 on the chip 3 to perform a scan test on the circuit system 1 via the scan chain path. Furthermore, the automatic test equipment ATE can receive the test output STR output by the circuit system 1 via the scan output terminal IO2 on the chip 3 to obtain the operating status of the circuit system 1. Generally speaking, the execution process of the scan test includes at least a shift phase and a capture phase, which is well known to those with ordinary knowledge in the technical field to which the present disclosure belongs. Therefore, in the following paragraphs, Figure 1 The displacement phase and the capture phase are briefly explained using the structure of as an example.

[0023] In the shift phase, the scan enable signal sen has a first logic value. In response to the triggering of at least one pulse in the clock signal CLK, the scan flip-flop circuit 10 and the scan flip-flop circuit 12 each temporarily stores the data value received at the second data input terminal SI, and each outputs the previously temporarily stored data value to the scan flip-flop circuit (not shown) coupled to the data output terminal Q, so as to serially transmit multiple data values ​​of the test pattern STP in the scan chain path. Before the shift phase is about to end, the scan flip-flop circuit 10 and the scan flip-flop circuit 12 will each store a corresponding data value among the multiple data values ​​of the test pattern STP.

[0024] In the capture phase, the scan enable signal sen has a second logic value. Initially, the timing exception domain 16 performs operations based on the data value temporarily stored by the scan flip-flop circuit 12. The full-speed domain 14 performs operations based on the data value temporarily stored by the scan flip-flop circuit 10, the data value temporarily stored by the scan flip-flop circuit 12, and the operation data value generated by the timing exception domain 16. Thereafter, in response to the triggering of at least one pulse in the clock signal CLK, the scan flip-flop circuit (not shown) coupled to the data output terminal of the full-speed domain 14 temporarily stores the data value generated by the operation of the full-speed domain 14. Furthermore, the scan flip-flop circuit 10 and the scan flip-flop circuit 12 each temporarily stores the data value generated by the operation of the combinational logic circuit (not shown) coupled to the first data input terminal D.

[0025] After the capture phase is over, the circuit system 1 enters the shift phase. The multiple data values ​​generated by the operation of the multiple combinational logic circuits of the circuit system 1 will be transmitted serially in the scan chain path and finally received by the automatic test equipment ATE. In this way, the automatic test equipment ATE can know the operation status of the multiple combinational logic circuits of the circuit system 1 based on the multiple data values ​​it receives (i.e., the test output STR). In the above scan test, the operation of the remaining combinational and sequential logic circuits in the circuit system 1 can be deduced in the same way, so it will not be repeated here.

[0026] In the related art, scan testing generally includes testing for stuck-at faults, transition delay faults, etc. Figure 1 In the timing exception domain 16, a timing exception path such as a false path or a multicycle path is set, so that an unknown or unexpected data value may be generated under the transition delay fault test due to the transition of the scan flip-flop circuit 12 (for example, from a temporary logic "0" to a temporary logic "1", from a temporary logic "1" to a temporary logic "0", etc.). Although the full-speed domain 14 does not have this problem, it may be affected by receiving the unknown data value generated by the timing exception domain 16, further resulting in an increase in the number of test patterns, test time and test cost.

[0027] In view of this, the present disclosure proposes a circuit capable of preventing the full-speed domain 14 from receiving unknown data values ​​under a transition delay fault test. Figure 2 For detailed instructions, see Figure 2 , Figure 2 The application is illustrated according to some embodiments of the present disclosure. Figure 1 1 is a block diagram of a clock control circuit 200 of a circuit system 1. In some embodiments, the clock control circuit 200 is used to control the circuit system 1, and includes a first gating control circuit 20, a first gating circuit 22, a second gating control circuit 24, and a second gating circuit 26. In terms of structure, the first gating circuit 22 is coupled between the first gating control circuit 20 and the clock input terminal of the scan flip-flop circuit 12. The second gating control circuit 24 is coupled to the first gating control circuit 20. In addition, the second gating circuit 26 is coupled to the second gating control circuit 24, the data output terminal Q of the scan flip-flop circuit 12, the full-speed domain 14, and the timing exception domain 16.

[0028] like Figure 2As shown, the first gating control circuit 20 is used to receive the clock signal CLK, the scan enable signal sen, the scan mode signal smode and the reset signal Reset. The first gating circuit 22 is used to receive the clock signal CLK, the scan enable signal sen and the scan mode signal smode. The second gating control circuit 24 is used to receive the scan mode signal smode and the test switching signal PLLBP.

[0029] In some embodiments, the scan mode signal smode is used to control whether the circuit system 1 performs a scan test. For example, when the scan mode signal smode has a first logic value, the circuit system 1 performs a scan test. When the scan mode signal smode has a second logic value, the circuit system 1 does not perform a scan test (for example, the circuit system 1 can operate in a function mode). The scan enable signal sen is used to control the circuit system 1 to operate in a displacement phase or a capture phase in the scan test, which can be referred to the above description of the displacement phase and the capture phase, and will not be repeated here. Furthermore, the test switching signal PLLBP is used to control the type of the scan test. For example, when the test switching signal PLLBP has a first logic value, the type of the scan test is a fixed-state fault test. When the test switching signal PLLBP has a second logic value, the type of the scan test is a transition delay fault test.

[0030] See also Figure 3 , Figure 3 is a circuit diagram of a clock control circuit 200 according to some embodiments of the present disclosure. Figure 3 Zhongyu Figure 1 The same or similar components are denoted by the same symbols, and description thereof will not be repeated here.

[0031] exist Figure 3 In the embodiment of the present invention, the first gating control circuit 20 includes a logic circuit 201 and a switch control circuit 202. The first input terminal of the logic circuit 201 is used to receive the clock signal CLK, and the second input terminal of the logic circuit 201 is used to receive the scan mode signal smode. The output terminal of the logic circuit 201 is coupled to the clock input terminal of the switch control circuit 202. The input enable terminal SE of the switch control circuit 202 is used to receive the scan enable signal sen. The data output terminal Q of the switch control circuit 202 is coupled to the first data input terminal D of the switch control circuit 202, the first gating circuit 22 and the second gating control circuit 24. In addition, the switch control circuit 202 is used to receive the reset signal Reset.

[0032] Specifically, if Figure 3 As shown, the logic circuit 201 can be implemented by an AND gate, and the switch control circuit 202 can be implemented by a scanning flip-flop circuit. Figure 3 The connection of the second data input terminal SI of the switch control circuit 202 is not shown, but it should be understood that the second data input terminal SI of the switch control circuit 202 can be coupled to the data output terminal of at least one scan flip-flop circuit in the circuit system 1. In other words, the second data input terminal SI of the switch control circuit 202 can be coupled to the scan chain path including the scan flip-flop circuit 10, the scan flip-flop circuit 12 and other scan flip-flop circuits not shown.

[0033] exist Figure 3 In the embodiment of the present invention, the first gating circuit 22 includes a logic circuit 221 and a switch circuit 222. The first input terminal of the logic circuit 221 is used to receive a scan enable signal sen, and the second input terminal of the logic circuit 221 is used to receive a scan mode signal smode. The primary enable terminal TE of the switch circuit 222 is coupled to the output terminal of the logic circuit 221. The secondary enable terminal EN of the switch circuit 222 is coupled to the data output terminal Q of the switch control circuit 202. The clock input terminal CKI of the switch circuit 222 is used to receive a clock signal CLK. The clock output terminal CKO of the switch circuit 222 is coupled to the clock input terminal of the scan flip-flop circuit 12. Specifically, the logic circuit 221 can be implemented by an AND gate, and the switch circuit 222 can be implemented by an integrated clock gating (IGC) circuit.

[0034] exist Figure 3 In the embodiment of the present invention, the second gating control circuit 24 includes a logic circuit 241, a logic circuit 242 and a logic circuit 243. A first input terminal of the logic circuit 241 is used to receive the scan mode signal smode, and a second input terminal of the logic circuit 241 is coupled to the data output terminal Q of the switch control circuit 202. A first input terminal of the logic circuit 242 is coupled to the output terminal of the logic circuit 241, and an output terminal of the logic circuit 242 is coupled to the second gating circuit 26. An input terminal of the logic circuit 243 is used to receive the test switching signal PLLBP, and an output terminal of the logic circuit 243 is coupled to a second input terminal of the logic circuit 242. Specifically, the logic circuit 241 and the logic circuit 242 can be implemented by an AND gate, and the logic circuit 243 can be implemented by a NOT gate.

[0035] exist Figure 3In the embodiment of the present invention, the second gating circuit 26 includes a logic circuit 261. A first input terminal of the logic circuit 261 is coupled to the data output terminal Q of the scan flip-flop circuit 12 and the full-speed domain 14, a second input terminal of the logic circuit 261 is coupled to the output terminal of the logic circuit 242 in the second gating control circuit 24, and an output terminal of the logic circuit 261 is coupled to the timing exception domain 16. Specifically, the logic circuit 261 can be implemented by an OR gate. It should be understood that the number of the logic circuit 261 can be one or more.

[0036] Then match Figure 4 The clock control method 400 shown in FIG. 1 details the operation of the clock control circuit 200 under the transition delay fault test. Figure 4 , Figure 4 4 is a flow chart of a clock control method 400 according to some embodiments of the present disclosure. In some embodiments, the clock control method 400 may be executed by the clock control circuit 200. Figure 4 As shown, the clock control method 400 includes steps S401-S402.

[0037] In step S401 , when the circuit system 1 operates in a capture phase in a scan test, the first gating circuit 22 selectively transmits the clock signal CLK to the scan flip-flop circuit 12 according to the logic value of the first control signal TP.

[0038] In step S402 , when the circuit system 1 operates in the capture phase of the scan test, the output signal SOB of the scan flip-flop circuit 12 is selectively transmitted to the timing exception domain 16 by the second gating circuit 26 according to the logic value of the second control signal FIX.

[0039] Figure 5A and Figure 5B The clock control circuit 200 is a schematic diagram of the operation of the circuit system 1 in the capture phase under the transition delay fault test according to some embodiments of the present disclosure. Here, the steps S401-S402 are described in detail by taking the embodiment of FIG. 5A as an example.

[0040] Please see the first gating control circuit 20 in FIG. 5A. In some embodiments, the data value of the test pattern STP temporarily stored by the switch control circuit 202 after the shifting stage is defaulted to logic "0". Accordingly, as shown in FIG. 5A, the switch control circuit 202 outputs the first control signal TP of the second logic value (e.g., logic "0") through the data output terminal Q during the capture stage. Furthermore, since the first data input terminal D and the data output terminal Q of the switch control circuit 202 are coupled to each other, the switch control circuit 202 temporarily stores the data value of logic "0" received by the first data input terminal D according to the clock signal CLK output by the logic circuit 201 when the scan mode signal smode has the first logic value and the scan enable signal sen has the second logic value, thereby outputting the first control signal TP of the second logic value through the data output terminal Q again.

[0041] Please see the first gating circuit 22 in FIG. 5A. The logic circuit 221 outputs an output logic value of a second logic value according to the scan enable signal sen of the second logic value and the scan mode signal smode of the first logic value. When the output logic value received by the primary enable terminal TE is the second logic value (e.g., logic "0"), the switch circuit 222 blocks the clock signal CLK from being transmitted to the clock input terminal of the scan flip-flop circuit 12 according to the first control signal TP of the second logic value received by the secondary enable terminal EN.

[0042] Please see the second gating control circuit 24 in FIG. 5A. The logic circuit 241 outputs the second logic value (e.g., logic "0") to the logic circuit 242 according to the scan mode signal smode of the first logic value and the first control signal TP of the second logic value. The logic circuit 243 outputs the first logic value (e.g., logic "1") to the logic circuit 242 according to the test switching signal PLLBP of the second logic value. Accordingly, the logic circuit 242 outputs the second control signal FIX of the second logic value.

[0043] Please see the second gating circuit 26 in FIG. 5A . Since the logic circuit 261 is implemented by an OR gate, the logic circuit 261 can be regarded as a short circuit when the second control signal FIX has a second logic value, further allowing the output signal SOB of the scan flip-flop circuit 12 to be transmitted to the timing exception domain 16 .

[0044] As can be seen from the description of FIG. 5A above, when the circuit system 1 operates in the capture phase under the transition delay fault test, the first gating circuit 22 blocks the clock signal CLK from being transmitted to the scan flip-flop circuit 12 according to the first control signal TP of the second logic value (corresponding to step S401), and the second gating circuit 26 provides the output signal SOB of the scan flip-flop circuit 12 to the timing exception domain 16 according to the second control signal FIX of the second logic value (corresponding to step S402). In this way, the scan flip-flop circuit 12 will not be triggered to operate by the clock signal CLK, so that the scan flip-flop circuit 12 will not transition. Furthermore, since the scan flip-flop circuit 12 will not transition, the data value transmitted from the scan flip-flop circuit 12 to the timing exception domain 16 via the second gating circuit 26 is fixed, and further, the timing exception domain 16 will not generate unknown data values ​​to the full-speed domain 14.

[0045] Next, the steps S401-S402 are described in detail by taking the embodiment of FIG. 5B as an example. Please see the first strobe control circuit 20 in FIG. 5B. In some embodiments, the data value of the test pattern STP temporarily stored by the switch control circuit 202 after the shift phase is defaulted to logic "1". Accordingly, as shown in FIG. 5B, the switch control circuit 202 outputs the first control signal TP of the first logic value (for example, logic "1") through the data output terminal Q during the capture phase. Furthermore, since the first data input terminal D and the data output terminal Q of the switch control circuit 202 are coupled to each other, the switch control circuit 202 temporarily stores the data value of logic "1" received by the first data input terminal D according to the clock signal CLK output by the logic circuit 201 when the scan mode signal smode has the first logic value and the scan enable signal sen has the second logic value, thereby outputting the first control signal TP of the first logic value through the data output terminal Q again.

[0046] Please see the first gating circuit 22 in FIG. 5B. The logic circuit 221 outputs an output logic value of a second logic value according to the scan enable signal sen of the second logic value and the scan mode signal smode of the first logic value. The switch circuit 222 provides the clock signal CLK to the clock input terminal of the scan flip-flop circuit 12 according to the first control signal TP of the first logic value received by the secondary enable terminal EN when the output logic value received by the primary enable terminal TE is the second logic value (e.g., logic "0").

[0047] Please see the second gating control circuit 24 in FIG. 5B. The logic circuit 241 outputs the first logic value (e.g., logic "1") to the logic circuit 242 according to the scan mode signal smode of the first logic value and the first control signal TP of the first logic value. The logic circuit 243 outputs the first logic value (e.g., logic "1") to the logic circuit 242 according to the test switching signal PLLBP of the second logic value. Accordingly, the logic circuit 242 outputs the second control signal FIX of the first logic value.

[0048] Please see the second gating circuit 26 in FIG. 5B. Since the logic circuit 261 is implemented by an OR gate, the logic circuit 261 will output a fixed logic "1" to the timing exception domain 16 when the second control signal FIX has a first logic value. The logic "1" output by the logic circuit 261 can be referred to as a default signal having a first logic value.

[0049] As can be seen from the description of FIG. 5B above, when the circuit system 1 operates in the capture phase under the transition delay fault test, the first gating circuit 22 provides the clock signal CLK to the scan flip-flop circuit 12 according to the first control signal TP of the first logic value (corresponding to step S401), and the second gating circuit 26 blocks the output signal SOB of the scan flip-flop circuit 12 from being transmitted to the timing exception domain 16 according to the second control signal FIX of the first logic value (corresponding to step S402). In other words, the scan flip-flop circuit 12 is triggered to operate by the clock signal CLK, so that the scan flip-flop circuit 12 may transition. Nevertheless, since the second gating circuit 26 provides a default signal (i.e., logic "1") with a fixed first logic value to the timing exception domain 16, the timing exception domain 16 will not generate an unknown data value to the full-speed domain 14.

[0050] Depend on Figure 5A and Figure 5B It can also be known from the description that the first gating control circuit 20 is used to output the first control signal TP, and the logic value of the first control signal TP is determined by the test pattern STP. The first gating circuit 22 is used to be controlled by the first control signal TP, the scan enable signal sen and the scan mode signal smode to block or output the clock signal CLK to the scan flip-flop circuit 12. The second gating control circuit 24 is used to be controlled by the first control signal TP, the scan mode signal smode and the test switching signal PLLBP to determine the second control signal FIX (for example, determine the logic value of the second control signal FIX). Furthermore, the second gating circuit 26 is used to be controlled by the second control signal FIX to block or output the output signal SOB of the scan flip-flop circuit 12 to the timing exception domain 16.

[0051] It should be understood that the clock control method 400 of the present disclosure is not limited to Figure 4Steps S401 to S402 are shown. For example, when the circuit system 1 operates in the shift phase under the transition delay fault test, the logic circuit 221 will output the output logic value of the first logic value (for example, logic "1") according to the scan enable signal sen of the first logic value and the scan mode signal smode of the first logic value. In the case where the output logic value received by the main enable terminal TE is the first logic value, the switch circuit 222 will provide the clock signal CLK to the clock input terminal of the scan flip-flop circuit 12 regardless of whether the first control signal TP has the first or second logic value. In this way, the scan flip-flop circuit 12 can be set to a corresponding data value among the multiple data values ​​of the test pattern STP. It can be seen that, in some embodiments, the clock control method 400 may also include another step. In the other step, when the circuit system 1 operates in the shift phase, the clock signal CLK is transmitted to the scan flip-flop circuit 12 by the first selection circuit 22.

[0052] Following the above instructions, please refer to Figure 6 , Figure 6 FIG. 2 is a schematic diagram of the operation of the clock control circuit 200 when the circuit system 1 is operating in the capture phase under the stuck-at fault test according to some embodiments of the present disclosure. Figure 6 In the embodiment of the present invention, the operation of the first gating control circuit 20 and the first gating circuit 22 is similar to Figure 5A and Figure 5B The embodiments are the same or similar, so they are not described here in detail.

[0053] Please see Figure 6 The logic circuit 243 outputs a second logic value (e.g., logic "0") to the logic circuit 242 according to the test switching signal PLLBP of the first logic value. Accordingly, no matter whether the logic circuit 241 outputs the first logic value or the second logic value, the logic circuit 242 outputs the second control signal FIX of the second logic value. Figure 6 Since the second gating control circuit 24 fixedly outputs the second control signal FIX of the second logic value, the logic circuit 261 fixedly operates as a short circuit, and further enables the output signal SOB of the scan flip-flop circuit 12 to be transmitted to the timing exception domain 16. In this way, the clock control circuit 200 will not affect the operation of the circuit system 1 under the stuck-at fault test.

[0054] Depend on Figure 6As can be seen from the description, when the circuit system 1 operates in the capture phase under the stuck-at fault test, the first gating circuit 22 selectively transmits the clock signal CLK to the scan flip-flop circuit 12 according to the logic value of the first control signal TP (corresponding to step S401), but the second gating circuit 26 fixedly provides the output signal SOB of the scan flip-flop circuit 12 to the timing exception domain 16 because the second control signal FIX is maintained at the second logic value. That is, in some embodiments, in another step after step S401, when the circuit system 1 operates in the capture phase, the output signal SOB of the scan flip-flop circuit 12 is provided to the timing exception domain 16 by the second gating circuit 26 according to the second control signal FIX of the second logic value.

[0055] See also Figure 7 , Figure 7 is a schematic diagram of the operation of the clock control circuit 200 when the circuit system 1 operates in the functional mode according to some embodiments of the present disclosure. Figure 7 In the first gate control circuit 20. When the scan mode signal smode has a second logic value, the first gate control circuit 20 outputs a first control signal TP of a fixed first logic value through the control of the reset signal Reset.

[0056] Please see Figure 7 The first gating circuit 22 in the embodiment. The logic circuit 221 outputs an output logic value of a second logic value (e.g., logic "0") according to the scanning mode signal smode of the second logic value. When the output logic value received by the primary enable terminal TE is the second logic value, the switch circuit 222 provides the clock signal CLK to the clock input terminal of the scanning flip-flop circuit 12 according to the first control signal TP of the first logic value received by the secondary enable terminal EN. Since the first gating control circuit 20 fixedly outputs the first control signal TP of the first logic value at this time, the first gating circuit 22 will continue to provide the clock signal CLK to the scanning flip-flop circuit 12.

[0057] Please see Figure 7 The logic circuit 241 outputs a second logic value (e.g., logic "0") to the logic circuit 242 according to the scan mode signal smode of the second logic value and the first control signal TP of the first logic value. Accordingly, no matter whether the logic circuit 243 outputs the first logic value or the second logic value, the logic circuit 242 fixedly outputs the second control signal FIX of the second logic value.

[0058] Please see Figure 7Since the second gating control circuit 24 fixedly outputs the second control signal FIX of the second logic value, the logic circuit 261 fixedly operates as a short circuit, and further enables the output signal SOB of the scan flip-flop circuit 12 to be transmitted to the timing exception domain 16. In this way, the clock control circuit 200 will not affect the operation of the circuit system 1 operating in the functional mode.

[0059] Depend on Figure 7 As can be seen from the description, in some embodiments, the clock control method 400 may further include at least two other steps. In the first of the two other steps, when the circuit system 1 operates in the functional mode, the first control signal TP of the first logic value is output to the first gating circuit 22 by the first gating control circuit 20 according to the reset signal Reset. In the second of the two other steps, when the circuit system 1 operates in the functional mode, the clock signal CLK is provided to the scan flip-flop circuit 12 by the first gating circuit 22 according to the first control signal TP of the first logic value.

[0060] From the above-mentioned implementation of the present disclosure, it can be known that, by means of the clock control circuit 200 of the present disclosure, the full-speed domain 14 in the circuit system 1 can avoid receiving unknown data values ​​under the transition delay fault test. In this way, the number of test patterns used for the circuit system 1 and the test time and cost of the circuit system 1 can be greatly reduced. In addition, the clock control circuit 200 of the present disclosure can also avoid affecting the operation of the circuit system 1 when the circuit system 1 is operated under the stuck-at fault test or in the functional mode.

[0061] Although the present disclosure has been disclosed in the implementation mode as above, it is not intended to limit the present disclosure. A person having ordinary knowledge in the technical field can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

[0062]

Explanation of symbols

[0063] 1: Circuit system

[0064] 3: Chip

[0065] 10,12: Scanning flip-flop circuit

[0066] 14: Full speed range

[0067] 16: Timing exception domain

[0068] 20: First selection control circuit

[0069] 22: First selection circuit

[0070] 24: Second selection control circuit

[0071] 26: Second selection circuit

[0072] 200: Clock control circuit

[0073] 201, 221, 241, 242, 243, 261: Logic circuits

[0074] 202: Switch control circuit

[0075] 222: Switching Circuit

[0076] 400: Clock Control Method

[0077] ATE: Automatic Test Equipment

[0078] CKI: Clock input

[0079] CKO: Clock output

[0080] CLK: Clock signal

[0081] D: First data input terminal

[0082] EN: Secondary enable terminal

[0083] FIX: Second control signal

[0084] IO1: Scan input terminal

[0085] IO2: Scan output terminal

[0086] PLLBP: Test switching signal

[0087] Q: Data output terminal

[0088] Reset: Reset signal

[0089] S401~S402: Steps

[0090] SE: Input enable terminal

[0091] SI: Second data input terminal

[0092] SOB: Output signal

[0093] STP: Test Pattern

[0094] STR: Test output

[0095] sen: scan enable signal

[0096] smode: scan mode signal

[0097] TE: Main enable terminal

[0098] TP: First control signal

Claims

1. A clock control circuit for controlling a circuit system, wherein the circuit system comprises a scan flip-flop circuit, a full-speed domain, and a timing exception domain, the scan flip-flop circuit is used to output data to the full-speed domain and the timing exception domain, and the clock control circuit comprises: A first gating control circuit, used for outputting a first control signal; A first gating circuit is coupled between the first gating control circuit and the scan flip-flop circuit and is used to be controlled by the first control signal, the scan enable signal and the scan mode signal to block or output a clock signal to the scan flip-flop circuit; A second gating control circuit is coupled to the first gating control circuit and is controlled by the first control signal, the scan mode signal and the test switching signal to determine a second control signal; as well as The second gating circuit is coupled to the scan flip-flop circuit, the second gating control circuit and the timing exception domain, and is used to receive the second control signal and the output signal of the scan flip-flop circuit, and is used to be controlled by the second control signal to block or output the output signal to the timing exception domain.

2. The clock control circuit of claim 1 , wherein the first gating circuit provides the clock signal to the scan flip-flop circuit when the first control signal has a first logic value and the scan mode signal has a second logic value different from the first logic value; wherein the first gating circuit provides the clock signal to the scan flip-flop circuit when the scan mode signal has the first logic value and the scan enable signal has the first logic value; Wherein the first gating circuit blocks or outputs the clock signal to the scan flip-flop circuit according to the logic value of the first control signal when the scan mode signal has the first logic value and the scan enable signal has the second logic value different from the first logic value.

3. The clock control circuit as claimed in claim 1, wherein the first gating circuit comprises: A logic circuit, for receiving the scan enable signal and the scan mode signal, and for outputting an output logic value according to the scan enable signal and the scan mode signal; as well as A switch circuit is coupled to the clock input terminal of the first selection control circuit, the logic circuit and the scanning flip-flop circuit, and is used to receive the clock signal, the output logic value and the first control signal, and is used to output the clock signal when the output logic value is a first logic value, and is used to output or block the clock signal according to the logic value of the first control signal when the output logic value is a second logic value different from the first logic value.

4. The clock control circuit as claimed in claim 1 , wherein the second gating circuit outputs a default signal having the first logic value to the timing exception domain when the second control signal has the first logic value; The second gating circuit provides the output signal to the timing exception domain when the second control signal has a second logic value different from the first logic value.

5. The clock control circuit as claimed in claim 1 , wherein the second gating control circuit outputs the second control signal having a second logic value different from the first logic value when the test switching signal has a first logic value; wherein the second gating control circuit outputs the second control signal having the second logic value when the scanning mode signal has the second logic value; Wherein, when the test switching signal has the second logic value and the scan mode signal has the first logic value, the second selection control circuit outputs the second control signal having the first logic value or the second logic value according to the logic value of the first control signal.

6. The clock control circuit as claimed in claim 1, wherein the first gating control circuit is used to receive the clock signal, the scan mode signal, the scan enable signal and a reset signal; wherein the first gating control circuit is used for outputting the first control signal having the first logic value or a second logic value different from the first logic value according to a test pattern when the scan mode signal has the first logic value; The first gating control circuit is used for outputting the first control signal having the first logic value through the control of the reset signal when the scan mode signal has the second logic value.

7. The clock control circuit as claimed in claim 1, wherein the first gating control circuit comprises: a logic circuit, wherein a first input terminal of the logic circuit is used to receive the clock signal, and a second input terminal of the logic circuit is used to receive the scan mode signal; as well as a switch control circuit, for receiving a reset signal and the scan enable signal, wherein a clock input terminal of the switch control circuit is coupled to an output terminal of the logic circuit, a data output terminal of the switch control circuit is coupled to the first gating circuit, the second gating control circuit and a first data input terminal of the switch control circuit, and a second data input terminal of the switch control circuit is coupled to a scan chain path of the circuit system; The scan chain path includes the scan flip-flop circuit.

8. A clock control method for a circuit system, wherein the circuit system comprises a scan flip-flop circuit, a full-speed domain, and a timing exception domain, the scan flip-flop circuit is used to output data to the full-speed domain and the timing exception domain, and the clock control method comprises: When the circuit system operates in a capture phase in a scan test, a clock signal is provided to the scan flip-flop circuit according to a first control signal having a first logic value through a first gating circuit coupled to a clock input terminal of the scan flip-flop circuit; as well as When the circuit system operates in the capture phase, the first selection circuit blocks the clock signal from being transmitted to the scan flip-flop circuit according to the first control signal having a second logic value different from the first logic value, wherein the logic value of the first control signal is determined by a test pattern used to test the circuit system.

9. The clock control method according to claim 8, further comprising: When the circuit system operates in the capture phase, the output signal of the scan flip-flop circuit is provided to the timing exception domain according to the second control signal having the second logic value through the second selection circuit coupled between the data output terminal of the scan flip-flop circuit and the timing exception domain.

10. The clock control method according to claim 9, further comprising: When the circuit system operates in the capture phase, the second gating circuit blocks the output signal of the scan flip-flop circuit from being transmitted to the timing exception domain according to the second control signal having the first logic value.

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