Frequency divider and frequency division control circuit

Abstract

The embodiment of the invention discloses a frequency divider. The frequency divider comprises an odd number path, an even number path and a frequency dividing ratio judging device, the odd-numbered paths, the even-numbered paths and the frequency dividing ratio judger can receive the frequency dividing ratio sent by the frequency dividing ratio provider and a clock signal input by the input clock; the odd number path is used for triggering a first counter and a second counter included in the odd number path to count the input clock signals and outputting a first output signal under the condition that the frequency dividing ratio represents an odd number; the even-number path is used for triggering a third counter included in the even-number path to count the input clock signal and outputting a second output signal under the condition that the frequency dividing ratio represents an even number; and the frequency dividing ratio judging device is used for determining a frequency dividing signal at least from the first output signal or the second output signal and the clock signal according to the frequency dividing ratio and outputting the frequency dividing signal.

Description

Technical Field

[0001] The present application relates to but is not limited to the field of digital circuit technology, and in particular to a frequency divider and a frequency division control circuit. Background Art

[0002] Chip design generally relies on a phase-locked loop (PLL) to provide the chip's internal clock, and the frequency divider is an indispensable module in the phase-locked loop design. Figure 1 As shown, the frequency divider 101 (Feedback Divider) divides the output clock of the voltage controlled oscillator 102 (Voltage Controlled Oscillator, VCO) to obtain the divided clock, and then uses the frequency detector 103 to compare the phase of the divided clock and the reference clock (refclk), and then according to the comparison result (high up or low down), the charge pump / low pass filter 104 (Charge Pump, CP / Low Pass Filter, LPF) is used to feedback adjust (vctrl) the output clock of the voltage controlled oscillator 102. When the output clock of the frequency divider matches the reference clock in phase, the phase-locked loop 105 is considered to be locked. At this time, the output clock of the voltage controlled oscillator 102 can be used as the internal standard clock of the chip. Since the frequency of the reference clock is generally fixed, if the chip needs a different internal clock frequency, the frequency division ratio of the frequency divider needs to be programmed to obtain VCO output clocks of different frequencies.

[0003] In addition, the internal chips of some high-speed digital circuits usually require the divider to provide a clock with a 50% duty cycle. This is because the registers inside the high-speed chip contain both rising edge triggers and falling edge triggers. If the duty cycle is not 50%, the logic timing inside the chip is difficult to control and logic errors are prone to occur. When the frequency division ratio N is an even number, it is relatively simple to achieve a 50% duty cycle. It only requires inverting the output clock of the divider every N / 2 input clock cycles; when N is an odd number, in order to obtain a 50% duty cycle, the inversion point of the output clock of the divider needs to occur within the accuracy of half an input clock cycle; in traditional technology, in order to achieve a clock output with a 50% duty cycle for odd frequency division, the structure of the counter is generally changed, or auxiliary circuits are added, which makes the design circuit of the divider complex and increases the difficulty of the divider design. Summary of the invention

[0004] In view of this, the embodiments of the present application at least provide a frequency divider and a frequency division control circuit.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a frequency divider, which includes: an odd channel, an even channel, and a frequency division ratio determiner; the odd channel, the even channel, and the frequency division ratio determiner can all receive the frequency division ratio sent by the frequency division ratio provider, and the clock signal of the input clock input; the odd channel is used to trigger the first counter and the second counter contained therein to count the input clock signal and output a first output signal when the frequency division ratio represents an odd number; the even channel is used to trigger the third counter contained therein to count the input clock signal and output a second output signal when the frequency division ratio represents an even number; the frequency division ratio determiner is used to determine and output the frequency division signal from at least the first output signal or the second output signal, and the clock signal according to the frequency division ratio.

[0007] Compared with the conventional technology of adding auxiliary circuits or changing the counter structure to realize the frequency divider, the present application does not need to change the counter structure to realize the half-cycle technology, but sets two counters in the odd-numbered paths to meet the accuracy of half the input clock cycle. Moreover, the present application adopts a fully digital circuit structure, and does not need to match the delay of any path. Without adding auxiliary circuits, the half-cycle frequency division accuracy can be accurately achieved. In this way, while improving the accuracy of the frequency divider, it also reduces the complexity of the circuit design and the difficulty of designing the frequency divider.

[0008] In some embodiments, the odd path includes: a counting logic determination circuit; the counting logic determination circuit is respectively connected to the first counter and the second counter; the first counter is used to count the rising edge of the input clock signal and send the first count value obtained by counting to the counting logic determination circuit; the second counter is used to count the falling edge of the input clock signal and send the second count value obtained by counting to the counting logic determination circuit; the counting logic determination circuit is used to determine the first output signal based on the received first count value and / or the second count value.

[0009] In some embodiments, the counting logic determination circuit is also used to determine that the first output signal is in a first potential state when the first count value or the second count value is greater than a first pre-designed value; the first preset count value is determined based on the counting range of the first counter and the second counter; or, when the first count value or the second count value is not greater than the first pre-designed value, determine that the first output signal is in a second potential state.

[0010] In an embodiment of the present application, by setting two counters in the odd-numbered paths to count the rising and falling edges of the input clock respectively, the counting accuracy can be directly improved to half a clock cycle, thereby directly achieving a fifty percent duty cycle without any adjustment or assistance of auxiliary circuits, thereby reducing the difficulty of divider design.

[0011] In some embodiments, the odd path also includes: a register; the register is connected to the counting logic determination circuit; the clock signal is a periodic signal; the counting logic determination circuit is also used to use the first count value and the second count value received in the current clock cycle to predict the first predicted count value of the rising edge of the first counter in the next clock cycle, and the second predicted count value of the falling edge of the second counter; determine the signal to be output based on the first predicted count value and the second predicted count value, and store the signal to be output in the register; the register is used to output the signal to be output as the next first output signal when the next clock cycle arrives.

[0012] In the embodiment of the present application, taking into account that when the counter is a binary counter, a multi-bit binary number involves multiple bits being carried at the same time when carrying, which may cause a delay, thereby causing glitches in the determined first output signal. Therefore, a register is added after the counting logic judgment circuit, so as to judge the output signal of the next clock cycle one clock cycle in advance, so that when the next clock cycle is reached, the predicted result of the previous clock cycle is output, thereby eliminating glitches.

[0013] In some embodiments, the even-numbered path includes: a clock output unit; the clock output unit is connected to the third counter; the third counter is used to count the rising edge or falling edge of the clock signal and send the third count value obtained by counting to the clock output unit; the clock output unit is used to determine that the potential state of the second output signal is inverted when the third count value reaches a second pre-designed value; the second preset count value is determined based on the counting range of the third counter.

[0014] In some embodiments, the frequency division ratio determiner is also used to determine the clock signal as the frequency division signal and output it when the frequency division ratio is less than a preset value; to determine the first output signal as the frequency division signal and output it when the frequency division ratio is not less than a preset value and is an odd number; and to determine the second output signal as the frequency division signal and output it when the frequency division ratio is not less than a preset value and is an even number.

[0015] In the embodiment of the present application, the frequency division ratio determiner can determine the output result of the corresponding path as the final frequency division result according to different frequency division ratios, and can output the result of the corresponding path when the frequency division ratio continuously changes, without programming blind spots.

[0016] In some embodiments, the odd path is used to enable the first counter and the second counter contained therein to stop counting and output a third output signal when the division ratio represents an even number; the even path is used to enable the third counter contained therein to stop counting and output a fourth output signal when the division ratio represents an odd number; the division ratio determiner is further used to determine and output a division signal from the first output signal, the fourth output signal, and the clock signal according to the division ratio; or, determine and output a division signal from the third output signal, the second output signal, and the clock signal.

[0017] In an embodiment of the present application, different paths are triggered for counting according to whether the frequency division ratio represents an odd number or an even number, and when the frequency division ratio is an odd number, the even path is silent, and when the frequency division ratio is an even number, the odd path is silent. In this way, by shutting down one of the paths according to the parity of the frequency division ratio, power consumption can be reduced.

[0018] In some embodiments, the frequency divider is a loop feedback frequency divider of a phase-locked loop supporting fractional frequency division, or a post-output frequency divider of the phase-locked loop supporting fractional frequency division.

[0019] On the other hand, an embodiment of the present application provides a frequency division control circuit, the frequency division control circuit includes a frequency division ratio provider, a phase-locked loop forward path, a first frequency divider, and a second frequency divider, the first frequency divider and the second frequency divider have the same structure as the frequency divider described above; the phase-locked loop forward path can receive a reference clock signal; the frequency division ratio provider is connected to the first frequency divider and the second frequency divider respectively; the frequency division ratio provider is used to send the frequency division ratio to the first frequency divider and the second frequency divider; the phase-locked loop forward path is connected to the first frequency divider respectively The first frequency divider is connected to the first frequency divider and the second frequency divider; the forward path of the phase-locked loop is used to perform phase synchronization based on the reference clock signal to generate a clock signal, and input the clock signal to the first frequency divider and the second frequency divider; the first frequency divider is used to divide the input clock signal based on the received frequency division ratio, and feed back the first frequency division signal obtained by the division to the forward path of the phase-locked loop; the second frequency divider is used to divide the input clock signal based on the received frequency division ratio, and output the second frequency division signal obtained by the division.

[0020] Compared with the frequency divider in the traditional technology that adds auxiliary circuits or changes the counter structure to achieve frequency division in the phase-locked loop, the frequency divider in the present application does not need to change the counter structure to achieve half-cycle technology, but instead sets two counters in the odd path to meet the accuracy of half the input clock cycle. In addition, the present application adopts a fully digital circuit structure, which does not need to match the delay of any path. Without adding auxiliary circuits, the frequency division accuracy of half a cycle can be accurately achieved. In this way, the complexity of the circuit design and the difficulty of the frequency divider design are reduced, while the accuracy of the frequency divider is improved, thereby improving the accuracy of the frequency division control circuit.

[0021] In some embodiments, the forward path of the phase-locked loop includes: a frequency detector, a low-pass filter, and a voltage-controlled oscillator; the first frequency divider is connected to the frequency detector; the first frequency divider is used to send the first frequency-divided signal obtained by frequency division to the frequency detector; the frequency detector is connected to the low-pass filter; the frequency detector is used to identify the phase difference between the received first frequency-divided signal and the reference clock signal, and send the error voltage generated based on the phase difference to the low-pass filter; the low-pass filter is connected to the voltage-controlled oscillator; the low-pass filter is used to filter the received error voltage to form a control voltage, and send it to the voltage-controlled oscillator; the voltage-controlled oscillator is connected to the first frequency divider; the voltage-controlled oscillator is used to control the output of the clock signal according to the received control voltage, and input the clock signal into the first frequency divider.

[0022] In some embodiments, the voltage-controlled oscillator is connected to the second frequency divider; the voltage-controlled oscillator is also used to input the clock signal into the second frequency divider; the second frequency divider is connected to the processing chip; the second frequency divider is used to divide the input clock signal and send the obtained second divided signal to the processing chip.

[0023] In the embodiment of the present application, by setting two counters in the odd path to count the rising edge and the falling edge of the input clock, the counting accuracy can be directly improved to half the input clock cycle. Compared with the traditional technology, since no auxiliary circuit or change of the counter structure is required, the output clock duty cycle of 50% can be directly achieved, which reduces the difficulty of designing the divider. In addition, the present application implements the odd path and the even path using a fully digital circuit design, which can reduce the design area of ​​the divider compared to the analog circuit. At the same time, by combining two counters in the odd path to count the rising edge and the falling edge of each clock cycle in the clock signal respectively, the counting of each half clock cycle is achieved, and the counting accuracy can be improved to half the input clock cycle, thereby improving the accuracy of the divider and the accuracy of the divider control circuit.

[0024] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0026] Figure 1 A schematic diagram of an exemplary phase-locked loop structure provided for related technology;

[0027] Figure 2 A schematic diagram of an exemplary frequency divider structure provided in an embodiment of the present application Figure 1 ;

[0028] Figure 3 A schematic diagram of the correspondence between a clock signal and a frequency division signal under different frequency division ratios provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of an exemplary frequency divider structure provided in an embodiment of the present application Figure 2 ;

[0030] Figure 5 A schematic diagram of an exemplary method of determining a first output signal provided in an embodiment of the present application;

[0031] Figure 6 A schematic diagram of an exemplary frequency divider structure provided in an embodiment of the present application Figure 3 ;

[0032] Figure 7 A schematic diagram of an exemplary frequency divider structure provided in an embodiment of the present application Figure 4 ;

[0033] Figure 8 A schematic diagram of an exemplary frequency divider structure provided in an embodiment of the present application Figure 5 ;

[0034] Fig. 9 A schematic diagram of an exemplary frequency division control circuit provided in an embodiment of the present application Figure 1 ;

[0035] Fig.10 A schematic diagram of an exemplary frequency division control circuit provided in an embodiment of the present application Figure 2 ;

[0036] Fig.11 A schematic diagram of an exemplary frequency division control circuit provided in an embodiment of the present application Figure 3 . DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0038] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing this application and are not intended to limit this application.

[0040] In the conventional technology, the implementation method of a programmable divider generating a divided clock may be: a first implementation method (see patent CN102035540A): when the division ratio is an even number, the divided clock is directly output; when the division ratio is an odd number, the divided clock generated by the divider is adjusted to a 50% duty cycle clock through a sampling circuit, a D flip-flop, and a delay buffer chain; a second implementation method (see patent CN106788400B): a broadband programmable divider is formed by n cascaded 2 / 3 division units, and a 50% duty cycle is obtained by adjusting two complementary voltage-time converters. For the first case, it is necessary to ensure that the delay path of the delay buffer chain matches the delay path of the sampling circuit output, so that the rising edge of the high-frequency clock output by the delay buffer chain is completely aligned with the transition edge of the low-frequency clock output by the sampling circuit. However, in actual applications, since each chip has a small difference in register delay during large-scale tape-out, it is difficult to match the delay paths of the two without increasing the complexity of the design, and thus it is impossible to guarantee a 50% duty cycle. In addition, since the D flip-flop is triggered on the falling edge, the rising edge of the clock obtained by the final frequency division and the rising edge of the original clock will have a delay of half the original clock, which will introduce redundant phase differences in the fractional frequency division phase-locked loop that requires continuous programming of the division ratio, thereby reducing the accuracy of the phase-locked loop. Since the phase-locked loop needs to provide a standard clock for the entire chip, its design accuracy requirements are very high. For the second case, the cascaded 2 / 3 divider units cannot achieve continuous programming of any division ratio. For example, when the division ratio jumps from 63 (7'b011_1111) to 64 (7'b100_0000), the simultaneous setting of the last 6 levels of 2 / 3 dividers will cause an error in the first division cycle after the division ratio jumps. This error will break the stability of the PLL loop at each division ratio jump, which will not only prolong the lock time, but also regularly introduce excess phase noise, thereby reducing the accuracy of the PLL. In addition, the 50% duty cycle adjustment circuit needs to be implemented by two complementary voltage-to-time converters. This converter requires a DC bias voltage and is an analog custom circuit. The power consumption and design area are greater than the full digital, synthesizable digital circuit.

[0041] The present application embodiment provides a frequency divider, exemplarily, as Figure 2 As shown, the frequency divider 201 includes: an odd channel 202, an even channel 203, and a frequency division ratio determiner 204; the odd channel 202, the even channel 203, and the frequency division ratio determiner 204 can all receive the frequency division ratio sent by the frequency division ratio provider 205, and the clock signal input by the input clock 206;

[0042] The odd number path 202 is used to trigger the first counter 207 and the second counter 208 included therein to count the input clock signal and output a first output signal when the frequency division ratio represents an odd number;

[0043] The even number path 203 is used to trigger the third counter 209 included therein to count the input clock signal and output a second output signal when the frequency division ratio represents an even number;

[0044] The frequency division ratio determiner 204 is used to determine and output a frequency division signal from at least the first output signal or the second output signal and the clock signal according to the frequency division ratio.

[0045] In the embodiments of the present application, Figure 2 As shown, the frequency divider 201 includes an odd channel 202, an even channel 203, and a frequency division ratio determiner 204; the odd channel 202 includes: a first counter 207 and a second counter 208, and the even channel 203 includes: a third counter 209; the odd channel 202, the even channel 203, and the frequency division ratio determiner 204 can all receive the frequency division ratio div_ratio sent by the frequency division ratio provider 205, and the clock signal clk_in input by the input clock 206; the odd channel 202 can trigger the first counter 207 and the second counter 208 contained therein when the frequency division ratio represents an odd number. The second counter 208 counts the input clock signal clk_in and outputs a first output signal clk_odd; the even path 203 can trigger the third counter 209 contained therein to count the input clock signal clk_in and output a second output signal clk_even when the frequency division ratio represents an even number; the frequency division ratio determiner 204 can determine and output the frequency division signal clk_out from at least the first output signal clk_odd or the second output signal clk_even and the clock signal clk_in according to the frequency division ratio div_ratio. Exemplarily, the duty cycle of the clock signal clk_in is fifty percent, see Figure 3 31 in. The frequency division signal clk_out, see Figure 3 32 in. The frequency division ratio div_ratio see Figure 3 of 33.

[0046] like Figure 2 As shown, the frequency divider 201 includes an odd channel 202 and an even channel 203. The odd channel 202 counts the input clock signal clk_in through a first counter 207 and a second counter 208 to output a first output signal clk_odd. Figure 3 The frequency division signal when the frequency division ratio 33 is 3; the even channel 203 counts the input clock signal clk_in by setting the third counter 209 to output the second output signal clk_even, see Figure 3The frequency division signal when the frequency division ratio 33 is 4; since the odd-numbered path 202 and the even-numbered path 203 provided in the present application are both digital circuits, and different frequency division ratios correspond to different paths, it is possible to achieve no delay between the frequency division signal and the input clock signal, so that the frequency division ratio can take effect when it jumps, see Figure 3 The jump 34 in the figure is a direct jump when the frequency division ratio 33 jumps from 4 to 3.

[0047] In some embodiments, Figure 4 As shown, the odd path 202 also includes: a counting logic determination circuit 210, which is connected to the first counter 207 and the second counter 208 respectively; the first counter 207 is used to count the rising edge of the input clock signal and send the first count value obtained by counting to the counting logic determination circuit 210; the second counter 208 is used to count the falling edge of the input clock signal and send the second count value obtained by counting to the counting logic determination circuit 210; the counting logic determination circuit 210 is used to determine the first output signal based on the received first count value and / or second count value.

[0048] In the embodiments of the present application, Figure 4 As shown, the first counter 207 and the second counter 208 in the odd channel 202 count the rising edge and the falling edge of the input clock signal respectively to obtain a first count value and a second count value. Then, the first counter 207 and the second counter 208 respectively send the first count value and the second count value to the counting logic determination circuit 210, and the counting logic determination circuit 210 determines the first output signal based on the first count value and / or the second count value.

[0049] like Figure 3 As shown, when the frequency division ratio is 3, three clock cycles are the clock cycles counted by the first counter 207 and the second counter 208. For example, the clock cycles are shown in FIG. Figure 3 of 35.

[0050] like Figure 4 As shown, the counting logic determination circuit 210 may determine the first output signal based on the first counting value and the second counting value, or may determine the first output signal based on the first counting value or the second counting value.

[0051] In some embodiments, Figure 4As shown, the counting logic determination circuit 210 is also used to determine that the first output signal is in the first potential state when the first count value or the second count value is greater than the first pre-designed value; the first preset count value is determined based on the counting range of the first counter and the second counter; or, when the first count value and the second count value are both not greater than the first pre-designed value, determine that the first output signal is in the second potential state.

[0052] Exemplarily, the counting range of the first counter 207 and the second counter 208 is from 0 to the full frequency division ratio minus one, that is, the first counter 207 and the second counter 208 both start counting from 0, and the counting range can be [0: div_ratio-1]. If the first counter 207 and the second counter 208 reach div_ratio-1, they return to zero, and count repeatedly until the frequency division ratio jumps, and then continue to work according to the frequency division ratio after the jump. If the counting range of the first counter 207 and the second counter 208 is from 1 to the full frequency division ratio, that is, the first counter 207 and the second counter 208 both start counting from 1, the counting range is [1: div_ratio]. If the first counter 207 and the second counter 208 reach div_ratio, they return to zero, and count repeatedly until the frequency division ratio jumps, and then continue to work according to the frequency division ratio after the jump. Of course, the first counter 207 and the second counter 208 can also be cumulative counting, starting with cumulative counting from 0, or starting with cumulative counting from 1, without limiting the upper limit of counting.

[0053] Exemplarily, if the counting range of the first counter 207 and the second counter 208 is from 0 to the full frequency division ratio minus one, then the first pre-designed value is the half frequency division ratio, that is, if the first count value or the second count value is greater than the half frequency division ratio (div_ratio / 2), the first output signal is determined to be in the first potential state; if the first count value and the second count value are both not greater than the half frequency division ratio div_ratio / 2, the first output signal is determined to be in the second potential state. If the counting range of the first counter 207 and the second counter 208 is from one to the full frequency division ratio, then the first pre-designed value is the half frequency division ratio plus one, that is, if the first count value or the second count value is greater than the half frequency division ratio plus one (div_ratio / 2+1), the first output signal is determined to be in the first potential state; if the first count value and the second count value are both not greater than the half frequency division ratio plus one (div_ratio / 2+1), the first output signal is determined to be in the second potential state.

[0054] Exemplarily, the first potential state can be a low level, and the second potential state can be a high level. Of course, the first potential state can be a high level, and the second potential state can be a low level. The specific first potential state and the second potential state can be set according to application requirements and application scenarios, and this application does not limit this.

[0055] Exemplarily, the counting range of the first counter 207 and the second counter 208 is from zero to the full frequency division ratio minus one, and the clock signal is first high level and then low level (within one cycle) as an example for discussion. Figure 5 As shown, when the division ratio is 3 (see Figure 5 53), the first counter 207 and the second counter 208 are clocked by the clock signal clk_in (see Figure 5 51) is counted to obtain the first count value (see Figure 5 The count value corresponding to the up in the above, for example, up: 0, 0 is the first count value obtained by the rising edge of the current record. When the clock signal has a rising edge again, the first count value will also accumulate counts, that is, up: 1, until the counting range is full, that is, counting from zero to the full frequency division ratio minus one and then returning to zero. If the frequency division ratio does not change, continue to count from 0), the second counter 208 counts the falling edges of the clock signal clk_in to obtain a second count value (see Figure 5 The corresponding count value of the next, for example, next: 1, 1 is the second count value obtained by the falling edge of the current record. When the clock signal has a falling edge again, the first count value will also accumulate counts, that is, next: 1, until the counting range is full, that is, counting from zero to the full frequency division ratio minus one and then returning to zero. If the frequency division ratio does not change, continue to count from 0), then, the counting logic determination circuit 210 determines the first output signal based on the received first count value and the second count value. Figure 5 As shown, if the first count value or the second count value is greater than the half-frequency division ratio 3 / 2, the first output signal is determined to be a low level (see Figure 5 55 in the frequency division signal 52 in the frequency division signal 55), if the first count value and the second count value are not greater than the half frequency division ratio 3 / 2, it is determined that the first output signal is a high level (see Figure 5 54 in the divided signal 52). From Figure 5It can be seen that 55 in the frequency division signal 52 is determined based on the first count value (upper: 2) or the second count value (lower: 2) being greater than the half frequency division ratio 3 / 2, and the frequency division signal 54 is determined based on the first count value (upper: 0 or 1) and the second count value (lower: 0 or 1) being not greater than the half frequency division ratio 3 / 2. It can be seen that when the frequency division ratio is an odd number, the counting logic determination circuit 210 is required to determine the first output signal based on the first count value and / or the second count value. In this way, the present application can directly improve the counting accuracy to half the input clock cycle by setting the first counter 207 and / or the second counter 208 for recording the rising edge of the clock signal on the odd channel 202. In this way, the output clock duty cycle of 50% can be directly achieved without the help of any adjustment or delay circuit, thereby improving the frequency division accuracy of the frequency divider.

[0056] In some embodiments, Figure 6 As shown, the odd path 202 also includes: a register 211; the register 211 is connected to the counting logic determination circuit 210; the clock signal is a periodic signal; the counting logic determination circuit 210 is also used to use the first count value and the second count value received in the current clock cycle to predict the first predicted count value of the rising edge of the first counter 207 in the next clock cycle, and the second predicted count value of the falling edge of the second counter 208; based on the first predicted count value and the second predicted count value, determine the signal to be output, and store the signal to be output in the register 211; the register 211 is used to output the signal to be output as the next first output signal when the next clock cycle arrives.

[0057] In the embodiments of the present application, Figure 6 As shown, the odd path 202 also includes a register 211. Exemplarily, if both the first counter 207 and the second counter 208 are binary adder counters, then when a binary carry occurs, for example, when the first count value is carried from 011 to 100, the 3-bit value needs to be changed, that is, the highest bit 0 is changed to 1, and the two lower bits 1 are changed to 0. This may cause the 3-bit value to not jump at the same time, and other count values ​​such as 101, 110, or 010 may appear briefly, thereby causing a misjudgment when judging whether the first count value is greater than half the frequency division ratio, thereby causing a high and low level mixture in the first output signal, causing glitches in the first output signal. For example, if the frequency division ratio is 6, the above-mentioned short-lived 010 will affect the next first output signal to have glitches.

[0058] To solve this glitch, Figure 6As shown, the present application sets a register 211 in the odd channel 202. For example, the counting logic determination circuit 210 uses the first count value 011 and the second count value 010 received in the current clock cycle to predict the first predicted count value 100 of the rising edge of the first counter 207 and the second predicted count value 011 of the falling edge of the second counter 208 in the next clock cycle, and determines the signal to be output based on the first predicted count value 100 and the second predicted count value 011. Here, if the counting range of the first counter and the second counter is [0: div_ratio-1] as an example, if the frequency division ratio is 6 and the half frequency division ratio is 3, then one of the first predicted count value 100 or the second predicted count value 011 is greater than 3, then the signal to be output is low level, at this time, the signal to be output is stored in the register 211 as a low level; then, when the next clock cycle arrives, the signal to be output stored in the register 211 is output as the next first output signal, so that the burr can be eliminated by judging the result of the next clock cycle one clock cycle in advance.

[0059] For example, Figure 6 As shown, the odd channel 202 is provided with two counters (a first counter 207 and a second counter 208). When the frequency division ratio is an odd number, one counter (the first counter 207) accumulates counts upward at each rising edge of the input clock, and the other counter (the second counter 208) accumulates counts upward at each falling edge of the input clock. Here, the counting range of the two counters is [0: div_ratio-1] as an example for discussion: when they reach the maximum value (div_ratio-1), they return to zero, and this cycle repeats until the frequency division ratio jumps. When the rising edge counter is greater than div_ratio / 2 or when the falling edge counter is greater than div_ratio / 2, the output clock clk_odd is set to a low level, and clk_odd remains high at other times. In addition, in order to prevent the transient burr output by the counter from being transmitted to clk_odd, a register can be added between the counter result judgment logic (counting logic judgment circuit) and the output clock (first output signal) to eliminate the burr.

[0060] In some embodiments, Figure 7 As shown, the even channel 203 also includes a clock output unit 212, which is connected to the third counter 209. The third counter 209 is used to count the rising edge or falling edge of the input clock signal and send the third count value obtained by counting to the clock output unit 212; the clock output unit 212 is used to determine that the potential state of the second output signal is inverted when the third count value reaches a second preset value; the second preset count value is determined based on the counting range of the third counter.

[0061] In an embodiment of the present application, the counting range of the third counter may be from zero to half the frequency division ratio minus one, or from one to half the frequency division ratio, so that the counting is cyclic and then cleared. Of course, the third counter may also be cumulative counting, and the counting range is not fixed. Exemplarily, if the counting range of the third counter is from zero to half the frequency division ratio minus one, then the second preset count value is the half frequency division ratio, that is, when the third count value reaches the half frequency division ratio, it is determined that the potential state of the second output signal is reversed. If the counting range of the third counter is from one to half the frequency division ratio, then the second preset count value is the half frequency division ratio plus one, that is, when the third count value reaches the half frequency division ratio plus one, it is determined that the potential state of the second output signal is reversed.

[0062] In an embodiment of the present application, whether the rising edge or the falling edge of the clock signal recorded by the third counter 209 depends on whether the clock signal is first low level and then high level, or first high level and then low level after receiving the division ratio. If the clock signal is first low level and then high level, the recorded edge is the falling edge of the clock signal; if the clock signal is first high level and then low level, the recorded edge is the rising edge of the clock signal.

[0063] For example, Figure 7 As shown, the counting range of the third counter 209 is from zero to half the frequency division ratio minus one, that is, the counting range of the third counter 209 is [0: div_ratio / 2-1] as an example for discussion: if the third count value corresponding to the rising edge or falling edge of the clock signal recorded by the third counter 209 reaches div_ratio / 2-1, it is determined that the potential state of the second output signal is reversed. That is, if the second output signal was a high level before, the second output signal is reversed to a low level at this time; if the second output signal was a high level before, the second output signal is reversed to a high level at this time. In fact, when the count value of the third counter 209 reaches the maximum value, the second output signal is reversed, and the third counter 209 is reset to zero, and this cycle is repeated until the frequency division ratio jumps.

[0064] For example, the counting range of the third counter is from zero to half the frequency division ratio minus one. Figure 7 As shown, the even channel 203 is provided with a counter (third counter 209). When the frequency division ratio (div_ratio) is an even number, the counter accumulates upward counts at each rising or falling edge of the input clock (clk_in), and the counting range is [0: div_ratio / 2-1]. When the counter reaches the maximum value (div_ratio / 2-1), the output clock clk_even is inverted, and the counter is reset to zero, and this cycle repeats until the frequency division ratio jumps.

[0065] In some embodiments, Figure 2 As shown, the frequency division ratio determiner 204 is also used to determine the clock signal as a frequency division signal and output it when the frequency division ratio is less than a preset value; determine the first output signal as a frequency division signal and output it when the frequency division ratio is not less than the preset value and is an odd number; and determine the second output signal as a frequency division signal and output it when the frequency division ratio is not less than the preset value and is an even number.

[0066] In the embodiments of the present application, Figure 2 As shown, the frequency division ratio determiner 204 can receive the frequency division ratio provided by the frequency division ratio provider 205, and the frequency division ratio provided by the frequency division ratio provider 205 is a binary value, wherein the preset value can be 2, that is, 0010;

[0067] Exemplarily, the frequency division ratio provided by the frequency division ratio provider 205 may be 0111, 0001, or 0110. If the frequency division ratio determiner 205 receives the frequency division ratio 0111, it first determines whether 0111 is less than 0010. It can be seen that 0111 is greater than 0010. Then, the parity of the frequency division ratio 0111 is further determined based on the [0]th bit of the frequency division ratio 0111. If the [0]th bit is 1, it is an odd number. If it is 0, it is an even number. The [0]th bit of 0111 is 1. If the frequency division ratio is an odd number, the frequency division ratio is not less than the preset value and is an odd number. At this time, the frequency division ratio determiner 205 determines the first output signal as a frequency division signal and outputs it. If the frequency division ratio determiner 205 receives the frequency division ratio 0001, it determines whether 0001 is less than the preset value. It can be seen that 0001 is less than 0010. Then, the frequency division ratio is less than the preset value. At this time, the frequency division ratio determiner 205 determines the clock signal as a frequency division signal and outputs it (see Figure 3 If the frequency division ratio determiner 205 receives the frequency division ratio 0110, it first determines whether 0110 is less than the preset value. It can be seen that 0110 is greater than 0010. Then, the parity of the frequency division ratio is further determined based on the [0]th bit of the frequency division ratio 0110. The [0]th bit of 0110 is 0, indicating an even number. Then, the frequency division ratio is not less than the preset value and is an even number. At this time, the frequency division ratio determiner 205 determines the second output signal as the frequency division signal and outputs it.

[0068] In some embodiments, Figure 8As shown, the odd channel 202 is used to enable the first counter 207 and the second counter 208 contained therein to stop counting and output a third output signal when the frequency division ratio represents an even number; the even channel 203 is used to enable the third counter 209 contained therein to stop counting and output a fourth output signal when the frequency division ratio represents an odd number; the frequency division ratio determiner 204 is further used to determine and output the frequency division signal from the first output signal, the fourth output signal, and the clock signal according to the frequency division ratio; or, determine and output the frequency division signal from the third output signal, the second output signal, and the clock signal.

[0069] In the embodiments of the present application, Figure 8 As shown, if the frequency division ratio represents an even number, the first counter 207 and the second counter 208 in the odd number path 202 stop counting and output the third output signal. If the frequency division ratio represents an odd number, the third counter 209 in the even number path 203 stops counting and outputs the fourth output signal. In this way, the frequency divider will close one of the paths according to the odd or even nature of the frequency division ratio, which can reduce the power consumption of the frequency divider. In this way, when the frequency division ratio represents an even number, the frequency division ratio determiner 204 determines the frequency division signal from the second output signal, the third output signal, and the clock signal according to the frequency division ratio and outputs it; when the frequency division ratio represents an odd number, the frequency division ratio determiner 204 determines the frequency division signal from the first output signal, the fourth output signal, and the clock signal according to the frequency division ratio and outputs it.

[0070] For example, Figure 2 As shown, the first function of the frequency division ratio determiner 204 is to determine the odd or even of the frequency division ratio. div_ratio[0] represents the [0]th bit of the frequency division ratio. If div_ratio[0] is 1, it means that the frequency division ratio is an odd number, and the frequency division ratio determiner 204 outputs clk_odd as the frequency divider 201 output; div_ratio[0] is 0, it means that the frequency division ratio is an even number, and the frequency division ratio determiner 204 outputs clk_even as the frequency divider 201 output. The second function of the frequency division ratio determiner 204 is to determine whether to bypass the frequency division and output directly. That is, when the frequency division ratio is less than 2, the frequency division ratio determiner 204 will output clk_in directly without frequency division. For details, see Figure 3 When the frequency division ratio is 1, clk_in is directly used as the output of the frequency divider 201 .

[0071] In some embodiments, Figure 2 As shown, the frequency divider 201 is a loop feedback frequency divider of a phase-locked loop supporting fractional frequency division, or a post-output frequency divider of a phase-locked loop supporting fractional frequency division.

[0072] In the embodiments of the present application, Figure 2As shown, the divider 201 can be used as a loop feedback divider of a phase-locked loop or as a post-output divider of a phase-locked loop. The divider 201, as a loop feedback divider, divides the input clock signal, and then compares the phase with the reference clock of the phase-locked loop, and then adjusts the divided signal according to the comparison result, so as to obtain an accurate average fractional division ratio. As a post-output divider, the divider 201 can provide stable rising and falling edge timing, i.e., a 50% duty cycle clock, for the high-speed serial-to-parallel converter (SerDes) and double data rate (DDR) frequently used in the subsequent central processing unit (CPU) or (graphics processing unit, GPU), so as to ensure the accuracy of the internal logic sampling of the chip and avoid logic errors.

[0073] Exemplarily, the process of frequency division by the frequency divider 201 is as follows: Figure 2 As shown, the frequency division ratio and the clock to be divided are simultaneously input into the even path 203 and the odd path 202. When the frequency division ratio is an even number (div_ratio[0]=0), the rising edge counter of the even path 203 starts working, and the counter of the odd path 202 remains silent to save power. The output clock clk_even of the even path 203 is inverted when the counter reaches the maximum value (div_ratio / 2-1), and clk_odd remains constant during the whole process to save power, and the frequency divider 201 finally outputs clk_even; when the frequency division ratio is an odd number (div_ratio[0]=1), the rising edge and falling edge counters of the odd path 202 start working, and the counter of the even path 203 remains silent to save power. The output clock clk_odd of the odd channel 202 is low when the rising edge counter is greater than div_ratio / 2 or the falling edge counter is greater than div_ratio / 2, and clk_odd remains high at other times. clk_even remains constant in the whole process to save power consumption, and the frequency divider 201 finally outputs clk_odd. When the frequency division ratio is less than 2, clk_in is directly output without frequency division.

[0074] A frequency divider provided in an embodiment of the present application can directly improve the counting accuracy to half an input clock cycle by setting two counters in an odd path to count the rising edge and the falling edge of an input clock. Compared with the traditional technology, since a 50% output clock duty cycle can be directly achieved without any auxiliary circuit or change in the counter structure, the difficulty of designing the frequency divider is reduced. In addition, the present application implements the odd path and the even path using a fully digital circuit design, which can reduce the design area of ​​the frequency divider compared to an analog circuit. At the same time, the counting accuracy is improved to half an input clock cycle, which can improve the accuracy of the frequency divider.

[0075] The embodiment of the present application provides a frequency division control circuit, such as Fig. 9 As shown, the frequency division control circuit 901 includes a frequency division ratio provider 205, a phase-locked loop forward path 902, a first frequency divider 903, and a second frequency divider 904. The first frequency divider 903 and the second frequency divider 904 have the same structure as the frequency divider 201 described above; the phase-locked loop forward path 902 can receive a reference clock signal; the frequency division ratio provider 205 is connected to the first frequency divider 903 and the second frequency divider 904 respectively; the frequency division ratio provider 205 is used to send the frequency division ratio to the first frequency divider 903 and the second frequency divider 904; the phase-locked loop forward path 902 is connected to the first frequency divider 903 and the second frequency divider 904 respectively. A frequency divider 903 is connected to a second frequency divider 904; a phase-locked loop forward path 902 is used to perform phase synchronization based on a reference clock signal to generate a clock signal, and input the clock signal into the first frequency divider 903 and the second frequency divider 904; the first frequency divider 903 is used to divide the input clock signal based on a received frequency division ratio, and feed back the first frequency division signal obtained by the division to the phase-locked loop forward path 902; the second frequency divider 904 is used to divide the input clock signal based on the received frequency division ratio, and output the second frequency division signal obtained by the division.

[0076] In the embodiments of the present application, Fig. 9As shown, the frequency division control circuit 901 includes a frequency division ratio provider 205, a phase-locked loop forward path 902, and a first frequency divider 903 and a second frequency divider 904; the frequency division ratio provider 205 is connected to the first frequency divider 903 and the second frequency divider 904 respectively to send the frequency division ratio to the first frequency divider 903 and the second frequency divider 904; the phase-locked loop forward path 902 is connected to the first frequency divider 903 and the second frequency divider 904 respectively to perform phase synchronization based on a reference clock signal to generate a clock signal, and input the clock signal to the first frequency divider 903 and the second frequency divider 904; the first frequency divider 903 Based on the received frequency division ratio, the input clock signal can be divided, and the first frequency division signal obtained by the frequency division is fed back to the phase-locked loop forward path 902, so that the first frequency division signal of the first frequency divider 903 and the reference clock signal match in phase, and the frequency division control circuit 901 is locked; the second frequency divider 904 can divide the input clock signal based on the received frequency division ratio, and output the second frequency division signal obtained by the frequency division, that is, the duty cycle of the clock signal output by the phase-locked loop forward path 902 is controlled, so that the duty cycle of the second frequency division signal output by the frequency division control circuit 901 is 50%. Among them, the frequency division ratio provider 205 is a DSM (Delta-Sigma Modulation DSM), which is used to provide a frequency division ratio and supports a module for fractional frequency division.

[0077] Exemplarily, when the clock frequency inside the chip is not an integer multiple of the reference clock frequency, the frequency division ratio of the frequency divider needs to be a decimal. The general method of implementing a fractional frequency division ratio is to continuously program different frequency division ratios so that the average frequency division ratio over a period of time is equal to the target fractional value. For example, a phase-locked loop (frequency division control circuit) requires an output clock of 1.21GHz, and the reference clock frequency is 25MHz, then the target frequency division ratio is 1.21 / 25*1000=48.4. This can be achieved by continuously programming the frequency division ratio between 46 and 50 to obtain an average frequency division ratio of 48.4, and the frequency division ratio provider 205 is a device that provides the frequency division ratio timing.

[0078] In some embodiments, Fig.10As shown, the forward path 902 of the phase-locked loop includes: a frequency detector 905, a low-pass filter 906, and a voltage-controlled oscillator 907; the first frequency divider 903 is connected to the frequency detector 905; the first frequency divider 903 is used to send the first frequency-divided signal obtained by frequency division to the frequency detector 905; the frequency detector 905 is connected to the low-pass filter 906; the frequency detector 905 is used to identify the phase difference between the received first frequency-divided signal and the reference clock signal, and send the error voltage generated based on the phase difference to the low-pass filter 906; the low-pass filter 906 is connected to the voltage-controlled oscillator 907; the low-pass filter 906 is used to filter the received error voltage to form a control voltage, and send it to the voltage-controlled oscillator 907; the voltage-controlled oscillator 907 is connected to the first frequency divider 903; the voltage-controlled oscillator 907 is used to control the output clock signal according to the received control voltage, and input the clock signal into the first frequency divider 903.

[0079] In the embodiments of the present application, Fig.10 As shown, the first frequency divider 903 divides the clock signal output by the voltage-controlled oscillator 907, and then uses the frequency detector 905 to compare the phases of the first divided signal and the reference clock, and then controls the low-pass filter 906 according to the comparison result (high up or low down) to adjust the output frequency (clock signal) of the voltage-controlled oscillator 907 (VCO) based on the comparison result feedback (vctrl), so that the first divided signal of the frequency divider and the reference clock match in phase, wherein a charge pump (CP) (not shown in the figure) can also be deployed between the low-pass filter 906 and the frequency detector 905.

[0080] In some embodiments, Fig.11 As shown, the voltage-controlled oscillator 907 is connected to the second frequency divider 904; the voltage-controlled oscillator 907 is also used to input the clock signal into the second frequency divider 904; the second frequency divider 904 is connected to the processing chip 908; the second frequency divider 904 is used to divide the input clock signal and send the obtained second divided signal to the processing chip 908.

[0081] In the embodiments of the present application, Fig.11 As shown, the processing chip 908 can be a system-level chip such as a CPU, GPU, etc., and the second divider 904 is connected to the voltage-controlled oscillator 907 and the processing chip 908 respectively; the divider 505 divides the clock signal output by the voltage-controlled oscillator 907, and sends the obtained second divided signal with a duty cycle of 50% to the processing chip 908, so that the logic timing of the register inside the high-speed chip can be better controlled when including rising edge triggering and falling edge triggering, thereby avoiding logic errors.

[0082] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0083] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0084] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0085] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0086] In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by hardware related to program instructions, and the above program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above method embodiments are executed; and the above storage medium includes: mobile storage devices, read-only memory (ROM), disks or optical disks, etc. Various media that can store program codes.

[0087] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0088] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A frequency divider, characterized in that: The frequency divider comprises: an odd-numbered path, an even-numbered path, and a frequency division ratio determiner; The odd-numbered path, the even-numbered path, and the frequency division ratio determiner can all receive the frequency division ratio sent by the frequency division ratio provider and the clock signal of the input clock input; The odd-number path is used to trigger the first counter and the second counter contained therein to count the input clock signal and output a first output signal when the frequency division ratio represents an odd number; The even-numbered path is used to trigger the third counter contained therein to count the input clock signal and output a second output signal when the frequency division ratio represents an even number; The frequency division ratio determiner is used to determine and output a frequency division signal from at least the first output signal or the second output signal and the clock signal according to the frequency division ratio.

2. The frequency divider according to claim 1, characterized in that: The odd number path comprises: a counting logic determination circuit; the counting logic determination circuit is connected to the first counter and the second counter respectively; The first counter is used to count the rising edges of the input clock signal and send the first count value obtained by counting to the counting logic determination circuit; The second counter is used to count the falling edges of the input clock signal and send the second count value obtained by counting to the counting logic determination circuit; The counting logic determination circuit is used to determine the first output signal based on the received first counting value and / or the second counting value.

3. The frequency divider according to claim 2, characterized in that: The counting logic determination circuit is further used to determine that the first output signal is in a first potential state when the first count value or the second count value is greater than a first pre-designed value; The first preset count value is determined based on the count ranges of the first counter and the second counter; Alternatively, when both the first count value and the second count value are not greater than the first pre-designed value, the first output signal is determined to be in the second potential state.

4. The frequency divider according to claim 2 or 3, characterized in that: The odd path further comprises: a register; the register is connected to the counting logic determination circuit; the clock signal is a periodic signal; The counting logic determination circuit is further used to predict a first predicted count value of a rising edge of the first counter in a next clock cycle and a second predicted count value of a falling edge of the second counter by using the first count value and the second count value received in the current clock cycle; Determine a signal to be output based on the first predicted count value and the second predicted count value, and store the signal to be output in the register; The register is used to output the signal to be output as the next first output signal when the next clock cycle arrives.

5. The frequency divider according to claim 1, characterized in that: The even-numbered path comprises: a clock output unit; the clock output unit is connected to the third counter; The third counter is used to count the rising edge or the falling edge of the input clock signal, and send the third count value obtained by counting to the clock output unit; The clock output unit is used to determine that the potential state of the second output signal is inverted when the third count value reaches a second preset value; the second preset count value is determined based on the count range of the third counter.

6. The frequency divider according to any one of claims 1 to 3 and 5, characterized in that: The frequency division ratio determiner is further used to determine the clock signal as the frequency division signal and output it when the frequency division ratio is less than a preset value; When the frequency division ratio is not less than the preset value and is an odd number, the first output signal is determined as the frequency division signal and outputted; When the frequency division ratio is not less than the preset value and is an even number, the second output signal is determined as the frequency division signal and outputted.

7. The frequency divider according to any one of claims 1 to 3 and 5, characterized in that: The odd-numbered path is used to enable the first counter and the second counter contained therein to stop counting and output a third output signal when the frequency division ratio represents an even number; The even-numbered path is used to enable the third counter contained therein to stop counting and output a fourth output signal when the frequency division ratio represents an odd number; The frequency division ratio determiner is further used to determine and output a frequency division signal from the first output signal, the fourth output signal, and the clock signal according to the frequency division ratio; Alternatively, a frequency-divided signal is determined from the third output signal, the second output signal, and the clock signal and outputted.

8. The frequency divider according to any one of claims 1 to 3 and 5, characterized in that: The frequency divider is a loop feedback frequency divider of a phase-locked loop supporting fractional frequency division, or a post-output frequency divider of the phase-locked loop supporting fractional frequency division.

9. A frequency division control circuit, characterized in that: The frequency division control circuit comprises a frequency division ratio provider, a phase-locked loop forward path, a first frequency divider, and a second frequency divider, wherein the first frequency divider and the second frequency divider have the same structure as the frequency divider described in any one of claims 1 to 8; the phase-locked loop forward path can receive a reference clock signal; The frequency division ratio provider is connected to the first frequency divider and the second frequency divider respectively; the frequency division ratio provider is used to send the frequency division ratio to the first frequency divider and the second frequency divider; The phase-locked loop forward path is connected to the first frequency divider and the second frequency divider respectively; the phase-locked loop forward path is used to perform phase synchronization based on the reference clock signal to generate a clock signal, and input the clock signal to the first frequency divider and the second frequency divider; The first frequency divider is used to divide the input clock signal based on the received frequency division ratio, and feed back a first frequency division signal obtained by the frequency division to the forward path of the phase-locked loop; The second frequency divider is used to divide the input clock signal based on the received frequency division ratio, and output a second frequency-divided signal obtained by the frequency division.

10. The frequency division control circuit according to claim 9, characterized in that: The phase-locked loop forward path includes: a frequency detector, a phase detector, a low-pass filter, and a voltage-controlled oscillator; The first frequency divider is connected to the frequency detector and phase detector; the first frequency divider is used to send the first frequency divided signal obtained by frequency division to the frequency detector and phase detector; The phase frequency detector is connected to the low-pass filter; the phase frequency detector is used to identify the phase difference between the received first frequency-divided signal and the reference clock signal, and send the error voltage generated based on the phase difference to the low-pass filter; The low-pass filter is connected to the voltage-controlled oscillator; the low-pass filter is used to filter the received error voltage to form a control voltage, and send it to the voltage-controlled oscillator; The voltage-controlled oscillator is connected to the first frequency divider; the voltage-controlled oscillator is used to control the output of the clock signal according to the received control voltage, and input the clock signal into the first frequency divider.

11. The frequency division control circuit according to claim 9, characterized in that: The voltage-controlled oscillator is connected to the second frequency divider; the voltage-controlled oscillator is also used to input the clock signal into the second frequency divider; The second frequency divider is connected to the processing chip; the second frequency divider is used to divide the input clock signal and send the obtained second frequency-divided signal to the processing chip.

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