Multichannel high-speed sampling multistage phase correction method and system
By configuring a multi-channel analog-to-digital converter on the FPGA chip and performing multi-stage phase correction, the problems of clock offset and sampling error in high-complexity FPGA design are solved, and the stable and reliable operation of high-speed ADCs under complex operating conditions is achieved. Efficient calibration.
Patent Information
- Application Number
- CN202411401651.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-02-14
AI Technical Summary
In high-complexity FPGA design, the clock load is too heavy, the layout and routing difficulty increases, and the transmission quality of the road clock decreases, resulting in clock offset generated by the FPGA in the metastable state of the data sampling edge and the high and low temperature working state, which in turn leads to delay The value is difficult to correct and the sampling error is large, so it cannot guarantee the stable and reliable operation of the high-speed ADC.
Using multi-channel high-speed sampling multi-stage phase correction method, the operating channels and frequency of the multi-channel analog-to-digital converter are configured through the FPGA chip to correct the characteristic parameters of each channel, including DC bias, channel gain and phase delay, and pass delay Process and parallel conversion, adjust the parallel data of each channel, perform two-stage delay correction according to the detection threshold, determine the optimal sampling delay stage, and adjust the sampling position of the multi-channel analog-to-digital converter.
Improve the delay adjustment accuracy of multi-channel analog-to-digital converter signal lines, avoid sampling errors caused by differences in temperature, voltage, and device personality, ensure the stable and reliable operation of high-speed ADCs under complex operating conditions, and reduce the correction time and improve Work efficiency.
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Figure CN119449032A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of signal processing, and in particular relates to a multi-stage phase correction method and system for multi-channel high-speed sampling. Background Art
[0002] The sampling rate of high-speed analog-to-digital conversion ADC chips has developed from the previous MHz level to the current GHz level. With the continuous increase in signal sampling rate, signal skew jitter and noise are all swallowing up the timing margin. How to perform stable and reliable sampling and data conversion in high-speed systems will face great challenges. For example, the EV10AQ190A high-speed AD chip has a maximum input sampling clock frequency of 2.5GHz. After the internal clock circuit is divided, four channels with a sampling rate of 1.25GHz are equivalent to one channel of 5GHz sampling data. In such a high-speed interface design, the stable phase relationship and synchronization performance of the clock and data will directly affect the quality of signal acquisition. Source synchronization technology must be used to ensure that the sampling clock and data are strictly synchronized and the timing relationship is stable. For high-complexity FPGA design, the clock load is too heavy, the layout and wiring difficulty increases, and the transmission quality of the clock is reduced, causing the problem of metastable data sampling edge and the clock offset problem generated by the FPGA under high and low temperature working conditions. It is necessary to be able to adjust the phase relationship between the clock and data with high precision so that the sampling has a larger dynamic range to adapt to complex working conditions. Summary of the invention
[0003] In order to solve the above-mentioned problems in the prior art, that is, to solve the problem that the high-complexity FPGA design causes excessive clock load, increased difficulty in layout and wiring, decreased transmission quality of the clock, metastable data sampling edge, and clock offset generated by the FPGA under high and low temperature working conditions, which leads to the difficulty in correcting the delay value, large sampling error, and inability to ensure stable and reliable operation of the high-speed ADC, the first aspect of the present invention proposes a multi-stage phase correction method for multi-channel high-speed sampling, which is used to obtain the optimal sampling delay level, adjust the sampling position of the multi-channel analog-to-digital converter, and then achieve the optimal sampling position. The method includes:
[0004] S1, using an FPGA chip to configure the working channel and frequency of a multi-channel analog-to-digital converter, and by configuring the register of the multi-channel analog-to-digital converter, correcting the characteristic parameters of each channel; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel;
[0005] S2, using the FPGA chip to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals;
[0006] S3, combining the single-ended clock signal, delaying the single-ended data signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel;
[0007] S4, setting a detection threshold according to the DC bias; performing channel-level and signal-level delay correction on the parallel data of each channel based on the detection threshold to obtain sampled recorded data;
[0008] S5, based on the sampled and recorded data, determine the data stable sampling interval, obtain the optimal sampling delay level, and then adjust the sampling position of the multi-channel analog-to-digital converter to achieve the optimal sampling position.
[0009] In some preferred implementations, the single-ended data signal is multiple-channel; the single-ended clock signal is one-channel.
[0010] In some preferred embodiments, the single-ended data signal is delayed in combination with the single-ended clock signal, and the delayed data signal is serial-to-parallel converted by channel to obtain parallel data of each channel, and the method is as follows:
[0011] The single-ended clock signal is generated into a set frequency-divided data clock, and then the single-ended data signal is delayed, and the delayed data signal is serial-to-parallel converted according to the channel to obtain parallel data of each channel; the set frequency-divided data clock includes a 4-frequency-divided data clock.
[0012] In some preferred embodiments, the single-ended clock signal is generated as a set frequency-divided data clock, and then the single-ended data signal is delayed, and the delayed data signal is serial-to-parallel converted by channel to obtain parallel data of each channel, and the method is:
[0013] Inputting multiple single-ended data signals into the IDELAY2 module of the FPGA chip for delay processing;
[0014] The data signal after delay processing passes through the ISERDESE2 module of the FPGA chip and is sampled using the set frequency-divided data clock. After sampling, serial-to-parallel conversion is performed according to a set ratio to obtain parallel data for each channel.
[0015] In some preferred implementations, the sampling is performed using the set frequency-divided data clock, and the method is: performing DDR sampling using the set frequency-divided data clock.
[0016] In some preferred embodiments, the IDELAY2 module includes a multi-stage adjustable delay device; wherein the delay value of each stage of the multi-stage adjustable delay device is set according to a reference clock.
[0017] In some preferred implementations, based on the detection threshold, the parallel data of each channel is subjected to two-level delay corrections at the channel level and the signal level to obtain sampled recorded data, and the method is as follows:
[0018] S41, correct the channel-level delay i, for each channel of multi-channel data, correct the signal-level delay j in sequence from the first channel, set the other channels as the current channel-level delay i, record record_tap_m_n_i[j], if the parallel data obtained by the current delay meets the detection threshold, then record_tap_m_n_i[j] = 1, if not, then record_tap_m_n_i[j] = 0; wherein m is the number of channels, n is the number of data channels, i is the channel-level delay, j is the signal-level delay, i, j = 0, 1...N;
[0019] S42, when the channel-level delay i correction of multiple data is completed, set the channel-level delay i=i+1, and determine whether i is greater than N, if not, jump to S41, otherwise, end the delay correction.
[0020] In some preferred embodiments, based on the sampled and recorded data, a data stable sampling interval is determined to obtain an optimal sampling delay level, and the method is as follows:
[0021] Starting from the low bit of the sampled recorded data, continuous 1s are searched as the data stable sampling interval [a, b]; the longest data stable sampling interval is selected, and (ab) / 2 is calculated as the optimal sampling delay level.
[0022] The second aspect of the present invention provides a multi-stage phase correction system for multi-channel high-speed sampling, which is used to obtain the optimal sampling delay level, adjust the sampling position of the multi-channel analog-to-digital converter, and thus achieve the optimal sampling position. The system includes: an FPGA chip, a multi-channel analog-to-digital converter;
[0023] The FPGA chip is used to configure the working channel and frequency of the multi-channel analog-to-digital converter, and to modify the characteristic parameters of each channel by configuring the register of the multi-channel analog-to-digital converter; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel;
[0024] It is also used to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals;
[0025] Delaying the single-ended data signal in combination with the single-ended clock signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel;
[0026] A detection threshold is set according to the DC bias; based on the detection threshold, two-level delay corrections are performed on the parallel data of each channel at the channel level and the signal level to obtain sampled recorded data;
[0027] Based on the sampled and recorded data, a data stable sampling interval is determined to obtain an optimal sampling delay level, and then the sampling position of the multi-channel analog-to-digital converter is adjusted to achieve an optimal sampling position.
[0028] Beneficial effects of the present invention:
[0029] 1) The present invention performs delay adjustment on each signal line of the multi-channel analog-to-digital converter, with higher adjustment accuracy, avoiding sampling errors caused by temperature, voltage, and device individuality differences, and ensuring stable and reliable operation of the high-speed ADC;
[0030] 2) The present invention records the effective delay of each signal line and automatically finds the delay of the optimal sampling position to solve the problem that the delay value is difficult to correct under high-complexity FPGA design and high-dynamic conditions, thereby reducing the correction time and improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.
[0032] Figure 1 It is a flow chart of a multi-stage phase correction method for multi-channel high-speed sampling according to an embodiment of the present invention;
[0033] Figure 2 It is a simplified flow chart of a multi-stage phase correction method for multi-channel high-speed sampling according to an embodiment of the present invention;
[0034] Figure 3 is a schematic diagram of data clock generation according to an embodiment of the present invention;
[0035] Figure 4 It is a schematic diagram of a data signal delay processing and serial-to-parallel conversion process according to an embodiment of the present invention;
[0036] Figure 5 It is a schematic diagram of obtaining the optimal data sampling position according to an embodiment of the present invention. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.
[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.
[0040] A multi-stage phase correction method for multi-channel high-speed sampling in the first embodiment of the present invention is used to obtain the optimal sampling delay level, adjust the sampling position of the multi-channel analog-to-digital converter, and thus achieve the optimal sampling position, such as Figure 1 As shown, the following steps are included:
[0041] S1, using an FPGA chip to configure the working channel and frequency of a multi-channel analog-to-digital converter, and by configuring the register of the multi-channel analog-to-digital converter, correcting the characteristic parameters of each channel; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel;
[0042] S2, using the FPGA chip to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals;
[0043] S3, combining the single-ended clock signal, delaying the single-ended data signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel;
[0044] S4, setting a detection threshold according to the DC bias; performing channel-level and signal-level delay correction on the parallel data of each channel based on the detection threshold to obtain sampled recorded data;
[0045] S5, based on the sampled and recorded data, determine the data stable sampling interval, obtain the optimal sampling delay level, and then adjust the sampling position of the multi-channel analog-to-digital converter to achieve the optimal sampling position.
[0046] In order to more clearly illustrate the multi-stage phase correction method for multi-channel high-speed sampling of the present invention, the following is combined with the attached Figure 2Each step in an embodiment of the method of the present invention is described in detail.
[0047] The present invention is aimed at the sampling data errors caused by the discrete device parameters and transmission path differences of the high-speed source synchronous multi-channel interleaved sampling ADC chip. The two-wire differential LVDS signal is converted into a single-ended FPGA internal signal, and then the data delay is adjusted through the IDELAY module. After data training, the sampling clock can be aligned with the center of the data to prevent data glitches. Finally, the serial-to-parallel conversion is used to reduce the data rate, which is convenient for FPGA internal data processing. The present invention is applicable to fields such as signal processing, and realizes dynamic phase adjustment of the sampling clock and data to ensure stable and reliable operation of the high-speed ADC. The specific process is as follows:
[0048] S1, using an FPGA chip to configure the working channel and frequency of a multi-channel analog-to-digital converter, and by configuring the register of the multi-channel analog-to-digital converter, correcting the characteristic parameters of each channel; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel;
[0049] In this embodiment, it is preferred to use an FPGA chip to configure a multi-channel analog-to-digital converter (preferably EV10AQ190) to operate in a single-channel 5GHz mode, and by configuring the registers of the multi-channel analog-to-digital converter, each channel has the correct DC bias, channel gain and phase delay.
[0050] S2, using the FPGA chip to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals;
[0051] In this embodiment, the FPGA chip IBUFDS primitive is used to convert the differential data of each channel generated by the multi-channel analog-to-digital converter (the differential data of the present invention is preferably ten pairs, and the number of channels is preferably four, namely A, B, C, D, i.e. Figure 2 The ADC_A, ADC_B, ADC_C, ADC_D) pairs and the accompanying clock differential pairs of each channel are converted into single-ended data signals and single-ended clock signals, that is, 10 data channels for each of the four channels A, B, C, and D, a total of 40 single-ended data signals, and one single-ended clock signal (i.e. Figure 3 ADC_ADR).
[0052] S3, combining the single-ended clock signal, delaying the single-ended data signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel;
[0053] In this embodiment, if Figure 4As shown, multiple single-ended data signals are input into the IDELAY2 module of the FPGA chip for delay processing; the IDELAY2 module includes a multi-stage adjustable delay device (preferably 32 stages in the present invention); wherein the delay value of each stage of the multi-stage adjustable delay device is set according to the reference clock; the data signal after delay processing passes through the ISERDESE2 module of the FPGA chip, using the set divided frequency data clock (preferably 4-divided frequency data clock in the present invention), that is Figure 3 ADC_ADR obtains data clock clk_in and 4-frequency-divided clock clk_div_in through BUFG and BUFR modules for DDR sampling. After sampling, serial-to-parallel conversion is performed according to a set ratio (preferably 1:8 in the present invention) to obtain parallel data of each channel.
[0054] like Figure 4 As shown, taking channel A as an example, 40 channels of data are delayed using the IDELAY2 module. IDELAY2 has 32 levels of adjustable delay devices. The initial delay value is set to 0, that is, the output is delayed by 600ps relative to the input. The delay value of each level is determined by the reference clock REFCLK. In this example, the reference clock is 200MHz, that is, the delay value of each level is 1 / (32*REFCLK)=78ps. The delayed data signal is sampled by the ISERDESE2 module using a 4-frequency clock for DDR sampling, completing a 1:8 serial-to-parallel conversion to obtain parallel data for each channel.
[0055] S4, setting a detection threshold according to the DC bias; performing channel-level and signal-level delay correction on the parallel data of each channel based on the detection threshold to obtain sampled recorded data;
[0056] In this embodiment, the parallel data of each channel is compared with the DC bias. The parallel data output by EV10AQ190 is a 10-bit unsigned number, and the maximum output value is 1023, so theoretically the DC bias should be 511. After the register configuration in step 1, if the data sampling is correct, the parallel data should fluctuate around 511. Then set the detection threshold to 501-521, and continuously sample the data for 1000 clock cycles. If the obtained parallel data are all within the detection threshold, it is considered that the delay value of this group is correct.
[0057] The delay value correction method adopts two levels of correction: channel level and signal level, and records whether each delay value meets the stable sampling conditions. The correction method is as follows:
[0058] Correct the channel-level delay i (i=0,1...N, N is preferably 31 in the present invention), each channel has 10 data channels, and correct the signal-level delay j (j=0,1...N) in sequence starting from the first channel. The other 9 channels are set as the current channel-level delay i, and record record_tap_m_n_i[j] is recorded, where m is the channel number, n is the data channel number, i is the channel-level delay, and j is the signal-level delay, that is, record_tap_m_n_i[j] is 32-bit data. If the parallel data obtained by the current delay meets the detection threshold, record_tap_m_n_i[j]=1, if not, record_tap_m_n_i[j]=0. After adjusting the ten data channels, the channel-level delay is corrected to i+1, and the signal-level correction of the 10 data channels of each channel is repeated (i.e., the channel-level delay and the signal-level delay are two-level nested, with a total of ten data channels. The first channel starts with 0-31 adjustment, and the other channels are set to 0. The second channel starts with 0-31 adjustment, and the other channels are set to 0, until the tenth channel is adjusted from 0 to 31. The first channel starts with 0-31 adjustment, and the other channels are set to 1...., a total of 32*10 adjustments). Finally, 4*10*32=1280 groups of 32-bit sampling records are obtained.
[0059] S5, based on the sampled and recorded data, determine the data stable sampling interval, obtain the optimal sampling delay level, and then adjust the sampling position of the multi-channel analog-to-digital converter to achieve the optimal sampling position.
[0060] In this embodiment, the best sampling position is found according to the stable sampling and recording data, such as Figure 5 As shown in the figure, training is to adjust the sampling position by adjusting the delay series of IDELAY to achieve the best sampling position and finally determine the delay series, that is, to align the data center (DATA0, DATA1...) with the rising edge of the clock. According to the training code obtained by training in step 4, continuous 1s are searched from the low bit, which is considered to be the stable data sampling interval [a, b]. Max (ab) is taken to obtain the longest stable sampling interval, and (ab) / 2 is calculated. The result is the best sampling delay series, at which the data is at the best latching moment. According to the best sampling delay series, the sampling position of the multi-channel analog-to-digital converter is adjusted to achieve the best sampling position.
[0061] In summary, the present invention provides a multi-level phase correction technology for multi-channel high-speed sampling, targeting the sampling differences caused by temperature, voltage, and device personality differences in high-complexity FPGA designs and high-power and high-dynamic conditions. Through two-level phase correction methods at the channel level and signal level, the center alignment of the sampling clock and the data is guaranteed, ensuring stable and reliable operation of the high-speed ADC.
[0062] A multi-channel high-speed sampling multi-stage phase correction system according to a second embodiment of the present invention comprises: an FPGA chip, a multi-channel analog-to-digital converter;
[0063] The FPGA chip is used to configure the working channel and frequency of the multi-channel analog-to-digital converter, and to modify the characteristic parameters of each channel by configuring the register of the multi-channel analog-to-digital converter; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel;
[0064] It is also used to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals;
[0065] Delaying the single-ended data signal in combination with the single-ended clock signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel;
[0066] A detection threshold is set according to the DC bias; based on the detection threshold, two-level delay corrections are performed on the parallel data of each channel at the channel level and the signal level to obtain sampled recorded data;
[0067] Based on the sampled and recorded data, a data stable sampling interval is determined to obtain an optimal sampling delay level, and then the sampling position of the multi-channel analog-to-digital converter is adjusted to achieve an optimal sampling position.
[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0069] It should be noted that the multi-channel high-speed sampling multi-stage phase correction system provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.
[0070] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned multi-channel high-speed sampling multi-stage phase correction method.
[0071] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned multi-channel high-speed sampling multi-stage phase correction method.
[0072] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and computer-readable storage medium described above can refer to the corresponding process in the aforementioned method example and will not be repeated here.
[0073] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
[0074] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.
[0075] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0076] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A multi-stage phase correction method for multi-channel high-speed sampling, used to obtain the best sampling delay level, adjust the sampling position of the multi-channel analog-to-digital converter, and thus achieve the best sampling position, characterized in that: The method comprises the following steps: S1, using an FPGA chip to configure the working channel and frequency of a multi-channel analog-to-digital converter, and by configuring the register of the multi-channel analog-to-digital converter, correcting the characteristic parameters of each channel; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel; S2, using the FPGA chip to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals; S3, combining the single-ended clock signal, delaying the single-ended data signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel; S4, setting a detection threshold according to the DC bias; performing channel-level and signal-level delay correction on the parallel data of each channel based on the detection threshold to obtain sampled recorded data; S5, based on the sampled and recorded data, determine the data stable sampling interval, obtain the optimal sampling delay level, and then adjust the sampling position of the multi-channel analog-to-digital converter to achieve the optimal sampling position.
2. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 1, characterized in that: The single-ended data signal is multiple-channel; the single-ended clock signal is one-channel.
3. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 2, characterized in that: In combination with the single-ended clock signal, the single-ended data signal is delayed, and the delayed data signal is serial-to-parallel converted according to the channel to obtain parallel data of each channel, wherein the method is: The single-ended clock signal is generated into a set frequency-divided data clock, and then the single-ended data signal is delayed, and the delayed data signal is serial-to-parallel converted according to the channel to obtain parallel data of each channel; the set frequency-divided data clock includes a 4-frequency-divided data clock.
4. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 3 is characterized in that: The single-ended clock signal is generated into a set frequency-divided data clock, and then the single-ended data signal is delayed, and the delayed data signal is serial-to-parallel converted according to the channel to obtain parallel data of each channel, wherein the method is: Inputting multiple single-ended data signals into the IDELAY2 module of the FPGA chip for delay processing; The data signal after delay processing passes through the ISERDESE2 module of the FPGA chip and is sampled using the set frequency-divided data clock. After sampling, serial-to-parallel conversion is performed according to a set ratio to obtain parallel data for each channel.
5. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 4 is characterized in that: The method of using the set frequency-divided data clock for sampling is as follows: using the set frequency-divided data clock for DDR sampling.
6. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 4, characterized in that: The IDELAY2 module includes a multi-stage adjustable delay device, wherein the delay value of each stage of the multi-stage adjustable delay device is set according to a reference clock.
7. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 4, characterized in that: Based on the detection threshold, the parallel data of each channel is subjected to two-level delay correction, channel level and signal level, to obtain sampled recorded data, and the method is as follows: S41, correct the channel-level delay i, for each channel of multi-channel data, correct the signal-level delay j in sequence from the first channel, set the other channels as the current channel-level delay i, record record_tap_m_n_i[j], if the parallel data obtained by the current delay meets the detection threshold, then record_tap_m_n_i[j] = 1, if not, then record_tap_m_n_i[j] = 0; wherein m is the number of channels, n is the number of data channels, i is the channel-level delay, j is the signal-level delay, i, j = 0, 1...N; S42, when the channel-level delay i correction of multiple data is completed, set the channel-level delay i=i+1, and determine whether i is greater than N, if not, jump to S41, otherwise, end the delay correction.
8. The multi-stage phase correction method for multi-channel high-speed sampling according to claim 7, characterized in that: Based on the sampled and recorded data, a data stable sampling interval is determined to obtain an optimal sampling delay level, and the method is as follows: Starting from the low bit of the sampled recorded data, continuous 1s are searched as the data stable sampling interval [a, b]; the longest data stable sampling interval is selected, and (ab) / 2 is calculated as the optimal sampling delay level.
9. A multi-stage phase correction system for multi-channel high-speed sampling, used to obtain the best sampling delay level, adjust the sampling position of the multi-channel analog-to-digital converter, and thus achieve the best sampling position, characterized in that: The system includes: FPGA chip, multi-channel analog-to-digital converter; The FPGA chip is used to configure the working channel and frequency of the multi-channel analog-to-digital converter, and to modify the characteristic parameters of each channel by configuring the register of the multi-channel analog-to-digital converter; the characteristic parameters include DC bias, channel gain and phase delay; the working channel is a single channel; It is also used to convert the differential data pairs generated by each channel of the multi-channel analog-to-digital converter into single-ended data signals, and convert the accompanying clock differential pairs into single-ended clock signals; Delaying the single-ended data signal in combination with the single-ended clock signal, and performing serial-to-parallel conversion on the delayed data signal by channel to obtain parallel data for each channel; A detection threshold is set according to the DC bias; based on the detection threshold, two-level delay corrections are performed on the parallel data of each channel at the channel level and the signal level to obtain sampled recorded data; Based on the sampled and recorded data, a data stable sampling interval is determined to obtain an optimal sampling delay level, and then the sampling position of the multi-channel analog-to-digital converter is adjusted to achieve an optimal sampling position.