Asymmetric stacked PCB and impedance improvement method
By increasing the resin content in the butterfly area of the PCB board and adjusting the impedance line width in the large copper skin area, the problem of excessive difference in the dielectric layer thickness between the butterfly area and the large copper skin area is solved, and the impedances of both regions are qualified.
Patent Information
- Application Number
- CN202411038213.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
The thickness of the dielectric layer in the existing PCB boards in the butterfly area and the large copper-skin area is too large, resulting in the impedance of the butterfly area being unqualified.
Adjust the impedance by increasing the resin content in the dielectric layer in the butterfly area, and set the impedance line in the large copper skin area, adjusting its line width to match the preset impedance value.
The difference in the thickness of the dielectric layer between the butterfly area and the large copper skin area is achieved, so that the impedance of both areas can be qualified.
Smart Images
Figure CN119450888A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of PCB boards, and in particular to an asymmetric stacked PCB board and an impedance improvement method. Background Art
[0002] The existing PCB board inner layer BGA area is designed with an empty frame area, which is shaped like a butterfly and is called the butterfly area. The areas other than the butterfly area are large copper areas. When this design is added and pressed in the PCB process, more resin glue is needed to fill this area due to the local emptiness. Compared with other traditional boards using the same resin glue with the same resistance and capacitance, the dielectric layer thickness of the butterfly area design board will be thinner, resulting in unqualified impedance at this position. For PCB boards with butterfly area design, the difference in dielectric layer thickness between the butterfly area and the large copper area should not be too large, and the impedance of the butterfly area and the large copper area should not be unqualified.
[0003] Therefore, a method is needed to ensure that the impedance of the butterfly area and the large copper area are qualified without making the difference in dielectric layer thickness between the butterfly area and the large copper area too large. Summary of the invention
[0004] The main purpose of the present invention is to provide an asymmetric stacked PCB board and an impedance improvement method, which can solve the problem in the prior art that the difference in dielectric layer thickness between the butterfly area and the large copper area cannot be too large, and the butterfly area is unqualified.
[0005] To achieve the above-mentioned object, the first aspect of the present invention provides an asymmetric stacked PCB board, the asymmetric stacked PCB board at least comprising a prepreg made of a dielectric layer; a butterfly area and a large copper area are arranged on the dielectric layer; wherein the butterfly area is an empty frame area of a BGA area in the asymmetric stacked PCB board, and the large copper area is an area remaining in the asymmetric stacked PCB board after removing the butterfly area;
[0006] The butterfly area adopts a resin content higher than a preset thickness of the dielectric layer; wherein, increasing the preset thickness is used to adjust the impedance value of the butterfly area to a preset value.
[0007] In combination with the first aspect, in a possible implementation manner, an impedance line is set in the large copper area.
[0008] In combination with the first aspect, in a possible implementation manner, the line width of the impedance line is adjusted to a preset line width, wherein the preset line width is a line width that adjusts the impedance value of the impedance line to a preset value.
[0009] In combination with the first aspect, in a possible implementation manner, the asymmetric stacked PCB board further includes a copper clad board and copper foil.
[0010] In combination with the first aspect, in a possible implementation manner, the copper clad laminate, the prepreg, and the copper foil are stacked in sequence to form an asymmetric laminate structure.
[0011] To achieve the above object, the second aspect of the present invention provides an impedance improvement method applied to the asymmetric stacked PCB board as described in the first aspect, the method comprising:
[0012] Identify the butterfly area and the large copper area of the asymmetric stacked PCB board;
[0013] Impedance compensation is performed on the butterfly area and the large copper area respectively by using different impedance compensation methods.
[0014] In combination with the second aspect, in a possible implementation, the impedance compensation method for the butterfly area includes: increasing the resin content of the prepreg so that the thickness of the dielectric layer in the layer where the butterfly area is located increases by a preset thickness.
[0015] In combination with the second aspect, in a possible implementation method, the impedance compensation method for the large copper area includes: if the large copper area is designed with an impedance line, impedance compensation is performed on the line width of the impedance line at the corresponding position according to the change in the thickness of the semi-cured sheet.
[0016] In combination with the second aspect, in a possible implementation method, the above-mentioned impedance compensation for the line width of the impedance line at the corresponding position according to the change of the thickness of the semi-cured sheet includes: according to the change of the thickness of the semi-cured sheet, selecting the impedance line that needs to be impedance compensated in the large copper foil area to obtain the impedance line at the corresponding position; performing impedance compensation on the impedance line at the corresponding position.
[0017] In combination with the second aspect, in a possible implementation, the impedance compensation of the impedance line at the corresponding position includes: increasing the line width of the impedance line at the corresponding position by a preset line width, wherein increasing the preset line width is used to adjust the impedance value of the impedance line to a preset value.
[0018] The embodiments of the present invention have the following beneficial effects:
[0019] The present invention provides an asymmetric stacked PCB board and an impedance improvement method. Different impedance compensation modes are respectively adopted for a butterfly area and a large copper area. For the butterfly area, the impedance is adjusted by increasing the resin content in the dielectric layer of the butterfly area, so as to reduce the difference between the dielectric layer thickness of the butterfly area and the dielectric layer thickness of the large copper area. The present invention can achieve the impedance of both the butterfly area and the large copper area being qualified without making the dielectric layer thickness difference between the butterfly area and the large copper area too large. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0021] in:
[0022] Figure 1 This is a schematic diagram of an asymmetric stacked PCB board in an embodiment of the present invention;
[0023] Figure 2 A schematic diagram of a flow chart of an impedance improvement method in an embodiment of the present invention;
[0024] Figure 3 4 is a structural block diagram of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0026] An embodiment of the present invention provides an asymmetric stacked PCB board, which includes a copper clad board, a copper foil, and a prepreg made of a dielectric layer. The copper clad board, the prepreg, and the copper foil are stacked in sequence to form an asymmetric stacked structure. The inner BGA area of the asymmetric stacked PCB board is designed with an empty frame area, which is shaped like a butterfly and is called a butterfly area. The areas other than the butterfly area are large copper areas, such as Figure 1 As shown, Figure 1 This is a schematic diagram of an asymmetric stacked PCB board provided by an embodiment of the present invention, where the black portion within the frame is the butterfly area, and the non-black area is the large copper area.
[0027] In the existing PCB board, the dielectric layer thickness of the butterfly area is smaller than that of the large copper area, and the butterfly area is unqualified. In order to reduce the dielectric thickness difference between the butterfly area and the large copper area, in this embodiment, for the butterfly area, the impedance is adjusted by increasing the resin content in the dielectric layer of the butterfly area, so as to achieve the impedance of the butterfly area reaching a preset value on the basis of reducing the gap between the dielectric layer thickness of the butterfly area and the dielectric layer thickness of the large copper area. The preset thickness is a thickness that can adjust the impedance value of the butterfly area to the preset value after increasing the preset thickness, and the preset value is a qualified impedance value.
[0028] However, after the resin content in the butterfly area is increased, the increase in the dielectric layer will cause the impedance of the large copper area to change, making the impedance of the large copper area unqualified. Therefore, in this embodiment, the impedance of the large copper area needs to be adjusted to achieve qualified impedance of the large copper area on the basis of reducing the gap between the thickness of the dielectric layer in the butterfly area and the thickness of the dielectric layer in the large copper area.
[0029] In this embodiment, an impedance line is set in the large copper area, and the impedance value can be adjusted by adjusting the line width of the impedance line. Specifically, the line width of the impedance line is increased or decreased based on the existing line width of the impedance line, so that the line width of the impedance line is adjusted to a preset line width, wherein the preset line width is a line width that adjusts the impedance value of the impedance line to a preset value.
[0030] The embodiment of the present invention also provides an impedance improvement method for an asymmetric stacked PCB board, so as to adjust the impedance of an existing asymmetric stacked PCB board. Figure 2 As shown, Figure 2 A schematic diagram of a flow chart of an impedance improvement method provided by an embodiment of the present invention, such as Figure 2 As shown, the specific steps of this method are as follows:
[0031] Step S101, identifying the butterfly area and the large copper area of the asymmetric stacked PCB board.
[0032] Step S102: performing impedance compensation on the butterfly area and the large copper area respectively by using different impedance compensation methods.
[0033] Identify the butterfly area and large copper area of the asymmetric stacked PCB board, and perform impedance compensation on the butterfly area and the large copper area using different impedance compensation methods.
[0034] For the butterfly area, the thickness of the dielectric layer of the layer where the butterfly area is located is increased by a preset thickness by increasing the resin content of the prepreg. For the large copper area, if the large copper area is designed with an impedance line, the line width of the impedance line at the corresponding position is impedance compensated according to the change in the thickness of the prepreg. Specifically, after the thickness of the dielectric layer of the layer where the butterfly area is located is increased by a preset thickness, the impedance line that needs to be impedance compensated in the large copper area is selected to obtain the impedance line at the corresponding position, and impedance compensation is performed on the selected impedance line at the corresponding position. Impedance compensation is achieved by increasing the line width of the impedance line at the corresponding position by a preset line width.
[0035] Based on the above method, different impedance compensation methods can be adopted for the butterfly area and the large copper area respectively, so that the impedance of the butterfly area and the large copper area can be qualified without making the difference of the dielectric layer thickness between the butterfly area and the large copper area too large.
[0036] Figure 3FIG. 1 shows an internal structure diagram of a computer device in an embodiment. The computer device may be a terminal or a server. Figure 3 As shown, the computer device includes a processor, a memory and a network interface connected via a system bus. The memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement all the steps of the above method. The internal memory may also store a computer program. When the computer program is executed by the processor, the processor can implement all the steps of the above method. Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0037] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes each step of the aforementioned method.
[0038] In one embodiment, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the processor executes each step of the aforementioned method.
[0039] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0040] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0041] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. An asymmetric stacked PCB board, characterized in that: The asymmetric stacked PCB board at least includes a prepreg made of a dielectric layer; a butterfly area and a large copper area are arranged on the dielectric layer; wherein the butterfly area is an empty frame area of a BGA area in the asymmetric stacked PCB board, and the large copper area is an area remaining in the asymmetric stacked PCB board after removing the butterfly area; The butterfly area adopts a resin content higher than a preset thickness of the dielectric layer; wherein, increasing the preset thickness is used to adjust the impedance value of the butterfly area to a preset value.
2. The asymmetric stacked PCB board according to claim 1, characterized in that: The large copper area is provided with an impedance line.
3. The asymmetric stacked PCB board according to claim 3, characterized in that: The line width of the impedance line is adjusted to a preset line width, wherein the preset line width is a line width that adjusts the impedance value of the impedance line to a preset value.
4. The asymmetric stacked PCB board according to claim 1, characterized in that: The asymmetric stacked PCB board also includes a copper clad plate and copper foil.
5. The asymmetric stacked PCB board according to claim 4, characterized in that: The copper clad laminate, prepreg and copper foil are stacked in sequence to form an asymmetric laminate structure.
6. An impedance improvement method for an asymmetric stacked PCB board as described in claims 1-5, characterized in that: The method is: Identify the butterfly area and the large copper area of the asymmetric stacked PCB board; Impedance compensation is performed on the butterfly area and the large copper area respectively by using different impedance compensation methods.
7. The impedance improvement method according to claim 6, characterized in that: The impedance compensation method for performing impedance compensation on the butterfly area includes: By increasing the resin content of the prepreg, the thickness of the dielectric layer in the layer where the butterfly area is located increases to a preset thickness.
8. The impedance improvement method according to claim 6, characterized in that: The impedance compensation method for performing impedance compensation on the large copper area includes: If an impedance line is designed in the large copper area, impedance compensation is performed on the line width of the impedance line at the corresponding position according to the change in the thickness of the prepreg.
9. The impedance improvement method according to claim 8, characterized in that: The impedance compensation for the line width of the impedance line at the corresponding position according to the change of the thickness of the prepreg comprises: According to the change of the thickness of the prepreg, the impedance line that needs to be compensated for impedance in the large copper area is selected to obtain the impedance line of the corresponding position; Impedance compensation is performed on the impedance lines at the corresponding positions.
10. The impedance improvement method according to claim 9, characterized in that: The impedance compensation for the corresponding position impedance line includes: The preset line width is increased for the line width of the impedance line at the corresponding position, wherein the increase in the preset line width is used to adjust the impedance value of the impedance line to a preset value.