Memory and manufacturing method thereof

Abstract

The embodiment of the invention provides a memory and a manufacturing method thereof. According to the memory provided by the embodiment of the invention, the first active structure of the first transistor and the second active structure of the second transistor in the memory unit are electrically connected with the same bit line, so that the two transistors can share the same bit line, and the number of the bit lines in the memory can be greatly reduced; therefore, the design difficulty of the memory can be reduced, the manufacturing difficulty of the memory can be reduced, and the manufacturing cost of the memory can be reduced. Moreover, the storage unit comprises a first capacitor and a second capacitor, so that the storage unit can store two-digit data. Moreover, the first capacitor, the first transistor, the second transistor and the second capacitor of the memory unit are sequentially laminated on one side of the substrate, so that the area occupied by the memory unit can be reduced, and the memory density of the memory can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory and a method for manufacturing the same. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The present application proposes a memory and a manufacturing method thereof, which are at least intended to improve the deficiencies of the prior art.

[0005] In a first aspect, an embodiment of the present application provides a memory, comprising: at least one memory cell, at least one first word line, at least one second word line, and at least one bit line;

[0006] The memory cell includes a first capacitor, a first transistor, a second transistor, and a second capacitor stacked in sequence on one side of a substrate, the first capacitor being electrically connected to the first transistor, and the second capacitor being electrically connected to the second transistor; a bit line being arranged between the first transistor and the second transistor in a direction perpendicular to the substrate; a first active structure of the first transistor and a second active structure of the second transistor being electrically connected to the bit line, a first gate of the first transistor being electrically connected to a first word line, and a second gate of the second transistor being electrically connected to a second word line.

[0007] In a second aspect, an embodiment of the present application provides a method for manufacturing a memory, comprising:

[0008] forming a first capacitor on one side of the substrate;

[0009] A first dielectric layer, a first word line, and a second dielectric layer are sequentially formed in a stacked manner on a side of the first capacitor away from the substrate;

[0010] forming a first via hole in the second dielectric layer, the first word line, and the first dielectric layer based on a patterning process, so that at least a portion of the first capacitor is exposed;

[0011] A first active structure insulated from the first word line is formed in the first via hole; the first active structure includes a first electrode, a first channel portion, and a second electrode stacked from bottom to top;

[0012] forming a bit line on a side of the second electrode away from the substrate;

[0013] On the side of the bit line away from the substrate, a third dielectric layer, a second word line and a fourth dielectric layer are sequentially provided;

[0014] forming a second via hole in the fourth dielectric layer, the second word line, and the third dielectric layer based on a patterning process, so that at least a portion of the bit line is exposed;

[0015] forming a second active structure insulated from the second word line in the second via hole; the second active structure includes a third electrode, a second channel portion, and a fourth electrode stacked from bottom to top;

[0016] A second capacitor is formed on a side of the fourth electrode away from the substrate.

[0017] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0018] In the memory provided in the embodiment of the present application, by setting the first active structure of the first transistor and the second active structure of the second transistor in the memory cell to be electrically connected to the same bit line, the two transistors can share one bit line, thereby greatly reducing the number of bit lines in the memory, reducing the design difficulty of the memory, reducing the manufacturing difficulty of the memory, and thus helping to reduce the manufacturing cost of the memory.

[0019] Furthermore, in the memory provided in the embodiments of the present application, the memory cell includes a first capacitor and a second capacitor, enabling the memory cell to store two bits of data. Furthermore, the first capacitor, first transistor, second transistor, and second capacitor of the memory cell are sequentially stacked on one side of the substrate, which can reduce the area occupied by the memory cell, thereby helping to increase the storage density of the memory.

[0020] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0023] Figure 2 Provided in the embodiments of this application Figure 1 A schematic structural diagram of a first active structure in the memory shown;

[0024] Figure 3 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0025] Figure 4 Provided in the embodiments of this application Figure 3 A schematic cross-sectional view of the memory at point aa is shown;

[0026] Figure 5 A schematic flow chart of a memory manufacturing method provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of a cross-sectional film layer after forming a first capacitor on one side of a substrate in a method for manufacturing a memory provided by an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a cross-sectional film layer after forming a first dielectric layer on one side of a first capacitor in a method for manufacturing a memory provided by an embodiment of the present application;

[0029] Figure 8 A schematic top view of a film structure after a bit line is formed on one side of a first dielectric layer in a method for manufacturing a memory provided by an embodiment of the present application;

[0030] Figure 9 for Figure 8 Schematic diagram of the cross-section of the membrane layer at point aa in the membrane layer structure shown;

[0031] Figure 10 A schematic diagram of a cross-sectional film layer after forming a seventh dielectric layer in a memory manufacturing method provided by an embodiment of the present application;

[0032] Figure 11 A schematic top view of a film structure after forming a first transistor based on a CMP process in a memory manufacturing method provided by an embodiment of the present application;

[0033] Figure 12 for Figure 11 Schematic diagram of the cross-section of the membrane layer at point aa in the membrane layer structure shown;

[0034] Figure 13 A schematic top view of a film structure after forming a bit line in a memory manufacturing method provided by an embodiment of the present application;

[0035] Figure 14 for Figure 13 Schematic diagram of the cross-sectional membrane layer at point aa in the membrane layer structure shown.

[0036] Description of reference numerals:

[0037] 100 - substrate; 101 - fifth dielectric layer; 102 - first dielectric layer; 103 - second dielectric layer; 104 - third dielectric layer; 105 - fourth dielectric layer; 106 - eighth dielectric layer; 107 - sixth dielectric layer; 108 - active layer; 109 - seventh dielectric layer; 110 - array region; 111 - peripheral region;

[0038] 10- storage unit;

[0039] 11- first capacitor;

[0040] 12- a first transistor;

[0041] 121-first active structure;

[0042] 1211 - first electrode; 1201 - annular portion; 1202 - bottom plate portion;

[0043] 1212 - first channel portion; 1213 - second electrode;

[0044] 122-first gate;

[0045] 123-third medium structure;

[0046] 124-first dielectric structure;

[0047] 13- second transistor;

[0048] 131- second active structure;

[0049] 132-second gate;

[0050] 133-Fourth medium structure;

[0051] 134-second medium structure;

[0052] 14- Second capacitor.

[0053] 20-first word line; 30-second word line; 40-bit line; 50-peripheral circuit;

[0054] 51-first conductive structure;

[0055] 52-second conductive structure;

[0056] 53-third conductive structure;

[0057] 54-fourth conductive structure. DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0059] Those skilled in the art will understand that, unless otherwise stated, the singular forms "one", "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by this technical field. It should be understood that when we refer to an element as being "connected" to another element, the element may be directly connected to the other element, or it may refer to the establishment of a connection relationship between the element and the other element through an intermediate element. In addition, the "connection" used here may include wireless connection. The term "and / or" used here refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] Currently, a 2T0C memory cell can only store one bit of data at most. A 2T0C memory cell typically requires a read bit line, a read word line, a write bit line, a write word line, and a storage node located between two transistors. This requires at least five layers of metal structure, increasing the design difficulty, manufacturing difficulty, and manufacturing cost of the memory cell.

[0062] Moreover, as the number of metal structure layers increases, the probability of parasitic capacitance increases, which can easily have a negative impact on the performance of the memory.

[0063] The memory and the manufacturing method thereof provided in this application are intended to solve the above technical problems of the prior art.

[0064] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0065] The embodiment of the present application provides a memory, the structural diagram of which is as follows: Figure 1As shown, the memory includes at least one memory cell 10 , at least one first word line 20 , at least one second word line 30 and at least one bit line 40 .

[0066] The memory cell 10 includes a first capacitor 11, a first transistor 12, a second transistor 13, and a second capacitor 14 stacked in sequence on one side of a substrate 100. The first capacitor 11 is electrically connected to the first transistor 12, and the second capacitor 14 is electrically connected to the second transistor 13. A bit line 40 is arranged between the first transistor 12 and the second transistor 13 in a direction perpendicular to the substrate 100. The first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13 are both electrically connected to the bit line 40. The first gate 122 of the first transistor 12 is electrically connected to the first word line 20, and the second gate 132 of the second transistor 13 is electrically connected to the second word line 30.

[0067] In the memory provided in the embodiment of the present application, by setting the first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13 in the memory cell 10 to be electrically connected to the same bit line 40, the two transistors can share one bit line 40, thereby greatly reducing the number of bit lines 40 in the memory, reducing the design difficulty of the memory, reducing the manufacturing difficulty of the memory, and thus helping to reduce the manufacturing cost of the memory.

[0068] Furthermore, in the memory provided in the embodiment of the present application, the memory cell 10 includes a first capacitor 11 and a second capacitor 14, enabling the memory cell 10 to store two bits of data. Furthermore, the first capacitor 11, the first transistor 12, the second transistor 13, and the second capacitor 14 of the memory cell 10 are sequentially stacked on one side of the substrate 100, which can reduce the area occupied by the memory cell 10, thereby helping to improve the storage density of the memory.

[0069] In the embodiment of the present application, in order to facilitate readers to intuitively understand the structure of the storage unit 10, as shown in FIG. Figure 1 In the figure, only one storage unit 10 is shown schematically.

[0070] like Figure 1 As shown, the first word line 20, the bit line 40, and the second word line 30 are sequentially stacked on one side of the substrate 100 in a direction perpendicular to and away from the substrate 100. Optionally, the first word line 20, the bit line 40, and the second word line 30 all extend in a direction parallel to the substrate 100, the first word line 20 and the second word line 30 extend in the same direction, and the bit line 40 extends in a direction perpendicular to the first word line 20 and the second word line 30.

[0071] like Figure 1As shown, the memory cell 10 extends in a direction perpendicular to the substrate 100 and away from the substrate 100, and the first capacitor 11, the first transistor 12, the second transistor 13 and the second capacitor 14 of the memory cell 10 are stacked in sequence on one side of the substrate 100, which can reduce the area of ​​the memory cell 10's positive projection on the substrate 100 and the area occupied by the memory cell 10, thereby helping to improve the storage density of the memory.

[0072] In the embodiment of the present application, the first capacitor 11 is electrically connected to the first transistor 12. By controlling the conduction and closing of the first transistor 12, it is possible to read the data stored in the first capacitor 11 or store data in the first capacitor 11, so that the first capacitor 11 can store one bit of data. The second capacitor 14 is electrically connected to the second transistor 13. By controlling the conduction and closing of the second transistor 13, it is possible to read the data stored in the second capacitor 14 or store data in the second capacitor 14, so that the second capacitor 14 can store one bit of data. That is, the memory cell 10 provided in the embodiment of the present application can store two bits of data, thereby further improving the storage density of the memory.

[0073] In the embodiment of this application, Figure 1 As shown, along a direction perpendicular to the substrate 100 and away from the substrate 100, the first gate 122 of the first transistor 12 is electrically connected to the first word line 20 located below, the second gate 132 of the second transistor 13 is electrically connected to the second word line 30 located above, and the middle bit line 40 is located between the first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13, so that the first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13 are both electrically connected to the same bit line 40, so that each memory cell 10 only needs to be configured with one bit line 40, which can greatly reduce the number of bit lines 40 in the memory, reduce the design difficulty of the memory, reduce the manufacturing difficulty of the memory, and thus help reduce the manufacturing cost of the memory.

[0074] At the same time, by reducing the number of bit lines 40 in the memory, the probability of parasitic capacitance in the memory can be reduced, thereby helping to ensure the performance of the memory.

[0075] It should be noted that in order to facilitate readers to intuitively understand the structure of the memory, such as Figure 1 As shown, the first gate 122 and the first word line 20 are represented by different textures, and the second gate 132 and the second word line 30 are represented by different textures. In the actual production and manufacturing process of the memory, the first gate 122 can be made of the same material as the first word line 20 and formed at the same time, and the second gate 132 can be made of the same material as the second word line 30 and formed at the same time.

[0076] Alternatively, as Figure 2 As shown, in one embodiment of the present application, the first active structure 121 includes a first electrode 1211, a first channel portion 1212 and a second electrode 1213 that are sequentially away from the substrate 100 in a direction perpendicular to the substrate 100, the first electrode 1211 is electrically connected to the first capacitor 11, and the second electrode 1213 is electrically connected to the bit line 40.

[0077] In the embodiment of this application, Figure 2 As shown, the first active structure 121 includes a first electrode 1211 , a first channel portion 1212 and a second electrode 1213 , which are stacked in sequence along a direction perpendicular to and away from the substrate 100 .

[0078] In the embodiment of the present application, the portion of the first active structure 121 that can be affected by the electric field applied by the first gate 122 is the first channel portion 1212 .

[0079] In the embodiment of the present application, the first electrode 1211 is electrically connected to the first capacitor 11 , and the second electrode 1213 is electrically connected to the bit line 40 , so that by controlling the electric field generated by the first gate 122 , operations such as data reading and data writing of the first capacitor 11 can be achieved.

[0080] Optionally, the first electrode 1211 is one of a source electrode and a drain electrode, and the second electrode 1213 is the other of the source electrode and the drain electrode.

[0081] It should be noted that, in the embodiment of the present application, the first electrode 1211, the first channel portion 1212, and the second electrode 1213 are made of the same material, that is, during the manufacturing process of the memory, an integrated first active structure 121 can be formed. Figure 2 The dashed line in the figure indicates the boundary between the first electrode 1211, the first channel portion 1212 and the second electrode 1213. The first active structure 121 does not exist in the actual product. Figure 2 The dashed line is shown.

[0082] Optionally, in the embodiment of the present application, materials of the first electrode 1211 , the first channel portion 1212 , and the second electrode 1213 all include metal oxide semiconductor materials.

[0083] Optionally, the metal oxide semiconductor material includes IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), IWO (Indium Wolfram Oxide), ZnO x (ZnO), InOx (Indium oxide), In2O3 (Indium trioxide), InWO (Indium tungsten oxide), SnO2 (Tin dioxide), TiO x (titanium oxide), InSnO x (Indium Tin Oxide), Zn x O y N z (nitrogen-doped zinc oxide), Mg x Zn y O z (MgO-Zn), In x Zn y O z (Indium zinc oxide), In x Ga y Zn z O a (Indium Gallium Zinc Oxide), Zr x In y Zn z O a (zirconium zinc oxide), Hf x In y Zn z O a (Hafnium Indium Zinc Oxide), Sn x In y Zn z O a (tin indium zinc oxide), Al x ZnO (aluminum zinc oxide), Al x Sn y In z Zn a O d (aluminum tin indium zinc oxide), Si x In y Zn z O a (silicon indium zinc oxide), Zn x Sn y O z (zinc tin oxide), Al x Zn y Sn z O a (aluminum zinc tin oxide), Ga x Zn y Sn z O a (Gallium Zinc Tin Oxide), Zr x Zn y Sn z O a (zirconium zinc tin oxide) and InGaSiO (indium gallium silicon oxide), etc.

[0084] It should be noted that in the chemical formulas of the above materials, the subscripts x, y, z, a, and d represent the numbers of the corresponding atoms.

[0085] In one embodiment of the present application, the second active structure 131 includes a third electrode, a second channel portion, and a fourth electrode sequentially away from the substrate 100 in a direction perpendicular to the substrate 100 . The third electrode is electrically connected to the bit line 40 , and the fourth electrode is electrically connected to the second capacitor 14 .

[0086] In the embodiment of the present application, the structure of the second active structure 131 can refer to Figure 2 The first active structure 121 shown and the above description of the first active structure 121 are not repeated here.

[0087] In the embodiment of the present application, the first electrode 1211, the first channel portion 1212 and the second electrode 1213 are made of the same material, and the third electrode, the second channel portion and the fourth electrode are made of the same material, that is, the first transistor 12 and the second transistor 13 are both junction-less field-effect transistors, thereby reducing the manufacturing difficulty of the first transistor 12 and the second transistor 13, helping to improve the manufacturing rate of the first transistor 12 and the second transistor 13, and helping to reduce the manufacturing cost of the memory.

[0088] Optionally, in one embodiment of the present application, the first gate 122 is disposed around the outside of the first channel portion 1212 and is insulated from the first channel portion 1212 .

[0089] In the embodiment of this application, Figure 1 and Figure 2 As shown, the first gate 122 is disposed around the outside of the first channel portion 1212 so that the electric field generated by the first gate 122 can affect the first channel portion 1212 to control the turn-on of the first transistor 12 .

[0090] In the embodiment of the present application, by setting the first gate 122 to surround the outside of the first channel portion 1212, it helps to improve the gate control capability of the first gate 122, can increase the turn-on rate of the first transistor 12, and is beneficial to ensuring the threshold current of the first transistor 12, which helps to ensure the performance of the memory.

[0091] Alternatively, as Figure 1 As shown, a third dielectric structure 123 is provided between the first gate 122 and the first channel portion 1212 . The third dielectric structure 123 is disposed around the outside of the first channel portion 1212 , and the first gate 122 is disposed around the outside of the third dielectric structure 123 , so that the first gate 122 is insulated from the first channel portion 1212 .

[0092] Alternatively, as Figure 1As shown, the third dielectric structure 123 is disposed around the outside of the first active structure 121, and the first gate 122 is disposed around the outside of a portion of the third dielectric structure 123, thereby simplifying the manufacturing process of the third dielectric structure 123, helping to reduce the manufacturing difficulty of the third dielectric structure 123, and further helping to reduce the manufacturing difficulty and manufacturing cost of the memory.

[0093] In one embodiment of the present application, the second gate 132 is disposed around the outside of the second channel portion and is insulated from the second channel portion.

[0094] Alternatively, as Figure 1 As shown, the second gate 132 is arranged around the outside of a portion of the second active structure 131. By arranging the second gate 132 around the outside of the second channel portion in the second active structure 131, it helps to improve the gate control capability of the second gate 132, can increase the turn-on rate of the second transistor 13, and is beneficial to ensuring the threshold current of the second transistor 13, which helps to ensure the performance of the memory.

[0095] Alternatively, as Figure 1 As shown, a fourth dielectric structure 133 is provided between the second gate 132 and the second active structure 131 so as to insulate the second gate 132 from the second channel portion.

[0096] Alternatively, as Figure 1 As shown, the fourth dielectric structure 133 is disposed around the outside of the second active structure 131, and the second gate 132 is disposed around the outside of a portion of the fourth dielectric structure 133, thereby simplifying the manufacturing process of the fourth dielectric structure 133, helping to reduce the manufacturing difficulty of the fourth dielectric structure 133, and further helping to reduce the manufacturing difficulty and manufacturing cost of the memory.

[0097] Optionally, in the embodiment of the present application, the third dielectric structure 123 and the fourth dielectric structure 133 both include dielectric materials with a high K value. Optionally, the materials of the third dielectric structure 123 and the fourth dielectric structure 133 may include HfO (hafnium oxide).

[0098] Alternatively, as Figure 1 As shown, in one embodiment of the present application, the first active structure 121 and the second active structure 131 are both annular; the space formed by the peripheral wall of the first active structure 121 is filled with gas or the first dielectric structure 124; the space formed by the peripheral wall of the second active structure 131 is filled with gas or the second dielectric structure 134.

[0099] In the embodiment of this application, Figure 1 and Figure 2 As shown, the first active structure 121 is annular, and the peripheral wall of the annular first active structure 121 encloses a receiving space.

[0100] Optionally, the accommodating space may not be filled with a dielectric material, so that the first active structure 121 encloses an air gap.

[0101] Optionally, to facilitate subsequent manufacturing processes, a dielectric material may be used to fill the accommodation space, forming a first dielectric structure 124 surrounded by the first active structure 121. Optionally, the material of the first dielectric structure 124 includes SOD (Spin Oxide Dielectric), which has good fluidity and helps to completely fill the accommodation space.

[0102] In the embodiment of this application, Figure 1 As shown, the second active structure 131 is also annular, and the peripheral wall of the annular second active structure 131 forms an accommodating space.

[0103] Optionally, the accommodating space may not be filled with a dielectric material, so that the second active structure 131 encloses an air gap.

[0104] Optionally, in order to facilitate subsequent manufacturing processes, a dielectric material may be used to fill the accommodating space to form a second dielectric structure 134 surrounded by the second active structure 131. Optionally, the material of the second dielectric structure 134 includes SOD.

[0105] In the embodiment of the present application, by setting the first active structure 121 and the second active structure 131 to be ring-shaped, the first active structure 121 and the second active structure 131 are hollow structures, which helps to suppress or even eliminate FBE (Floating Body Effect) and helps to ensure the performance of the memory.

[0106] Optionally, in one embodiment of the present application, the first electrode 1211 and the third electrode both include a ring portion and a bottom plate portion connected to the ring portion; the bottom plate portion 1202 of the first electrode 1211 is connected to the first capacitor 11, and the bottom plate portion of the third electrode is connected to the bit line 40.

[0107] In the embodiment of this application, Figure 1 and Figure 2As shown, the first electrode 1211 includes a ring portion 1201 and a bottom plate portion 1202. One end of the ring portion 1201 is connected to the first channel portion 1212, and the other end is connected to the bottom plate portion 1202. Along a direction perpendicular to the substrate 100 and away from the substrate 100, the bottom plate portion 1202, the ring portion 1201, the first channel portion 1212 and the second electrode 1213 are stacked in sequence on one side of the first capacitor 11, so that the first active structure 121 forms a blind hole shape including a ring, which helps to reduce the manufacturing difficulty of the first active structure 121, is beneficial to improving the manufacturing rate of the first active structure 121, and thus helps to reduce the manufacturing cost of the memory.

[0108] At the same time, the bottom plate portion 1202 of the first electrode 1211 is connected to the first capacitor 11 , thereby increasing the contact area between the first electrode 1211 and the first capacitor 11 and helping to reduce the contact resistance between the first electrode 1211 and the first capacitor 11 .

[0109] In the embodiment of this application, Figure 1 As shown, the third electrode includes a ring portion and a bottom plate portion, one end of the ring portion is connected to the second channel portion, and the other end is connected to the bottom plate portion. Along a direction perpendicular to the substrate 100 and away from the substrate 100, the bottom plate portion, the ring portion, the second channel portion and the fourth electrode are stacked in sequence on one side of the bit line 40, so that the second active structure 131 forms a blind hole shape including a ring, which helps to reduce the manufacturing difficulty of the second active structure 131 and is beneficial to improving the manufacturing rate of the second active structure 131, thereby helping to reduce the manufacturing cost of the memory.

[0110] At the same time, the bottom plate portion of the third electrode is connected to the bit line 40 , thereby increasing the contact area between the third electrode and the bit line 40 , and helping to reduce the contact resistance between the third electrode and the bit line 40 .

[0111] Optionally, the accommodating space formed by the peripheral walls of the first active structure 121 and the second active structure 131 may be a sealed space, that is, the second electrode 1213 of the first active structure 121 includes a top plate portion for achieving sealing, and the fourth electrode of the second active structure 131 includes a top plate portion for achieving sealing.

[0112] Alternatively, as in 3 and Figure 4 As shown, in one embodiment of the present application, along a direction perpendicular to the substrate 100 , the orthographic projections of the first capacitor 11 , the first transistor 12 , the second transistor 13 , and the second capacitor 14 on the substrate 100 coincide with each other.

[0113] In the embodiment of this application, Figure 3 and Figure 4As shown, in each memory cell 10, the orthographic projections of the first capacitor 11, the first transistor 12, the second transistor 13, and the second capacitor 14 on the substrate 100 overlap, thereby reducing the area of ​​the orthographic projection of the memory cell 10 on the substrate 100, reducing the area occupied by the memory cell 10, and increasing the number of memory cells 10 arranged in the memory, which helps to improve the storage density of the memory.

[0114] Alternatively, as Figure 3 and Figure 4 As shown, a plurality of memory cells 10 are arranged in an array, the first word lines 20 and the second word lines 30 extend in the same direction, and the bit lines 40 extend in a direction perpendicular to the direction of the first word lines 20 and the second word lines 30 .

[0115] It should be noted that, in order to facilitate readers to intuitively understand the arrangement of the memory cell 10, the first word line 20, the second word line 30 and the bit line 40, as shown in FIG. Figure 3 As shown, each dielectric film layer in the memory is subjected to perspective processing.

[0116] Alternatively, as in 3 and Figure 4 As shown, in one embodiment of the present application, along a direction perpendicular to the substrate 100, the orthographic projections of the first word line 20 and the bit line 40 on the substrate 100 include a first overlapping area, the orthographic projections of the second word line 30 and the bit line 40 on the substrate 100 include a second overlapping area, and the first overlapping area and the second overlapping area overlap; the orthographic projections of the first capacitor 11, the first transistor 12, the second transistor 13 and the second capacitor 14 on the substrate 100 are all located in the first overlapping area and the second overlapping area.

[0117] In the embodiment of the present application, since the extension direction of the bit line 40 is perpendicular to the extension direction of the first word line 20, the orthographic projections of the first word line 20 and the bit line 40 on the substrate 100 include a first overlapping area, and since the extension direction of the bit line 40 is perpendicular to the extension direction of the second word line 30, the orthographic projections of the second word line 30 and the bit line 40 on the substrate 100 include a second overlapping area, as shown in FIG. Figure 3 and Figure 4 As shown, the orthographic projection of the first word line 20 on the substrate 100 and the orthographic projection of the second word line 30 on the substrate 100 at least partially overlap, so that the first overlapping region and the second overlapping region overlap.

[0118] like Figure 3 and Figure 4As shown, the orthographic projections of the first capacitor 11, the first transistor 12, the second transistor 13 and the second capacitor 14 on the substrate 100 are all located in the first overlapping area and the second overlapping area, that is, the orthographic projections of each memory cell 10 on the substrate 100 are all located in the first overlapping area and the second overlapping area, so that the intersection of the first word line 20 or the second word line 30 and the bit line 40 defines the position of the memory cell 10, which can further reduce the area occupied by the memory cell 10, can increase the number of memory cells 10 arranged in the memory, and help to further improve the storage density of the memory.

[0119] Optionally, in the embodiment of the present application, the first capacitor 11 and the second capacitor 14 are cylindrical capacitors, each including a first cylindrical electrode, a second cylindrical electrode, and a dielectric layer located between the first cylindrical electrode and the second cylindrical electrode.

[0120] Alternatively, as Figure 3 and Figure 4 As shown, in one embodiment of the present application, the substrate 100 includes an array area 110 and a peripheral area 111, and the peripheral area 111 is arranged outside the array area 110; the array area 110 is provided with a memory array, and the peripheral area 111 is provided with a peripheral circuit 50 electrically connected to the memory array, and the memory array includes: a memory cell 10, a first word line 20, a second word line 30 and a bit line 40.

[0121] Alternatively, as Figure 3 and Figure 4 As shown, in the embodiment of the present application, the substrate 100 includes an array region 110 and a peripheral region 111 . Optionally, the peripheral region 111 is disposed outside the array region 110 , and the peripheral region 111 surrounds the array region 110 .

[0122] It should be noted that, in order to facilitate readers to intuitively understand the relationship between the array area 110 and the surrounding area 111, as shown in FIG. Figure 3 As shown, the boundary between the array area 110 and the peripheral area 111 is represented by a dotted line, which does not exist in the actual product.

[0123] Alternatively, as Figure 3 and Figure 4 As shown, a memory array including memory cells 10 , first word lines 20 , second word lines 30 and bit lines 40 is disposed in an array region 110 , and a peripheral circuit 50 is disposed in a peripheral region 111 and electrically connected to the memory array.

[0124] Optionally, the peripheral circuit 50 includes a driving circuit, an address selection circuit, a voltage control circuit, a sense amplifier, a row decoder, a column decoder, and the like.

[0125] It should be noted that, in order to facilitate readers to intuitively understand the peripheral circuit 50, as shown in FIG. Figure 4 As shown, the peripheral circuit 50 is framed by a dotted line, but there is no dotted line in the actual product.

[0126] Alternatively, as Figure 4 As shown, the peripheral circuit 50 includes a first conductive structure 51, a second conductive structure 52, a third conductive structure 53 and a fourth conductive structure 54. Optionally, the fourth conductive structure 54 is a PAD (pad) of the peripheral circuit 50, and the third conductive structure 54 can be connected to other components.

[0127] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: any memory provided by the above embodiments.

[0128] In the embodiments of the present application, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0129] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0130] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any of the memories provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0131] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices may include any memory provided in the above embodiments.

[0132] Based on the same inventive concept, the embodiment of the present application provides a method for manufacturing a memory, and the flowchart of the method for manufacturing the memory is as follows: Figure 5 As shown, the method includes steps S501 to S509.

[0133] S501 , forming a first capacitor 11 on one side of the substrate 100 .

[0134] S502 , forming a first dielectric layer 102 , a first word line 20 , and a second dielectric layer 103 in a stacked manner on a side of the first capacitor 11 away from the substrate.

[0135] S503 , forming a first via hole in the second dielectric layer 103 , the first word line 20 and the first dielectric layer 102 based on a patterning process, such that at least a portion of the first capacitor 11 is exposed.

[0136] S504 , forming a first active structure 121 insulated from the first word line 20 in the first via hole; the first active structure 121 includes a first electrode 1211 , a first channel portion 1212 , and a second electrode 1213 stacked from bottom to top.

[0137] S505 , forming a bit line 40 on a side of the second electrode 1213 away from the substrate 100 .

[0138] S506 , on a side of the bit line 40 away from the substrate 100 , the third dielectric layer 104 , the second word line 30 , and the fourth dielectric layer 105 are sequentially formed.

[0139] S507 , forming a second via hole in the fourth dielectric layer 105 , the second word line 30 and the third dielectric layer 104 based on a patterning process, so that at least a portion of the bit line 40 is exposed.

[0140] S508 , forming a second active structure 131 insulated from the second word line 30 in the second via hole; the second active structure 131 includes a third electrode, a second channel portion, and a fourth electrode stacked from bottom to top.

[0141] S509 , forming a second capacitor 14 on a side of the fourth electrode away from the substrate 100 .

[0142] In the manufacturing method of the memory provided in the embodiment of the present application, by setting the first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13 in the memory cell 10 to be electrically connected to the same bit line 40, the two transistors can share one bit line 40, thereby greatly reducing the number of bit lines 40 in the memory, reducing the design difficulty of the memory, reducing the manufacturing difficulty of the memory, and thus helping to reduce the manufacturing cost of the memory.

[0143] At the same time, the memory cell 10 can store two bits of data, which can reduce the area occupied by the memory cell 10, thereby helping to improve the storage density of the memory.

[0144] In order to facilitate readers to intuitively understand the memory manufacturing method provided by the embodiment of the present application and the advantages of the manufacturing method, the following will be combined with Figure 6-Figure 14 A memory manufacturing method is described in detail.

[0145] Optionally, in an embodiment of the present application, before forming the first capacitor 11 on one side of the substrate 100 in step S501 , the step further includes: forming some components of the peripheral circuit 50 of the memory in the peripheral area 111 of the substrate 100 based on a semiconductor process.

[0146] Optionally, the peripheral region 111 surrounds the array region 110 for forming a memory array.

[0147] Optionally, in the embodiment of the present application, before forming the first capacitor 11 , some components in the peripheral circuit 50 are formed in the peripheral region 111 of the substrate 100 based on a CMOS (Complementary Metal Oxide Semiconductor) manufacturing process.

[0148] Optionally, the CMOS manufacturing process includes: an STI (Shallow Trench Isolation) process, a well formation process, a gate dielectric layer formation process, a gate formation process, an LDD (Lightly Doped Drain) process, and an isolation wall formation process.

[0149] Optionally, in one embodiment of the present application, the step S501 of forming the first capacitor 11 on one side of the substrate 100 includes: forming a fifth dielectric layer 101 on one side of the substrate 100 based on a deposition process; forming a via hole in a portion of the fifth dielectric layer 101 located in the array region based on a patterning process, and forming the first capacitor 11 in the via hole, such as Figure 6 shown.

[0150] Optionally, the material of the fifth dielectric layer 101 includes silicon oxide, and the depth of the via hole in the fifth dielectric layer 101 is less than the thickness of the fifth dielectric layer 101 .

[0151] Optionally, forming the first capacitor 11 in the via hole includes: depositing TiN (titanium nitride) to form a first columnar electrode, depositing a dielectric material to form a dielectric layer of the first capacitor 11 , and depositing TiN to form a second columnar electrode.

[0152] Optionally, the dielectric layer of the first capacitor 11 includes a multilayer stacked structure formed by at least one layer of ZrO2 (zirconium dioxide), at least one layer of Al2O3 (aluminum oxide), and at least one layer of ZrO2 (zirconium dioxide), and the multilayer stacked structure is referred to as ZAZ.

[0153] Optionally, in one embodiment of the present application, the above step S502 includes: forming a first dielectric layer 102 on a side of the first capacitor 11 away from the substrate, forming a first word line 20 on a side of the first dielectric layer 102 away from the substrate 100, and forming a second dielectric layer 103 covering the first word line 20.

[0154] Alternatively, as Figure 7 As shown, a first dielectric layer 102 is formed on a side of the first capacitor 11 away from the substrate based on a deposition process, so that the first dielectric layer 102 covers the first capacitor 11 .

[0155] Alternatively, as Figure 8 and Figure 9As shown, a plurality of first word lines 20 arranged in an array are formed on a side of the first dielectric layer 102 away from the substrate 100 based on a deposition process and a patterning process. Optionally, the extension direction of the first word lines 20 is parallel to the first direction.

[0156] Optionally, a metal layer is formed on a side of the first dielectric layer 102 away from the substrate 100 based on a deposition process, and the metal layer is processed by a patterning process to form a plurality of first word lines 20 .

[0157] Alternatively, as Figure 10 As shown, a second dielectric layer 103 is formed based on a deposition process, and the second dielectric layer 103 covers the first word line 20 and the area of ​​the first dielectric layer 102 not covered by the first word line 20 .

[0158] Optionally, during the process of forming the second dielectric layer 103 , a CMP (Chemical Mechanical Polishing) process may be used for planarization to ensure the flatness of the surface of the second dielectric layer 103 that is finally formed.

[0159] Optionally, in one embodiment of the present application, the above step S503 includes: forming a first via hole penetrating the second dielectric layer 103 , the first word line 20 and the first dielectric layer 102 based on a patterning process, so that at least a portion of the second columnar electrode of the first capacitor 11 is exposed.

[0160] Optionally, in one embodiment of the present application, the above step S504 forms a first active structure 121 insulated from the first word line 20 in the first via hole; the first active structure 121 includes a first electrode 1211, a first channel portion 1212, and a second electrode 1213 stacked from bottom to top, including: forming a third dielectric structure 123 covering the inner sidewall of the first via hole, the third dielectric structure 123 enclosing a third via hole; and forming a hole-shaped first active structure 121 in the third via hole.

[0161] Optionally, a sixth dielectric layer 107 covering the inner sidewall of the first via hole is formed based on a deposition process and a patterning process, such as Figure 10 As shown, the via hole formed by the sixth dielectric layer 107 exposes a portion of the first capacitor 11 , so as to facilitate the connection between the subsequently formed first active structure 123 and the first capacitor 11 .

[0162] Optionally, an active layer 108 is further formed on the inner sidewall of the sixth dielectric layer 107 so that the active layer 108 is connected to the first capacitor 11 ; a seventh dielectric layer 109 is formed on the inner sidewall of the active layer 108 so that the seventh dielectric layer 109 fills the via hole formed by the inner sidewall of the active layer 108 .

[0163] Optionally, after forming the sixth dielectric layer 107, the active layer 108, and the seventh dielectric layer 109, the method further includes: removing a portion of the sixth dielectric layer 107, a portion of the active layer 108, and a portion of the seventh dielectric layer 109 based on a CMP process to form a third dielectric structure 123, a first active structure 121, and a first dielectric structure 124, respectively, so that the upper surfaces of the third dielectric structure 123, the first active structure 121, and the first dielectric structure 124 are coplanar, as shown in FIG. Figure 11 and Figure 12 shown.

[0164] It should be noted that Figure 11 The second dielectric layer 103 is rendered transparent.

[0165] It is understood by those skilled in the art that since the material of the first gate 122 is the same as that of the first word line 20, part of the first word line 20 can be used as the first gate 122 of the first transistor 12. Figure 12 As shown, the first gate 122 is a portion of the first word line 20. Similarly, in subsequent manufacturing processes, a portion of the second word line 30 can be used as the second gate 132 of the second transistor 13.

[0166] Optionally, after forming the sixth dielectric layer 107 and before forming the first active structure 121, the method further includes: removing a portion of the sixth dielectric layer 107 using a CMP process to form a third dielectric structure 123. Optionally, in one embodiment of the present application, the above steps of forming the hole-shaped first active structure 121 in the third via hole include: forming an integrated first electrode 1211, a first channel portion 1212, and a second electrode 1213 on the inner sidewall of the third via hole using a deposition process; the first electrode 1211 is in the shape of a blind hole, and the first channel portion 1212 and the second electrode 1213 are both ring-shaped.

[0167] Optionally, in one embodiment of the present application, the above step S505 includes: forming a bit line 40 on a side of the second electrode 1213 away from the substrate 100 based on a deposition process and a patterning process, such as Figure 13 and Figure 14 shown.

[0168] Optionally, a metal layer is formed on a side of the second electrode 1213 and the second dielectric layer 103 away from the substrate 100 using a deposition process, and the metal layer is patterned to form a plurality of bit lines 40 arranged in an array. Optionally, the bit lines 40 extend in a direction parallel to the second direction, that is, the bit lines 40 extend in a direction perpendicular to the first word lines 20.

[0169] It should be noted that Figure 13 The second dielectric layer 103 is rendered transparent.

[0170] Optionally, in one embodiment of the present application, the above step S506 includes: forming a third dielectric layer 104 covering the bit line 40 based on a deposition process, forming a plurality of second word lines 30 arranged in an array on one side of the third dielectric layer 104, and forming a fourth dielectric layer 105 covering the second word lines 30, such as Figure 4 shown.

[0171] Optionally, a third dielectric layer 104 is formed on a side of the bit line 40 away from the substrate 100 based on a deposition process, so that the third dielectric layer 104 covers the bit line 40 .

[0172] Optionally, a metal layer is formed on a side of the third dielectric layer 104 away from the substrate 100 through a deposition process, and the metal layer is processed through a patterning process to form a plurality of second word lines 30. Optionally, the second word lines 30 extend in a direction parallel to the first direction, that is, the second word lines 30 extend in a direction parallel to the first word lines 20 and perpendicular to the bit lines 40.

[0173] Optionally, a fourth dielectric layer 105 is formed based on a deposition process, and the fourth dielectric layer 105 covers the second word line 30 and an area of ​​the third dielectric layer 104 not covered by the second word line 30 .

[0174] Optionally, during the process of forming the fourth dielectric layer 105 , a CMP process may be used for planarization to ensure the flatness of the surface of the fourth dielectric layer 105 finally formed.

[0175] Optionally, in an embodiment of the present application, the step S507 includes: forming a second via hole penetrating the fourth dielectric layer 105 , the second word line 30 , and the third dielectric layer 104 based on a patterning process, so that at least a portion of the bit line 40 is exposed.

[0176] Optionally, in one embodiment of the present application, the above step S508 forms a second active structure 131 insulated from the second word line 30 in the second via hole; the second active structure 131 includes a third electrode, a second channel portion, and a fourth electrode stacked from bottom to top, including: forming a fourth dielectric structure 133 covering the inner sidewall of the second via hole, the fourth dielectric structure 133 enclosing a fourth via hole; and forming a hole-shaped second active structure 131 in the fourth via hole.

[0177] Optionally, a second active structure 131 in the shape of a hole is formed in the fourth via hole, including: an integrated third electrode, a second channel portion and a fourth electrode formed on the inner side wall of the fourth via hole based on a deposition process; the third electrode is in the shape of a blind hole, and the second channel portion and the fourth electrode are both annular.

[0178] Optionally, specific process steps for forming the fourth dielectric structure 133 and the second active structure 131 may refer to the process steps for forming the third dielectric structure 123 and the first active structure 121 , and will not be repeated here.

[0179] Optionally, in one embodiment of the present application, the above-mentioned step S509 includes: forming an eighth dielectric layer 106 on a side of the fourth electrode away from the substrate 100 based on a deposition process; forming a via hole in the eighth dielectric layer 106 based on a patterning process, so that a portion of the second active structure 131 in the second transistor 13 is exposed; and forming a second capacitor 14 located in the via hole based on a deposition process.

[0180] Optionally, the manufacturing process and manufacturing materials of the second capacitor 14 may refer to the description of the first capacitor 11 , which will not be repeated here.

[0181] Optionally, after forming the second capacitor 14 , a dielectric material may be deposited to cover the second capacitor 14 to prevent a short circuit between adjacent memory cells 10 .

[0182] Optionally, in an embodiment of the present application, during the process of forming the first word line 20 in the upper step S502, the first conductive structure 51 of the peripheral circuit 50 can be formed simultaneously to form some components of the peripheral circuit 50, or to achieve electrical connection between some components in the peripheral circuit 50.

[0183] Optionally, in an embodiment of the present application, during the process of forming the bit line 40 in the upper step S505, the second conductive structure 52 of the peripheral circuit 50 can be formed simultaneously to form some components of the peripheral circuit 50, or to achieve electrical connection between some components in the peripheral circuit 50.

[0184] Optionally, in an embodiment of the present application, during the process of forming the second word line 30 in the upper step S507, the third conductive structure 53 of the peripheral circuit 50 can be formed simultaneously to form some components of the peripheral circuit 50, or to achieve electrical connection between some components in the peripheral circuit 50.

[0185] In the embodiment of the present application, by providing a first conductive structure 51 that simultaneously forms the first word line 20 and the peripheral circuit 50, a second conductive structure 52 that simultaneously forms the bit line 40 and the peripheral circuit 50, and / or a third conductive structure 53 that simultaneously forms the second word line 30 and the peripheral circuit 50, the manufacturing efficiency of the memory can be improved, which helps to reduce the manufacturing cost of the memory.

[0186] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0187] In the memory provided in the embodiment of the present application, by setting the first active structure 121 of the first transistor 12 and the second active structure 131 of the second transistor 13 in the memory cell 10 to be electrically connected to the same bit line 40, the two transistors can share one bit line 40, thereby greatly reducing the number of bit lines 40 in the memory, reducing the design difficulty of the memory, reducing the manufacturing difficulty of the memory, and thus helping to reduce the manufacturing cost of the memory.

[0188] Furthermore, in the memory provided in the embodiment of the present application, the memory cell 10 includes a first capacitor 11 and a second capacitor 14, enabling the memory cell 10 to store two bits of data. Furthermore, the first capacitor 11, the first transistor 12, the second transistor 13, and the second capacitor 14 of the memory cell 10 are sequentially stacked on one side of the substrate 100, which can reduce the area occupied by the memory cell 10, thereby helping to improve the storage density of the memory.

[0189] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0190] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0191] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0192] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0193] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0194] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A memory, characterized in that: include: at least one memory cell, at least one first word line, at least one second word line, and at least one bit line; The memory cell comprises a first capacitor, a first transistor, a second transistor and a second capacitor which are sequentially stacked on one side of a substrate, the first capacitor being electrically connected to the first transistor, and the second capacitor being electrically connected to the second transistor; the bit line being arranged between the first transistor and the second transistor in a direction perpendicular to the substrate; the first active structure of the first transistor and the second active structure of the second transistor being electrically connected to the bit line, the first gate of the first transistor being electrically connected to the first word line, and the second gate of the second transistor being electrically connected to the second word line.

2. The memory according to claim 1, characterized in that: The first active structure includes a first electrode, a first channel portion, and a second electrode which are sequentially away from the substrate in a direction perpendicular to the substrate, the first electrode is electrically connected to the first capacitor, and the second electrode is electrically connected to the bit line; The second active structure includes a third electrode, a second channel portion, and a fourth electrode which are sequentially away from the substrate in a direction perpendicular to the substrate. The third electrode is electrically connected to the bit line, and the fourth electrode is electrically connected to the second capacitor.

3. The memory according to claim 2, characterized in that: The first gate is disposed around the outer side of the first channel portion and is insulated from the first channel portion; The second gate is disposed around the outer side of the second channel portion and is insulated from the second channel portion.

4. The memory according to claim 2, characterized in that: The first active structure and the second active structure are both ring-shaped; The space enclosed by the peripheral wall of the first active structure is filled with gas or a first dielectric structure; The space enclosed by the peripheral wall of the second active structure is filled with gas or a second medium structure.

5. The memory according to claim 3 or 4, characterized in that: The first electrode and the third electrode each include an annular portion and a bottom plate portion connected to the annular portion; A bottom plate portion of the first electrode is connected to the first capacitor, and a bottom plate portion of the third electrode is connected to the bit line.

6. The memory according to claim 1, characterized in that: In a direction perpendicular to the substrate, the first capacitor, the first transistor, the second transistor and the second capacitor overlap in their orthographic projections on the substrate.

7. The memory according to claim 1, characterized in that: Along a direction perpendicular to the substrate, the orthographic projections of the first word line and the bit line on the substrate include a first overlapping area, the orthographic projections of the second word line and the bit line on the substrate include a second overlapping area, and the first overlapping area and the second overlapping area overlap; the orthographic projections of the first capacitor, the first transistor, the second transistor and the second capacitor on the substrate are all located in the first overlapping area and the second overlapping area.

8. The memory according to claim 1, characterized in that: The substrate comprises an array region and a peripheral region, wherein the peripheral region is arranged outside the array region; The array area is provided with a memory array, the peripheral area is provided with a peripheral circuit electrically connected to the memory array, and the memory array includes: the memory cell, the first word line, the second word line and the bit line.

9. A method for manufacturing a memory, characterized in that: include: forming a first capacitor on one side of the substrate; A first dielectric layer, a first word line, and a second dielectric layer are sequentially formed in a stacked manner on a side of the first capacitor away from the substrate; forming a first via hole in the second dielectric layer, the first word line and the first dielectric layer based on a patterning process, so that at least a portion of the first capacitor is exposed; A first active structure insulated from the first word line is formed in the first via hole; the first active structure includes a first electrode, a first channel portion, and a second electrode stacked from bottom to top; forming a bit line on a side of the second electrode away from the substrate; A third dielectric layer, a second word line and a fourth dielectric layer are sequentially provided on a side of the bit line away from the substrate; Forming a second via hole in the fourth dielectric layer, the second word line and the third dielectric layer based on a patterning process, so that at least a portion of the bit line is exposed; forming a second active structure insulated from the second word line in the second via hole; the second active structure comprises a third electrode, a second channel portion and a fourth electrode stacked from bottom to top; A second capacitor is formed on a side of the fourth electrode away from the substrate.

10. The method for manufacturing a memory according to claim 9, characterized in that: A first active structure insulated from the first word line is formed in the first via hole, comprising: forming a third dielectric structure covering the inner sidewall of the first via hole, wherein the third dielectric structure encloses a third via hole; forming the first active structure in a hole shape in the third via hole; And, forming a second active structure insulated from the second word line in the second via hole, comprising: forming a fourth dielectric structure covering the inner sidewall of the second via hole, wherein the fourth dielectric structure encloses a fourth via hole; The second active structure having a hole shape is formed in the fourth via hole.

11. The method for manufacturing a memory according to claim 10, characterized in that: The first active structure in a hole shape is formed in the third via hole, comprising: The first electrode, the first channel portion and the second electrode are formed as an integrated whole on the inner side wall of the third via hole based on a deposition process; the first electrode is in a blind hole shape, and the first channel portion and the second electrode are both in a ring shape; And, forming the second active structure in a hole shape in the fourth via hole, comprising: The third electrode, the second channel portion and the fourth electrode are integrated on the inner side wall of the fourth via hole based on a deposition process; the third electrode is in a blind hole shape, and the second channel portion and the fourth electrode are both in a ring shape.

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