Three-dimensional semiconductor memory device and electronic system including same

Abstract

The disclosure relates to a three-dimensional (3D) semiconductor memory device and an electronic system including the same. An example 3D semiconductor memory device includes: a peripheral circuit structure on a peripheral substrate; a stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure; an n-doped pattern, wherein the n-doped pattern is located on the stacked structure; a vertical structure, the vertical structure passing through the stack structure and extending into the n-doped pattern; a p-doped pattern, the p-doped pattern being located on the n-doped pattern; and an undoped pattern, the undoped pattern being located between the n-doped pattern and the p-doped pattern. The p-doped pattern includes: a p-doped horizontal pattern, the p-doped horizontal pattern being located on the undoped pattern; and a p-doped vertical pattern, the p-doped vertical pattern extending through the undoped pattern and the n-doped pattern and being in contact with the vertical structure.

Description

Technical Field

[0001] The present application relates to a three-dimensional semiconductor memory device and an electronic system including the same. Background Art

[0002] Semiconductor devices have been integrated to meet the performance level and manufacturing cost required by customers. The integration of two-dimensional or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, so that it is affected by the technical level used to form fine patterns. However, the extremely expensive processing equipment required to improve the fineness of the pattern may have practical limitations on improving the integration of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the invention

[0003] The present disclosure relates to a three-dimensional semiconductor memory device, including a three-dimensional semiconductor memory device with improved data erasing speed and an electronic system including the same. The three-dimensional semiconductor memory device can provide improved electrical characteristics and increased reliability.

[0004] The subject matter of the present disclosure is not limited to the above-mentioned contents, and other subject matters will be understood by those skilled in the art from the following description.

[0005] In general, according to some aspects, a three-dimensional semiconductor memory device includes: a peripheral circuit structure, the peripheral circuit structure is located on a peripheral substrate; a stacked structure, the stacked structure includes a plurality of gate electrodes stacked on the peripheral circuit structure; an n-doped pattern, the n-doped pattern is located on the stacked structure; a vertical structure, the vertical structure penetrates the stacked structure and extends into the n-doped pattern; a p-doped pattern, the p-doped pattern is located on the n-doped pattern; and an undoped pattern, the undoped pattern is located between the n-doped pattern and the p-doped pattern. The p-doped pattern includes: a p-doped horizontal pattern, the p-doped horizontal pattern is located on the undoped pattern; and a p-doped vertical pattern, the p-doped vertical pattern penetrates the undoped pattern and the n-doped pattern and contacts the vertical structure.

[0006] Generally, according to some aspects, a three-dimensional semiconductor memory device includes: a peripheral circuit structure, which is located on a peripheral substrate; a stacked structure, which includes a plurality of gate electrodes stacked on the peripheral circuit structure; an n-doped pattern, which is located on the stacked structure; a vertical structure, which penetrates the stacked structure and extends into the n-doped pattern; an undoped pattern, which is located on the n-doped pattern; a p-doped pattern, which penetrates the undoped pattern and the n-doped pattern and contacts the vertical structure; a metal contact, which is electrically connected to the n-doped pattern; and a p-contact plug, which is electrically connected to the p-doped pattern.

[0007] In general, according to some aspects, an electronic system includes: a three-dimensional semiconductor memory device; and a controller, the controller being electrically connected to the three-dimensional semiconductor memory device through an input / output pad, the controller controlling the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes: a peripheral circuit structure, the peripheral circuit structure being located on a peripheral substrate; a stacked structure, the stacked structure including a plurality of gate electrodes stacked on the peripheral circuit structure; an n-doped pattern, the n-doped pattern being located on the stacked structure; a vertical structure, the vertical structure penetrating the stacked structure and extending into the n-doped pattern; a p-doped pattern, the p-doped pattern being located on the n-doped pattern; and an undoped pattern, the undoped pattern being located between the n-doped pattern and the p-doped pattern. The p-doped pattern includes: a p-doped horizontal pattern, the p-doped horizontal pattern being located on the undoped pattern; and a p-doped vertical pattern, the p-doped vertical pattern penetrating the undoped pattern and the n-doped pattern and contacting the vertical structure.

[0008] In general, according to some aspects, a three-dimensional semiconductor memory device includes: a peripheral circuit structure, the peripheral circuit structure is located on a peripheral substrate; a stacked structure, the stacked structure includes a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked on the peripheral circuit structure; a vertical structure, the vertical structure penetrates the stacked structure; and a p-doped pattern, the p-doped pattern covers the stacked structure. The vertical structure includes: a header structure, the header structure penetrates the uppermost gate electrode of the plurality of gate electrodes; and a through structure, the through structure is located below the header structure. The p-doped pattern protrudes into the header structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A simplified block diagram illustrating an example of an electronic system including a three-dimensional semiconductor memory device is illustrated.

[0010] Figure 2A simplified perspective view showing an example of an electronic system including a three-dimensional semiconductor memory device is illustrated.

[0011] Figure 3 and Figure 4 Shown along Figure 2 Example cross-sectional views taken along lines II' and II-II'.

[0012] Figure 5 A plan view illustrating an example of a three-dimensional semiconductor memory device is illustrated.

[0013] Figure 6 Shown along Figure 5 Example cross-sectional views taken along lines AA' and BB'.

[0014] Figure 7 , Figure 8 , Fig.10 and Fig.11 The diagram shows Figure 6 An example enlarged cross-sectional view of portion P2.

[0015] Fig.9A and Fig. 9B The diagram shows that Figure 5 Example enlarged plan views of portion P1 at first and second levels.

[0016] Fig.12 A plan view showing another example of a three-dimensional semiconductor memory device is illustrated.

[0017] Fig.13 Shown along Figure 5 Example cross-sectional views taken along lines AA' and BB'.

[0018] Figures 14 to 16 The diagram shows Fig.13 An example enlarged cross-sectional view of portion P3.

[0019] Figures 17 to 23 An example cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device is illustrated.

[0020] Figures 24 to 30 Other example cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device are illustrated. DETAILED DESCRIPTION

[0021] Some embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings to help clearly illustrate the present disclosure.

[0022] Figure 1 A simplified block diagram illustrating an example of an electronic system including a three-dimensional semiconductor memory device is illustrated.

[0023] refer to Figure 1 , the electronic system 1000 includes a three-dimensional semiconductor memory device 1100 and a controller 1200 electrically connected to the three-dimensional semiconductor memory device 1100. The electronic system 1000 may be a storage device including a single or multiple three-dimensional semiconductor memory devices 1100, or may be an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, each including a single or multiple three-dimensional semiconductor memory device 1100.

[0024] The three-dimensional semiconductor memory device 1100 may be a non-volatile memory device, such as a three-dimensional NAND flash memory device to be discussed below. The three-dimensional semiconductor memory device 1100 may include a first region 1100F and a second region 1100S located on the first region 1100F. Different from what is shown, the first region 1100F may be disposed on the side of the second region 1100S. The first region 1100F may be a peripheral circuit region including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second region 1100S may be a memory cell region including a bit line BL, a common source line CSL, a word line WL, a first line LL1 and LL2, a second line UL1 and UL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0025] In the second region 1100S, each of the memory cell strings CSTR may include first transistors LT1 and LT2 adjacent to a common source line CSL, second transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the first transistors LT1 and LT2 and the second transistors UT1 and UT2. The number of the first transistors LT1 and LT2 and the number of the second transistors UT1 and UT2 may be changed differently. The memory cell string CSTR may be positioned between the common source line CSL and the first region 1100F.

[0026] For example, the second transistors UT1 and UT2 may include string selection transistors, and the first transistors LT1 and LT2 may include ground selection transistors. The first lines LL1 and LL2 may be gate electrodes of the first transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the second lines UL1 and UL2 may be gate electrodes of the second transistors UT1 and UT2.

[0027] For example, the first transistors LT1 and LT2 may include a first erase control transistor and a ground selection transistor connected in series. For example, the second transistors UT1 and UT2 may include a string selection transistor and a second erase control transistor.

[0028] The common source line CSL, the first lines LL1 and LL2, the word lines WL, and the second lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first region 1100F toward the second region 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from the first region 1100F toward the second region 1100S.

[0029] In the first region 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The logic circuit 1130 may control the decoder circuit 1110 and the page buffer 1120. The three-dimensional semiconductor memory device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first region 1100F toward the second region 1100S.

[0030] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 includes a plurality of three-dimensional semiconductor memory devices 1100 , and in this case, the controller 1200 may control the plurality of three-dimensional semiconductor memory devices 1100 .

[0031] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on a specific firmware, and may control the NAND controller 1220 to access the three-dimensional semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the three-dimensional semiconductor memory device 1100. The NAND interface 1221 may be used to transmit therethrough a control command intended to control the three-dimensional semiconductor memory device 1100, data intended to be written on the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100, and / or data intended to be read from the memory cell transistors MCT of the three-dimensional semiconductor memory device 1100. The host interface 1230 may provide the electronic system 1000 with communication with an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the three-dimensional semiconductor memory device 1100 in response to the control command.

[0032] Figure 2 A simplified perspective view showing an example of an electronic system including a three-dimensional semiconductor memory device is illustrated.

[0033] refer to Figure 2, the electronic system 2000 includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 provided in the main board 2001.

[0034] The mainboard 2001 may include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins on the connector 2006 may be changed based on the communication interface between the electronic system 2000 and the external host. The electronic system 2000 may communicate with the external host through one of the interfaces such as a universal serial bus (USB), a fast peripheral component interconnect (PIC-Express), a serial advanced technology attachment (SATA), and an M-PHY (UFS) for universal flash storage. For example, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0035] The controller 2002 may write data to the semiconductor package 2003 , may read data from the semiconductor package 2003 , or may increase the operation speed of the electronic system 2000 .

[0036] The DRAM 2004 may be a buffer memory that reduces the difference in speed between an external host and the semiconductor package 2003 used as a data storage space. The DRAM 2004 included in the electronic system 2000 may be used as a buffer memory and may provide a space for temporary data storage in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0037] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 located on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 located on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0038] The package substrate 2100 may be an integrated circuit board including the package pads 2130. Each of the semiconductor chips 2200 may include an input / output pad 2210. Each of the input / output pads 2210 may correspond to Figure 1 The input / output pads 1101 are provided. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a memory channel structure 3220. Each of the semiconductor chips 2200 may include a three-dimensional semiconductor memory device to be discussed below.

[0039] The connection structure 2400 may be, for example, a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a wire bonding manner and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, on each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a silicon via instead of the connection structure 2400 or the bonding wire.

[0040] Unlike what is shown, the controller 2002 and the semiconductor chip 2200 may be included in a single package. The controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate from the main board 2001 and may be connected to each other through connection lines provided in the interposer substrate.

[0041] Figure 3 and Figure 4 Shown along Figure 2 Example cross-sectional views taken along lines II' and II-II'.

[0042] refer to Figure 3 and Figure 4 The semiconductor package 2003 includes a package substrate 2100 , a plurality of semiconductor chips 2200 located on the package substrate 2100 , and a mold layer 2500 covering the package substrate 2100 and the semiconductor chips 2200 .

[0043] The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed or exposed on the top surface of the package substrate body 2120, a lower pad 2125 disposed or exposed on the bottom surface of the package substrate body 2120, and an inner wire 2135 located in the package substrate body 2120 and electrically connecting the upper pad 2130 to the lower pad 2125. The package upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the conductive connector 2800. Figure 2 2005 in the main board 2001 of the electronic system 2000 depicted in FIG.

[0044] refer to Figure 2 and Figure 3 The semiconductor chips 2200 may have sidewalls that are not aligned with each other or may include other sidewalls that are aligned with each other. The semiconductor chips 2200 may be electrically connected to each other through the connection structure 2400 shaped like a bonding wire. The semiconductor chips 2200 may be configured to be substantially the same as each other.

[0045] Each of the semiconductor chips 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100. The second structure 4200 and the first structure 4100 may be bonded to each other in a wafer bonding manner.

[0046] The first structure 4100 may include a peripheral circuit line 4110 and a first bonding pad 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 located between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and a word line electrically connected to the memory channel structure 4220 and the gate stack structure 4210 (see Figure 1 For example, the second bonding pad 4250 may be electrically connected to the bit line 4240 of the memory channel structure 4220 and electrically connected to the word line (see Figure 1 The gate connection line 4235 of WL) is electrically connected to the memory channel structure 4220 and the word line (see Figure 1The first bonding pad 4150 of the first structure 4100 may be bonded to and in contact with the second bonding pad 4250 of the second structure 4200. The first bonding pad 4150 and the second bonding pad 4250 may have a contact portion including, for example, copper (Cu).

[0047] Each of the semiconductor chips 2200 may further include an input / output pad 2210 and an input / output connection line 4265 located below the input / output pad 2210. The input / output connection line 4265 may be electrically connected to one of the second bonding pads 4250 and one of the peripheral circuit lines 4110.

[0048] Figure 5 A plan view illustrating an example of a three-dimensional semiconductor memory device is illustrated. Figure 6 Shown along Figure 5 Example cross-sectional views taken along lines AA' and BB'. Figure 7 The diagram shows Figure 6 An example enlarged cross-sectional view of portion P2.

[0049] refer to Figures 5 to 7 The three-dimensional semiconductor memory device includes a peripheral circuit structure PS and a cell array structure CS stacked on a peripheral substrate 10. The peripheral substrate 10 may correspond to Figure 3 and Figure 4 The peripheral circuit structure PS may correspond to Figure 3 and Figure 4 The cell array structure CS may correspond to the first structure 4100. Figure 3 and Figure 4 The second structure 4200.

[0050] Since the cell array structure CS is bonded to the peripheral circuit structure PS, the cell capacity per unit area of ​​the three-dimensional semiconductor memory device can be increased. In addition, since the peripheral circuit structure PS and the cell array structure CS are independently manufactured and then bonded to each other, the peripheral transistor PTR described later can be prevented from being damaged due to various heat treatment processes, and therefore, the reliability and electrical characteristics of the three-dimensional semiconductor memory device can be improved.

[0051] The peripheral substrate 10 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The peripheral substrate 10 may have a top surface perpendicular to the first direction D1. The top surface of the peripheral substrate 10 may be parallel to the second direction D2 and the third direction D3 intersecting each other. The first direction D1, the second direction D2, and the third direction D3 may be directions orthogonal to each other. A device isolation layer 15 may be provided in the peripheral substrate 10. The device isolation layer 15 may define an active area of ​​the peripheral substrate 10.

[0052] The peripheral circuit structure PS may include a peripheral transistor PTR located on the peripheral substrate 10, a peripheral contact plug 31, a peripheral circuit line 33 electrically connected to the peripheral transistor PTR through the peripheral contact plug 31, a first bonding pad 35 electrically connected to the peripheral circuit line 33, and a first dielectric layer 30 surrounding the peripheral transistor PTR, the peripheral contact plug 31, the peripheral circuit line 33, and the first bonding pad 35. The peripheral transistor PTR may be disposed on the active region of the peripheral substrate 10. The peripheral circuit line 33 may correspond to Figure 3 and Figure 4 The peripheral circuit line 4110, and the first bonding pad 35 may correspond to Figure 3 and Figure 4 The first bonding pad 4150 is provided.

[0053] The peripheral contact plugs 31 may each have a width in the second direction D2 or the third direction D3, and, for example, the width may increase in the first direction D1. The peripheral contact plugs 31 and the peripheral circuit lines 33 may include a conductive material such as a metal.

[0054] The peripheral transistor PTR can constitute, for example, a decoder circuit (see Figure 1 1110), page buffer (see Figure 1 1120), and logic circuits (see Figure 1 1130). The peripheral circuit line 33 and the first bonding pad 35 may be electrically connected to the peripheral transistors PTR through the peripheral contact plug 31. Each of the peripheral transistors PTR may be, for example, an NMOS transistor or a PMOS transistor.

[0055] The first dielectric layer 30 may be disposed on the peripheral substrate 10. On the peripheral substrate 10, the first dielectric layer 30 may cover the peripheral transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33. The first dielectric layer 30 may include a plurality of dielectric layers constituting a multilayer structure. For example, the first dielectric layer 30 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. The first dielectric layer 30 may not cover the top surface of the first bonding pad 35. The first dielectric layer 30 may have a top surface that is substantially coplanar with the top surface of the first bonding pad 35.

[0056] The cell array structure CS may be disposed on the peripheral circuit structure PS. The cell array structure CS may include a second bonding pad 45, a bit line BL, and a stack structure ST. The second bonding pad 45, the bit line BL, and the stack structure ST may correspond to Figure 3 and Figure 4 The second bonding pad 4250, the bit line 4240 and the gate stack structure 4210.

[0057] The cell array structure CS may include a cell array region CAR and a cell array extension region EXR. The cell array extension region EXR may extend from the cell array region CAR in the second direction D2, the third direction D3, or a direction opposite thereto.

[0058] The second bonding pad 45 may contact the first bonding pad 35 of the peripheral circuit structure PS. The cell circuit line 43 may be electrically connected to the second bonding pad 45 through the cell contact plug 41. The second dielectric layer 40 may surround the cell contact plug 41, the cell circuit line 43, and the second bonding pad 45. The second dielectric layer 40, the cell contact plug 41, the cell circuit line 43, and the second bonding pad 45 may be disposed on the first dielectric layer 30.

[0059] The second dielectric layer 40 may include a plurality of dielectric layers constituting a multi-layer structure. For example, the second dielectric layer 40 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0060] The cell contact plugs 41 may each have a width in the second direction D2 and the third direction D3, and, for example, the width may decrease in the first direction D1. The cell contact plugs 41 and the cell circuit lines 43 may include a conductive material such as metal.

[0061] Some of the cell contact plugs 41 may connect the bit lines BL to the vertical structure VS discussed below. The bit lines BL may extend, for example, in the third direction D3 and may be spaced apart from each other in the second direction D2. The bit lines BL may include a conductive material such as a metal.

[0062] The second dielectric layer 40 may not cover the bottom surface of the second bonding pad 45. The second dielectric layer 40 may have a bottom surface that is substantially coplanar with the bottom surface of the second bonding pad 45. The bottom surface of the second bonding pad 45 may be in direct contact with the top surface of the first bonding pad 35 accordingly. The first bonding pad 35 and the second bonding pad 45 may include a metal, such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni) or tin (Sn). For example, the first bonding pad 35 and the second bonding pad 45 may include copper (Cu). The first bonding pad 35 and the second bonding pad 45 may constitute an integrated shape without an interface between them. Although the first bonding pad 35 and the second bonding pad 45 are shown as having side walls aligned with each other, the present disclosure is not limited thereto, and when viewed in a plan view, the first bonding pad 35 and the second bonding pad 45 may have side walls separated from each other.

[0063] The stacked structure ST and the third dielectric layer may be disposed on the second dielectric layer 40. The third dielectric layer may surround the stacked structure ST. The third dielectric layer may include a plurality of dielectric layers having a multilayer structure. The third dielectric layer may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. For example, the third dielectric layer may include a high density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS).

[0064] The stacking structure ST may be provided in plurality. For example, when viewed in a plan view, a plurality of stacking structures ST may extend in the second direction D2 and may be spaced apart from each other in the third direction D3. The separation grooves STR described later may separate the stacking structures ST from each other in the third direction D3. For ease of discussion, the following will focus on a single stacking structure ST, and the following description may also apply to other stacking structures ST.

[0065] The stack structure ST may include a first stack structure ST1 and a second stack structure ST2. The first stack structure ST1 may include first interlayer dielectric layers ILD1 and first gate electrodes GE1 that are alternately stacked, and the second stack structure ST2 may include second interlayer dielectric layers ILD2 and second gate electrodes GE2 that are alternately stacked (see Figure 6 ).

[0066] The first stacked structure ST1 may be disposed on the peripheral substrate 10, and the second stacked structure ST2 may be disposed between the first stacked structure ST1 and the peripheral substrate 10. For example, the second stacked structure ST2 may be disposed on the bottom surface of the lowest first interlayer dielectric layer in the first interlayer dielectric layers ILD1 of the first stacked structure ST1. The uppermost second interlayer dielectric layer in the second interlayer dielectric layers ILD2 of the second stacked structure ST2 may contact the lowermost first interlayer dielectric layer ILD1 of the first stacked structure ST1, but the present disclosure is not limited thereto. For example, a single interlayer dielectric layer may be disposed between the uppermost second gate electrode in the second gate electrode GE2 of the second stacked structure ST2 and the first gate electrode GE1 of the first stacked structure ST1.

[0067] The first gate electrode GE1 and the second gate electrode GE2 may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. For example, the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may include high-density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS).

[0068] Although not shown, the third stack structure may be further disposed between the second stack structure ST2 and the peripheral substrate 10. The third stack structure may have features that are the same as or similar to those of the first and second stack structures ST1 and ST2.

[0069] Although not shown, when viewed in a cross-sectional view, the stacked structure ST may have a stepped structure along the second direction D2 on the cell array extension region EXR. For example, the thickness of the stacked structure ST on the cell array extension region EXR in the first direction D1 may decrease as the distance from the cell array region CAR increases. The length of the first gate electrode GE1 and the second gate electrode GE2 in the second direction D2 may increase as the distance from the peripheral substrate 10 increases. The lowermost second gate electrode GE2 of the first gate electrode GE1 and the second gate electrode GE2 may have the smallest length, and the uppermost first gate electrode GE1 of the first gate electrode GE1 and the second gate electrode GE2 may have the largest length. When viewed in a plan view, the sidewalls of the first gate electrode GE1 and the second gate electrode GE2 may be spaced apart from each other at a specific interval in the second direction D2. Each of the first gate electrode GE1 and the second gate electrode GE2 may include a pad portion PAD or an end portion in the second direction D2. The pad portion PAD may be a section of each of the first gate electrode GE1 and the second gate electrode GE2 constituting the stepped structure of the stacked structure ST. The through-plug TP may extend in the first direction D1 and may be electrically connected to the pad portion PAD.

[0070] One or more first gate electrodes GE1 may be a ground selection line GSL. The ground selection line GSL may control the reference Figure 1 The ground selection transistor in the discussed first transistors LT1 and LT2. For example, the ground selection line GSL may be positioned at an upper portion of the stack structure ST.

[0071] The channel hole CH may penetrate the cell array structure CS on the cell array region CAR and the cell array extension region EXR. Each of the channel holes CH may pass through at least one selected from the stack structure ST and the third dielectric layer along the first direction D1. For example, each of the channel holes CH may include a first channel hole CH1 penetrating the first stack structure ST1 and a second channel hole CH2 penetrating the second stack structure ST2. Each of the first channel hole CH1 and the second channel hole CH2 may have a width in the second direction D2 and / or the third direction D3, and the width may decrease as the distance from the peripheral substrate 10 increases. The first channel hole CH1 and the second channel hole CH2 may be connected to each other and may have different diameters at their connected boundaries. For example, the diameter of the upper portion of the second channel hole CH2 may be smaller than the diameter of the lower portion of the second channel hole CH2. The first channel hole CH1 and the second channel hole CH2 may have a step difference at their connection boundary. However, the present disclosure is not limited thereto, and unlike what is shown, three or more channel holes having a step difference at each of two or more boundaries thereof may be provided. Alternatively, unlike what is shown, a channel hole having a flat sidewall without a step difference may be provided.

[0072] On the cell array region CAR, the vertical structure VS may pass through the stack structure ST in the first direction D1 and may fill the channel hole CH. The vertical structure VS may correspond to Figure 3 and Figure 4 The memory channel structure 4220 of the vertical structure VS may be provided. The channel pad CHP may be provided at a lower portion of the vertical structure VS. The vertical structure VS may be electrically connected to the cell contact plug 41 and the bit line BL through the channel pad CHP. On the cell array extension region EXR, the dummy vertical structure DVS may pass through at least one selected from the stacked structure ST and the third dielectric layer in the first direction D1, and may fill the channel hole CH. The vertical structure VS and the dummy vertical structure DVS may each have a bottom surface having, for example, a circular shape, an elliptical shape, or a bar shape.

[0073] Each of the vertical structures VS may include: a data storage pattern DSP that conformally covers the inner sidewall of the channel hole CH; a vertical semiconductor pattern VSP that conformally covers the inner sidewall of the data storage pattern DSP; and a buried dielectric pattern VI that is surrounded by the vertical semiconductor pattern VSP and the channel pad CHP and fills the inner space of the channel hole CH. The vertical semiconductor pattern VSP may be arranged between the data storage pattern DSP and the buried dielectric pattern VI. The vertical semiconductor pattern VSP may have a macaroni shape or a tubular shape with its top end closed. The data storage pattern DSP may have a tubular shape with its top end open. The vertical semiconductor pattern VSP may include, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. The channel pad CHP may include, for example, a semiconductor material doped with impurities or a conductive material.

[0074] The data storage pattern DSP may include a blocking dielectric layer BLK, a charge storage layer CIL, and a tunnel dielectric layer TIL sequentially stacked on the inner sidewall of the channel hole CH (see Figure 7 ). The charge storage layer CIL may be interposed between the blocking dielectric layer BLK and the tunneling dielectric layer TIL. Between the stacked structure ST and the vertical semiconductor pattern VSP, the blocking dielectric layer BLK, the charge storage layer CIL, and the tunneling dielectric layer TIL may extend along the inner sidewalls of the channel hole CH. The data storage pattern DSP may not cover the upper portion of the vertical semiconductor pattern VSP in the channel contact hole CCH to be discussed below.

[0075] The data storage pattern DSP may store and / or change data by using Fowler-Nordheim tunneling caused by a voltage difference between the vertical semiconductor pattern VSP and the first gate electrode GE1 and the second gate electrode GE2. For example, the blocking dielectric layer BLK and the tunneling dielectric layer TIL may include silicon oxide, and the charge storage layer CIL may include at least one selected from silicon nitride and silicon oxynitride.

[0076] The n-doped pattern ND may be disposed on the stacked structure ST. The n-doped pattern ND may cover the stacked structure ST. The n-doped pattern ND may cover the uppermost first interlayer dielectric layer in the first interlayer dielectric layer ILD1. The n-doped pattern ND may be disposed on the cell array region CAR. For example, although not shown, the n-doped pattern ND may also be disposed on the cell array extension region EXR. The n-doped pattern ND may include a semiconductor material doped with n-type impurities. The n-doped pattern ND may include polysilicon doped with n-type impurities.

[0077] The undoped pattern UD may be disposed on the n-doped pattern ND. The undoped pattern UD may cover the n-doped pattern ND. The undoped pattern UD may be disposed on the cell array region CAR. For example, although not shown, the undoped pattern UD may also be disposed on the cell array extension region EXR. The undoped pattern UD may include a semiconductor material that is not doped with impurities or is doped with a smaller amount of impurities. For example, the undoped pattern UD may include polycrystalline silicon that is not doped with impurities. For another example, the undoped pattern UD may include polycrystalline silicon doped with impurities, the amount of these impurities being less than the amount of impurities in the polycrystalline silicon doped into the n-doped pattern ND and the p-doped pattern PD to be discussed below. In this case, the impurities in the undoped pattern UD may be impurities diffused from the n-doped pattern ND or the p-doped pattern PD to be discussed below, and therefore the undoped pattern UD may include a relatively small amount of impurities.

[0078] The channel contact hole CCH may be disposed in the n-doped pattern ND and the undoped pattern UD. The channel contact hole CCH may extend along the first direction D1 in the n-doped pattern ND and the undoped pattern UD. Each of the plurality of channel contact holes CCH may be disposed on and vertically overlap the corresponding vertical structure VS.

[0079] The vertical structure VS may extend into the n-doped pattern ND, and the upper portion of the vertical structure VS may be positioned in the channel contact hole CCH. For example, the vertical semiconductor pattern VSP and the buried dielectric pattern VI may extend into the n-doped pattern ND, and their upper portions may be positioned in the channel contact hole CCH. In the channel contact hole CCH, the upper portion of the vertical semiconductor pattern VSP may surround the upper portion of the buried dielectric pattern VI. In the channel contact hole CCH, the upper portion of the vertical semiconductor pattern VSP may contact the p-doped pattern PD to be discussed below. For example, the upper portion of the vertical semiconductor pattern VSP may include p-type impurities.

[0080] The p-doped pattern PD may be disposed on the undoped pattern UD. The p-doped pattern PD may cover the undoped pattern UD. The p-doped pattern PD may be disposed on the cell array region CAR. For example, although not shown, the p-doped pattern PD may also be disposed on the cell array extension region EXR. The p-doped pattern PD may include a semiconductor material doped with p-type impurities. For example, the p-doped pattern PD may include polysilicon doped with p-type impurities.

[0081] The p-doped pattern PD may include a p-doped horizontal pattern PDy and a p-doped vertical pattern PDx. The p-doped horizontal pattern PDy may cover the undoped pattern UD. The p-doped vertical pattern PDx may extend from the vertical structure VS toward the p-doped horizontal pattern PDy. The p-doped vertical pattern PDx may penetrate the undoped pattern UD and the n-doped pattern ND, and may fill the channel contact hole CCH. In the channel contact hole CCH, the p-doped vertical pattern PDx may contact the vertical structure VS. For example, in the channel contact hole CCH, the p-doped vertical pattern PDx may contact the upper portion of the vertical semiconductor pattern VSP and may be electrically connected to the vertical semiconductor pattern VSP. The p-doped vertical pattern PDx and the vertical semiconductor pattern VSP may contact each other without a boundary.

[0082] The undoped pattern UD may be between the p-doped pattern PD and the n-doped pattern ND. For example, the undoped pattern UD may be between the p-doped horizontal pattern PDy and the n-doped pattern ND, and may extend in the second direction D2 and the third direction D3. The undoped pattern UD may separate the p-doped horizontal pattern PDy and the n-doped pattern ND from each other. Because the undoped pattern UD separates the p-doped horizontal pattern PDy and the n-doped pattern ND from each other, the junction leakage between the p-doped pattern PD and the n-doped pattern ND may be minimized. In summary, the reliability and electrical characteristics of the three-dimensional semiconductor memory device may be improved.

[0083] In the data erasing operation of the three-dimensional semiconductor memory device, the p-doped pattern PD can be used as a path along which holes are provided to the vertical structure VS. The erasing operation of the plurality of memory cell transistors MCT can be performed simultaneously through the p-doped pattern PD. Therefore, the erasing operation speed of the three-dimensional semiconductor memory device can be increased, and accordingly, its performance can be improved.

[0084] The separation trenches STR may extend in the second direction D2. The separation trenches STR may separate the stack structures ST from each other in the third direction D3. The separation trenches STR may extend from the cell array region CAR toward the cell array extension region EXR.

[0085] The separation groove STR may include a first separation groove STR1 penetrating the first stacking structure ST1 and a second separation groove STR2 penetrating the second stacking structure ST2. Each of the first separation groove STR1 and the second separation groove STR2 may have a width in the second direction D2 and / or the third direction D3, and the width may decrease as the distance from the peripheral substrate 10 increases. The first separation groove STR1 and the second separation groove STR2 may be connected to each other and may have different widths at their connecting boundaries. For example, the diameter of the upper portion of the second separation groove STR2 may be smaller than the diameter of the lower portion of the first separation groove STR1. The first separation groove STR1 and the second separation groove STR2 may have a step difference at their connecting boundary. However, the present disclosure is not limited thereto, and unlike what is shown, three or more separation grooves having a step difference at each of two or more boundaries thereof may be provided. Alternatively, unlike what is shown, a separation groove having a flat sidewall without a step difference may be provided.

[0086] The separation pattern SS may fill the separation trench STR. The separation pattern SS may correspond to Figure 3 and Figure 4 The separation pattern SS may be provided between the plurality of stacked structures ST and may separate the stacked structures ST from each other in the third direction D3.

[0087] The separation pattern SS may include a metal contact MC extending along the first direction D1 between adjacent stacked structures ST, and may also include a separation dielectric pattern SI between the metal contact MC and the stacked structure ST. The metal contact MC may also extend into and contact the n-doped pattern ND. The separation dielectric pattern SI may separate the metal contact MC from the stacked structure ST. The metal contact MC may extend much further than the separation dielectric pattern SI in the first direction D1. The metal contact MC may include a conductive material such as a metal. The separation dielectric pattern SI may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0088] The metal contact MC may be electrically connected to the n-doped pattern ND. Electrons may be supplied from the metal contact MC to the vertical structure VS through the n-doped pattern ND.

[0089] The upper dielectric layer UI may be disposed on the p-doped pattern PD. The p-contact hole PCH may be disposed in the upper dielectric layer UI and the p-doped pattern PD. The p-contact hole PCH may extend from the top surface of the upper dielectric layer UI to the upper portion of the p-doped pattern PD. The p-contact plug PC may fill the p-contact hole PCH. The p-contact plug PC may be electrically connected to the p-doped pattern PD. The upper circuit line UL may be disposed on the upper dielectric layer UI and the p-contact plug PC. The upper circuit line UL may be electrically connected to the p-doped pattern PD through the p-contact plug PC. The upper circuit line UL may electrically control the p-doped pattern PD. The p-contact plug PC and the upper circuit line UL may include a conductive material, such as a metal.

[0090] refer to Figures 8 to 16 Various embodiments of the three-dimensional semiconductor memory device will be described below. For the sake of brevity, repeated descriptions will be omitted.

[0091] Figure 8 , Fig.10 and Fig.11 The diagram shows Figure 6 An example enlarged cross-sectional view of portion P2. Fig.9A and Fig. 9B The diagram shows the Figure 5 An example enlarged plan view of a portion P1 of the first level and the second level. Fig.12 A plan view showing another example of a three-dimensional semiconductor memory device is illustrated.

[0092] refer to Figures 8 to 9B The n-doped pattern ND and the p-doped pattern PD each have a doping concentration that varies according to regions. In this specification, the doping concentration of the n-doped pattern ND indicates an n-type impurity concentration, and the doping concentration of the p-doped pattern PD indicates a p-type impurity concentration.

[0093] The doping concentration of the n-doping pattern ND may vary in the downward direction. For example, the doping concentration of the n-doping pattern ND may increase continuously or discontinuously in the downward direction. In the present specification, the phrase "the doping concentration varies discontinuously" may be defined to include a case where the doping concentration varies relatively greatly even if the doping concentration is continuous.

[0094] The doping concentration of the n-doped pattern ND may decrease as the distance from the undoped pattern UD decreases. For example, the n-doped pattern ND may include a first n-doped region ND1, a second n-doped region ND2, and a third n-doped region ND3 sequentially defined from its lower portion. The doping concentration of the second n-doped region ND2 may be less than the doping concentration of the first n-doped region ND1 and greater than the doping concentration of the third n-doped region ND3. For example, in a direction pointing from the first n-doped region ND1 to the second n-doped region ND2 or from the second n-doped region ND2 to the third n-doped region ND3, the doping concentration may be discontinuously reduced at the boundary between the first n-doped region ND1 and the second n-doped region ND2 or between the second n-doped region ND2 and the third n-doped region ND3. For another example, the third n-doped region ND3 may not be defined. For another example, the fourth n-doped region may also be defined.

[0095] The doping concentration of the p-doped pattern PD may change as the distance from the undoped pattern UD or the n-doped pattern ND decreases. The doping concentration of the p-doped horizontal pattern PDy may decrease continuously or discontinuously in the downward direction. The doping concentration of the p-doped vertical pattern PDx may decrease continuously or discontinuously as the distance from the inner sidewall of the channel contact hole CCH decreases.

[0096] The p-doped pattern PD may include a first p-doped region PD1 and a second p-doped region PD2 having a doping concentration greater than that of the first p-doped region PD1. The first p-doped region PD1 may be defined on the inner sidewall of the channel contact hole CCH and on the top surface of the undoped pattern UD. The second p-doped region PD2 may fill the channel contact hole CCH, and on the top surface of the undoped pattern UD, the second p-doped region PD2 may cover the first p-doped region PD1. For example, in a direction from the second p-doped region PD2 to the first p-doped region PD1, the doping concentration may be discontinuously reduced at the boundary between the second p-doped region PD2 and the first p-doped region PD1. For another example, a third p-doped region may also be defined.

[0097] A lower portion of the p-doped vertical pattern PDx may be surrounded by the n-doped pattern ND, and for example, at the first level LV1, the p-doped vertical pattern PDx may be surrounded by the n-doped pattern ND. An upper portion of the p-doped vertical pattern PDx may be surrounded by the undoped pattern UD, and for example, at the second level LV2, the p-doped vertical pattern PDx may be surrounded by the undoped pattern UD.

[0098] When viewed in a plan view, the doping concentration of the lower portion of the p-doped vertical pattern PDx may decrease continuously or discontinuously as the distance from the n-doped pattern ND decreases (see FIG. 2 ). Fig.9A). For example, at the first horizontal height LV1, the second p-doped region PD2 may fill the channel contact hole CCH, and the first p-doped region PD1 may be disposed between the second p-doped region PD2 and the n-doped pattern ND. In a direction pointing from the second p-doped region PD2 to the first p-doped region PD1, the doping concentration of the lower portion of the p-doped vertical pattern PDx may be discontinuously reduced at a boundary between the second p-doped region PD2 and the first p-doped region PD1.

[0099] When viewed in a plan view, the doping concentration of the upper portion of the p-doped vertical pattern PDx may decrease continuously or discontinuously as the distance from the undoped pattern UD decreases (see FIG. 2 ). Fig. 9B ). For example, at the second horizontal height LV2, the second p-doped region PD2 may fill the channel contact hole CCH, and the first p-doped region PD1 may be disposed between the second p-doped region PD2 and the undoped pattern UD. In a direction pointing from the second p-doped region PD2 to the first p-doped region PD1, the doping concentration of the upper portion of the p-doped vertical pattern PDx may be discontinuously reduced at a boundary between the second p-doped region PD2 and the first p-doped region PD1.

[0100] The doping concentration of each of the n-doped pattern ND and the p-doped pattern PD may be adjusted to minimize junction leakage between the n-doped pattern ND and the p-doped pattern PD. In summary, the reliability and electrical characteristics of a three-dimensional semiconductor memory device may be improved.

[0101] refer to Fig.10 , the p-doped pattern PD may include an ohmic region OR. The ohmic region OR may include n-type impurities. The ohmic region OR may be adjacent to the p-contact plug PC. For example, the ohmic region OR may be disposed along an outer wall of the p-contact hole PCH. The p-contact plug PC and the p-doped pattern PD may form an ohmic junction through the ohmic region OR. The n-doping concentration of the ohmic region may vary according to the region, but the present disclosure is not limited thereto.

[0102] refer to Fig.11 and Fig.12 , the metal contact MC is provided as a discrete component with respect to the separation pattern SS. For example, the separation pattern SS does not include the metal contact MC.

[0103] refer to Fig.11, the metal contact trench MTR penetrates the p-doped pattern PD and the undoped pattern UD, and extends into the n-doped pattern ND. The metal contact MC fills the metal contact trench MTR. The metal contact MC contacts the n-doped pattern ND and is electrically connected to the n-doped pattern ND. For example, a dielectric spacer IS is further provided on the inner sidewall of the metal contact trench MTR. The dielectric spacer IS separates the metal contact MC from the p-doped pattern PD and the undoped pattern UD.

[0104] refer to Fig.12 , when viewed in a plan view, the metal contact MC is spaced apart from the separation pattern SS. For example, the separation pattern SS extends from the stacked structure ST into the n-doped pattern ND. For another example, the metal contact MC extends from the p-doped pattern PD and the undoped pattern UD into the n-doped pattern ND. When viewed in a plan view, the metal contact MC is shown as having a linear shape, but the present disclosure is not limited thereto.

[0105] Fig.13 Shown along Figure 5 Example cross-sectional views taken along lines AA' and BB'. Figures 14 to 16 The diagram shows Fig.13 An example enlarged cross-sectional view of portion P3.

[0106] refer to Fig.13 and Fig.14 , the p-doped pattern PD covers the stacked structure ST. Figure 6 Unlike the discussion, neither the n-doped pattern ND nor the undoped pattern UD is disposed between the p-doped pattern PD and the stacked structure ST.

[0107] The channel contact hole CCH may be provided in the stacked structure ST. The channel contact hole CCH may be defined on the channel hole CH and vertically overlapped therewith. The channel contact hole CCH may penetrate the uppermost first gate electrode GE1 and the uppermost first interlayer dielectric layer ILD1. The channel contact hole CCH may penetrate two or more first gate electrodes in the first gate electrode GE1, and may also penetrate two or more first interlayer dielectric layers in the first interlayer dielectric layer ILD1. For example, the two or more first gate electrodes GE1 may be referred to as ground selection lines GSL, and the two or more first interlayer dielectric layers ILD1 may be referred to as ground interlayer dielectric layers Ig. In this case, two or more ground selection lines GSL may be provided. One of the first gate electrodes GE1 below the channel contact hole CCH may also be a ground selection line GSL.

[0108] The channel contact hole CCH may have a width in the second direction D2 and / or the third direction D3, and the width may increase in the downward direction. When viewed in the second direction D2 and / or the third direction D3, the width at the bottom end of the channel contact hole CCH may be greater than the width at the top end of the channel hole CH. The channel contact hole CCH and the channel hole CH may be connected to each other and may have a step difference at their connection boundaries.

[0109] The vertical structure VS may include a header structure HV in the channel contact hole CCH and a through structure PV in the first channel hole CH1 and the second channel hole CH2. The through structure PV may be positioned below the header structure HV. When viewed in the second direction D2 and / or the third direction D3, the width at the bottom end of the header structure HV may be greater than the width at the top end of the through structure PV.

[0110] The head structure HV may include a first head portion HV1 on the inner sidewall of the channel contact hole CCH, a first head portion HV1 on the inner bottom wall of the channel contact hole CCH, and a second head portion HV2 connecting the first head portion HV1 to the through structure PV. The first head portion HV1, the second head portion HV2, and the through structure PV may be connected to have a stepped shape. The buried dielectric pattern VI of the second head portion HV2 may protrude more than the vertical semiconductor pattern VSP of the second head portion HV2 in the first direction D1. The bottom surface of the second head portion HV2 may be in contact with the first gate electrode GE1, but the present disclosure is not limited thereto.

[0111] The p-doped pattern PD may include a p-doped vertical pattern PDx filling the channel contact hole CCH and a p-doped horizontal pattern PDy covering the stack structure ST. In the channel contact hole CCH, the p-doped vertical pattern PDx may be surrounded by the head structure HV. The p-doped vertical pattern PDx may protrude into the head structure HV. The p-doped vertical pattern PDx may contact and be electrically connected to the vertical semiconductor pattern VSP.

[0112] The contact trench CTR may be disposed on the separation trench STR. The contact trench CTR may be disposed in the stacked structure ST. The contact trench CTR may penetrate the uppermost first gate electrode GE1 and the uppermost first interlayer dielectric layer ILD1. For example, the contact trench CTR may penetrate the first gate electrode GE1 and the first interlayer dielectric layer ILD1 through which the channel contact hole CCH passes.

[0113] The width of the contact groove CTR in the third direction D3 may increase in the downward direction. When viewed in the third direction D3, the width at the bottom end of the contact groove CTR may be greater than the width at the top end of the separation groove STR. The contact groove CTR and the separation groove STR may be connected to each other and may have a step difference at their connection boundary.

[0114] The separation dielectric pattern SI may cover the inner wall of the contact trench CTR and the inner wall of the separation trench STR. The separation dielectric pattern SI may have a stepped profile at a boundary between the contact trench CTR and the separation trench STR.

[0115] The metal contact MC may include a head contact HC located in the contact trench CTR and a through contact PC filling the separation trench STR below the head contact HC. The width at the bottom end of the head contact HC may be greater than the width at the top end of the through contact PC. The head contact HC may protrude more than the separation dielectric pattern SI in the first direction D1. The head contact HC may extend into the p-doped pattern PD and be electrically connected to the p-doped pattern PD. A void VD may be provided in the metal contact MC and surrounded by the metal contact MC.

[0116] The p-doped pattern PD may have an inversion region INR adjacent to the stacked structure ST and between the vertical structure VS and the metal contact MC. The inversion region INR may be controlled by a ground selection line GSL. The ground selection line GSL may cause the inversion region INR to have an inversion state, and the inversion region INR may serve as a channel along which electrons move between the metal contact MC and the vertical structure VS.

[0117] The ground selection line GSL may have a first pitch PI1 in the first direction D1. In the present specification, the term "pitch" may be defined as the minimum thickness or width between specific components that are repeatedly and cyclically arranged. The ground interlayer dielectric layer Ig may have a first thickness TK1 in the first direction D1, and the ground selection line GSL may have a second thickness TK2 in the first direction D1. The first pitch PI1 may be defined as the sum of the first thickness TK1 and the second thickness TK2.

[0118] The first pitch PI1, the first thickness TK1, and the second thickness TK2 can be freely adjusted to control the properties and effects of the ground selection line GSL. For example, the first thickness TK1 can be set larger, or the second thickness TK2 can be set smaller, and thus the damage caused by the breakdown of the three-dimensional semiconductor memory device can be minimized. For another example, the first thickness TK1 can be set smaller, or the second thickness TK2 can be set larger, and thus the ground selection line GSL can effectively control the inversion region INR.

[0119] Among the gate electrodes GE1 and GE2, the gate electrode of the memory cell transistor MCT may have a second pitch PI2 in the first direction D1. The interlayer dielectric layers other than the ground interlayer dielectric layer Ig among the interlayer dielectric layers ILD1 and ILD2 may have a third thickness TK3 in the first direction D1, and the gate electrode of the memory cell transistor MCT may have a fourth thickness TK4 in the first direction D1. The second pitch PI2 may be defined as the sum of the third thickness TK3 and the fourth thickness TK4. The first pitch PI1 and the second pitch PI2 may be the same or different from each other. The first thickness TK1 and the third thickness TK3 may be the same or different from each other. The second thickness TK2 and the fourth thickness TK4 may be the same or different from each other.

[0120] refer to Fig.15 , the first interlayer dielectric layer ILD1 may further include an additional dielectric layer Ia. The additional dielectric layer Ia may cover the bottom surface of the second head portion HV2, and may separate the second head portion HV2 from the first gate electrode GE1 below the second head portion HV2. For example, the additional dielectric layer Ia and the first interlayer dielectric layer ILD1 adjacent to each other in the first direction D1 may be connected to each other without a boundary. The additional dielectric layer Ia may adjust the pitch of the ground selection line GSL located on the region adjacent to the bottom end of the head structure HV.

[0121] refer to Fig.16 , the p-doped pattern PD may include an ohmic region OR. The ohmic region OR may include n-type impurities. The ohmic region OR may be adjacent to the p-contact plug PC. For example, the ohmic region OR may be disposed along an outer wall of the p-contact hole PCH. The p-contact plug PC and the p-doped pattern PD may form an ohmic junction through the ohmic region OR.

[0122] Figures 17 to 23 An exemplary cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device is illustrated. Figures 17 to 23 , the following will describe the manufacturing reference Figure 6 Methods for three-dimensional semiconductor memory devices are discussed.

[0123] refer to Figure 5 and Fig.17 , a peripheral circuit structure PS is formed on the peripheral substrate 10. The formation of the peripheral circuit structure PS includes forming a device isolation layer 15 in the peripheral substrate 10, forming a peripheral transistor PTR on an active area of ​​the peripheral substrate 10 defined by the device isolation layer 15, and forming a peripheral contact plug 31 electrically connected to the peripheral transistor PTR, a peripheral circuit line 33, a first bonding pad 35, and a first dielectric layer 30 covering the peripheral contact plug 31, the peripheral circuit line 33, and the first bonding pad 35.

[0124] The first bonding pad 35 may have its top surface substantially coplanar with the top surface of the first dielectric layer 30. In the following description, the phrase “substantially coplanar with” may mean that a planarization process may be performed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0125] In the following reference Fig.18 and Fig.19 In the description of Figure 6 The "bottom surface" in the three-dimensional semiconductor memory device fabricated as described herein, and the term "bottom surface" may refer to the Figure 6 Similarly, the language "upper" and "lower" may refer to the top surface of the three-dimensional semiconductor memory device being fabricated. Figure 6 The "lower part" and the "upper part" in the three-dimensional semiconductor memory device fabricated are described.

[0126] refer to Figure 5 and Fig.18 , a unit array substrate 100 is provided. The unit array substrate 100 includes a first unit array substrate 110, a second unit array substrate 120, and a third unit array substrate 130 which are sequentially stacked.

[0127] The first unit array substrate 110 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The second unit array substrate 120 may include a material having an etching selectivity relative to the first unit array substrate 110. For example, the second unit array substrate 120 may include silicon oxide. The third unit array substrate 130 may include a semiconductor material, such as polysilicon.

[0128] The mold structure ML may be formed on the cell array substrate 100. The mold structure ML may include a first mold structure ML1 and a second mold structure ML2 located on the first mold structure ML1. The formation of the mold structure ML may include sequentially forming the first mold structure ML1 and the second mold structure ML2.

[0129] For example, a first mold structure ML1 may be first formed on the unit array substrate 100. The formation of the first mold structure ML1 may include alternately stacking a first interlayer dielectric layer ILD1 and a first sacrificial layer SL1. In the first mold structure ML1, the first sacrificial layer SL1 may be formed of a material that can be etched with an etching selectivity relative to the first interlayer dielectric layer ILD1. For example, the first sacrificial layer SL1 may be formed of a dielectric material different from the dielectric material of the first interlayer dielectric layer ILD1. For example, the first sacrificial layer SL1 may be formed of silicon nitride, and the first interlayer dielectric layer ILD1 may be formed of silicon oxide.

[0130] Afterwards, the first channel hole CH1 and the first separation trench STR1 may be formed to pass through the first interlayer dielectric layer ILD1 and the first sacrificial layer SL1 in the first direction D1. The first channel hole CH1 and the first separation trench STR1 may be formed by an anisotropic etching process performed on the first molding structure ML1. The first channel hole CH1 and the first separation trench STR1 may extend into the third unit array substrate 130.

[0131] The second mold structure ML2 may be formed on the first mold structure ML1. The second mold structure ML2 may include second interlayer dielectric layers ILD2 and second sacrificial layers SL2 alternately stacked. The second interlayer dielectric layers ILD2 and the second sacrificial layers SL2 may have features identical or similar to those of the first interlayer dielectric layers ILD1 and the first sacrificial layers SL1.

[0132] Afterwards, the second channel hole CH2 and the second separation trench STR2 may be formed to pass through the second interlayer dielectric layer ILD2 and the second sacrificial layer SL2 in the first direction D1. The second channel hole CH2 and the second separation trench STR2 may be formed by an anisotropic etching process performed on the second molding structure ML2. The second channel hole CH2 and the second separation trench STR2 may vertically overlap with the first channel hole CH1 and the first separation trench STR1, respectively. The first channel hole CH1 and the second channel hole CH2 may constitute the channel hole CH. The first separation trench STR1 and the second separation trench STR2 may constitute the separation trench STR.

[0133] refer to Figure 5 and Fig.19 , the vertical structure VS may be formed to fill the channel hole CH. The formation of the vertical channel structure VS may include sequentially forming a data storage pattern DSP, a vertical semiconductor pattern VSP, and a buried dielectric pattern VI in the channel hole CH. The channel pad CHP may be formed to fill the upper portion of the channel hole CH. The separation trench STR may be filled with a separation sacrificial pattern to avoid forming the vertical structure VS in the separation trench STR when the vertical structure VS is formed. The separation sacrificial pattern may be removed after the vertical structure VS is formed, and the separation trench STR may be exposed to the outside again.

[0134] An isotropic etching process in which the separation trench STR is used as a path may be performed and the first and second sacrificial layers SL1 and SL2 may be removed. First and second gate electrodes GE1 and GE2 may be formed at locations where the first and second sacrificial layers SL1 and SL2 are removed, and thus a stacked structure ST may be formed.

[0135] The separation pattern SS may be formed to fill the separation trench STR. The formation of the separation pattern SS may include sequentially forming a separation dielectric pattern SI and a metal contact MC in the separation trench STR. Thereafter, a second dielectric layer 40, a cell contact plug 41, a cell circuit line 43, and a second bonding pad 45 may be formed on the stacked structure ST. The cell contact plug 41, the cell circuit line 43, and the second bonding pad 45 may be electrically connected to each other, and the second dielectric layer 40 may be formed to surround the cell contact plug 41, the cell circuit line 43, and the second bonding pad 45.

[0136] refer to Figure 5 and Fig. 20 , the peripheral circuit structure PS and the cell array structure CS may be bonded to each other. For example, the first bonding pad 35 of the peripheral circuit structure PS may be bonded to and contact the second bonding pad 45 of the cell array structure CS. Therefore, the first dielectric layer 30 and the second dielectric layer 40 may also be bonded to each other.

[0137] When the first bonding pad 35 and the second bonding pad 45 are bonded to each other, the cell array structure CS may be inverted. Therefore, when describing the manufacturing method after bonding, the terms "top surface", "bottom surface", "upper portion" and "lower portion" may refer to the cell array structure CS. Figure 6 The terms "top surface," "bottom surface," "upper portion," and "lower portion" are discussed.

[0138] refer to Figure 5 and Fig.21 , the unit array substrate 100 may be removed. The removal of the unit array substrate 100 may be achieved by at least one selected from a grinding process, a planarization process, a dry etching process, and / or a wet etching process. For example, the removal of the unit array substrate 100 may include sequentially removing the first unit array substrate 110, the second unit array substrate 120, and the third unit array substrate 130.

[0139] The removal of the cell array substrate 100 may expose the data storage pattern DSP of the vertical structure VS, the separation dielectric pattern SI of the separation pattern SS, and the uppermost first interlayer dielectric layer ILD1. The exposed portion of the data storage pattern DSP may be removed, and the exposed portion of the separation dielectric pattern SI may be removed. Therefore, the vertical semiconductor pattern VSP may be exposed above the channel hole CH, and the metal contact MC may be exposed above the separation trench STR. P-type impurities may also be doped into the exposed portion of the vertical semiconductor pattern VSP, but the present disclosure is not limited thereto.

[0140] refer to Figure 5 and Fig. 22, an n-doped pattern ND may be formed on the stacked structure ST. The n-doped pattern ND may be formed to cover the exposed portion of the vertical semiconductor pattern VSP and the exposed portion of the metal contact MC. For example, the n-doped pattern ND may be formed to cover the top surface of the vertical semiconductor pattern VSP and the top surface of the metal contact MC. Figure 8 As discussed, the n-doped pattern ND may be formed to have a doping concentration varying according to regions. For example, the formation of the n-doped pattern ND may include sequentially forming a first n-doped region ND1 , a second n-doped region ND2 , and a third n-doped region ND3 .

[0141] The undoped pattern UD may be formed to cover the n-doped pattern ND. The channel contact hole CCH may be formed to penetrate the undoped pattern UD and the n-doped pattern ND. The channel contact hole CCH may be formed to vertically overlap the channel hole CH. In the channel contact hole CCH, a portion of the vertical semiconductor pattern VSP may be exposed to the outside again.

[0142] refer to Figure 5 and Fig.23 , a p-doped pattern PD may be formed on the undoped pattern UD. The p-doped pattern PD may fill the channel contact hole CCH and may cover the top surface of the undoped pattern UD. In the channel contact hole CCH, the p-doped pattern PD may contact and be electrically connected to the vertical semiconductor pattern VSP. As shown in FIG. Figure 8 As discussed, the p-doped pattern PD may be formed to have a doping concentration that varies according to regions. The formation of the p-doped pattern PD may include sequentially forming Figure 8 For example, the first p-doped region PD1 may be formed to conformally cover the inner side surface of the channel contact hole CCH and the top surface of the undoped pattern UD, and the second p-doped region PD2 may be formed to fill the channel contact hole CCH and cover the first p-doped region PD1.

[0143] After forming the p-doped pattern PD, a laser annealing process may be further performed The laser annealing process may crystallize the semiconductor material in the n-doped pattern ND and the p-doped pattern PD and may activate impurities.

[0144] An upper dielectric layer UI may be formed on the p-doped pattern PD. A p-contact hole PCH may be formed to penetrate the upper dielectric layer UI and extend into the p-doped pattern PD. The p-contact hole PCH may expose the p-doped pattern PD to the outside at a lower portion of the p-contact hole PCH.

[0145] After forming the p contact hole PCH, a P-doped pattern PD may be formed on the exposed portion of the p contact hole PCH. Fig.10The formation of the ohmic region OR may include doping n-type impurities into the exposed portion of the p-doped pattern PD.

[0146] Return to reference Figure 5 and Figure 6 , a p contact plug PC and an upper circuit line UL may be formed. The p contact plug PC may be formed to fill the p contact hole PCH, and the upper circuit line UL may be formed on the upper dielectric layer UI. The p contact plug PC and the upper circuit line UL may be formed by a damascene process, but the present disclosure is not limited thereto.

[0147] Figures 24 to 30 Other exemplary cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device are illustrated. Figures 24 to 30 , the following will describe the manufacturing reference Fig.13 Methods for three-dimensional semiconductor memory devices are discussed.

[0148] refer to Figure 5 and Fig.24 , some of the first interlayer dielectric layers ILD1 and some of the first sacrificial layers SL1 are alternately stacked on the unit array substrate 100. Some of the first interlayer dielectric layers ILD1 are ground interlayer dielectric layers Ig, and some of the first sacrificial layers SL1 are ground sacrificial layers SLg.

[0149] The channel contact hole CCH and the contact trench CTR may be formed to penetrate the ground interlayer dielectric layer Ig and the ground sacrificial layer SLg. The channel contact hole CCH and the contact trench CTR may extend into the cell array substrate 100 (eg, into the third cell array substrate 130).

[0150] refer to Figure 5 and Fig.25 , the buried sacrificial pattern BS may be formed to fill the channel contact hole CCH and the contact trench CTR. The formation of the buried sacrificial pattern BS may include depositing the buried sacrificial pattern BS to fill the channel contact hole CCH and the contact trench CTR and cover the ground interlayer dielectric layer Ig, and removing the buried sacrificial pattern BS covering the ground interlayer dielectric layer Ig. The removal of the buried sacrificial pattern BS may include performing a planarization process. During the removal process, the buried sacrificial pattern BS may expose the top surface of the ground interlayer dielectric layer Ig and may remain in the channel contact hole CCH and the contact trench CTR. For example, the buried sacrificial pattern BS may include a metal or a metal nitride.

[0151] Although not shown, after forming the buried sacrificial pattern BS, a reference dielectric layer may be further formed on the buried sacrificial pattern BS and the ground interlayer dielectric layer Ig. Fig.15The additional dielectric layer Ia discussed. Thereafter, the additional dielectric layer Ia may be left or removed based on the influence of subsequent processes or pitch adjustment. Thereafter, a first interlayer dielectric layer ILD1 and a first sacrificial layer SL1 may also be formed on the buried sacrificial pattern BS and the ground interlayer dielectric layer Ig, as a result of which a first mold structure ML1 may be formed.

[0152] refer to Figure 5 and Fig.26 The first channel hole CH1 and the first separation trench STR1 may be formed to penetrate the first interlayer dielectric layer ILD1 and the first sacrificial layer SL1. The first channel hole CH1 and the first separation trench STR1 may extend into the buried sacrificial pattern BS and may expose the inside of the buried sacrificial pattern BS to the outside.

[0153] The second mold structure ML2 may be formed on the first mold structure ML1, and thus the mold structure ML may be formed on the unit array substrate 100. Thereafter, the second channel hole CH2 and the second separation trench STR2 may be formed to pass through the second interlayer dielectric layer ILD2 and the second sacrificial layer SL2 in the first direction D1. The second channel hole CH2 and the second separation trench STR2 may vertically overlap the first channel hole CH1 and the first separation trench STR1, respectively.

[0154] The buried sacrificial pattern BS exposed by the first channel hole CH1 may be removed. Therefore, the channel contact hole CCH and the contact trench CTR may become empty. The ground interlayer dielectric layer Ig and the ground sacrificial layer SLg may be exposed outward on the inner side surface of the channel contact hole CCH and the inner side surface of the contact trench CTR.

[0155] refer to Figure 5 and Fig. 27 , the vertical structure VS may be formed to fill the channel hole CH and the channel contact hole CCH. In this process, the step difference between the channel contact hole CCH and the channel hole CH may form a gap VD in the vertical structure VS. The channel pad CHP may be formed to fill the upper portion of the channel hole CH. The vertical structure VS may include a head structure HV located in the channel contact hole CCH and a through structure PV located in the first channel hole CH1 and the second channel hole CH2.

[0156] The separation trench STR and the contact trench CTR may be filled with separation sacrificial patterns to prevent the vertical structure VS from being formed therein when forming the vertical structure VS. The separation sacrificial patterns may be removed after forming the vertical structure VS, and the separation trench STR and the contact trench CTR may be exposed outward again.

[0157] By similar reference Fig.19In the process discussed, the first sacrificial layer SL1 and the second sacrificial layer SL2 may be replaced with the first gate electrode GE1 and the second gate electrode GE2, and thus a stacked structure ST may be formed. A separation dielectric pattern SI and a metal contact MC of the separation pattern SS may be formed to fill the separation trench STR. In this process, a step difference between the contact trench CTR and the separation trench STR may form a gap VD in the metal contact MC. The metal contact MC may include a head contact HC located in the contact trench CTR and a through contact PC filling the separation trench STR below the head contact HC. Thereafter, a second dielectric layer 40, a cell contact plug 41, a cell circuit line 43, and a second bonding pad 45 may be formed on the stacked structure ST.

[0158] refer to Figure 5 and Fig.28 , the peripheral circuit structure PS and the cell array structure CS may be bonded to each other. Therefore, the header structure HV may be positioned at an upper portion of the vertical structure VS. After bonding, the header structure HV may include a third header portion HV3 covering the first header portion HV1.

[0159] refer to Figure 5 and Fig.29 , the unit array substrate 100 may be removed. The removal of the unit array substrate 100 may expose the upper portion of the header structure HV and the upper portion of the separation pattern SS outwardly. The exposed upper portion of the header structure HV may be removed. For example, the upper portions of the third header portion HV3 and the first header portion HV1 located above the stacked structure ST may be removed, and the void VD in the header structure HV may be exposed. In this process, a portion of the buried dielectric pattern VI located in the channel contact hole CCH may also be removed. Therefore, in the channel contact hole CH, the vertical semiconductor pattern VSP of the first header portion HV1 may be exposed.

[0160] The exposed upper portion of the separation pattern SS may be removed. For example, the separation dielectric pattern SI may be removed from the exposed upper portion of the separation pattern SS, and the head contact HC may be left and exposed to the outside without being removed. The upper portion of the head contact HC may protrude upward from the stack structure ST. The head contact HC may separate the gap VD therein from the outside.

[0161] refer to Figure 5 and Fig.30, a p-doped pattern PD may be formed on the stacked structure ST. The p-doped pattern PD may fill the channel contact hole CCH and may cover the top surface of the stacked structure ST and the upper portion of the head contact HC. In the channel contact hole CCH, the p-doped pattern PD may contact and be electrically connected to the vertical semiconductor pattern VSP. The p-doped pattern PD may contact and be electrically connected to the upper portion of the head contact HC.

[0162] Return to reference Figure 5 and Fig.13 , an upper dielectric layer UI may be formed on the p-doped pattern PD. A p-contact hole PCH may be formed to penetrate the upper dielectric layer UI and extend into the p-doped pattern PD. A p-contact plug PC may be formed to fill the p-contact hole PCH, and an upper circuit line UL may be formed on the upper dielectric layer UI.

[0163] According to the present disclosure, a data erase operation of a three-dimensional semiconductor memory device can be performed using a p-doped pattern, and an erase operation can be performed on a plurality of memory cell transistors at the same time. As a result, the erase operation speed of the three-dimensional semiconductor memory device and the electronic system including the same can be improved.

[0164] In addition, the undoped pattern can be positioned between the p-doped pattern and the n-doped pattern, and thus the junction leakage between the p-doped pattern and the n-doped pattern can be minimized. Therefore, the electrical characteristics of the three-dimensional semiconductor memory device and the electronic system including the same can be improved and the reliability thereof can be increased.

[0165] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope of the claimed protection, but rather as descriptions of features specific to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. In contrast, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described above as working in certain combinations, and even if initially claimed to be protected as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a sub-combination or a variant of a sub-combination.

[0166] The above-mentioned description provides some embodiments for illustrating the present disclosure. However, the present disclosure is not limited to the above-mentioned embodiments, and it will be understood by those skilled in the art that changes in form and details can be made without departing from the spirit and essential features of the present disclosure.

Claims

1. A three-dimensional semiconductor memory device, comprising: A circuit structure, wherein the circuit structure is located on a substrate; a stacked structure, the stacked structure comprising a plurality of gate electrodes stacked on the circuit structure; an n-doped pattern, the n-doped pattern being located on the stacked structure; a vertical structure extending through the stacked structure into the n-doped pattern; a p-doped pattern, the p-doped pattern being located on the n-doped pattern; as well as an undoped pattern, the undoped pattern being located between the n-doped pattern and the p-doped pattern, Wherein, the p-doping pattern comprises: a p-doped horizontal pattern, the p-doped horizontal pattern being located on the undoped pattern; and A p-doped vertical pattern extends through the undoped pattern and the n-doped pattern and contacts the vertical structure.

2. The three-dimensional semiconductor memory device according to claim 1, wherein: The undoped pattern vertically separates the p-doped horizontal pattern from the n-doped pattern.

3. The three-dimensional semiconductor memory device according to claim 1, wherein: The undoped pattern covers a top surface of the n-doped pattern.

4. The three-dimensional semiconductor memory device according to claim 1, wherein: The stacked structure includes a plurality of structures horizontally spaced apart from each other, and The three-dimensional semiconductor memory device includes a separation structure that separates the plurality of structures from each other and extends into the n-doped pattern.

5. The three-dimensional semiconductor memory device according to claim 4, wherein: The partition structure comprises: a metal contact electrically connected to the n-doped pattern; and A separation dielectric pattern is disposed between the metal contact and the stack structure. 6 . The three-dimensional semiconductor memory device of claim 1 , comprising a metal contact extending through the p-doped pattern and the undoped pattern into the n-doped pattern.

7. The three-dimensional semiconductor memory device according to claim 1, wherein: The doping concentration of the n-doped pattern increases continuously or discontinuously in a downward direction.

8. The three-dimensional semiconductor memory device according to claim 1, wherein: The doping concentration of the p-doped horizontal pattern decreases continuously or discontinuously in a downward direction.

9. The three-dimensional semiconductor memory device according to claim 1, wherein: An upper portion of the p-doped vertical pattern is surrounded by the undoped pattern, and A lower portion of the p-doped vertical pattern is surrounded by the n-doped pattern.

10. The three-dimensional semiconductor memory device according to claim 9, wherein: In a plan view of the three-dimensional semiconductor memory device, a doping concentration of an upper portion of the p-doped vertical pattern decreases continuously or discontinuously as a distance from the undoped pattern decreases.

11. The three-dimensional semiconductor memory device according to claim 9, wherein: In a plan view of the three-dimensional semiconductor memory device, a doping concentration of a lower portion of the p-doped vertical pattern decreases continuously or discontinuously as a distance from the n-doped pattern decreases.

12. The three-dimensional semiconductor memory device according to claim 1, comprising a p-type contact plug electrically connected to the p-doped pattern, in, The p-doped pattern includes an ohmic region adjacent to the p-contact plug, and Wherein, the ohmic region includes n-type impurities.

13. The three-dimensional semiconductor memory device according to claim 1, wherein: The width of the p-doped vertical pattern in the horizontal direction decreases in a downward direction.

14. A three-dimensional semiconductor memory device, comprising: A circuit structure, wherein the circuit structure is located on a substrate; a stacked structure, the stacked structure comprising a plurality of gate electrodes stacked on the circuit structure; an n-doped pattern, the n-doped pattern being located on the stacked structure; a vertical structure extending through the stacked structure into the n-doped pattern; an undoped pattern, the undoped pattern being located on the n-doped pattern; a p-doped pattern extending through the undoped pattern and the n-doped pattern and contacting the vertical structure; a metal contact electrically connected to the n-doped pattern; as well as A p-contact plug is electrically connected to the p-doped pattern.

15. The three-dimensional semiconductor memory device according to claim 14, wherein: The p-doped pattern covers a top surface of the undoped pattern.

16. The three-dimensional semiconductor memory device according to claim 14, wherein: The n-doped pattern comprises: a first n-doped region; and a second n-doped region, wherein the doping concentration of the second n-doped region is less than the doping concentration of the first n-doped region, and The second n-doped region is closer to the undoped pattern than the first n-doped region.

17. The three-dimensional semiconductor memory device according to claim 14, wherein: The p-doping pattern comprises: a first p-doped region; and a second p-doped region, wherein the doping concentration of the second p-doped region is greater than the doping concentration of the first p-doped region, and The first p-doped region is closer to the undoped pattern than the second p-doped region.

18. The three-dimensional semiconductor memory device according to claim 14, wherein: The metal contact extends from a bottom end or a top end of the n-doped pattern into the n-doped pattern.

19. An electronic system, comprising: Three-dimensional semiconductor memory devices; as well as a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad, the controller being configured to control the three-dimensional semiconductor memory device, Wherein, the three-dimensional semiconductor memory device comprises: A circuit structure, wherein the circuit structure is located on a substrate; a stacked structure, the stacked structure comprising a plurality of gate electrodes stacked on the circuit structure; an n-doped pattern, the n-doped pattern being located on the stacked structure; a vertical structure extending through the stacked structure into the n-doped pattern; a p-doped pattern, the p-doped pattern being located on the n-doped pattern; and an undoped pattern, the undoped pattern being located between the n-doped pattern and the p-doped pattern, Wherein, the p-doping pattern comprises: a p-doped horizontal pattern, the p-doped horizontal pattern being located on the undoped pattern; and A p-doped vertical pattern extends through the undoped pattern and the n-doped pattern and contacts the vertical structure.

20. The electronic system according to claim 19, wherein: The undoped pattern vertically separates the p-doped horizontal pattern from the n-doped pattern.

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