Memory structure and manufacturing method thereof

Abstract

The invention provides a memory structure and a manufacturing method thereof. The memory structure comprises: a substrate having a first surface and a second surface opposite to each other, the substrate comprising an array region and a logic region adjacent to the array region, the array region having a plurality of first conductive paths penetrating from the first surface to the second surface, the logic region having a second conductive path penetrating from the first surface to the second surface, the first conductive path and the second conductive path have the same height; the plurality of memory units are located on the first surface, each memory unit covers one first conductive path, and the plurality of memory units are in one-to-one correspondence with the plurality of first conductive paths; the at least one top electrode layer is located on the surfaces of the sides, away from the substrate, of the multiple memory units; and the top metal wiring layer is positioned on one side, provided with the top electrode layer, of the substrate, so that the top metal wiring layer is electrically connected with at least one top electrode layer. According to the invention, the manufacturing cost of the memory structure is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a memory structure and a method for manufacturing the memory structure. Background Art

[0002] The MRAM memory storage unit MTJ is usually composed of three basic units: a ferromagnetic layer, an insulating tunnel layer, and a fixed layer. When the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite, the memory device exhibits a high resistance state Rap. When the magnetic moment directions of the two layers are the same, it exhibits a low resistance state Rp, which is used to store information "1" and "0". As a new type of memory, MRAM has huge advantages over traditional Flash storage in terms of read and write speed and device reliability;

[0003] However, when the industry manufactures memory now, the general integration scheme is generally to first prepare the bottom through holes in the storage array area and the storage cells, then prepare the bottom through holes in the non-storage array area, and then prepare the top metal layer common to the storage area and the non-storage area, and make the top metal layer electrically connected to multiple storage cells through the top through holes. Therefore, the bottom through holes in the storage array area and the bottom through holes in the non-storage area and the top through holes on the storage cells need to be formed in multiple photolithography steps, and since a mask needs to be used for production in each photolithography process, a large number of mask layers are required, which increases the manufacturing cost. Summary of the invention

[0004] The main purpose of the present invention is to provide a memory structure and a method for manufacturing the memory structure, so as to solve the problems of complex manufacturing process and high cost in the prior art.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present invention, a memory structure is provided, comprising: a substrate having a first surface and a second surface opposite to each other, and the substrate comprises an array area and a logic area adjacent to the array area, the array area having a plurality of first conductive paths extending from the first surface to the second surface, the logic area having a second conductive path extending from the first surface to the second surface, the first conductive path and the second conductive path having the same height; a plurality of memory cells located on the first surface, each memory cell covering a first conductive path, and the plurality of memory cells corresponding to the plurality of first conductive paths one by one; at least one top electrode layer located on a surface of the plurality of memory cells away from the substrate; and a top metal wiring layer located on a side of the substrate having the top electrode layer, and electrically connecting the top metal wiring layer to the at least one top electrode layer.

[0006] Further, each memory cell has a first projection on the substrate, at least one top electrode layer has a second projection on the substrate, and the first projection is located within the second projection.

[0007] Furthermore, the top electrode layer includes multiple top electrode layers, and the multiple top electrode layers correspond one-to-one to the multiple memory cells. The surface of the memory cell away from the first conductive path is the third surface. Each top electrode layer covers the third surface, and the top metal wiring layer electrically connects the multiple top electrode layers.

[0008] Furthermore, the memory structure further includes: a protection layer, wherein the protection layer at least covers the sidewalls of the memory unit.

[0009] Furthermore, the top metal wiring layer is also electrically connected to the second conductive path.

[0010] Furthermore, the memory cell includes one or more of a magnetic random access memory cell, a phase change random access memory cell, a resistive random access memory cell and a ferroelectric random access memory cell.

[0011] Further, in the case where the memory cell is a magnetic random access memory cell, the at least one top electrode layer comprises at least one layer.

[0012] Further, at least one top electrode layer includes multiple layers, and a material of at least one layer of the at least one top electrode layer is a ferromagnetic material.

[0013] To achieve the above-mentioned purpose, according to another aspect of the present invention, a method for manufacturing a memory structure is provided, comprising: providing a substrate having a first surface and a second surface opposite to each other, and the substrate comprising an array area and a logic area adjacent to the array area, forming a plurality of first conductive paths and a second conductive path in the substrate by a single photolithography process, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface, so that each memory cell covers a first conductive path, and the plurality of memory cells correspond to the plurality of first conductive paths one by one; forming at least one top electrode layer on the surface of the plurality of memory cells away from the substrate; and forming a top metal wiring layer on the side of the substrate having the top electrode layer, so that the top metal wiring layer is electrically connected to the at least one top electrode layer.

[0014] Furthermore, the step of forming a top electrode layer includes: after the step of forming a memory cell, depositing a first insulating material and a second insulating material in sequence on a side of the substrate having the memory cell, so that the first insulating material covers the memory cell and the first surface, and the second insulating material covers the first insulating material; removing a portion of the first insulating material and a portion of the second insulating material by chemical mechanical polishing to form a fourth surface exposing a plurality of memory cells; and forming a top electrode layer on the fourth surface.

[0015] The technical solution of the present invention is applied to provide a memory structure, which includes a substrate, a plurality of memory cells, at least one top electrode layer and a top metal wiring layer, and the substrate includes a plurality of first conductive paths located in an array area and a second conductive path located in a logic area, the plurality of memory cells are located on the plurality of first conductive paths to achieve electrical connection between each memory cell and each first conductive path, the at least one top electrode layer is located on a surface of the plurality of memory cells away from the substrate side, thereby achieving electrical connection between the top electrode layer and each memory cell, the top metal wiring layer is located on a side of the top electrode layer away from the substrate, and the top metal wiring layer is electrically connected to the at least one top electrode layer, wherein, since the heights of the plurality of first conductive paths and the second conductive paths in the substrate of the memory structure provided by the present solution are consistent, the plurality of first conductive paths and the second conductive paths can be formed at one time by using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths, and then a plurality of memory cells and at least one top conductive path covering the plurality of first conductive paths are formed on the first surface. After a top electrode layer, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the multiple memory cells in the array area are higher than the height of the second conductive path. Therefore, a top metal wiring layer electrically connected to at least one top electrode layer can be directly formed on the side of the substrate having the top electrode layer, so that the top metal wiring layer can be electrically connected to the multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cell corresponding to the array area is lower than the top conductive path of the logic area, and it is necessary to form a top conductive path again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cell corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to additionally form a conductive path electrically connecting the multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the photolithography steps, reducing the number of mask layers, and thereby reducing the manufacturing cost of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A schematic cross-sectional structure diagram of a memory structure according to an embodiment of the present invention is shown;

[0018] Figure 2A schematic cross-sectional structure diagram of a substrate provided in a method for manufacturing a memory structure according to an embodiment of the present invention is shown;

[0019] Figure 3 Shown in Figure 2 A schematic cross-sectional structure diagram of a memory cell film deposited on a substrate shown;

[0020] Figure 4 Shows the etching Figure 3 The schematic diagram of the cross-sectional structure of the memory cell formed by the memory cell thin film shown;

[0021] Figure 5 Shows the flattening Figure 4 A schematic diagram of a cross-sectional structure of a top surface of a memory cell after a planarized surface is formed;

[0022] Figure 6 Shown in Figure 5 A schematic cross-sectional structure diagram of a top electrode layer formed on a planarized surface is shown;

[0023] Figure 7 Shown in Figure 6 The cross-sectional structure schematic diagram of the top electrode layer with the second insulating material deposited on the side away from the substrate is shown;

[0024] Figure 8 Shown in Figure 5 A schematic cross-sectional structure diagram of a plurality of top electrode layers formed on a planarized surface shown;

[0025] Fig. 9 Shown in Figure 8 A schematic cross-sectional structure diagram of the plurality of top electrode layers after a second insulating material is deposited on a side away from the substrate;

[0026] Fig.10 Shows the removal Fig. 9 A schematic diagram of a cross-sectional structure of a top metal wiring layer after some materials in the structure are formed;

[0027] Fig.11 Shown in Figure 4 A schematic cross-sectional structure diagram of depositing a second insulating material on the structure shown to form a fourth planarized surface;

[0028] Fig.12 Shows the etching Fig.11 A schematic diagram of the cross-sectional structure after the fourth planarized surface and the deposition of the top electrode material is shown;

[0029] Fig.13 Shows the etching Fig.12 A schematic cross-sectional structure diagram of the structure shown in the figure after forming a top electrode layer and depositing the second insulating material;

[0030] Fig.14 Shows the removal Fig.13 A schematic diagram of the cross-sectional structure of a top metal wiring layer is formed after some materials in the structure are removed.

[0031] The above drawings include the following reference numerals:

[0032] 10. substrate; 20. first conductive path; 30. second conductive path; 40. memory cell; 401. lower electrode layer; 402. storage layer; 403. upper electrode layer; 50. top electrode layer; 60. top metal wiring layer; 70. protective layer; 80. insulating dielectric layer; 90. first metal wiring layer; 100. second metal wiring layer; 110. memory cell film; 111. lower electrode material layer; 112. storage material layer; 113. upper electrode material layer; 120. first insulating material; 130. second insulating material; 140. top electrode material; 150. etch stop layer. DETAILED DESCRIPTION

[0033] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] As mentioned in the background technology, when the industry manufactures memory, the general integration scheme is generally to first prepare the bottom through holes and memory cells in the memory array area, then prepare the bottom through holes in the non-memory array area, and then prepare the top metal layer common to the memory area and the non-memory area, and make the top metal layer electrically connected to multiple memory cells through the top through holes. Therefore, the bottom through holes in the memory array area and the bottom through holes in the non-memory area and the top through holes on the memory cells need to be formed in multiple photolithography steps, and since a mask needs to be used for production in each photolithography process, a large number of mask layers are required, which increases the manufacturing cost. In order to solve the above technical problems, the inventors of the present application provide a memory structure and a method for manufacturing the memory structure.

[0037] In some optional implementations, a memory structure is provided, such as Figure 1 As shown, the memory structure includes a substrate 10 having a first surface and a second surface opposite to each other, a plurality of memory cells 40 located on the first surface, at least one top electrode layer 50 located on the plurality of memory cells 40, and a top metal wiring layer 60 located on a side of the top electrode layer 50 away from the substrate 10. Specifically, the substrate 10 includes an array region and a logic region adjacent to the array region, the array region has a plurality of first conductive paths 20 penetrating from the first surface to the second surface, the logic region has a second conductive path 30 penetrating from the first surface to the second surface, the first conductive paths 20 and the top metal wiring layer 60 are connected to each other. The height of the second conductive path 30 is the same; each of the plurality of memory cells 40 covers a different first conductive path 20, that is, the number of the plurality of memory cells 40 can be the same as the number of the plurality of first conductive paths 20 in the substrate 10, and the plurality of memory cells 40 and the plurality of first conductive paths 20 correspond to each other; the at least one top electrode layer 50 is located on the surface of the plurality of memory cells 40 away from the substrate 10; the top metal wiring layer 60 is located on the side of the substrate 10 having the top electrode layer 50, and the top metal wiring layer 60 is electrically connected to the at least one top electrode layer 50. Optionally, the substrate 10 further comprises a first metal wiring layer 90 and a second metal wiring layer 100, wherein the first metal wiring layer 90 is disposed in contact with the side of the first conductive path 20 away from the memory cell 40, and the second metal wiring layer 100 is disposed in contact with the side of the second conductive path 30 away from the memory cell 40.

[0038] Specifically, the substrate 10 may include but is not limited to a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, and a silicon-coated insulating substrate, etc., and those skilled in the art may make reasonable choices according to actual needs. The plurality of first conductive paths 20 and the second conductive paths 30 may all be conductive paths formed of metal materials. Optionally, the metal materials in the first conductive paths 20 and the second conductive paths 30 may include but are not limited to one metal or a combination of multiple metals selected from W, Cu, TaN, and TiN. Further, any two adjacent first conductive paths 20 are arranged at intervals, and optionally, any first conductive path 20 and the second conductive path 30 are arranged at intervals. It should be noted that the plurality of first conductive paths 20 and the second conductive paths 30 in the substrate 10 are formed by etching and filling in one photolithography process, and all extend from the first surface of the substrate 10 to the second surface. Therefore, the first conductive paths 20 and the second conductive paths 30 have the same height in a direction perpendicular to the first surface.

[0039] Specifically, Figure 1 As shown, each of the above-mentioned multiple memory cells 40 may include a lower electrode layer 401, a storage layer 402 and an upper electrode layer 403 which are stacked in sequence, and the above-mentioned lower electrode layer 401 is located between the storage layer 402 and the first surface of the substrate 10. Further, the lower electrode layer 401 in each memory cell 40 covers a first conductive path 20, and any two adjacent lower electrode layers 401 in the multiple memory cells 40 are arranged at intervals, so that the multiple lower electrodes in the multiple memory cells 40 correspond one-to-one to the multiple first conductive paths 20, and the lower electrode layer 401, the storage layer 402 and the upper electrode layer 403 of each memory cell 40 in the multiple memory cells 40 correspond one-to-one, so that the multiple memory cells 40 correspond one-to-one to the multiple first conductive paths 20.

[0040] Specifically, the above-mentioned top electrode layer 50 may include one or more, and in the case where there is one top electrode layer 50, the top electrode layer 50 is located on the side of the multiple memory cells 40 away from the substrate 10, and the surface of the multiple memory cells 40 away from the substrate 10 (i.e., the third surface) is completely covered by the above-mentioned top electrode layer 50, so that the multiple memory cells 40 share the above-mentioned top electrode layer 50; in the case where there are multiple top electrode layers 50, the surface of each memory cell 40 away from the substrate 10 is the third surface, and the multiple top electrode layers 50 correspond one-to-one to the multiple memory cells 40, that is, a top electrode layer 50 is arranged on each of the above-mentioned third surfaces, so that any two adjacent top electrode layers 50 are arranged at intervals, and optionally, the top metal wiring layer 60 electrically connects the multiple top electrode layers 50.

[0041] Specifically, Figure 1As shown, the top metal wiring layer 60 is used to electrically connect the multiple memory cells 40 and interconnect the multiple memory cells 40. In the case where the multiple memory cells 40 have a top electrode layer 50 on the side away from the substrate 10, since the multiple memory cells 40 are electrically connected through the top electrode layer 50, the top metal wiring layer 60 is arranged on the surface of the top electrode layer 50 on the side away from the substrate 10, that is, the purpose of interconnecting the top metal wiring layer 60 and the multiple memory cells 40 is achieved; in the case where the multiple memory cells 40 have multiple top electrode layers 50 on the side away from the substrate 10, and any two adjacent top electrode layers 50 are arranged at intervals, in order to form an interconnection structure between any two adjacent memory cells 40, the top metal wiring layer 60 is arranged on the surface of the side of the multiple top electrode layers 50 away from the substrate 10, and the top metal wiring layer 60 is electrically connected to the multiple top electrode layers 50.

[0042] Optionally, the materials of the upper electrode and the lower electrode may include but are not limited to one or more metal materials such as Ti, TiN, Ta, TaN and W, and the material of the top metal wiring layer 60 may include but is not limited to metal copper. Those skilled in the art can flexibly select the materials of the upper electrode and the lower electrode according to actual needs.

[0043] In the above-mentioned embodiment, since the heights of the plurality of first conductive paths and the second conductive paths in the substrate of the memory structure provided by the present solution are consistent, the plurality of first conductive paths and the second conductive paths can be formed at one time by using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths. Subsequently, after a plurality of memory cells and at least one top electrode layer covering the plurality of first conductive paths are formed on the above-mentioned first surface, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the plurality of memory cells in the array area are higher than the heights of the second conductive path. Therefore, the memory cells can be directly formed by forming a plurality of first conductive paths and a plurality of second conductive paths on the substrate. A top metal wiring layer electrically connected to at least one top electrode layer is formed on one side of the top electrode layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cell corresponding to the array area is lower than the top conductive path of the logic area, and it is necessary to form a top conductive path again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cell corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to form an additional conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the number of photolithography steps, reducing the number of mask layers, and thereby reducing the manufacturing cost of the memory structure.

[0044] In some optional embodiments, each of the memory cells 40 has a first projection on the substrate 10 , and at least one of the top electrode layers 50 has a second projection on the substrate 10 , and the first projection is located within the second projection.

[0045] In the above embodiment, since the first projection of the memory cell 40 on the substrate 10 is located in the second projection of the top electrode layer 50 on the substrate 10, the size of the at least one top electrode layer 50 is larger than the size of the memory cell 40, so that in the back-end process steps of manufacturing the memory structure, the at least one top electrode layer 50 can protect the memory cell 40. Optionally, the memory cell 40 can be prevented from being over-etched.

[0046] Specifically, in the case where there is one top electrode layer 50, the projection of the top electrode layer 50 on the substrate 10 is the second projection, and the projections of the above-mentioned multiple memory cells 40 on the substrate 10 correspond to multiple first projections, so that the multiple first projections are all located in the above-mentioned second projection; specifically, in the case where there are multiple top electrode layers 50, the projection of each top electrode layer 50 among the multiple top electrode layers 50 on the substrate 10 is the second projection, and the projection of each memory cell 40 among the multiple memory cells 40 on the substrate 10 is the first projection, the multiple first projections correspond one-to-one to the multiple second projections, and each first projection is located in each corresponding second projection.

[0047] Since the top electrode layer 50 is located on the surface of the multiple memory cells 40 away from the above-mentioned substrate 10, the top electrode layer 50 is electrically connected to the memory cells 40. However, in the case where the top electrode layer 50 includes multiple top electrode layers, since any two adjacent top electrode layers 50 are electrically isolated, any two adjacent memory cells 40 are electrically isolated. In some optional embodiments, in order to form an electrical connection relationship between any two adjacent memory cells 40 when the top electrode layer 50 includes multiple top electrode layers, each of the above-mentioned top electrode layers 50 covers the surface of one of the above-mentioned memory cells 40 away from the above-mentioned first conductive path 20, and the above-mentioned top metal wiring layer 60 is electrically connected to the multiple above-mentioned top electrode layers 50, and the multiple above-mentioned top electrode layers 50 correspond one-to-one to the multiple above-mentioned memory cells 40.

[0048] In some optional embodiments, such as Figure 1 As shown, the memory structure further includes: a protective layer 70, and the protective layer 70 at least covers the sidewalls of the memory unit 40. Further, the first surface corresponding to the array region has an exposed surface other than that covered by the plurality of memory units 40, and the protective layer 70 also covers the exposed surface; further, in the case where the protective layer 70 also covers the exposed surface, the memory structure further includes: an insulating dielectric layer 80, and in the case where there is only one top electrode layer 50, the insulating dielectric layer 80 is located between the protective layer 70 covering the exposed surface and the top electrode layer 50, and in the case where there are multiple top electrode layers 50, the insulating dielectric layer 80 is also located between the top metal wiring layer 60 and the protective layer 70.

[0049] In the above embodiment, in order to prevent water, oxygen, etc. from damaging the memory cell 40 in the memory structure, the protective layer 70 is arranged around the memory cell 40. Further, in order to play the role of an etching barrier in the memory structure, the protective layer 70 is located on a portion of the first surface of the substrate 10 corresponding to the array region (i.e., the exposed surface except for the surface covered by the plurality of memory cells 40). Optionally, the material of the protective layer 70 may include but is not limited to silicon nitride and aluminum oxide, etc. Further, the material of the insulating dielectric layer 80 may include but is not limited to any one or more of silicon dioxide, carbon oxide, fluorine silicon glass, phosphorus silicon glass, borophosphorus silicon glass, tetraethyl orthosilicate, Low-K dielectric and Ultra-Low-K dielectric. It should be noted that there is a high etching selectivity between the protective layer 70 and the insulating dielectric layer 80.

[0050] Furthermore, in order to flatten the surface of the memory cell 40 away from the substrate 10, an insulating dielectric layer 80 is also provided on the side of the protective layer 70 away from the substrate 10, wherein the projection of the top electrode layer 50 on the substrate 10 and the projection of the insulating dielectric layer 80 on the substrate 10 at least partially overlap.

[0051] The multiple first conductive paths 20 in the array area of ​​the above-mentioned memory structure are electrically connected to the multiple memory cells 40, the above-mentioned multiple memory cells 40 are electrically connected to one or more top electrode layers 50, and the one or more top electrode layers 50 are electrically connected to the top metal wiring layer 60. Furthermore, in order to form an electrical connection between the array area and the logic area of ​​the memory structure, in some optional embodiments, the above-mentioned top metal wiring layer 60 is also electrically connected to the above-mentioned second conductive path 30.

[0052] Since the memory structure may include a magnetic random access memory structure, a phase change random access memory structure, a resistive random access memory structure and a ferroelectric random access memory structure, in some optional embodiments, the above-mentioned memory unit 40 includes one or more of a magnetic random access memory unit 40, a phase change random access memory unit 40, a resistive random access memory unit 40 and a ferroelectric random access memory unit 40.

[0053] In some optional embodiments, when the memory cell 40 is the magnetic random access memory cell 40, at least one of the top electrode layers 50 includes at least one layer. Further, at least one of the top electrode layers 50 includes multiple layers, and the material of at least one layer of the at least one top electrode layer 50 is a ferromagnetic material.

[0054] Optionally, the material of the at least one top electrode layer 50 may be a metal material, and the metal material may include but is not limited to non-magnetic materials such as TaN, TiN, and W. In the above embodiment, in order to significantly enhance the ability of the magnetic random access memory unit 40 to resist external magnetic field interference, the material of the at least one top electrode layer 50 may be a ferromagnetic material, and the ferromagnetic material may include but is not limited to other ferromagnetic materials such as NiFe, CoFe, FeV, or any other metal material known to those skilled in the art that can be used as the top electrode layer 50 and a combination thereof. Further, the at least one top electrode layer 50 may include multiple layers, wherein the material of the multiple top electrode layers 50 may all be non-magnetic materials, or the material of the multiple top electrode layers 50 may all be ferromagnetic materials, or the material of some layers in the multiple top electrode layers 50 may be non-magnetic materials, and the material of another part of the multiple top electrode layers 50 may be ferromagnetic materials.

[0055] Among them, it should be noted that, in the above-mentioned memory structure in this embodiment, the multiple magnetic random access memory units 40 can be arranged side by side along a direction. In the case where the top electrode layer 50 located on the surface of the multiple magnetic random access memory units 40 away from the substrate 10 in the above-mentioned memory structure is a single layer, the extension direction of the top electrode layer 50 is the direction from one magnetic random access memory unit 40 to another magnetic random access memory unit 40, so that the top electrode layer 50 is a long strip structure in the extension direction, and the long strip structure is parallel to the routing direction of the bit line BL in the memory structure, thereby significantly enhancing the magnetic random access memory unit 40's ability to resist external magnetic field interference.

[0056] According to another aspect of the present invention, the inventor of the present application also provides a method for manufacturing a memory structure, which manufacturing method includes: providing a substrate having a first surface and a second surface relative to each other, and the substrate includes an array area and a logic area adjacent to the array area, and using a single photolithography process to form a plurality of first conductive paths and a second conductive path in the substrate, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface so that each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond one to one to the plurality of first conductive paths; forming at least one top electrode layer on the surface of the plurality of memory cells away from the substrate; and forming a top metal wiring layer on the side of the substrate having the top electrode layer so that the top metal wiring layer is electrically connected to at least one of the top electrode layers.

[0057] In the above embodiment, a substrate having a first conductive path and a second conductive path is provided, and the first conductive path and the second conductive path in the substrate are highly consistent, that is, the above-mentioned multiple first conductive paths and second conductive paths are formed at one time by using the same photolithography process, thereby reducing the number of masks when forming the first conductive path and the second conductive path, and then after multiple memory cells and at least one top electrode layer covering the multiple first conductive paths are formed on the above-mentioned first surface, a top metal wiring layer electrically connected to at least one top electrode layer is formed directly on the side of the substrate having the top electrode layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Therefore, compared with the prior art, the present application does not need to additionally form a conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the photolithography steps, reducing the number of mask layers, and thereby reducing the manufacturing cost of the memory structure.

[0058] The exemplary embodiments of the method for manufacturing the memory structure provided by the present invention will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0059] like Figure 2As shown, a substrate 10 is provided, the substrate 10 has a first surface and a second surface opposite to each other, and the substrate 10 includes an array area and a logic area adjacent to the array area. First, a first mask covering the first surface is formed on the first surface of the substrate 10, wherein the first mask includes a plurality of first hollow areas corresponding to the array area and a second hollow area corresponding to the logic area. Then, the plurality of first hollow areas and the second hollow areas are etched to form a plurality of first through holes from the first surface to the second surface in the array area, and a second through hole from the first surface to the second surface is formed in the logic area. Then, after removing the first mask, a conductive material is deposited on the first surface, and the conductive material fills the plurality of first through holes and the second through holes. Then, a planarization process can be used to remove the conductive material on the first surface, so that the remaining conductive material in the plurality of first through holes forms a plurality of first conductive paths 20, and the remaining conductive material in the second through holes forms a second conductive path 30. Optionally, the planarization process can include a chemical mechanical polishing process. Optionally, the conductive material can include, but is not limited to, one metal or a combination of multiple metals selected from W, Cu, TaN, and TiN. Optionally, the substrate further comprises a first metal wiring layer 90 and a second metal wiring layer 100 , the first conductive path 20 is located on the first metal wiring layer 90 , and the second conductive path 30 is located on the second metal wiring layer 100 .

[0060] Furthermore, if Figure 3 As shown, in Figure 2 The memory cell film 110 corresponding to the memory cell 40 is deposited on the substrate 10 shown. Specifically, the memory cell film 110 may include a lower electrode material layer 111, a storage material layer 112 and an upper electrode material layer 113 formed by sequential deposition. Optionally, the lower electrode material layer 111 and the upper electrode material layer 113 may include but are not limited to metal layers such as Ti, TiN, Ta, TaN and W. Optionally, a hard mask material layer (not shown in the figure) may also be included on the upper electrode material layer 113. The hard mask material layer may include but is not limited to metal layers such as Ti, TiN, Ta, TaN and W or dielectric layers such as silicon oxide and silicon nitride. Optionally, the storage material layer 112 may include a free layer, a barrier layer and a reference layer stacked in sequence. The free layer is arranged in contact with the lower electrode material layer 111, and the reference layer is arranged in contact with the upper electrode material layer 113.

[0061] Furthermore, first Figure 3The memory cell film 110 shown in the figure is covered with a second mask on one side, and the second mask has a plurality of memory cell patterns corresponding to the plurality of first conductive paths 20 in the array region, and then the memory cell film 110 is etched according to the memory cell patterns (wherein, in the case where the memory cell film 110 is also covered with a hard mask material layer, the hard mask material layer and the memory cell film 110 are sequentially etched), thereby removing the memory cell film 110 except for the memory cell film 110 covering the plurality of first conductive paths 20, so that the remaining memory cell film 110 forms a memory cell 40, as shown in FIG. Figure 4 As shown, a portion of the first surface is exposed. Optionally, the projection shape of the memory unit 40 on the substrate 10 can be circular.

[0062] Furthermore, Figures 4 to 6 As shown, a top electrode layer 50 is formed on a side of the plurality of memory cells away from the substrate 10, wherein, in some optional embodiments, the step of forming the top electrode layer 50 includes: after the step of forming the memory cells 40, sequentially depositing a first insulating material 120 and a second insulating material 130 on a side of the substrate 10 having the memory cells 40, so that the first insulating material 120 covers the memory cells 40 and the first surface, and the second insulating material 130 covers the first insulating material 120; chemical mechanical polishing is used to remove a portion of the first insulating material 120 and a portion of the second insulating material 130 to form a fourth surface exposing the plurality of memory cells 40; and the top electrode layer 50 is formed on the fourth surface.

[0063] Specifically, Figure 4 As shown, after forming the memory cell 40, a first insulating material 120 is deposited on one side of the exposed first surface, so that the first insulating material 120 covers the exposed first surface and the exposed surface of the memory cell 40. Optionally, the first insulating material 120 may include but is not limited to silicon nitride and aluminum oxide. Those skilled in the art may reasonably select the first insulating material 120 used for protection in the prior art according to actual needs.

[0064] Furthermore, if Figure 5 As shown, in Figure 4In the structure shown, in order to make the above-mentioned multiple memory cells 40 have a flat upper surface (that is, the surface of each memory cell 40 away from the side of the substrate 10), the second insulating material 130 is first deposited so that the above-mentioned second insulating material 130 covers the above-mentioned first insulating material 120, and then chemical mechanical polishing can be used to remove part of the second insulating material 130 and the first insulating material 120, so that the upper surfaces of the multiple memory cells 40 are exposed to form a fourth surface, which is a flattened surface.

[0065] Furthermore, if Figure 6 As shown, in Figure 5 A top electrode material is deposited on the fourth surface (planarized surface) shown, so that the top electrode material covers the above-mentioned fourth surface (optionally, an etch stop material can also be deposited so that the etch stop material covers the side surface of the above-mentioned top electrode material away from the substrate 10), and then in order to form a top electrode layer 50 on the surface of multiple memory cells 40 away from the substrate 10, a third mask is formed on the fourth surface (or on the surface where the etch stop material is away from the top electrode material), and the third mask covers the above-mentioned top electrode material (or etch stop material) corresponding to the array area, and exposes the top electrode material corresponding to the logic area, so that the top electrode material (and etch stop material) corresponding to the logic area and a portion of the second insulating material 130 can be removed by etching to form a top electrode layer 50 (and an etch stop layer 150 corresponding to the etch stop material).

[0066] Furthermore, if Figure 7 As shown, in order to flatten the surface of the top electrode layer 50 away from the plurality of memory cells 40, Figure 6 The second insulating material 130 is deposited again on the side of the top electrode layer 50 (and the etch stop layer 150 corresponding to the etch stop material) and the remaining second insulating material 130 away from the substrate 10 .

[0067] Further, the chemical mechanical polishing process is used to remove Figure 7 Part of the second insulating material 130 (and the etch stop layer 150 corresponding to the etch stop material) in the structure shown is removed to expose the top electrode layer 50, and then a fourth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the fourth mask covers the above-mentioned top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic area, and then the above-mentioned second insulating material 130 not covered by the fourth mask is removed by etching, and when the first insulating material 120 is used as an etching barrier layer, the first insulating material 120 located in the logic area is removed, so that the second conductive path 30 is exposed, so that the logic area and the array area form a step structure, as shown in FIG. Figure 1As shown, the remaining first insulating material forms a protective layer 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then a top metal material is deposited on the exposed top electrode layer 50 and one side of the exposed second conductive path 30, so that the top metal material fills the above-mentioned step structure, and a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 in the logic area and the multiple memory cells 40 in the array area.

[0068] Or illustratively, Figure 8 As shown, in other embodiments, Figure 5 A top electrode material is deposited on the fourth surface (planarized surface) shown in the figure, so that the top electrode material covers the above-mentioned fourth surface (optionally, an etch stop material can also be deposited so that the etch stop material covers the surface of the side of the above-mentioned top electrode material away from the substrate 10), and then in order to form multiple top electrode layers 50 on the surface of the multiple memory cells 40 away from the substrate 10, a fifth mask is formed on the fourth surface (and on the surface of the etch stop material away from the top electrode material), and the fifth mask includes a plurality of mother-child boards arranged at intervals, and the plurality of mother-child boards cover portions of the top electrode material (and the etch stop material) corresponding to the multiple memory cells 40 in the array area, and expose the remaining top electrode material, so that the top electrode material (and the etch stop material) except for the portions of the top electrode material (or the etch stop material) corresponding to the multiple memory cells 40 and a portion of the second insulating material 130 can be removed by etching to form multiple top electrode layers 50 (and an etch stop layer 150 formed by the remaining etch stop material). It can be understood that since the top electrode material between any two adjacent mother-substrates is exposed, after the etching process, part of the second insulating material 130 between any two adjacent top electrode layers 50 or any two adjacent memory cells 40 is also removed, thereby forming a pit between any two adjacent top electrode layers 50 or any two adjacent memory cells 40.

[0069] Furthermore, if Fig. 9 As shown, in order to flatten the surface of the top electrode layer 50 away from the plurality of memory cells 40, Figure 8 The second insulating material 130 is deposited again on the side of the multiple top electrode layers 50 (and the etch stop layer 150 formed by the remaining etch stop material) and the remaining second insulating material 130 away from the substrate 10; optionally, the second insulating material 130 fills the above-mentioned pits.

[0070] Further, the chemical mechanical polishing process is used to remove Fig. 9A portion of the second insulating material 130 in the structure shown (and the etch stop layer 150 formed by the remaining etch stop material) is removed to expose the top electrode layer 50, and then a sixth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the sixth mask covers the above-mentioned top electrode layer 50 and exposes the second insulating material 130 except for the top electrode layer 50. Then, the above-mentioned second insulating material 130 not covered by the sixth mask is removed by etching, and with the first insulating material 120 serving as an etch barrier layer, the first insulating material 120 located in the logic area is removed to expose the second conductive path 30, so that the logic area and the array area form a step structure, and a portion of the second insulating material 130 located between any two adjacent memory cells 40 is removed to form a groove, so that the side walls of any two adjacent top electrode layers 50 are exposed, so as to form a step structure between the logic area and the array area. Fig.10 As shown, the remaining first insulating material forms a protective layer 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then a top metal material is deposited on the exposed top electrode layer 50, on one side of the exposed second conductive path 30, and in the groove between any two adjacent top electrode layers 50, so that the top metal material fills the above-mentioned step structure, and after filling the groove, any two adjacent top electrode layers 50 are electrically connected, and then a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 in the logic area and the multiple memory cells 40 in the array area.

[0071] Or illustratively, Fig.11 As shown, in other embodiments, Figure 4 In the structure shown, in order to make the above-mentioned multiple memory cells 40 have a flat upper surface (that is, the surface of each memory cell 40 away from the substrate 10), the second insulating material 130 is first deposited so that the above-mentioned second insulating material 130 covers the above-mentioned first insulating material 120, and then chemical mechanical polishing can be used to remove part of the second insulating material 130, so that the first insulating material 120 on the surface of the multiple memory cells 40 away from the substrate 10 is exposed, forming a fourth planarized surface.

[0072] Furthermore, if Fig.12 As shown, in Fig.11A seventh mask is formed on the fourth planarized surface shown in the figure, and the seventh mask covers a portion of the fourth planarized surface corresponding to the logic area, and exposes a portion of the fourth planarized surface corresponding to the array area, and then removes the exposed portion of the second insulating material 130 and a portion of the first insulating material 120 by etching, and exposes the upper surface of the plurality of memory cells 40 away from the substrate 10, so that after removing the seventh mask, there is a step structure between the array area and the logic area (the height of the array area in the direction perpendicular to the first surface is lower than the height of the logic area), so that after depositing the top electrode material 140 on the step structure, there is still a height difference between the array area and the logic area;

[0073] Chemical mechanical polishing is then used to Fig.12 The top electrode material 140 in the structure shown is planarized to remove the height difference between the array region and the logic region. Since the height of the array region is lower, all the top electrode material 140 in the logic region is removed after planarization, and the second insulating material 130 is exposed, so that Fig.13 As shown, the remaining top electrode material in the array region forms the top electrode layer 50 of the memory structure. Fig.13 As shown, in order to planarize the surface of the top electrode layer 50 away from the plurality of memory cells 40, the second insulating material 130 is deposited again on the exposed surface of the top electrode layer 50 and the side of the second insulating material 130 remaining after planarization away from the substrate 10;

[0074] Further, a portion of the second insulating material 130 is removed by a chemical mechanical polishing process to expose the top electrode layer 50, and then an eighth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the eighth mask covers the above-mentioned top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic area, and then the above-mentioned second insulating material 130 not covered by the eighth mask is removed by etching, and when the first insulating material 120 is used as an etching barrier layer, the first insulating material 120 located in the logic area is removed, so that the second conductive path 30 is exposed, so that the logic area and the array area form a step structure, so as to Fig.14 As shown, the remaining first insulating material forms a protective layer 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then a top metal material is deposited on the exposed top electrode layer 50 and one side of the exposed second conductive path 30, so that the top metal material fills the above-mentioned step structure, and a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 in the logic area and the multiple memory cells 40 in the array area.

[0075] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0076] Since the heights of the multiple first conductive paths and the second conductive paths in the substrate of the memory structure provided by the present solution are consistent, the multiple first conductive paths and the second conductive paths can be formed at one time by using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths. Subsequently, after multiple memory cells and at least one top electrode layer covering the multiple first conductive paths are formed on the first surface, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the multiple memory cells in the array area are higher than the heights of the second conductive path. Therefore, the top electrode layer can be directly formed on the substrate. A top metal wiring layer electrically connected to at least one top electrode layer is formed on one side of the layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cell corresponding to the array area is lower than the top conductive path of the logic area, and it is necessary to form a top conductive path again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cell corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to form an additional conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the number of photolithography steps, reducing the number of mask layers, and further reducing the manufacturing cost of the memory structure.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory structure, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, and the substrate includes an array area and a logic area adjacent to the array area, wherein the array area has a plurality of first conductive paths extending from the first surface to the second surface, and the logic area has a second conductive path extending from the first surface to the second surface, and the first conductive path and the second conductive path have the same height; A plurality of memory cells are located on the first surface, and each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond to the plurality of the first conductive paths one by one; at least one top electrode layer, located on a surface of the plurality of memory cells away from the substrate; The top metal wiring layer is located on the side of the substrate having the top electrode layer, and is configured to electrically connect the top metal wiring layer to at least one of the top electrode layers.

2. The memory structure according to claim 1, characterized in that: Each of the memory cells has a first projection on the substrate, and at least one of the top electrode layers has a second projection on the substrate, wherein the first projection is located within the second projection.

3. The memory structure according to claim 1, characterized in that: The top electrode layers include multiple top electrode layers, and the multiple top electrode layers correspond one-to-one to the multiple memory cells. The surface of the memory cell away from the first conductive path is the third surface. Each top electrode layer covers the third surface. The top metal wiring layer electrically connects the multiple top electrode layers.

4. The memory structure according to claim 1, characterized in that: The memory structure also includes: A protection layer at least covers a side wall of the memory cell.

5. The memory structure according to any one of claims 1 to 4, characterized in that: The top metal wiring layer is also electrically connected to the second conductive path.

6. The memory structure according to any one of claims 1 to 4, characterized in that: The memory unit includes one or more of a magnetic random access memory unit, a phase change random access memory unit, a resistive random access memory unit and a ferroelectric random access memory unit.

7. The memory structure according to claim 6, characterized in that: In the case where the memory cell is the magnetic random access memory cell, at least one of the top electrode layers includes at least one layer.

8. The memory structure according to claim 7, characterized in that: At least one of the top electrode layers comprises multiple layers, and a material of at least one layer of at least one of the top electrode layers is a ferromagnetic material.

9. A method for manufacturing a memory structure, characterized in that: include: Providing a substrate having a first surface and a second surface opposite to each other, and the substrate including an array area and a logic area adjacent to the array area, and forming a plurality of first conductive paths and a second conductive path in the substrate by a single photolithography process, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface so that each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond to the plurality of the first conductive paths one by one; forming at least one top electrode layer on the surface of the plurality of memory cells away from the substrate; A top metal wiring layer is formed on a side of the substrate having the top electrode layer, so that the top metal wiring layer is electrically connected to at least one of the top electrode layers.

10. The manufacturing method according to claim 9, characterized in that: The steps of forming the top electrode layer include: After the step of forming the memory cell, a first insulating material and a second insulating material are sequentially deposited on a side of the substrate having the memory cell, so that the first insulating material covers the memory cell and the first surface, and the second insulating material covers the first insulating material; removing a portion of the first insulating material and a portion of the second insulating material by chemical mechanical polishing to form a fourth surface exposing the plurality of memory cells; The top electrode layer is formed on the fourth surface.

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