Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, display panel and display device

Abstract

The invention relates to a low-temperature polycrystalline silicon thin film transistor, a manufacturing method of the low-temperature polycrystalline silicon thin film transistor, a display panel and a display device. The manufacturing method of the low-temperature polycrystalline silicon thin film transistor comprises the following steps: sequentially forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer on a buffer layer; forming a via hole which sequentially penetrates through the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer to expose the active material layer; and heavy doping is carried out on the active material layer and the area corresponding to the via hole, then activating treatment is carried out, and the doping concentration is gradually reduced from the self-weight doped area to the periphery after activating treatment, so that an active layer is formed. The manufacturing method of the low-temperature polycrystalline silicon thin film transistor is simple in process, the LDD structure of the thin film transistor can be formed on the premise that Mask and process complexity are not increased by moving a source and drain electrode heavy doping process and activating treatment backwards, and the purpose of reducing electric leakage of a device is achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a low-temperature polysilicon thin film transistor and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] In the pixel circuit of display technology, due to the high leakage of low-temperature polysilicon TFT, the technical direction of low leakage is considered from the process perspective, that is, the LTPS circuit uses LDD structure to reduce TFT leakage, or LTPO technology, that is, the switch tube is made of IGZO-TFT with lower leakage. However, LTPS LDD structure or LTPO technology will increase the mask, which will not only increase the cost but also increase the process complexity and process precision requirements. Summary of the invention

[0003] Based on this, it is necessary to provide a low-temperature polysilicon thin-film transistor and its manufacturing method, display panel, and display device to reduce device leakage without increasing the complexity of the mask and process.

[0004] A method for manufacturing a low-temperature polycrystalline silicon thin film transistor comprises the following steps:

[0005] An active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer are sequentially formed on the buffer layer;

[0006] forming a via hole, wherein the via hole sequentially penetrates the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to expose the active material layer; and

[0007] The active material layer and the region corresponding to the via hole are heavily doped, and then activated. After the activation, the doping concentration gradually decreases from the heavily doped region to the periphery to form an active layer.

[0008] The manufacturing method of the low-temperature polysilicon thin-film transistor is simple in process. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin-film transistor can be formed without increasing the complexity of the mask and process, thereby achieving the purpose of reducing device leakage. At the same time, it can also improve the channel edge effect of the thin-film transistor and improve the Hump problem.

[0009] In a feasible implementation, the operation of heavily doping the region corresponding to the active material layer and the via hole is: using an ion beam to perform ion implantation on the region corresponding to the active material layer and the via hole, wherein the ion implantation dose is 5E14 / cm 2 ~1E15 / cm 2 .

[0010] In a feasible implementation, the doping element used to heavily dope the region of the active material layer corresponding to the via hole is selected from at least one of boron and phosphorus.

[0011] In a feasible implementation, the activation treatment is performed by heat treatment at 400° C. to 450° C. for 0.5 h to 1 h.

[0012] In a feasible implementation, the active layer further includes a transistor channel region, and the transistor channel region is close to a side with a lower doping concentration.

[0013] In a feasible implementation, the via hole includes a first via hole and a second via hole;

[0014] The activation treatment further comprises the following steps:

[0015] A source electrode and a drain electrode are formed on the interlayer dielectric layer, the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole.

[0016] A low-temperature polysilicon thin film transistor comprises a buffer layer, an active layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer which are stacked in sequence;

[0017] The low-temperature polysilicon thin film transistor has a via hole, and the via hole sequentially penetrates the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer;

[0018] The area of ​​the active layer corresponding to the via hole is a heavily doped area, and the doping concentration in the active layer gradually decreases from the heavily doped area to the periphery.

[0019] The low-temperature polysilicon thin-film transistor of the technical solution of the present invention can form an LDD structure of the thin-film transistor without increasing the complexity of the mask and process by postponing the heavy doping process of the source and drain and the activation process, thereby achieving the purpose of reducing device leakage. At the same time, it can also improve the channel edge effect of the thin-film transistor and improve the Hump problem.

[0020] In a feasible implementation, the via hole includes a first via hole and a second via hole;

[0021] The low-temperature polysilicon thin film transistor further includes a source electrode and a drain electrode. The source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole.

[0022] A display panel comprises a low-temperature polysilicon thin film transistor manufactured by any of the above-mentioned methods for manufacturing a low-temperature polysilicon thin film transistor, or the above-mentioned low-temperature polysilicon thin film transistor.

[0023] The display panel of the technical solution of the present invention includes the above-mentioned low-temperature polysilicon thin film transistor. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin film transistor can be formed without increasing the mask and process complexity, thereby achieving the purpose of reducing device leakage. At the same time, it can also play a role in improving the channel edge effect of the thin film transistor and improving the Hump problem.

[0024] A display device comprises the above-mentioned display panel.

[0025] The display device of the technical solution of the present invention includes the above-mentioned display panel, and the above-mentioned display panel includes the above-mentioned low-temperature polysilicon thin film transistor. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin film transistor can be formed without increasing the complexity of the mask and process, thereby achieving the purpose of reducing device leakage. At the same time, it can also play a role in improving the channel edge effect of the thin film transistor and improving the Hump problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A flowchart of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention after an active material layer is formed on a buffer layer;

[0028] Figure 3 It is a schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment after a first gate insulating layer is formed on an active material layer;

[0029] Figure 4 A schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention after a gate metal layer is formed on a first gate insulating layer;

[0030] Figure 5 It is a schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment after a second gate insulating layer and an interlayer dielectric layer are sequentially formed on a first gate insulating layer and a gate metal layer;

[0031] Figure 6 A schematic diagram of a method for manufacturing a low-temperature polysilicon thin-film transistor after forming a via hole according to an embodiment;

[0032] Figure 7 It is a schematic diagram of heavily doping an active material layer in a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment;

[0033] Figure 8A schematic diagram of an activation process in a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment;

[0034] Fig. 9 is a schematic cross-sectional view of a method for manufacturing a low-temperature polysilicon thin film transistor after activation treatment according to an embodiment;

[0035] Fig.10 A schematic plan view of a method for manufacturing a low-temperature polysilicon thin film transistor after activation treatment according to an embodiment of the present invention;

[0036] Fig.11 It is a schematic diagram of a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment after a source electrode and a drain electrode are formed on an interlayer dielectric layer. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0039] See also Figure 1 A method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention comprises the following steps:

[0040] S10, forming an active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer in sequence on the buffer layer.

[0041] An active material layer (PSI) 120 ′ is formed on the buffer layer (Buffer) 110 , such as Figure 2As shown. The active material layer (PSI) 120' can be formed on the buffer layer (Buffer) 110 by conventional means in the art, for example, an amorphous silicon layer is deposited on the buffer layer (Buffer) 110, and the amorphous silicon layer is converted into a polycrystalline silicon active material layer (PSI) 120' by a low temperature crystallization process, and the low temperature crystallization process can be solid phase crystallization (SPC), excimer laser crystallization (ELA), rapid thermal annealing (RTA) or metal lateral induction method (MILC).

[0042] The buffer layer 110 may be silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer. In addition, the buffer layer (Buffer) 110 can be located on the substrate, and the substrate plays a bearing role and can be a transparent substrate, such as a glass substrate.

[0043] A first gate insulating layer (GI) 130 is formed on the active material layer (PSI) 120 ′. Figure 3 As shown. A first gate insulating layer (GI) 130 may be formed on the active material layer (PSI) 120' by conventional means in the art. The first gate insulating layer (GI) 130 may be silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer stacked together.

[0044] A gate metal layer (M1) 140 is formed on the first gate insulating layer (GI) 130. Figure 4 As shown. A gate metal layer (M1) 140 may be formed on the first gate insulating layer (GI) 130 by conventional means in the art, for example, a whole metal layer is first formed on the first gate insulating layer (GI) 130, and then the whole metal layer is etched to obtain the gate metal layer (M1) 140. The material of the whole metal layer may be, but is not limited to, a combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu).

[0045] A second gate insulating layer (CI) 150 and an interlayer dielectric layer (ILD) 160 are sequentially formed on the first gate insulating layer (GI) 130 and the gate metal layer (M1) 140, such as Figure 5 As shown. Conventional means in the art may be used to sequentially form a second gate insulating layer (CI) 150 and an interlayer dielectric layer (ILD) 160 on the first gate insulating layer (GI) 130 and the gate metal layer (M1) 140. The second gate insulating layer (CI) 150 may be silicon oxide (SiO x ) layer, silicon nitride (SiN x) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer stacked together.

[0046] S20, forming a via hole, wherein the via hole sequentially penetrates the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer to expose the active material layer.

[0047] The via hole 170 may be formed by an etching process. The via hole 170 sequentially penetrates the interlayer dielectric layer (ILD) 160, the second gate insulating layer (CI) 150, and the first gate insulating layer (GI) 130, and exposes the active material layer (PSI) 120'. The area corresponding to the active material layer (PSI) 120' and the via hole 170 is the heavily doped region 121. Figure 6 Further, the via 170 includes a first via 171 and a second via 172 , and the first via 171 and the second via 172 both penetrate the interlayer dielectric layer (ILD) 160 , the second gate insulating layer (CI) 150 , and the first gate insulating layer (GI) 130 in sequence.

[0048] Among them, the area of ​​the active material layer (PSI) 120' corresponding to the via hole is the heavily doped area 121, which means that the projection area of ​​the bottom opening of the via hole 170 on the active layer (PSI) 120 is the heavily doped area 121. Further, the heavily doped area 121 is determined by the projection area of ​​the bottom opening of the via hole 170 on the active material layer (PSI) 120', that is, the area of ​​the heavily doped area 121 is equal to the projection area of ​​the bottom opening of the via hole 170 on the active material layer (PSI) 120'. The present invention does not limit the size of the via hole 170.

[0049] S30, heavily doping the area of ​​the active material layer corresponding to the via hole, and then performing an activation treatment, after which the doping concentration gradually decreases from the heavily doped area to the periphery to form an active layer.

[0050] In a feasible implementation, the operation of heavily doping the region corresponding to the active material layer (PSI) 120' and the via hole 170 is as follows: ion implantation is performed on the region corresponding to the active material layer (PSI) 120' and the via hole 170 using an ion beam, and the ion implantation dose is 5E14 / cm 2 ~1E15 / cm 2 ,like Figure 7 Further, the dose of ion implantation may be, but is not limited to, 5E14 / cm 2 、6E14 / cm 2 、7E14 / cm 2 、8E14 / cm 2 、9E14 / cm 2 or 1E15 / cm 2 .

[0051] In a feasible implementation, the doping element heavily doped in the region of the active material layer (PSI) 120 ′ corresponding to the via hole 170 is selected from at least one of boron and phosphorus.

[0052] In a feasible implementation, the activation treatment is performed by heat treatment at 400°C to 450°C for 0.5h to 1h. Figure 8 As shown. Further, the temperature of the heat treatment may be but is not limited to 400°C, 405°C, 410°C, 415°C, 420°C, 425°C, 430°C, 435°C, 440°C, 445°C or 450°C, and the time of the heat treatment may be but is not limited to 0.5h, 0.6h, 0.7h, 0.8h, 0.9h or 1h. The activation treatment enables the heavily doped region 121 to perform injection damage repair and diffusion of the injected ions at high temperature, and forms an annular diffusion around the heavily doped region 121 with the heavily doped region 121 as the center, and the doping concentration gradually decreases from the heavily doped region 121 to the periphery. Further, after the activation treatment, the doped ions form an annular diffusion to form a lightly doped region 122 with a relatively low concentration around the heavily doped region 121, and after the activation treatment, the active material layer (PSI) 120' forms an active layer 120, as shown Fig. 9 and Fig.10 shown.

[0053] In a feasible implementation, the active layer 120 further includes a transistor channel region 123, which is close to the side with lower doping concentration, that is, connected to the lightly doped region 122. The region where the transistor channel region 123 is located is the projection region of the gate metal layer (M1) 140 on the active layer (PSI) 120. In other words, the periphery of the transistor channel region 123 is the lightly doped region 122. Fig.10 As shown, the improvement of the channel edge effect is as follows: the source and drain doping is annular diffusion, the middle resistance is low, and the resistance on both sides of the transistor channel region 123 is high. The current direction passes through paths ① and ② as shown in the figure. As the length of path ② increases, the current will decrease, thereby achieving the purpose of weakening the channel edge effect.

[0054] In a feasible implementation, the activation treatment further includes the following steps: forming a source electrode 180 and a drain electrode 190 on the interlayer dielectric layer (ILD) 160, the source electrode 180 is connected to the active layer 120 through the first via hole 171, and the drain electrode 190 is connected to the active layer 120 through the second via hole 172. Fig.11As shown. The operation of forming the source 180 and the drain 190 on the interlayer dielectric layer (ILD) 160 is: firstly, a whole metal layer is formed on the interlayer dielectric layer (ILD) 160, and then the whole metal layer is etched to obtain the source 180 and the drain 190. The material of the whole metal layer can be, but is not limited to, a combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu).

[0055] The manufacturing method of the low-temperature polysilicon thin-film transistor is simple in process. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin-film transistor can be formed without increasing the complexity of the mask and process, thereby achieving the purpose of reducing device leakage. At the same time, it can also improve the channel edge effect of the thin-film transistor and improve the Hump problem.

[0056] See also Fig.11 A low-temperature polysilicon thin film transistor 100 according to an embodiment of the present invention is manufactured by using any of the above-mentioned methods for manufacturing a low-temperature polysilicon thin film transistor.

[0057] Specifically, a low-temperature polysilicon thin film transistor 100 of one embodiment includes a buffer layer (Buffer) 110, an active layer 120, a first gate insulating layer (GI) 130, a gate metal layer (M1) 140, a second gate insulating layer (CI) 150 and an interlayer dielectric layer (ILD) 160 which are stacked in sequence.

[0058] The low temperature polysilicon thin film transistor 100 has a via hole 170 , which sequentially penetrates the interlayer dielectric layer (ILD) 160 , the second gate insulating layer (CI) 150 and the first gate insulating layer (GI) 130 and exposes the active layer 120 .

[0059] The region of the active layer 120 corresponding to the via hole 170 is a heavily doped region 121 , and the doping concentration in the active layer 120 gradually decreases from the heavily doped region 121 to the periphery. In other words, the periphery of the heavily doped region 121 is a lightly doped region 122 .

[0060] On the basis of the above-mentioned embodiment, the active layer 120 further includes a transistor channel region 123 . The transistor channel region 123 is close to the side with lower doping concentration, that is, connected to the lightly doped region 122 .

[0061] In addition, the low-temperature polysilicon thin film transistor 100 further includes a source 180 and a drain 190 , and the source 180 and the drain 190 are connected to the heavily doped region 121 via vias 170 , respectively.

[0062] Based on the above-mentioned embodiment, the via 170 includes a first via 171 and a second via 172 ; the low-temperature polysilicon thin film transistor 100 also includes a source 180 and a drain 190 , the source 180 is connected to the active layer 120 through the first via 171 , and the drain 190 is connected to the active layer 120 through the second via 172 .

[0063] The low-temperature polysilicon thin-film transistor of the technical solution of the present invention can form the LDD (Lightly Doped Drain) structure of the thin-film transistor without increasing the complexity of the mask and process by postponing the heavy doping process of the source and drain and the activation treatment, thereby achieving the purpose of reducing device leakage. At the same time, it can also play a role in improving the channel edge effect of the thin-film transistor and improving the Hump problem.

[0064] A display panel according to one embodiment includes a low-temperature polysilicon thin film transistor manufactured by any of the above-mentioned methods for manufacturing a low-temperature polysilicon thin film transistor, or the above-mentioned low-temperature polysilicon thin film transistor.

[0065] The display panel of the technical solution of the present invention includes the above-mentioned low-temperature polysilicon thin film transistor. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin film transistor can be formed without increasing the mask and process complexity, thereby achieving the purpose of reducing device leakage. At the same time, it can also play a role in improving the channel edge effect of the thin film transistor and improving the Hump problem.

[0066] A display device according to one embodiment includes the above-mentioned display panel.

[0067] The display device of the technical solution of the present invention includes the above-mentioned display panel, and the above-mentioned display panel includes the above-mentioned low-temperature polysilicon thin film transistor. By postponing the source and drain heavy doping process and activation treatment, the LDD structure of the thin film transistor can be formed without increasing the complexity of the mask and process, thereby achieving the purpose of reducing device leakage. At the same time, it can also play a role in improving the channel edge effect of the thin film transistor and improving the Hump problem.

[0068] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a low-temperature polycrystalline silicon thin film transistor, characterized in that: The steps include: An active material layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer are sequentially formed on the buffer layer; forming a via hole, wherein the via hole sequentially penetrates the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer to expose the active material layer; as well as The active material layer and the region corresponding to the via hole are heavily doped, and then activated. After the activation, the doping concentration gradually decreases from the heavily doped region to the periphery to form an active layer.

2. The method for manufacturing a low-temperature polysilicon thin film transistor according to claim 1, characterized in that: The operation of heavily doping the region corresponding to the active material layer and the via hole is: using an ion beam to perform ion implantation on the region corresponding to the active material layer and the via hole, wherein the ion implantation dose is 5E14 / cm 2 ~1E15 / cm 2 .

3. The method for manufacturing a low-temperature polysilicon thin film transistor according to claim 1, characterized in that: The doping element used to heavily dope the region of the active material layer corresponding to the via hole is selected from at least one of boron and phosphorus.

4. The method for manufacturing a low-temperature polysilicon thin film transistor according to claim 1, characterized in that: The activation treatment is performed by heat treatment at 400° C. to 450° C. for 0.5 h to 1 h.

5. The method for manufacturing a low-temperature polysilicon thin film transistor according to claim 1, characterized in that: The active layer further includes a transistor channel region, and the transistor channel region is close to a side with a lower doping concentration.

6. The method for manufacturing a low temperature polysilicon thin film transistor according to claim 1, characterized in that: The via hole comprises a first via hole and a second via hole; The activation treatment further comprises the following steps: A source electrode and a drain electrode are formed on the interlayer dielectric layer, the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole.

7. A low temperature polysilicon thin film transistor, characterized in that: It includes a buffer layer, an active layer, a first gate insulating layer, a gate metal layer, a second gate insulating layer and an interlayer dielectric layer which are stacked in sequence; The low-temperature polysilicon thin film transistor has a via hole, and the via hole penetrates from the interlayer dielectric layer to the first gate insulating layer and exposes the active layer; The area of ​​the active layer corresponding to the via hole is a heavily doped area, and the doping concentration in the active layer gradually decreases from the heavily doped area to the periphery.

8. The low temperature polysilicon thin film transistor according to claim 7, characterized in that: The via hole comprises a first via hole and a second via hole; The low-temperature polysilicon thin film transistor further includes a source electrode and a drain electrode. The source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole.

9. A display panel, characterized in that: A low-temperature polycrystalline silicon thin film transistor manufactured by the method for manufacturing a low-temperature polycrystalline silicon thin film transistor according to any one of claims 1 to 6, or a low-temperature polycrystalline silicon thin film transistor according to claim 7 or 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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