GaN power device with vertical structure and preparation method thereof

Abstract

The invention relates to a vertical structure GaN power device and a preparation method thereof. The vertical structure GaN power device comprises a hard substrate; the protective glue layer, the first source electrode, the gate electrode and the second source electrode are arranged on the hard substrate, and a passivation layer is arranged on the protective glue layer in the peripheral area of the source electrode and the gate electrode; the AlGaN barrier layer, the GaN channel layer and the GaN conducting layer are arranged on the passivation layer, the source electrode and the gate electrode; the first current blocking layer region and the second current blocking layer region extend to a certain depth in the channel layer along the upper surface of the conductive layer, and a current channel is formed between the first current blocking layer region and the second current blocking layer region; the drain electrode is arranged on the conductive layer and the current blocking layer; due to the arrangement of the current blocking layer region, the defects of high cost and low quality of subsequent secondary epitaxial growth caused by the fact that photoetching and other processes are generally required to be introduced due to the formation of the current blocking region during epitaxial growth of a traditional GaN power device with a vertical structure are overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a vertical structure GaN power device and a preparation method thereof. Background Art

[0002] GaN power devices have two structural types: lateral and vertical. People have conducted extensive research on lateral GaN power devices and have made good progress. Its advantages include simple manufacturing process, low conduction and switching losses, etc., while its disadvantage is that the breakdown voltage depends on the distance between the gate and the drain. Therefore, to increase the breakdown voltage of lateral GaN power devices, the size of the device must be increased, which limits its application in high withstand voltage and small size requirements. Unlike lateral GaN power devices where the source, gate and drain are located in the same plane, the source and gate of vertical structure GaN power devices are located in one plane, while the drain is located in the opposite plane. Therefore, to improve the breakdown voltage, the increase in the lateral size of vertical structure GaN power devices is not a limiting factor. However, the traditional vertical structure GaN power devices have high requirements for epitaxial process, and the resulting high cost and low stability limit their wide application. Summary of the invention

[0003] In view of the technical problems existing in the prior art, the primary purpose of the present invention is to provide a vertical structure GaN power device and a preparation method thereof. On the basis of the epitaxial structure of a lateral structure GaN power device, a hard substrate is bonded on the top of the lateral structure GaN power device, and then the growth substrate is peeled off to form a first current blocking region and a second current blocking region on the exposed epitaxial structure side, and a current channel is formed between the first current blocking region and the second current blocking region to form a vertical structure GaN power device. The current blocking region can be formed by a deposition process after etching, or by an ion implantation process, thereby avoiding the disadvantage that the current blocking layer of the traditional vertical structure GaN power device needs to be epitaxially grown twice during epitaxial growth, and the preparation of a vertical structure GaN power device with high stability and low cost is achieved in a relatively simple method.

[0004] In one aspect, the present invention provides a method for preparing a vertical structure GaN power device, comprising the following steps:

[0005] A GaN conductive layer, a GaN channel layer and an AlGaN barrier layer are sequentially grown on a growth substrate to form an epitaxial stack;

[0006] depositing a passivation layer on the AlGaN barrier layer;

[0007] forming a first source electrode, a second source electrode and a gate electrode on the passivation layer to form a front device;

[0008] Attaching the first source electrode, the second source electrode and the gate electrode to a hard substrate on which a protective adhesive layer is spin-coated, and bonding the front device to the hard substrate;

[0009] peeling off the growth substrate to expose the conductive layer;

[0010] A first current blocking layer region and a second current blocking layer region are formed along the upper surface of the conductive layer to a certain depth in the channel layer, wherein a current channel is formed between the first current blocking layer region and the second current blocking layer region;

[0011] A drain electrode is formed on the current blocking layer and the conductive layer.

[0012] Furthermore, the steps of forming a first current blocking layer region and a second current blocking layer region include: etching along the surface of the conductive layer to a certain depth in the channel layer to form a first opening region and a second opening region, and using a magnetron sputtering process, a plasma chemical vapor deposition process or an atomic layer deposition process to deposit current blocking layer material in the first opening region and the second opening region to fill the opening region.

[0013] Furthermore, an ion implantation process is used to form the first current blocking layer region and the second current blocking layer region.

[0014] Furthermore, after depositing the passivation layer and before forming the first source electrode, the second source electrode and the gate electrode on the passivation layer, the method further includes etching the epitaxial stack along the surface of the passivation layer to the surface of the conductive layer adjacent to the growth substrate to form a mesa isolation structure.

[0015] In one aspect, the present invention also provides a vertical structure GaN power device, comprising a hard substrate;

[0016] A protective glue layer, a first source electrode, a gate electrode, and a second source electrode are disposed on the hard substrate, wherein the protective glue layer fills the surrounding areas of the first source electrode, the gate electrode, and the second source electrode;

[0017] A passivation layer is provided on the protective glue layer in the surrounding areas of the first source electrode, the gate electrode and the second source electrode;

[0018] An AlGaN barrier layer disposed on the passivation layer, the first source electrode, the second source electrode and the gate electrode;

[0019] A GaN channel layer disposed on the barrier layer and a GaN conductive layer disposed on the channel layer;

[0020] A first current blocking layer region and a second current blocking layer region extending along the upper surface of the conductive layer to a certain depth in the channel layer, wherein a current channel is formed between the first current blocking layer region and the second current blocking layer region;

[0021] The drain electrode is disposed on the conductive layer and the current blocking layer.

[0022] Furthermore, it also includes a mesa isolation structure arranged along the edge of the power device, and the mesa isolation structure extends along the lower surface of the passivation layer to the surface of the current blocking layer adjacent to the drain.

[0023] Furthermore, the thickness of the protective adhesive layer on the hard substrate at the location of the mesa isolation structure is greater than the thickness of the protective adhesive layer between the passivation layer and the hard substrate;

[0024] The thickness of the passivation layer is smaller than the thickness of the first source electrode, the second source electrode, and the gate electrode.

[0025] Furthermore, the material of the current blocking layer region is AlN, silicon nitride or a high-resistance material formed by ion implantation.

[0026] Furthermore, it also includes an AlN insertion layer disposed between the channel layer and the barrier layer.

[0027] Furthermore, along the direction from the source electrode to the gate electrode, the width of the current channel is smaller than the width of the gate electrode.

[0028] Compared with the prior art, the present invention has at least the following advantages:

[0029] Based on the epitaxial structure of a lateral structure GaN power device, the present invention sets a current blocking layer region in the exposed back region of the device after stripping off the growth substrate, thereby avoiding the disadvantages of high cost and low quality of subsequent secondary epitaxial growth due to the formation of the current blocking region in the epitaxial growth of traditional vertical structure GaN power devices. The material layer of the device of the present invention is formed by one continuous epitaxial growth, and the setting of the first current blocking layer region and the second current blocking region can be formed by etching followed by sputtering, plasma chemical vapor deposition or atomic layer deposition, or by ion implantation after forming a mask pattern on the surface of the conductive layer. No secondary epitaxial growth is required, and the preparation of a vertical structure GaN power device with high stability and low cost is achieved in a relatively simple method, and compared with traditional vertical structure GaN power devices, the device has fewer defects and lower on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of the overall structure of a vertical structure GaN power device in one embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of the structure of a front-end device in one embodiment of the present invention;

[0032] Figure 3 It is a schematic structural diagram of a vertical structure GaN power device epitaxial wafer in one embodiment of the present invention;

[0033] Figure 4 is a structural diagram of depositing a passivation layer in one embodiment of the present invention;

[0034] Figure 5 is a structural diagram of table isolation in one embodiment of the present invention;

[0035] Figure 6 is a structural diagram of a mesa isolation and an evaporation electrode layer in one embodiment of the present invention;

[0036] Figure 7 is a bonding schematic diagram in one embodiment of the present invention;

[0037] Figure 8 is a schematic diagram of a laser lift-off method according to an embodiment of the present invention;

[0038] Fig. 9 is a schematic diagram of the structure after the sapphire substrate is removed in one embodiment of the present invention;

[0039] Fig.10 is a schematic diagram of a structure in which an AlN current blocking layer is formed by sputtering in one embodiment of the present invention;

[0040] Fig.11 It is a structural diagram of a vertical structure GaN power device made by evaporating the drain in one embodiment of the present invention. DETAILED DESCRIPTION

[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings of the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention. The experimental methods described in the following embodiments are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, can be obtained from public commercial channels.

[0042] Spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures.

[0043] In addition, the use of terms such as "first", "second", etc. to describe various elements, layers, regions, sections, etc. is not intended to be limiting. The use of "having", "containing", "including", "comprising", etc. is open-ended, indicating the presence of the stated elements or features, but does not exclude additional elements or features. Unless the context clearly states otherwise.

[0044] The first surface (upper surface) refers to, for example, the surface of the temporary substrate facing the drain in a vertical structure device, or the surface of the growth substrate facing the source electrode and the gate electrode in a front device; the second surface (lower surface) is arranged opposite to the first surface.

[0045] The present invention provides a vertical structure GaN power device, which includes a hard substrate (temporary hard substrate), a protective glue layer, a first source electrode, a second source electrode, a gate electrode, a passivation layer, an AlGaN barrier layer, a GaN channel layer, a GaN conductive layer, a current blocking layer and a drain electrode. The hard substrate is, for example, a suitable hard substrate such as a silicon substrate, which is not specifically limited here.

[0046] The protective glue layer, the first source electrode, the second source electrode and the gate electrode are arranged on the first surface of the hard substrate, the protective glue layer fills the surrounding areas of the first source electrode, the second source electrode and the gate electrode, and the first source electrode and the second source electrode are located on both sides of the gate electrode.

[0047] The passivation layer is arranged around the first source electrode, the gate electrode and the second source electrode, and the first surface of the passivation layer is flush with the first surfaces of the first source electrode, the second source electrode and the gate electrode. The AlGaN barrier layer is arranged on the first surfaces of the passivation layer, the first source electrode, the gate electrode and the second source electrode, and the gate electrode is located at the center of the second surface of the AlGaN barrier layer.

[0048] The GaN channel layer is located on the first surface of the AlGaN barrier layer, and the GaN conductive layer is located on the first surface of the GaN channel layer. Figure 1 It is shown that an AlN insertion layer is arranged between the GaN channel layer and the AlGaN barrier layer.

[0049] The first current blocking layer region and the second current blocking layer region are located on both sides of the device, extending along the first surface of the GaN conductive layer to a certain depth in the GaN channel layer, for example, the distance between the lower surface of the first and second current blocking layer regions and the lower surface of the channel layer is 100nm to 200nm. The GaN conductive layer and the GaN channel layer region enclosed between the first current blocking layer region and the second current blocking layer region constitute a current channel of a vertical structure. The current channel is located directly above the gate, and in the direction from the first source to the second source, the width of the current channel is less than the width of the gate.

[0050] The edge of the device is provided with a mesa isolation structure, which extends along the second surface of the passivation layer to the first surface of the current blocking layer. The thickness of the protective glue layer located on the first surface of the hard substrate in the mesa isolation structure area is greater than the thickness of the first source electrode, the gate electrode and the second source electrode, and wraps part of the side wall of the mesa isolation structure. Figure 2 As shown, after an epitaxial stack is grown on a growth substrate such as a sapphire substrate, a passivation layer is deposited and an electrode pattern is formed by etching. After the electrode is formed, the electrode side is pressed onto a hard substrate spin-coated with a protective adhesive layer through a bonding process. The protective adhesive layer is filled between the electrodes, adhered to the surface of the electrode and the passivation layer, and wrapped around part of the side wall of the mesa isolation structure to support the epitaxial stack.

[0051] The material of the first current blocking layer region and the second current blocking layer region is, for example, a material with good insulation properties such as AlN and silicon nitride, or a high-resistance material formed by ion implantation.

[0052] The drain electrode is arranged on the first current blocking layer region, the second current blocking layer region and the GaN conductive layer.

[0053] The present invention also provides a method for preparing the vertical structure GaN power device, comprising the following steps:

[0054] A GaN conductive layer, a GaN channel layer, and an AlGaN barrier layer are sequentially grown on a growth substrate to form an epitaxial stack. In a preferred embodiment, an AlN insertion layer is also grown between the GaN channel layer and the AlGaN barrier layer. The growth of each epitaxial layer is performed using a metal organic chemical vapor deposition (MOCVD) process. Specifically, Figure 3 As shown, a 200nm GaN conductive layer, a 900nm GaN channel layer, a 1.25nm AlN insertion layer, and a 20nm AlGaN barrier layer are sequentially grown on a sapphire substrate to obtain an epitaxial wafer of a vertical structure GaN power device.

[0055] like Figure 4 As shown, a passivation layer is deposited on the AlGaN barrier layer. Specifically, a 200 nm Si3N4 layer is deposited on the surface of the AlGaN barrier layer of the epitaxial wafer using a plasma chemical vapor deposition (PECVD) process as a passivation layer.

[0056] The epitaxial stack is etched along the surface of the passivation layer to the surface of the growth substrate. Figure 5 As shown, a mesa isolation pattern is patterned on the surface of the passivation layer by photolithography, and an inductively coupled plasma (ICP) is used to etch a mesa isolation structure, with a depth extending from the upper surface of the passivation layer to the lower surface of the GaN conductive layer.

[0057] Then, if Figure 6As shown, the source electrode pattern is patterned by photolithography on the surface of the passivation layer, and the source electrode of Ti / Al / Ni / Au (20 / 130 / 50 / 100nm) is evaporated by electron beam evaporation (EBL), that is, the source electrode includes a 20nm Ti layer, a 130nm Al layer, a 50nm Ni layer and a 100nm Au layer arranged in sequence from top to bottom, and the Au layer is in contact with the barrier layer. After the source electrode is deposited, annealing treatment is performed at 850℃ for 30s; the gate electrode pattern is patterned by photolithography on the surface of the passivation layer, and the gate electrode evaporated by electron beam evaporation is Ni / Au (50 / 180nm), that is, the gate electrode includes a 50nm Ni layer and a 180nm Au layer arranged in sequence from top to bottom, and a sapphire substrate front device is obtained.

[0058] Then, the first source electrode, the second source electrode and the gate electrode are attached to a hard substrate on which a protective glue layer is spin-coated, and the sapphire substrate front device is bonded to the hard substrate. Figure 7 As shown, specifically, a Si substrate is selected as a temporary hard substrate, and a protective glue layer is spin-coated on the Si substrate. The spin coating process is 500 rpm for 5 s and then 2000 rpm for 30 s. The thickness of the spin-coated glue is 1 μm. Subsequently, it is heated on a 300°C hot stage for 5 min to complete curing. The bonding parameters are 200°C and 500N.

[0059] The growth substrate is then peeled off to expose the conductive layer. Figure 8 As shown, the bonded device is placed in a polishing machine to complete the polishing of the sapphire substrate for laser stripping. The polished epitaxial wafer is placed in a laser stripping device, the laser wavelength is 248nm KrF excimer laser, the photon energy is in the range of 3.50-5.00eV, which is lower than the band gap energy of sapphire 9.9eV, but higher than GaN 3.44eV, to ensure that the laser energy is absorbed by the GaN layer, generating Ga metal and nitrogen, and the nitrogen causes cracks in the GaN layer and the sapphire substrate, achieving sapphire substrate stripping, and obtaining Fig. 9 The device structure shown is a GaN conductive layer exposed after the sapphire substrate is peeled off.

[0060] A first current blocking layer region and a second current blocking layer region are formed, the first current blocking layer region and the second current blocking layer region extend along the surface of the conductive layer to a certain depth in the channel layer, and a current channel is formed between the first current blocking layer region and the second current blocking layer region.

[0061] like Fig.10As shown, in one embodiment, the current blocking layer region is made of AlN material. First, a pattern of a patterned current blocking layer is formed on the GaN conductive layer by photolithography. An inductively coupled plasma (ICP) etching process is used to etch along the upper surface of the GaN conductive layer to a certain depth in the GaN channel layer to form a first opening region and a second opening region. The depth of the opening region is 1 μm. Then, a magnetron sputtering coater is used to sputter AlN to fill the first opening region and the second opening region to form a first current blocking layer region and a second current blocking layer region.

[0062] In another embodiment, a pattern of a current blocking layer region is formed on the GaN conductive layer, and an ion implantation process is used to destroy the crystal periodicity of the GaN conductive layer and the GaN channel layer in the pattern region to realize a high resistance region, thereby forming a first current blocking layer region and a second current blocking layer region, and the first current blocking layer region and the second current blocking layer region extend along the upper surface of the conductive layer to a certain depth in the channel layer. For example, Mg ion implantation is used to form the high resistance region.

[0063] A drain electrode is formed on the current blocking layer and the conductive layer. Fig.11 As shown, the drain electrode pattern is patterned by photolithography on the surface of the GaN conductive layer and the current blocking layer, and the Ti / Al / Ni / Au (20 / 130 / 50 / 100nm) source electrode is evaporated by electron beam evaporation (EBL), that is, the source electrode includes a 20nm Ti layer, a 130nm Al layer, a 50nm Ni layer and a 100nm Au layer arranged in sequence from top to bottom. After the source electrode is deposited, annealing treatment is performed at 850°C for 30s to obtain the vertical structure GaN power device.

[0064] The vertical structure GaN power device and the preparation method thereof provided by the present invention are based on the epitaxial structure of the lateral structure GaN power device, and a hard substrate is combined on the source electrode and the gate electrode side by protective glue, and after the growth substrate is peeled off, a first current blocking layer region and a second current blocking layer region are formed from the exposed GaN conductive layer surface to a certain depth in the GaN channel layer, and a current channel is formed between the first current blocking layer region and the second current blocking layer region, thereby constituting a vertical structure GaN power device. The current blocking layer region can be set by etching the GaN conductive layer to a certain depth in the GaN channel layer to form an opening region, and then formed by sputtering, atomic layer deposition or plasma chemical vapor deposition process, or by forming a mask pattern on the upper surface of the conductive layer, and then formed by ion implantation. This setting method avoids the disadvantage that the current blocking layer of the traditional vertical structure GaN power device needs secondary epitaxial growth during epitaxial growth, and realizes the preparation of a vertical structure GaN power device with high stability and low cost by a relatively simple method.

[0065] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A method for preparing a vertical structure GaN power device, characterized in that: The following steps are involved: A GaN conductive layer, a GaN channel layer and an AlGaN barrier layer are sequentially grown on a growth substrate to form an epitaxial stack; depositing a passivation layer on the AlGaN barrier layer; forming a first source electrode, a second source electrode and a gate electrode on the passivation layer to form a front device; Attaching the first source electrode, the second source electrode and the gate electrode to a hard substrate on which a protective adhesive layer is spin-coated, and bonding the front device to the hard substrate; peeling off the growth substrate to expose the conductive layer; A first current blocking layer region and a second current blocking layer region are formed along the upper surface of the conductive layer to a certain depth in the channel layer, wherein a current channel is formed between the first current blocking layer region and the second current blocking layer region; A drain electrode is formed on the current blocking layer and the conductive layer.

2. The preparation method according to claim 1, characterized in that: The steps of forming a first current blocking layer region and a second current blocking layer region include: etching along the surface of the conductive layer to a certain depth in the channel layer to form a first opening region and a second opening region, and using a magnetron sputtering process, a plasma chemical vapor deposition process or an atomic layer deposition process to deposit current blocking layer material in the first opening region and the second opening region to fill the opening region.

3. The preparation method according to claim 1, characterized in that: An ion implantation process is used to form a first current blocking layer region and a second current blocking layer region.

4. The preparation method according to any one of claims 1 to 3, characterized in that: After depositing the passivation layer and before forming the first source electrode, the second source electrode and the gate electrode on the passivation layer, the method further includes etching the epitaxial stack along the surface of the passivation layer to the surface of the conductive layer adjacent to the growth substrate to form a mesa isolation structure.

5. A vertical structure GaN power device, characterized in that: including a hard substrate; A protective glue layer, a first source electrode, a gate electrode, and a second source electrode are disposed on the hard substrate, wherein the protective glue layer fills the surrounding areas of the first source electrode, the gate electrode, and the second source electrode; A passivation layer is provided on the protective glue layer in the surrounding areas of the first source electrode, the gate electrode and the second source electrode; An AlGaN barrier layer disposed on the passivation layer, the first source electrode, the second source electrode and the gate electrode; A GaN channel layer disposed on the barrier layer and a GaN conductive layer disposed on the channel layer; A first current blocking layer region and a second current blocking layer region extending along the upper surface of the conductive layer to a certain depth in the channel layer, wherein a current channel is formed between the first current blocking layer region and the second current blocking layer region; The drain electrode is disposed on the conductive layer and the current blocking layer.

6. The power device according to claim 5, characterized in that: It also includes a mesa isolation structure arranged along the edge of the power device, wherein the mesa isolation structure extends along the lower surface of the passivation layer to the surface of the current blocking layer adjacent to the drain electrode.

7. The preparation method according to claim 4 or the power device according to claim 5 or 6, characterized in that: The thickness of the protective adhesive layer on the hard substrate at the mesa isolation structure position is greater than the thickness of the protective adhesive layer between the passivation layer and the hard substrate; The thickness of the passivation layer is smaller than the thickness of the first source electrode, the second source electrode, and the gate electrode.

8. The preparation method according to claim 4 or the power device according to claim 7, characterized in that: The material of the current blocking layer region is AlN, silicon nitride or a high-resistance material formed by ion implantation.

9. The preparation method according to claim 8 or the power device according to claim 8, characterized in that: Also included is an AlN insertion layer disposed between the channel layer and the barrier layer.

10. The preparation method according to any one of claims 7 to 9 or the power device according to any one of claims 7 to 9, characterized in that: Along the direction from the source electrode to the gate electrode, the width of the current channel is smaller than the width of the gate electrode.

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