SIP (Session Initiation Protocol) packaged power supply anti-reversion device and packaging manufacturing method thereof

Abstract

The invention relates to the technical field of power supply anti-reversion devices, and discloses an SIP packaged power supply anti-reversion device and a packaging manufacturing method thereof, and the power supply anti-reversion device comprises a first electrode, a second electrode, a ceramic metal substrate, a plurality of bare Mos chips, and a printed circuit board provided with a passive device. According to the invention, the bare Mos chip is adopted to replace a discrete Mos chip adopted by a known power supply anti-reversion device in the prior art, so that the manufacturing cost of the power supply anti-reversion device is reduced, and the heat dissipation capability of the power supply anti-reversion device is improved; according to the invention, the copper clamp is used as an interconnection structure between two adjacent bare core Mos chips, and the interconnection resistance between the two bare core Mos chips can be effectively reduced, so that the conduction resistance can be reduced, and the heating and power consumption of the bare core Mos chips can be reduced; the SIP packaging scheme is adopted to package and manufacture the power supply anti-reversion device, which is more beneficial to the compact and miniaturized design of the power supply anti-reversion device.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply anti-reverse devices, and in particular to a power supply anti-reverse device of a SIP package and a packaging manufacturing method thereof. Background Art

[0002] The contents in this section merely provide background information related to the present invention and may not constitute prior art.

[0003] Mosfet power reverse protection is a circuit device that uses a field effect transistor (Mosfet) to prevent the power polarity from being reversed. It is widely used in portable electronic products, industrial equipment, automotive electronic systems and other fields.

[0004] At present, the Mosfet power anti-reverse device is generally manufactured by board-level modular packaging (also known as T2-level packaging). In this type of packaging solution, the already packaged discrete Mos plastic-encapsulated components (also known as packaged discrete Mos chips), control chips, capacitors, resistors and other devices are usually welded on the PCB printed circuit board through electronic assembly to complete the board-level assembly; then, the printed circuit board is mounted on a ceramic metal substrate in a cavity, and the printed circuit board is fixed in the cavity with a fixing glue.

[0005] As for the power supply anti-reverse device packaged and manufactured using the above-mentioned packaging scheme, although it has the characteristics of easy implementation and low manufacturing difficulty, the power supply anti-reverse device packaged and manufactured using this type of packaging scheme generally has problems such as large on-resistance, long heat dissipation path, poor heat dissipation effect of MOS chip, large assembly volume, and high packaging cost. Summary of the invention

[0006] In view of this, the first object of the present invention is to provide a SIP packaged power anti-reverse device, in order to solve the problems of large on-resistance, long heat dissipation path, poor heat dissipation effect of MOS chip, large assembly volume, high packaging cost, etc. in the power anti-reverse device packaged and manufactured using the board-level modular packaging solution. The second object of the present invention is to provide a method for packaging and manufacturing the SIP packaged power anti-reverse device.

[0007] The purpose of the present invention is achieved through the following technical solutions:

[0008] In one aspect, the present invention discloses a SIP packaged power supply anti-reverse device, comprising:

[0009] a first electrode;

[0010] a second electrode, the polarity of the second electrode being opposite to the polarity of the first electrode;

[0011] A ceramic metal substrate, wherein a heat sink is provided on the ceramic metal substrate;

[0012] A plurality of bare core MOS chips are arranged side by side on one side of the ceramic metal substrate and connected to the heat sink on the ceramic metal substrate; the source electrodes of two adjacent bare core MOS chips are interconnected by a copper clip, and the copper clip is interconnected with the first electrode;

[0013] A printed circuit board with passive components is provided, and the printed circuit board is arranged on the other side of the ceramic metal substrate; wire bonding is performed between the plurality of bare core MOS chips and the printed circuit board, between the passive components on the printed circuit board, and between the printed circuit board and the second electrode.

[0014] Furthermore, the power supply anti-reverse device also includes a protective shell, and the protective shell includes a shell body and a cover body;

[0015] The shell defines an upwardly open accommodation cavity, the accommodation cavity is provided with an upwardly open accommodation groove, the ceramic metal substrate defines the bottom wall of the accommodation groove, a plurality of the bare core MOS chips and the printed circuit board are accommodated in the accommodation groove, and the first electrode and the second electrode are arranged in the accommodation cavity beside the accommodation groove;

[0016] The cover is configured to seal the opening of the accommodating cavity.

[0017] Furthermore, a conductive transition sheet is provided between the printed circuit board and the second electrode, and the printed circuit board is bonded to the second electrode through the conductive transition sheet.

[0018] On the other hand, the present invention discloses a method for packaging and manufacturing a power anti-reverse device of the SIP package as described above, the method comprising the following steps:

[0019] Step S1. Sintering a plurality of the bare-die MOS chips on one side of the ceramic-metal substrate; wherein the plurality of the bare-die MOS chips are arranged side by side on the ceramic-metal substrate;

[0020] Step S2. Welding a copper clip between the source electrodes of two adjacent bare core MOS chips so that the two adjacent bare core MOS chips are interconnected; and the copper clip is interconnected with the first electrode;

[0021] Step S3. bonding the printed circuit board provided with the passive components to the other side of the ceramic metal substrate;

[0022] Step S4. According to the power anti-reverse circuit of the power anti-reverse device, wires are used to complete bonding between the plurality of bare core MOS chips and the printed circuit board, between the passive components on the printed circuit board, and between the printed circuit board and the second electrode.

[0023] Furthermore, in step S1, the process of sintering the plurality of bare core MOS chips on the ceramic metal substrate adopts a nano-silver sintering process.

[0024] Furthermore, in step S2, the solder used to solder the copper clip on the source electrode of each bare core MOS chip is high-lead solder.

[0025] Furthermore, the passive components on the printed circuit board include a control chip and a capacitor. The control chip is bonded to the printed circuit board via conductive silver glue. The capacitor is soldered to the printed circuit board. The solder used for soldering the capacitor is SAC305 solder.

[0026] Furthermore, in step S4, the lead wire used for bonding is a gold wire with a diameter of 25 μm.

[0027] Furthermore, the method further comprises the steps of:

[0028] Step S5. Weld the cover body to the shell to seal the opening of the accommodating cavity on the shell through the cover body.

[0029] Furthermore, in step S5, the cover is welded to the shell by parallel sealing welding, and during the welding process, the cover and the shell are placed in a nitrogen atmosphere.

[0030] The technical solution of the embodiment of the present invention has at least the following advantages and beneficial effects:

[0031] 1. The power backlash preventer disclosed in the present invention adopts a bare core MOS chip to replace the discrete MOS chip used in the power backlash preventer known in the prior art, and directly sinters the bare core MOS chip on a ceramic metal substrate, which is conducive to reducing the manufacturing cost of the power backlash preventer. At the same time, by directly connecting the bare core MOS chip to the heat sink on the ceramic metal substrate, it is conducive to shortening the heat conduction path of the bare core MOS chip and improving the heat dissipation capacity of the bare core MOS chip.

[0032] 2. The power reverse protector disclosed in the present invention adopts a copper clip as the interconnection structure between two adjacent bare-core MOS chips. Compared with the known power reverse protector in the prior art that uses a printed circuit board wire to connect two adjacent discrete MOS chips, it can effectively reduce the interconnection resistance between the two bare-core MOS chips, thereby reducing the on-resistance and reducing the heat generation and power consumption of the bare-core MOS chips. Compared with thick aluminum wires, the use of copper clips can also help improve the current carrying capacity, and has the advantages of simple process and low cost.

[0033] 3. The present invention adopts the SIP packaging solution to package and manufacture the power anti-reverse device, which can effectively reduce the packaging size, thickness and weight of the power anti-reverse device, thereby being more conducive to the compact and miniaturized design of the power anti-reverse device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a power supply anti-reverse device in a SIP package provided by an embodiment of the present invention;

[0035] Figure 2 for Figure 1 The internal structure diagram of the SIP packaged power anti-reverse device after removing the cover body is shown in FIG.

[0036] Figures 3A-3D for Figure 2 The packaging manufacturing flow chart of the SIP package power reverse protector is shown.

[0037] Icon: 10-protective shell, 11-shell, 111-accommodating cavity, 112-accommodating groove, 12-cover, 20-bare core Mos chip, 30-printed circuit board, 31-control chip, 32-first capacitor, 33-second capacitor, 34-third capacitor, 40-first electrode, 50-second electrode, 60-ceramic metal substrate, 70-copper clip, 80-conductive transition piece. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described in conjunction with specific implementation methods below. The same figure marks in the accompanying drawings represent the same components. It should be noted that the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Compared to the embodiments shown in the drawings, feasible embodiments within the scope of the present invention may have fewer components, other components not shown in the drawings, different components, differently arranged components, or differently connected components, etc. In addition, two or more components in the drawings may be implemented in a single component, or a single component shown in the drawings may be implemented as multiple separate components.

[0040] In the first aspect, an embodiment of the present invention discloses a power backlash preventer, and in particular, can be a power backlash preventer manufactured based on a system in packaging (SIP) solution, in order to solve the problems of large on-resistance, long heat dissipation path, poor heat dissipation effect of MOS chip, large assembly volume, high packaging cost, etc. existing in the power backlash preventer manufactured by adopting a board-level modular packaging solution in the prior art.

[0041] like Figure 1 and Figure 2 As shown, Figure 1 FIG. 4 shows the appearance of an exemplary power reverse protection device disclosed in this embodiment. Figure 2 The internal structure of the power reverse protection device is shown. Figure 1 and Figure 2 In the power reverse protection device shown, the power reverse protection device may include a protective shell 10, a plurality of bare core MOS chips 20, and a printed circuit board 30 provided with passive components.

[0042] In this embodiment, the protective shell 10 is used to provide a carrier for the installation of multiple bare core MOS chips 20 and printed circuit boards 30 and other components. Figure 1 and Figure 2 As shown, the protective shell 10 may include a shell 11 and a cover 12 , the shell 11 defines an upwardly open accommodation cavity 111 , and a plurality of bare core MOS chips 20 and a printed circuit board 30 are accommodated in the accommodation cavity 111 .

[0043] At the same time, an upwardly open receiving groove 112 can be further provided in the receiving cavity 111. When the power anti-reverse device packaging is completed, multiple bare core MOS chips 20 and a printed circuit board 30 can be accommodated in the receiving groove 112 to further optimize the structural design of the power anti-reverse device.

[0044] like Figure 2As shown, the power reverse preventer may further include a first electrode 40 and a second electrode 50, and the first electrode 40 and the second electrode 50 may be arranged side by side in the accommodation cavity 111 located beside the accommodation groove 112. The polarity of the first electrode 40 is opposite to the polarity of the second electrode 50. For example, the first electrode 40 may be a positive electrode or a negative electrode, and when the first electrode 40 is a positive electrode, the second electrode 50 is a negative electrode; when the first electrode 40 is a negative electrode, the second electrode 50 is a positive electrode.

[0045] The cover 12 is configured to seal the opening of the accommodating cavity 111. Specifically, after the plurality of bare core MOS chips 20 and the printed circuit board 30 are accommodated and packaged in the accommodating groove 112, the cover 12 can be welded to the housing 11 by welding or the like, so as to seal the opening of the accommodating cavity 111 through the cover 12, thereby providing protection for the plurality of bare core MOS chips 20 and the printed circuit board 30 and other components through the relatively closed accommodating cavity 111.

[0046] Furthermore, the power supply anti-reverse device may also include a ceramic metal substrate 60, which defines the bottom wall of the receiving groove 112. In other words, the bottom wall of the receiving groove 112 is the ceramic metal substrate 60. Among them, multiple bare core MOS chips 20 can be arranged side by side on one side of the ceramic metal substrate 60, and the printed circuit board 30 can be arranged on the other side of the ceramic metal substrate 60. For example, in Figure 2 or Figure 3C In the state shown, a plurality of bare core MOS chips 20 can be arranged side by side on the left side of the ceramic metal substrate 60, and the printed circuit board 30 can be arranged on the right side of the ceramic metal substrate 60. For example, the drawings of this embodiment show a situation where three bare core MOS chips 20 are arranged on the ceramic metal substrate 60. Of course, the number of bare core MOS chips 20 is not limited thereto, and the specific number can be configured according to the power anti-reverse circuit of the power anti-reverse device.

[0047] At the same time, the ceramic metal substrate 60 has a heat sink (not shown in the figure) suitable for absorbing and dissipating heat, and the multiple bare core MOS chips 20 arranged on the ceramic metal substrate 60 are connected to the heat sink on the ceramic metal substrate 60. Among them, the multiple bare core MOS chips 20 can be sintered on the ceramic metal substrate 60 by a process such as sintering, so that the multiple bare core MOS chips 20 are connected to the heat sink on the ceramic metal substrate 60.

[0048] It can be understood that this embodiment uses a bare core MOS chip 20 to replace the discrete MOS chip used in the power anti-reverse device known in the prior art, and directly sinters the bare core MOS chip 20 on the ceramic metal substrate 60, which is conducive to reducing the manufacturing cost of the power anti-reverse device. At the same time, by directly connecting the bare core MOS chip 20 to the heat sink on the ceramic metal substrate 60, it is conducive to shortening the heat conduction path of the bare core MOS chip 20 and improving the heat dissipation capacity of the bare core MOS chip 20.

[0049] Further, continue to refer to Figure 2 or Figure 3C , the power anti-reverse device disclosed in this embodiment may also include a copper clip 70 (Cu-Clip). Among the multiple bare core Mos chips 20, the source electrodes of two adjacent bare core Mos chips 20 are connected by the copper clip 70, so that the source electrodes of the two adjacent bare core Mos chips 20 are interconnected by the copper clip 70. In addition, one end of the copper clip 70 can be connected to the first electrode 40, so that the copper clip 70 and the first electrode 40 are interconnected. It is worth noting that in actual implementation, the polarity of the first electrode 40 should be determined according to the type of the bare core Mos chip 20. For example, when the bare core Mos chip 20 is an NMos tube, the first electrode 40 is usually a negative electrode, and when the bare core Mos chip 20 is a PMos tube, the first electrode 40 is usually a positive electrode. For example, the bare core Mos chip described in this embodiment can be an NMos tube, in which case the first electrode 40 is a negative electrode and the second electrode 50 is a positive electrode.

[0050] It can be understood that the power reverse protector disclosed in this embodiment uses a copper clip 70 as an interconnection structure between two adjacent bare core MOS chips 20. Compared with the known power reverse protector in the prior art that uses a printed circuit board conductor (generally a thick aluminum wire) to connect two adjacent discrete MOS chips, it can effectively reduce the interconnection resistance between the two bare core MOS chips 20, thereby reducing the on-resistance and reducing the heat generation and power consumption of the bare core MOS chips 20. Compared with the thick aluminum wire, the use of the copper clip 70 also helps to improve the current carrying capacity, and has the advantages of simple process and low cost.

[0051] Combination Figure 2 As shown, the printed circuit board 30 located beside the multiple bare core MOS chips 20 can be a component bonded to the ceramic metal substrate 60. After the printed circuit board 30 is bonded to the ceramic metal substrate 60, the multiple bare core MOS chips 20 can be bonded (ie, electrically connected) to predetermined positions on the printed circuit board 30 using wires such as gold wires according to the power anti-reverse circuit of the power anti-reverse device, and the printed circuit board 30 is also bonded to the second electrode 50 through wires.

[0052] Typically, the passive components on the printed circuit board 30 may include control chips 31, capacitors, and other components. Figure 2 In the power anti-reverse device shown, the printed circuit board 30 may include a control chip 31, a first capacitor 32, a second capacitor 33 and a third capacitor 34. Among them, the control chip 31 can be a component bonded to the printed circuit board 30, and the first capacitor 32, the second capacitor 33 and the third capacitor 34 can be components welded on the printed circuit board 30. In addition, the control chip 31, the capacitor and other components on the printed circuit board 30 can be wire-bonded according to the power anti-reverse circuit of the power anti-reverse device. It should be noted that in actual implementation, the types and / or quantities of passive components on the printed circuit board 30 are not limited thereto, and the specific types and / or quantities can be configured according to the power anti-reverse circuit of the power anti-reverse device.

[0053] Continue to refer to Figure 2 A conductive transition piece 80 may also be provided in the accommodation cavity 111 between the printed circuit board 30 and the second electrode 50, and the printed circuit board 30 is bonded to the second electrode 50 through the conductive transition piece 80. That is, the printed circuit board 30 is bonded to the conductive transition piece 80, and the conductive transition piece 80 is further bonded to the second electrode 50. By providing the conductive transition piece 80, it is helpful to reduce the length of the lead wire required to bond the printed circuit board 30 to the second electrode 50.

[0054] On the other hand, an embodiment of the present invention further discloses a packaging and manufacturing method of the power anti-reverse device as described above, so as to more clearly and intuitively understand the packaging and manufacturing process of the power anti-reverse device.

[0055] Specifically, the packaging manufacturing method disclosed in this embodiment may include the following steps:

[0056] Step S1. Figure 3A As shown, a plurality of bare-die MOS chips 20 may be sintered on one side, such as the left side, of the ceramic metal substrate 60 by using a nano-silver sintering process. The plurality of bare-die MOS chips 20 may be arranged side by side on the ceramic metal substrate 60 .

[0057] Step S2. Figure 3B As shown, a copper clip 70 is welded between the source electrodes of two adjacent bare core MOS chips 20 to form an interconnection between the two adjacent bare core MOS chips 20. In addition, one end of the copper clip 70 can be welded to the first electrode 40 to form an interconnection between the copper clip 70 and the first electrode 40. For example, one end of the copper clip 70 close to the first electrode 40 can be welded to the first electrode 40 to optimize the structural design of the power anti-reverse device as much as possible.

[0058] The solder used when welding the copper clip 70 on the source electrode of each bare core MOS chip 20 can be high-lead solder to ensure good welding quality.

[0059] Step S3. Figure 3C As shown, the printed circuit board 30 provided with passive components may be bonded to the other side, for example, the right side, of the ceramic metal substrate 60 using conductive adhesive.

[0060] In combination with the above, the passive components on the printed circuit board 30 may include a control chip 31, a first capacitor 32, a second capacitor 33, and a third capacitor 34. Among them, the control chip 31 may be bonded to a predetermined position on the printed circuit board 30 by using conductive silver glue, and each capacitor may be welded to a predetermined position on the printed circuit board 30 by welding, and the solder used for welding each capacitor may be SAC305 solder.

[0061] Step S4. After the multiple bare core MOS chips 20 and the printed circuit board 30 are installed in place, according to the power anti-reverse circuit of the power anti-reverse device, the bonding between the multiple bare core MOS chips 20 and the printed circuit board 30, between the passive components on the printed circuit board 30, and between the printed circuit board 30 and the second electrode 50 is completed by using leads. The bonding between the printed circuit board 30 and the second electrode 50 can specifically include: bonding between the printed circuit board 30 and the conductive transition piece 80, and bonding between the conductive transition piece 80 and the second electrode 50. Among them, the lead used for bonding can be a gold wire of φ25μm.

[0062] Step S5. Figure 3D As shown, after completing the bonding process described in step S4, the cover 12 of the protective shell 10 is welded to the shell 11, so as to seal the opening of the accommodating cavity 111 on the shell 11 through the cover 12. The cover 12 can be welded to the shell 11 by a parallel sealing welding method, and during the welding process, the cover 12 and the shell 11 should be placed in a nitrogen atmosphere to effectively improve the welding quality of the cover 12.

[0063] Thus, the purpose of packaging and manufacturing the power anti-reverse device disclosed in the above embodiment has been achieved. Moreover, the power anti-reverse device packaged and manufactured by the packaging and manufacturing method has at least the beneficial effects of the power anti-reverse device described above.

[0064] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A SIP packaged power supply anti-reverse device, characterized in that: include: a first electrode; a second electrode, the polarity of the second electrode being opposite to the polarity of the first electrode; A ceramic metal substrate, wherein a heat sink is provided on the ceramic metal substrate; A plurality of bare core MOS chips are arranged side by side on one side of the ceramic metal substrate and connected to the heat sink on the ceramic metal substrate; the source electrodes of two adjacent bare core MOS chips are interconnected by a copper clip, and the copper clip is interconnected with the first electrode; A printed circuit board with passive components is provided, and the printed circuit board is arranged on the other side of the ceramic metal substrate; wire bonding is performed between the plurality of bare core MOS chips and the printed circuit board, between the passive components on the printed circuit board, and between the printed circuit board and the second electrode.

2. The SIP packaged power supply anti-reverse device according to claim 1, characterized in that: Also included is a protective shell, the protective shell comprising a shell body and a cover body; The shell defines an upwardly open accommodation cavity, the accommodation cavity is provided with an upwardly open accommodation groove, the ceramic metal substrate defines the bottom wall of the accommodation groove, a plurality of the bare core MOS chips and the printed circuit board are accommodated in the accommodation groove, and the first electrode and the second electrode are arranged in the accommodation cavity beside the accommodation groove; The cover is configured to seal the opening of the accommodating cavity.

3. The SIP packaged power supply anti-reverse device according to claim 1, characterized in that: A conductive transition sheet is provided between the printed circuit board and the second electrode, and the printed circuit board is bonded to the second electrode through the conductive transition sheet.

4. A method for packaging and manufacturing a power anti-reverse device of a SIP package as claimed in claim 2, characterized in that: The following steps are involved: Step S1. Sintering a plurality of the bare-die MOS chips on one side of the ceramic-metal substrate; wherein the plurality of the bare-die MOS chips are arranged side by side on the ceramic-metal substrate; Step S2. Welding a copper clip between the source electrodes of two adjacent bare core MOS chips so that the two adjacent bare core MOS chips are interconnected; and the copper clip is interconnected with the first electrode; Step S3. bonding the printed circuit board provided with the passive components to the other side of the ceramic metal substrate; Step S4. According to the power anti-reverse circuit of the power anti-reverse device, wires are used to complete bonding between the plurality of bare core MOS chips and the printed circuit board, between the passive components on the printed circuit board, and between the printed circuit board and the second electrode.

5. The method for packaging and manufacturing a power anti-reverse device of a SIP package according to claim 4, characterized in that: In step S1, a process of sintering a plurality of the bare core MOS chips on the ceramic metal substrate adopts a nano-silver sintering process.

6. The method for packaging and manufacturing a power anti-reverse device of a SIP package according to claim 4, characterized in that: In step S2, the solder used when soldering the copper clip on the source electrode of each bare core MOS chip is high-lead solder.

7. The method for packaging and manufacturing a power backlash protector of a SIP package according to claim 4, characterized in that: The passive components on the printed circuit board include a control chip and a capacitor. The control chip is bonded to the printed circuit board through conductive silver glue. The capacitor is welded on the printed circuit board. The solder used for welding the capacitor is SAC305 solder.

8. The method for packaging and manufacturing a power backlash protector of a SIP package according to claim 4, characterized in that: In step S4, the lead wire used for bonding is a gold wire with a diameter of 25 μm.

9. The method for packaging and manufacturing a power backlash protector of a SIP package according to claim 4, characterized in that: Also includes the steps: Step S5. Weld the cover body to the shell to seal the opening of the accommodating cavity on the shell through the cover body.

10. The method for packaging and manufacturing a power backlash protector of a SIP package according to claim 9, characterized in that: In step S5, the cover is welded to the shell by parallel sealing welding, and during the welding process, the cover and the shell are placed in a nitrogen atmosphere.

Images