High-speed bootstrap switch with fast conduction path
By introducing a fast conduction circuit into the traditional gate voltage bootstrap switch, the problem of the sharing capacitance effect between parasitic capacitors and bootstrap capacitors at high speed sampling rate is solved, and faster gate voltage establishment and smaller circuit size are achieved, reducing power consumption and area loss.
Patent Information
- Application Number
- CN202411683060.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-18
AI Technical Summary
At high-speed sampling rate, the shared capacitance effect between parasitic capacitors and bootstrap capacitors in traditional gate voltage bootstrap switches results in the gate voltage establishment voltage being smaller than expected, increasing on-resistance and waste of area.
A fast conduction circuit is introduced to reduce the shared capacitance effect of the parasitic capacitor and the bootstrap capacitor by charging the charging capacitor before the sampling phase starts, thereby increasing the gate voltage.
It effectively improves the establishment speed and final value of the gate voltage of the sampling switch, reduces the size and on-resistance of the sampling switch, and reduces the power consumption and area loss of the circuit.
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Figure CN119652295A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a high-speed bootstrap switch with a fast conduction path. Background Art
[0002] The gate voltage of the sampling switch MS is bootstrapped to the sum of the power supply voltage and the input voltage (i.e., VDD+V in ), making the gate-source voltage of MS constant, reducing the injection of nonlinear current, and having a larger input signal swing. However, with the increase of input signal frequency and sampling rate,
[0003] Please refer to Figure 1 , Figure 1 A schematic diagram of a conventional gate voltage bootstrap switch structure provided as the background technology of this application.
[0004] like Figure 1 As shown in Figure 1, as the sampling rate rises to gigahertz, the sampling phase or holding phase time will be shortened to a few hundred picoseconds. When the gate voltage bootstrap switch is in the holding phase, the clock signal THSN is at a high level. At this time, V P Pull down to VSS. When the gate voltage bootstrap switch is in the sampling phase, the clock signal THS is at a high level. At this time, MN1 (i.e., NMOS tube 1) and MP1 (i.e., PMOS tube 1) are turned on, and V P With capacitor C boost Connected, V P The nodes include the gate capacitances of MS, MN1, and MN2, and the drain capacitances of MP1 and MN5.
[0005] These total parasitic capacitances (Cpair) will share charge with Cboost, causing the actual voltage established by Vp to be less than VDD+Vin, increasing the on-resistance of MS. Considering the influence of parasitic capacitance, the gate-source voltage difference VGS of MS can be expressed by the following formula (1):
[0006]
[0007] From formula (1), we can see that C boost The larger the V GS The closer to VDD, but in order to maintain the phase, in order to ensure that MN4 and MP2 can charge the bootstrap capacitor to VDD, their size needs to be further increased, which further causes area waste.
[0008] Therefore, how to reduce the power consumption and area loss of the circuit in the bootstrap switch becomes a technical problem that those skilled in the art need to solve urgently. Summary of the invention
[0009] The object of the present invention is to provide a high-speed bootstrap switch with a fast conduction path, so as to reduce the power consumption and area of the circuit in the bootstrap switch.
[0010] In order to achieve the above object, the present invention provides the following technical solutions:
[0011] A high-speed bootstrap switch with a fast conduction path, comprising: a fast conduction circuit and a gate voltage bootstrap switch circuit;
[0012] The gate voltage bootstrap switch circuit comprises a sampling switch, a parasitic capacitor and a bootstrap capacitor; wherein the gate of the sampling switch is connected to the fast conduction circuit and the upper electrode of the parasitic capacitor respectively; the lower electrode of the parasitic capacitor is grounded; the gate voltage bootstrap switch circuit is used to increase the gate voltage of the sampling switch through the bootstrap capacitor in the case of a sampling phase;
[0013] The fast conduction circuit includes: a charging capacitor; the fast conduction circuit is used to charge the charging capacitor in the holding phase, and before the sampling phase starts, the parasitic capacitor is charged through the charging capacitor, so that the parasitic capacitor and the bootstrap capacitor jointly increase the gate voltage of the sampling switch until the gate voltage bootstrap switch circuit completes the bootstrap.
[0014] In an optional implementation manner of the present application, the gate voltage bootstrap switch circuit further includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fifth PMOS tube and a sixth PMOS tube;
[0015] The gate of the sampling switch is respectively connected to the upper electrode of the parasitic capacitor, the gate of the first NMOS tube, the gate of the second NMOS tube and the gate of the fifth NMOS tube; the drain of the sampling switch is connected to the output end of the gate voltage bootstrap switch; the source of the sampling switch is respectively connected to the drain of the first NMOS tube and the input end of the gate voltage bootstrap switch;
[0016] The source of the first NMOS tube is respectively connected to the source of the second NMOS tube, the source of the third NMOS tube, the drain of the fourth NMOS tube and the lower electrode of the bootstrap capacitor;
[0017] The drain of the second NMOS tube is respectively connected to the drain of the third PMOS tube, the drain of the third NMOS tube and the gate of the first PMOS tube;
[0018] The gate of the third NMOS tube and the gate of the third PMOS tube are connected to the first phase source; the source of the third PMOS tube is connected to the power supply;
[0019] The source of the fourth NMOS tube is grounded, and the gate of the fourth NMOS tube is connected to the second phase source;
[0020] The upper electrode of the bootstrap capacitor is connected to the drain of the second PMOS tube and the source of the first PMOS tube respectively;
[0021] The source of the second PMOS tube is connected to a power supply; the gate of the second PMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the sampling switch and the drain of the fifth NMOS tube;
[0022] The gate of the fifth NMOS tube is connected to a power supply; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube;
[0023] The source of the sixth NMOS tube is connected to the ground; and the gate of the sixth NMOS tube is connected to the second phase source.
[0024] In an optional implementation manner of the present application, the fifth NMOS tube is in a normally open state.
[0025] In an optional implementation manner of the present application, it is characterized in that when the first phase source is at a low level and the second phase source is at a high level, the gate voltage bootstrap switch circuit maintains the phase;
[0026] When the first phase source is at a high level and the second phase source is at a low level, the gate voltage bootstrap switch circuit is in a sampling phase;
[0027] Wherein, when the first phase source is at a high level, the second phase source is at a low level; when the first phase source is at a low level, the second phase source is at a high level.
[0028] In an optional implementation manner of the present application, the fast conduction circuit further includes:
[0029] a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube;
[0030] Wherein, the source of the seventh NMOS tube is grounded; the gate of the seventh NMOS tube is connected to the second phase source; the drain of the seventh NMOS tube is connected to the drain of the fourth PMOS tube;
[0031] The gate of the fourth PMOS tube is connected to the third phase source; the source of the fourth PMOS tube is connected to the power supply;
[0032] The lower electrode of the charging capacitor is connected to the drain of the seventh NMOS tube and the drain of the fourth PMOS tube respectively; the lower electrode of the charging capacitor is connected to the drain of the fifth PMOS tube and the drain of the sixth PMOS tube respectively;
[0033] The source of the fifth PMOS tube is respectively connected to the gate of the sixth PMOS tube, the drain of the ninth NMOS tube and the source of the seventh PMOS tube; the source of the sixth PMOS tube is connected to a power supply;
[0034] The gate of the ninth NMOS tube is connected to a power supply; the source of the ninth NMOS tube is connected to the drain of the eighth NMOS tube;
[0035] The gate of the eighth NMOS tube is connected to the second phase source; the source of the eighth NMOS tube is grounded;
[0036] The gate of the seventh PMOS tube is grounded; the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the source of the eighth PMOS tube is connected to the fourth phase source; the drain of the eighth PMOS tube is connected to the upper electrode of the parasitic capacitor.
[0037] In an optional implementation manner of the present application, the fast conduction circuit is used to make the third phase source maintain the output high potential after the fast conduction circuit enters the sampling phase from the holding phase, and then turn off the fourth PMOS through the third phase source, so that the seventh NMOS tube pulls down the lower electrode potential of the charging capacitor to zero; turn off the fifth PMOS tube through the third phase source; and make the sixth PMOS tube pull up the upper electrode potential of the charging capacitor to the power supply voltage;
[0038] Furthermore, after the fast conduction circuit enters the sampling phase from the holding phase, a low level is output to the fourth PMOS tube and the fifth PMOS tube through the third phase source, and while the fast conduction circuit enters the sampling phase from the holding phase, a low level is output to the eighth PMOS tube through the fourth phase source, thereby turning on the fourth PMOS tube and the fifth PMOS tube when the seventh NMOS tube and the eighth NMOS tube are turned off, thereby turning on the lower electrode voltage of the charging capacitor to the power supply voltage, and turning the upper electrode voltage to twice the power supply voltage, and charging the parasitic capacitor.
[0039] In an optional implementation manner of the present application, the first phase source and the second phase source are connected to the first clock circuit and the second clock circuit respectively;
[0040] Wherein, the first clock circuit comprises: an inverter 1; the first clock circuit is used to receive a clock signal and output a periodic first phase signal;
[0041] The second clock circuit comprises: two inverters 1 connected in series; the second clock circuit is used to receive the clock signal and output a periodic second clock signal.
[0042] In an optional implementation manner of the present application, the third phase source and the fourth phase source are connected to a third clock circuit and a fourth clock circuit respectively;
[0043] Wherein, the third clock circuit comprises: four inverters 1 connected in series; the third clock circuit is used to receive a clock signal and output a periodic third phase signal;
[0044] The fourth clock circuit comprises: four inverters 1 and two inverters 2 connected in series; a NAND gate circuit; a single inverter 1;
[0045] The four inverters 1 and the two inverters 2 connected in series are used to receive the clock signal and output a periodic fifth phase signal;
[0046] The single inverter 1 is used to receive a clock signal and output a periodic first phase signal;
[0047] The input end of the NAND gate circuit is respectively connected to the output ends of four inverters 1 and two inverters 2 connected in series, and the output end of the single inverter 1; the fourth clock circuit is used to output a fourth phase signal according to the fifth phase signal and the first phase signal.
[0048] In an optional implementation manner of the present application, the size of the inverter 1 is larger than the size of the inverter 2.
[0049] Compared with the prior art, the high-speed bootstrap switch with a fast conduction path provided by the present invention adds a fast conduction circuit on the basis of the traditional gate voltage bootstrap switch. After the sampling phase starts, the parasitic capacitance in the gate voltage bootstrap switch circuit is quickly charged by the fast conduction circuit, and the shared capacitance effect of the parasitic capacitance and the bootstrap capacitance is reduced in a short time, so that the gate voltage of the sampling switch is jointly increased by the parasitic capacitance and the bootstrap capacitance until the bootstrap of the gate voltage bootstrap switch circuit is achieved, which effectively improves the establishment speed and the establishment final value of the gate voltage of the sampling switch, and is conducive to reducing the size and on-resistance of the sampling switch. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0051] Figure 1 A schematic diagram of a conventional gate voltage bootstrap switch structure provided as the background technology of this application;
[0052] Figure 2 A structural diagram of a high-speed bootstrap switch with a fast conduction path provided in an embodiment of the present application;
[0053] Figure 3 A high-speed bootstrap switch circuit diagram with a fast conduction path provided in an embodiment of the present application;
[0054] Figure 4 A clock circuit structure diagram provided for an embodiment of the present application;
[0055] Figure 5 A schematic diagram of the periodicity of a phase signal provided in an embodiment of the present application;
[0056] Figure 6 A schematic diagram showing the comparison results of the voltage difference between the upper and lower plates of the bootstrap capacitor in the sampling phase provided in the embodiment of the present application;
[0057] Figure 7 A schematic diagram of the comparison results of the MS gate voltage provided in the embodiment of the present application. DETAILED DESCRIPTION
[0058] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.
[0059] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
[0060] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0061] This application provides a high-speed bootstrap switch with a fast turn-on path, please refer to Figure 2 , Figure 2 A structural diagram of a high-speed bootstrap switch with a fast conduction path provided in an embodiment of the present application.
[0062] like Figure 2 As shown, the high-speed bootstrap switch with a fast conduction path includes: a fast conduction circuit 101 and a gate voltage bootstrap switch circuit 102;
[0063] The gate voltage bootstrap switch circuit 102 is specifically as follows Figure 1 The conventional gate voltage bootstrap switch shown in FIG. 1 mainly includes a sampling switch MS, a parasitic capacitor C pair And the bootstrap capacitor C boost .
[0064] The gate of the sampling switch MS is connected to the fast conduction circuit 101 and the parasitic capacitor C pair The upper electrode is connected to the parasitic capacitance C pair The lower electrode of the gate voltage bootstrap switch circuit 102 is used to connect the bootstrap capacitor C boost Increase the gate voltage of the sampling switch.
[0065] The fast conduction circuit 101 includes: a charging capacitor C copy ; The fast conduction circuit 101 is used to charge the capacitor C in the maintenance phase copy Before the sampling phase begins, the capacitor C copy is the parasitic capacitance C pair Charge so that the parasitic capacitance C pair With the bootstrap capacitor C boost The gate voltage of the sampling switch MS is jointly increased until the gate voltage bootstrap switch circuit completes bootstrapping.
[0066] For details, please refer to Figure 3, Figure 3 A high-speed bootstrap switch circuit diagram with a fast conduction path provided in an embodiment of the present application.
[0067] like Figure 3 As shown, the gate voltage bootstrap switch circuit also includes: a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fifth NMOS tube MN5 and a sixth NMOS tube MN6.
[0068] Among them, the gate of the sampling switch MS is respectively connected to the parasitic capacitor C pair The upper electrode of MN1, the gate of MN2 and the gate of MN5 are connected; the drain of the sampling switch MS is connected to the output terminal V out The source of the sampling switch MS is connected to the drain of MN1 and the input terminal V of the gate voltage bootstrap switch respectively. in connected;
[0069] The source of MN1 is connected to the source of MN2, the source of MN3, the drain of MN4 and the bootstrap capacitor C boost The lower electrode is connected;
[0070] The drain of MN2 is connected to the drain of MP3 tube, the drain of MN3 and the gate of MP1 tube respectively;
[0071] The gate of MN3 and the gate of MP3 are connected to the first phase source (THS); the source of MP3 is connected to the power supply;
[0072] The source of MN4 is grounded, and the gate of MN4 is connected to the second phase source (THSN);
[0073] Bootstrap capacitor C boost The upper electrodes are connected to the drain of MP2 and the source of MP1 respectively;
[0074] The source of MP2 is connected to the power supply; the gate of MP2 is connected to the drain of MP1, the gate of the sampling switch MS and the drain of MN5 respectively;
[0075] The gate of MN5 is connected to the power supply; the source of MN5 is connected to the drain of MN6;
[0076] The source of MN6 is connected to the ground; the gate of MN6 is connected to the second phase source (THSN).
[0077] Among them, MN5 is a normally-on NMOS tube to prevent the voltage across the source and drain of MN6 from being too high and causing breakdown.
[0078] Furthermore, the fast conduction circuit further includes: a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, and an eighth PMOS tube MP8.
[0079] The source of MN7 is grounded; the gate of MN7 is connected to the second phase source (THSN); the drain of MN7 is connected to the drain of MP4;
[0080] The gate of MP4 is connected to the third phase source (THSNdelay1); the source of MP4 is connected to the power supply;
[0081] The lower electrode of the charging capacitor is connected to the drain of MN7 and the drain of MP4 respectively; the charging capacitor C copy The lower electrodes are connected to the drain of MP5 and the drain of MP6 respectively;
[0082] The source of MP5 is connected to the gate of MP6, the drain of MN9 and the source of MP7 respectively; the source of MP6 is connected to the power supply;
[0083] The gate of MN9 is connected to the power supply; the source of MN9 is connected to the drain of MN8;
[0084] The gate of MN8 is connected to the second phase source (THSN); the source of MN8 is grounded;
[0085] The gate of MP7 is grounded; the drain of MP7 is connected to the source of MP8; the source of MP8 is connected to the fourth phase source (Tdelaypre); the drain of MP8 is connected to the upper electrode of the parasitic capacitor.
[0086] Among them, MN9 and MP7 are normally open MOS tubes set to prevent the MOS tube from being broken down due to excessive voltage across the source and drain of MN8 and MP.
[0087] In the actual application process, the gate voltage bootstrap switch circuit is to maintain the phase, the first phase source (THS) is at a low level, and the second phase source is at a high level. At this time, MN4 and MN6 are turned on, and the node voltage V P is pulled down to VSS, MP2 is turned on. When the hold phase ends, the bootstrap capacitor C boost The lower plate is at a low level, the upper plate is at a high level, and the bootstrap capacitor C boost Charging. MP3 is turned on, the gate voltage of MP1 is VDD, and MP1, MN1, MS, and MN2 are turned off.
[0088] When the gate voltage bootstrap switch circuit enters the sampling phase, when the first phase source (THS) becomes high level, the second phase source (THNS) becomes low level. MN4, MN6, and MP3 are cut off, MN3 is turned on, the gate voltage of MP1 is temporarily pulled down to VSS, MP1 is turned on, and the voltage of VP rises. As VP rises, MN1, MN2, and MS are turned on, and the bootstrap capacitor C boost The lower plate voltage becomes V in Since the voltage across the capacitor cannot change suddenly, the bootstrap capacitor C boost The upper plate voltage rises to the power supply voltage VDD and V in The sum of the parasitic capacitance C is not considered. pair In the case of charge sharing, the voltage of VP is also the power supply voltage VDD and V in The VP voltage is stably transmitted to the gate and source of the MS to ensure that the MS gate voltage is consistent with V in The difference is greater than or equal to VDD, thus completing the gate voltage bootstrap. MN2 provides a low-resistance path in series with the gate of MP1. In the stable state, the gate voltage of MP1 is equal to Vin. At this time, the absolute value of the gate-source voltage difference on MP1, MN1, and MS is VDD.
[0089] However, in actual application, due to the parasitic capacitance C pair The influence of the charge sharing effect will produce a charge sharing effect, making V P The voltage is less than VDD and V in and each time after the sampling phase begins, the bootstrap capacitor C boost Both need to drive V P From VSS to VDD and V in However, since the RC constant of loop 1 in the gate voltage bootstrap switch circuit is relatively large. Therefore, the bootstrap capacitor C boost Both need to drive V P The voltage rise process is slow. In high sampling rate applications, VP may not rise to the voltage between VDD and V in time due to insufficient time. in sum.
[0090] Furthermore, for the fast turn-on circuit, in order to facilitate understanding of the fast turn-on circuit, the level periodicity among the first phase source, the second phase source, the third phase source and the fourth phase source is first described.
[0091] Specifically, the first phase source, the second phase source, the third phase source and the fourth phase source are connected to the first clock circuit, the second clock circuit, the third clock circuit and the fourth clock circuit respectively.
[0092] Please refer to Figure 4 , Figure 4A diagram of the clock circuit structure provided in an embodiment of the present application.
[0093] The first clock circuit comprises: an inverter 1; the first clock circuit is used to receive a clock signal and output a periodic first phase signal;
[0094] The second clock circuit comprises: two inverters 1 connected in series; the second clock circuit is used to receive the clock signal and output a periodic second clock signal.
[0095] The third phase source and the fourth phase source are connected to the third clock circuit and the fourth clock circuit respectively;
[0096] The third clock circuit comprises: four inverters 1 connected in series; the third clock circuit is used to receive a clock signal and output a periodic third phase signal;
[0097] The fourth clock circuit comprises: four inverters 1 and two inverters 2 connected in series; a NAND gate circuit; a single inverter 1;
[0098] The four inverters 1 and the two inverters 2 connected in series are used to receive the clock signal and output a periodic fifth phase signal;
[0099] The single inverter 1 is used to receive a clock signal and output a periodic first phase signal;
[0100] The input end of the NAND gate circuit is respectively connected to the output ends of four inverters 1 and two inverters 2 connected in series, and the output end of the single inverter 1; the fourth clock circuit is used to output a fourth phase signal according to the fifth phase signal and the first phase signal.
[0101] The size of the first inverter is larger than that of the second inverter.
[0102] In an optional implementation manner of the present application, the size of the inverter 1 is 4, and the size of the inverter 2 is 1.
[0103] For further information, please refer to Figure 5 , Figure 5 A schematic diagram of the periodicity of a phase signal provided in an embodiment of the present application.
[0104] For ease of expression, the first phase signal to the fourth phase signal are corresponded here to the first phase source to the fourth phase source in the circuit structure, that is, the first phase signal corresponds to the first phase source (THS), the second phase signal corresponds to the second phase source (THSN), the third phase signal corresponds to the third phase source (THSNdelay1), and the fourth phase signal corresponds to the fourth phase source (Tdelaypre).
[0105] Correspondingly, the fifth phase signal corresponds to THSNdelay2.
[0106] like Figure 5 As shown, when the first phase signal outputs a low level, the second phase signal outputs a high level, that is, when the first phase source (THS) is a low level, the second phase source (THSN) outputs a high level.
[0107] On the contrary, when the first phase signal is at a high level, the second phase signal is at a low level, that is, when the first phase source (THS) is at a high level, the second phase source (THSN) outputs a low level. The periods of the first phase signal to the fifth phase signal are the same, but the third phase signal has a certain phase difference α relative to the second phase signal, and similarly, the fifth phase signal has a certain phase difference β relative to the second phase signal.
[0108] Further, for the fast turn-on circuit, while keeping the second phase source (THSN) at a high level, the third phase source (THSNdelay1) at a high level, and the fourth phase source (Tdelaypre) at a high level, MN7 and MN8 are turned on, and the gate of MP6 is at a low level, MN7 and MP6 charge the capacitor C copy Charges to VDD.
[0109] After entering the sampling phase, after the second phase source (THSN) becomes a high level, the third phase source (THSNdelay1) becomes a low level, and the fourth phase source also becomes a low level within the time range corresponding to the phase β.
[0110] In this state, MN7 and MN8 are turned off, and the charging capacitor C copy Both ends are floating, MP4 and MP5 are turned on, and the charging capacitor C copy The lower plate voltage becomes VDD. Since the voltage across the capacitor cannot change suddenly, the charging capacitor C copy The upper plate voltage becomes twice VDD. Furthermore, since the drain of MP5 is connected to the drain of MP6, and the source of MP5 is connected to the gate of MP6, the voltages of the gate and source of MP6 are the same, and the phase of the third phase source (THSNdelay1) is delayed relative to the second phase source (THSN), thereby ensuring that MN7 and MP6 continue to be dielectric during the conversion period, and the charging capacitor C is not released. copy The charge on .
[0111] Since the fourth phase source (Tdelaypre) is at a low level, MP8 is turned on, charging capacitor C copy Use twice VDD for parasitic capacitance C pairCharge until the fourth phase source (Tdelaypre) becomes high or the voltage of VP is high enough.
[0112] Further, for the conventional gate voltage bootstrap switch provided in the prior art (see Figure 1 ) and the high-speed bootstrap switch with a fast conduction path provided by the embodiment of the present application (see Figure 3 ) The power supply voltage is 1V, the input signal Vpp=0.6V, the input common mode is 0.5V, the input signal frequency is 0.466GHz, and the sampling clock frequency is 6GHz. The bootstrap capacitor C of the conventional gate voltage bootstrap switch and the high-speed bootstrap switch with a fast turn-on path can be obtained. boost The comparison results of the voltage difference between the upper and lower plates in the sampling phase, and the comparison results of the MS gate voltage establishment.
[0113] Please refer to Figure 6 and Figure 7 ,in, Figure 6 A schematic diagram showing the comparison results of the voltage difference between the upper and lower plates of the bootstrap capacitor in the sampling phase provided in the embodiment of the present application; Figure 7 A schematic diagram of the comparison results of the MS gate voltage provided in the embodiment of the present application.
[0114] Figure 6 In the figure, curve 1 is a curve showing the change of the voltage difference between the upper and lower plates of the bootstrap capacitor of a high-speed bootstrap switch with a fast conduction path during the sampling phase over time; curve 2 is a curve showing the change of the voltage difference between the upper and lower plates of the bootstrap capacitor of a traditional gate voltage bootstrap switch during the sampling phase over time.
[0115] like Figure 6 As shown, during the sampling phase, the voltage difference between the upper and lower plates of the bootstrap capacitor of the high-speed bootstrap switch with a fast conduction path is significantly higher than that of the traditional gate voltage bootstrap switch.
[0116] Furthermore, Figure 7 In FIG. 4 , curve 3 is a curve for establishing the MS gate voltage of a high-speed bootstrap switch with a fast turn-on path; curve 4 is a curve for establishing the MS gate voltage of a conventional gate voltage bootstrap switch.
[0117] like Figure 7 As shown, the MS gate voltage building speed of the high-speed bootstrap switch with a fast turn-on path is significantly higher than the MS gate voltage building speed of the traditional gate voltage bootstrap switch.
[0118] In summary, the high-speed bootstrap switch with a fast conduction path provided in the embodiment of the present application adds a fast conduction circuit on the basis of the traditional gate voltage bootstrap switch. After the sampling phase starts, the parasitic capacitance in the gate voltage bootstrap switch circuit is quickly charged by the fast conduction circuit, and the shared capacitance effect of the parasitic capacitance and the bootstrap capacitance is reduced in a short time, so that the gate voltage of the sampling switch is jointly increased by the parasitic capacitance and the bootstrap capacitance until the bootstrap of the gate voltage bootstrap switch circuit is achieved, which effectively improves the establishment speed and the establishment final value of the gate voltage of the sampling switch, and is conducive to reducing the size and on-resistance of the sampling switch.
[0119] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0120] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A high-speed bootstrap switch with a fast turn-on path, characterized in that: include: Fast turn-on circuit and gate voltage bootstrap switch circuit; The gate voltage bootstrap switch circuit comprises a sampling switch, a parasitic capacitor and a bootstrap capacitor; wherein the gate of the sampling switch is connected to the fast conduction circuit and the upper electrode of the parasitic capacitor respectively; the lower electrode of the parasitic capacitor is grounded; the gate voltage bootstrap switch circuit is used to increase the gate voltage of the sampling switch through the bootstrap capacitor in the case of a sampling phase; The fast conduction circuit includes: a charging capacitor; the fast conduction circuit is used to charge the charging capacitor in the holding phase, and before the sampling phase starts, the parasitic capacitor is charged through the charging capacitor, so that the parasitic capacitor and the bootstrap capacitor jointly increase the gate voltage of the sampling switch until the gate voltage bootstrap switch circuit completes the bootstrap.
2. The high-speed bootstrap switch with a fast turn-on path according to claim 1, characterized in that: The gate voltage bootstrap switch circuit also includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fifth NMOS tube and a sixth NMOS tube; The gate of the sampling switch is respectively connected to the upper electrode of the parasitic capacitor, the gate of the first NMOS tube, the gate of the second NMOS tube and the gate of the fifth NMOS tube; the drain of the sampling switch is connected to the output end of the gate voltage bootstrap switch; the source of the sampling switch is respectively connected to the drain of the first NMOS tube and the input end of the gate voltage bootstrap switch; The source of the first NMOS tube is respectively connected to the source of the second NMOS tube, the source of the third NMOS tube, the drain of the fourth NMOS tube and the lower electrode of the bootstrap capacitor; The drain of the second NMOS tube is respectively connected to the drain of the third PMOS tube, the drain of the third NMOS tube and the gate of the first PMOS tube; The gate of the third NMOS tube and the gate of the third PMOS tube are connected to the first phase source; the source of the third PMOS tube is connected to the power supply; The source of the fourth NMOS tube is grounded, and the gate of the fourth NMOS tube is connected to the second phase source; The upper electrode of the bootstrap capacitor is connected to the drain of the second PMOS tube and the source of the first PMOS tube respectively; The source of the second PMOS tube is connected to a power supply; the gate of the second PMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the sampling switch and the drain of the fifth NMOS tube; The gate of the fifth NMOS tube is connected to a power supply; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; The source of the sixth NMOS tube is connected to the ground; and the gate of the sixth NMOS tube is connected to the second phase source.
3. The high-speed bootstrap switch with a fast turn-on path according to claim 2, characterized in that: The fifth NMOS tube is in a normally open state.
4. The high-speed bootstrap switch with a fast turn-on path according to claim 2, characterized in that: When the first phase source is at a low level and the second phase source is at a high level, the gate voltage bootstrap switch circuit maintains the phase; When the first phase source is at a high level and the second phase source is at a low level, the gate voltage bootstrap switch circuit is in a sampling phase; Wherein, when the first phase source is at a high level, the second phase source is at a low level; when the first phase source is at a low level, the second phase source is at a high level.
5. The high-speed bootstrap switch with a fast turn-on path according to claim 1, characterized in that: The fast conduction circuit further includes: a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube; Wherein, the source of the seventh NMOS tube is grounded; the gate of the seventh NMOS tube is connected to the second phase source; the drain of the seventh NMOS tube is connected to the drain of the fourth PMOS tube; The gate of the fourth PMOS tube is connected to the third phase source; the source of the fourth PMOS tube is connected to the power supply; The lower electrode of the charging capacitor is connected to the drain of the seventh NMOS tube and the drain of the fourth PMOS tube respectively; the lower electrode of the charging capacitor is connected to the drain of the fifth PMOS tube and the drain of the sixth PMOS tube respectively; The source of the fifth PMOS tube is respectively connected to the gate of the sixth PMOS tube, the drain of the ninth NMOS tube and the source of the seventh PMOS tube; the source of the sixth PMOS tube is connected to a power supply; The gate of the ninth NMOS tube is connected to a power supply; the source of the ninth NMOS tube is connected to the drain of the eighth NMOS tube; The gate of the eighth NMOS tube is connected to the second phase source; the source of the eighth NMOS tube is grounded; The gate of the seventh PMOS tube is grounded; the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the source of the eighth PMOS tube is connected to the fourth phase source; the drain of the eighth PMOS tube is connected to the upper electrode of the parasitic capacitor.
6. The high-speed bootstrap switch with a fast turn-on path according to claim 5, characterized in that: The fast conduction circuit is used to make the third phase source keep outputting a high potential after the fast conduction circuit enters the sampling phase from the holding phase, and then turn off the fourth PMOS through the third phase source, so that the seventh NMOS tube pulls down the lower electrode potential of the charging capacitor to zero; turn off the fifth PMOS tube through the third phase source; and make the sixth PMOS tube pull up the upper electrode potential of the charging capacitor to the power supply voltage; Furthermore, after the fast conduction circuit enters the sampling phase from the holding phase, a low level is output to the fourth PMOS tube and the fifth PMOS tube through the third phase source, and while the fast conduction circuit enters the sampling phase from the holding phase, a low level is output to the eighth PMOS tube through the fourth phase source, thereby turning on the fourth PMOS tube and the fifth PMOS tube when the seventh NMOS tube and the eighth NMOS tube are turned off, thereby turning on the lower electrode voltage of the charging capacitor to the power supply voltage, and turning the upper electrode voltage to twice the power supply voltage, and charging the parasitic capacitor.
7. The high-speed bootstrap switch with a fast turn-on path according to claim 2, characterized in that: The first phase source and the second phase source are connected to the first clock circuit and the second clock circuit respectively; Wherein, the first clock circuit comprises: an inverter 1; the first clock circuit is used to receive a clock signal and output a periodic first phase signal; The second clock circuit comprises: two inverters 1 connected in series; the second clock circuit is used to receive the clock signal and output a periodic second clock signal.
8. The high-speed bootstrap switch with a fast turn-on path according to claim 5, characterized in that: The third phase source and the fourth phase source are connected to the third clock circuit and the fourth clock circuit respectively; Wherein, the third clock circuit comprises: four inverters 1 connected in series; the third clock circuit is used to receive a clock signal and output a periodic third phase signal; The fourth clock circuit comprises: four inverters 1 and two inverters 2 connected in series; a NAND gate circuit; a single inverter 1; The four inverters 1 and the two inverters 2 connected in series are used to receive the clock signal and output a periodic fifth phase signal; The single inverter 1 is used to receive a clock signal and output a periodic first phase signal; The input end of the NAND gate circuit is respectively connected to the output ends of four inverters 1 and two inverters 2 connected in series, and the output end of the single inverter 1; the fourth clock circuit is used to output a fourth phase signal according to the fifth phase signal and the first phase signal.
9. The high-speed bootstrap switch with a fast turn-on path according to claim 8, characterized in that: The size of the first inverter is larger than that of the second inverter.