Power semiconductor device and preparation method thereof

Abstract

The invention relates to a power semiconductor device and a preparation method thereof, and relates to the power semiconductor device, in order to further reduce on-resistance and improve device stability, a third semiconductor layer connected to a drain electrode is additionally arranged beside the drain electrode in the horizontal direction, and under the state of drain electrode bias voltage, the third semiconductor layer can reduce the on-resistance on the premise of ensuring normal conduction of the device. The third semiconductor layer injects holes into the buffer layer, so that electrons captured in crystal defects in the buffer layer are released, the on-resistance of the device is reduced, and the stability of the device is improved; the third semiconductor layer is separated from the barrier layer in the vertical direction, so that the two-dimensional electron gas below the third semiconductor layer cannot be exhausted, and the device can be normally conducted.

Description

Technical Field

[0001] The present invention relates to power semiconductor devices, in particular to power gallium nitride devices and methods for manufacturing the same. Background Art

[0002] Compared with silicon materials, gallium nitride materials have larger energy band gaps, higher electron mobility, saturated electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors (HEMTs) are common power devices and are widely used in high-frequency applications such as radio frequency and microwave.

[0003] In the existing GaN high electron mobility transistor structure, the substrate and the layers above it are usually made of different materials, so there is a lattice mismatch and thermal expansion coefficient mismatch, and crystal defects will be formed in the buffer layer during the wafer manufacturing process. When the transistor is turned off and the drain bias is high, electrons will be injected from the substrate and captured in the crystal defects in the buffer layer. On the other hand, under the conditions of high drain bias and high drain current during the hard switching conversion of the transistor, hot electrons will be injected from the two-dimensional electron gas and captured in the crystal defects in the buffer layer. The above-mentioned electrons captured in the buffer layer will consume part of the electrons in the two-dimensional electron gas, resulting in a reduction in the electron density of the two-dimensional electron gas, an increase in the on-resistance of the transistor, and a reduction in the performance, stability and reliability of the transistor. Summary of the invention

[0004] In order to improve the above problem, the present invention adds a P-type semiconductor layer connected to the drain beside the drain in the horizontal direction.

[0005] A power semiconductor device, the device comprises a substrate layer located at the bottom, a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a first dielectric layer located above the barrier layer, a second dielectric layer located above the first dielectric layer, a source metal layer and a drain metal layer located on both sides of the device, the barrier layer and the channel layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer, a first semiconductor layer for forming an enhancement-mode device is provided between the barrier layer and the first dielectric layer, a first opening position is provided in the first dielectric layer above the first semiconductor layer, a gate metal layer is provided at the first opening position, the gate metal layer is separated from the source metal layer and the drain metal layer by the second dielectric layer, a second structure is further provided between the barrier layer and the first dielectric layer at a position close to the drain metal layer, the second structure comprises a second semiconductor layer located above the barrier layer and a third semiconductor layer provided above the second semiconductor layer, the third semiconductor layer and the drain metal layer are connected.

[0006] Furthermore, the third semiconductor layer and the drain metal layer are connected at the periphery of the device.

[0007] Furthermore, the side surfaces of the second semiconductor layer and the third semiconductor layer are adjacent to and in contact with the drain metal layer.

[0008] Furthermore, side portions of the second semiconductor layer and the third semiconductor layer extend into the drain metal layer.

[0009] Furthermore, a second opening position is provided in the first dielectric layer above the third semiconductor layer, a dielectric layer opening is provided in the second opening position, a drain field plate is also provided above the second dielectric layer, the drain field plate is connected to the drain metal layer, and the dielectric layer opening extends upward and is connected to the drain field plate.

[0010] Furthermore, a source field plate connected to the source metal layer is provided above the second dielectric layer.

[0011] Furthermore, the third semiconductor layer is in the shape of a strip, or one or more independent squares, rectangles, circles or ellipses.

[0012] The present invention also provides a method for preparing the power semiconductor device, the method comprising the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a preliminary protective layer on the barrier layer, and then etch the preliminary protective layer to form a patterned second-step protective layer with a first window position; the third step is to form a second semiconductor layer at the first window position of the second-step protective layer and on the surface of the barrier layer; Step 4, etching the two-step protective layer to form a three-step protective layer with a second window position; Step 5, forming a first semiconductor layer at the second window position of the three-step protective layer and on the surface of the barrier layer, and forming a third semiconductor layer on the surface of the second semiconductor layer; Step 6: remove the three-step protective layer by wet etching, and then form a preliminary first dielectric layer on the surface of the barrier layer, the first semiconductor layer and the third semiconductor layer; The seventh step is to etch the preliminary first dielectric layer to form a patterned first dielectric layer, and form a first opening position above the first semiconductor layer; The eighth step is to form a gate metal layer at a first opening position on the surface of the first semiconductor layer; The ninth step is to form a preliminary second dielectric layer on the upper surface, and then etch the preliminary second dielectric layer to form a patterned second dielectric layer; In the tenth step, a source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side.

[0013] The present invention also provides another method for preparing the power semiconductor device, which comprises the following steps: The process steps from the first step to the eighth step are the same as the process steps of the first preparation method; In the ninth step, a preliminary second dielectric layer is formed on the surface of the first dielectric layer, and then the preliminary second dielectric layer is etched to form a second-step second dielectric layer, wherein the first opening window in the second step is close to the drain electrode and has a larger range; Step 10, etching the second dielectric layer to form a second dielectric layer; In the eleventh step, a source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side.

[0014] The present invention also provides another method for preparing the power semiconductor device, which comprises the following steps: The process from the first step to the second step is the same as the process from the first step to the second step of the first preparation method; The third step is to form a second semiconductor layer at the first window position of the second-step protective layer and on the surface of the barrier layer, and then to form a first semiconductor layer on the surface of the second semiconductor layer; The fourth step is to remove the second-step protective layer, and then form a third-step protective layer on the barrier layer, and then etch the third-step protective layer to form a patterned fourth-step protective layer with a second window position; Step 5, forming a first semiconductor layer at the second window position of the four-step protective layer and on the surface of the barrier layer; The subsequent steps are the same as those of the first preparation method.

[0015] Under the drain bias state, the third semiconductor layer (P-type semiconductor layer) injects holes into the buffer layer, thereby releasing the electrons trapped in the crystal defects in the buffer layer, reducing the on-resistance of the device and improving its stability. On the other hand, the third semiconductor layer (P-type semiconductor layer) is separated from the barrier layer in the vertical direction, so it does not deplete the two-dimensional electron gas below it, allowing the device to conduct normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a cross-sectional schematic diagram of a device structure embodiment of the present invention.

[0017] Figure 2 It is a cross-sectional schematic diagram of another device structure embodiment of the present invention.

[0018] Figure 3 It is a cross-sectional schematic diagram of another device structure embodiment of the present invention.

[0019] Figure 4 It is a cross-sectional schematic diagram of another device structure embodiment of the present invention.

[0020] Figure 5 FIG. 4 is a cross-sectional schematic diagram of another device structure embodiment of the present invention.

[0021] Figure 6-Figure 15 for Figure 1 A cross-sectional schematic diagram of an embodiment of a method for manufacturing a device structure.

[0022] Figure 16-Figure 19 for Figure 2 A schematic cross-sectional view of key steps of an embodiment of a method for manufacturing a device structure.

[0023] Figure 20-21 for Figure 3 A schematic cross-sectional view of key steps of an embodiment of a method for manufacturing a device structure.

[0024] Figure 22-Figure 24 for Figure 1 A schematic cross-sectional view of key steps of another embodiment of a method for manufacturing a device structure.

[0025] Fig.25 for Figure 4 AA' transverse cross-sectional view of a device structure embodiment.

[0026] Fig.26 for Figure 4 A transverse cross-sectional view taken along line AA' of another embodiment of a device structure embodiment.

[0027] Fig. 27 for Figure 4 A transverse cross-sectional view taken along line AA' of yet another embodiment of a device structure embodiment. Specific embodiments

[0028] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", and "horizontal" described in this document correspond to the relative positions of the reference diagrams, and are not limited to fixed directions in specific implementations. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0029] Example 1 Figure 1 FIG. 1 is a cross-sectional schematic diagram of a first device structure embodiment of the present invention, the structure comprising: a substrate layer 100 at the bottom; a buffer layer 101 located above the substrate layer 100; A channel layer 102 located above the buffer layer 101; a barrier layer 103 located above the channel layer 102; A semiconductor layer 205 (second semiconductor layer), a P-type cap layer 206 a (first semiconductor layer) and a first dielectric layer 207 located above the barrier layer 103 ; A P-type semiconductor layer 206b (third semiconductor layer) located above the semiconductor layer 205 (second semiconductor layer); The gate metal layer 208 is located above the P-type cap layer 206a; A second dielectric layer 209 located above the first dielectric layer 207; The source metal layer 210 is located on the left of the gate metal layer 208 and the drain metal layer 211 is located on the right of the gate metal layer 208 .

[0030] In the above structure, the barrier layer 103 forms a heterojunction with the channel layer 102 thereunder, and a two-dimensional electron gas 104 is formed on the surface of the channel layer 102 to form a current channel between the source metal layer 210 and the drain metal layer 211 when the device is turned on.

[0031] In the above structure, when the device is turned off, the P-type cap layer 206 a depletes the two-dimensional electron gas 104 thereunder, thereby forming an enhancement-mode device.

[0032] In the above structure, the P-type semiconductor layer 206b is connected to the drain metal layer 211 at the periphery of the device. Under the drain bias state, the P-type semiconductor layer 206b will inject holes into the buffer layer 101, thereby releasing the electrons trapped in the crystal defects in the buffer layer, reducing the on-resistance of the device and improving its stability.

[0033] In the above structure, the P-type semiconductor layer 206 b is located above the semiconductor layer 205 and is separated from the barrier layer 103 , and will not deplete the two-dimensional electron gas 104 thereunder, so that the device can be normally turned on.

[0034] In the above structure, the P-type cap layer 206 a and the P-type semiconductor layer 206 b may be made of different or the same materials, and may be formed separately using different process steps or formed together using the same process steps.

[0035] Example 2 A variation of the device structure of the present invention is shown in FIG. Figure 2 As shown, and Figure 1 The difference between the embodiments is that the right edge of the P-type semiconductor layer 206 b and the right edge of the semiconductor layer 205 located thereunder are in contact with the left edge of the drain metal layer 211 respectively.

[0036] In the above structure, the P-type semiconductor layer 206b does not need to be connected to the drain metal layer 211 at the periphery of the device, which simplifies the layout design and reduces the chip area. The above structure can be formed by adjusting the layout design and process.

[0037] Example 3 A variation of the device structure of the present invention is shown in FIG. Figure 3 As shown, and Figure 1 The difference between the embodiments is that the right side of the P-type semiconductor layer 206 b and the semiconductor layer 205 thereunder partially extend into and contact the left side of the drain metal layer 211 .

[0038] In the above structure, the P-type semiconductor layer 206b does not need to be connected to the drain metal layer 211 at the periphery of the device, which simplifies the layout design and reduces the chip area. The above structure can be formed by adjusting the layout design and process (refer to Figure 20-21 ).

[0039] Example 4 A variation of the device structure of the present invention is shown in FIG. Figure 4 As shown, and Figure 1 The embodiment differs in that Figure 4 The embodiment adds a drain field plate 213 located above the second dielectric layer 209 and the drain metal layer 211. When the drain is biased, in order to overcome the peak electric field formed below the left edge of the semiconductor layer 205 and on the upper surface of the barrier layer 103 due to the semiconductor layer 205, the embodiment provides a drain field plate 213 to reduce the above-mentioned peak electric field, thereby reducing the number of hot electrons generated at this position.

[0040] In the above structure, the P-type semiconductor layer 206b is connected to the drain metal layer 211 through the dielectric layer opening 212 and the drain field plate 213. The P-type semiconductor layer 206b does not need to be connected to the drain metal layer 211 at the periphery of the device, which simplifies the layout design and reduces the chip area.

[0041] The drain field plate 213 may be made of the same material as the drain metal layer 211 and may be formed together using the same process steps.

[0042] Example 5 A variation of the device structure of the present invention is shown in FIG. Figure 5 As shown, and Figure 4 The embodiment differs in that Figure 5 The embodiment adds a source field plate 214 located above the second dielectric layer 209 and the source metal layer 210. The function of the source field plate 214 is to reduce the peak electric field formed at the right edge of the P-type cap layer 206a below the source field plate 214 and the upper surface of the barrier layer 103 when the drain is biased, thereby reducing the number of hot electrons generated at this position, and further reducing the number of hot electrons injected into the buffer layer 101.

[0043] The source field plate 214 may be made of the same material as the source metal layer 210 and may be formed together using the same process steps.

[0044] Example 6 According to the features of the device structure embodiments of the present invention described above, combined with the existing manufacturing process of GaN high electron mobility transistors, various methods for forming the device structure embodiments of the present invention can be obtained. Figure 1 Device structure formation method such as Figure 6-Figure 15 Shown: In the first step, a buffer layer 101 is formed on the substrate layer 100, a channel layer 102 is formed on the buffer layer 101, and a barrier layer 103 is formed on the channel layer 102. Figure 6 shown.

[0045] The material of the substrate layer 100 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.

[0046] The buffer layer 101 may include one material or a combination of multiple materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which helps to reduce leakage current.

[0047] The material of the channel layer 102 is usually gallium nitride (GaN), and may also include a combination of one or more materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN), and its band gap is smaller than the band gap of the material of the barrier layer 103 located thereon.

[0048] The material of the barrier layer 103 is usually aluminum gallium nitride (AlGaN), and may also include a combination of one or more materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN), and its band gap is greater than the band gap of the material of the channel layer 102 located thereunder.

[0049] The channel layer 102 and the barrier layer 103 form a heterojunction, and a preliminary two-dimensional electron gas 904 is formed on the surface of the channel layer 102 below the heterojunction.

[0050] The above structure can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial growth and other processes.

[0051] In the second step, a preliminary protection layer is formed on the barrier layer 103, and then the preliminary protection layer is subjected to photolithography, dry etching, wet etching and other process steps to form a patterned second-step protection layer 915 with a first window position, such as Figure 7 shown.

[0052] The material of the second-step protection layer 915 is generally silicon oxide or nitride such as silicon oxide (SiO2) or silicon nitride (Si3N4), etc., which can be formed by chemical vapor deposition, physical vapor deposition and other processes.

[0053] In the third step, a semiconductor layer 205 is formed on the surface of the barrier layer 103 at the first window position of the second-step protective layer 915, such as Figure 8 shown.

[0054] The material of the semiconductor layer 205 may be the same as that of the barrier layer 103 , and may be formed by processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and epitaxial growth.

[0055] In the fourth step, the two-step protective layer 915 is subjected to photolithography, dry etching, wet etching and other process steps to form a patterned three-step protective layer 815 with a second window position, such as Fig. 9 shown.

[0056] In the fifth step, a P-type cap layer 206a is formed on the second window position of the three-step protection layer 815 and the surface of the barrier layer 103, and a P-type semiconductor layer 206b is formed on the surface of the semiconductor layer 205. Fig.10 shown.

[0057] In the above structure, the P-type cap layer 206a depletes the two-dimensional electron gas 104 below it, forming an enhancement-mode device. The P-type semiconductor layer 206b is located above the semiconductor layer 205 and is separated from the barrier layer 103, and does not deplete the two-dimensional electron gas 104 below it.

[0058] In the above structure, the P-type cap layer 206a and the P-type semiconductor layer 206b are made of the same material and are formed together in the same process steps. The material of the P-type cap layer 206a and the P-type semiconductor 206b is usually doped gallium nitride (GaN), and may also include a combination of one or more materials such as doped gallium nitride (GaN), doped aluminum nitride (AlN), doped indium nitride (InN), doped aluminum gallium nitride (AlGaN), doped indium gallium nitride (InGaN), doped aluminum indium nitride (AlInN), and doped aluminum indium gallium nitride (AlInGaN), and the doped material includes magnesium (Mg) or other suitable P-type doping elements. The above structure can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial growth, and the like.

[0059] In the sixth step, the three-step protection layer 815 is removed by wet etching, and then a preliminary first dielectric layer 907 is formed on the surface of the barrier layer 103, the P-type cap layer 206a and the P-type semiconductor layer 206a. Fig.11 shown.

[0060] The material of the preliminary first dielectric layer 907 is usually composed of oxide or nitride, such as aluminum oxide (Al2O3), silicon oxide (SiO2), aluminum nitride (AlN), silicon nitride (Si3N4), etc., and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition and other processes.

[0061] In the seventh step, the preliminary first dielectric layer 907 is subjected to photolithography, dry etching, wet etching and other process steps to form a first opening position in the P-type cap layer 206a to form a patterned first dielectric layer 207, such as Fig.12 shown.

[0062] In the eighth step, a gate metal layer 208 is formed at the first opening position. Fig.13 Typically, the gate metal layer 208 forms a Schottky contact with the P-type cap layer 206a thereunder.

[0063] The gate metal layer 208 may be formed by evaporation, sputtering or other processes, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other suitable materials.

[0064] In the ninth step, a preliminary second dielectric layer is formed on the upper surface, and then photolithography, dry etching, wet etching and other process steps are performed on the preliminary second dielectric layer to form a patterned second dielectric layer 209, such as Fig.14 shown.

[0065] The material of the second dielectric layer 209 is usually composed of oxide or nitride, such as aluminum oxide (Al2O3), silicon oxide (SiO2), aluminum nitride (AlN), silicon nitride (Si3N4), etc., and can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. The material of the second dielectric layer 209 can be the same as or different from the material of the first dielectric layer 207.

[0066] In the tenth step, a source metal layer 210 is formed on the left side of the gate metal layer 208 and a drain metal layer 211 is formed on the right side thereof, as shown in FIG. Fig.15 Typically, the source metal layer 210 and the drain metal layer 211 form an ohmic contact with the barrier layer 103 thereunder.

[0067] The source metal layer 210 and the drain metal layer 211 may be formed by evaporation, sputtering and other processes, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.

[0068] Example 7 An exemplary Figure 2 The important steps of the method for forming the device structure embodiment are as follows: Figure 16-19 Shown: The process steps from the first step to the eighth step are similar to the process steps from the first step to the eighth step of Example 6. The difference is that the window opening range of the two-step protective layer 915 of Example 7 is larger than the window opening range of the two-step protective layer 915 of Example 6, such as Fig.16 As shown; In this embodiment, the first window opening range not only includes the range for forming the semiconductor layer 205 and the P-type semiconductor layer 206b, but also includes the range for forming the drain metal layer 211. The semiconductor layer 205 and the P-type semiconductor layer 206b are first formed in the first window opening range.

[0069] In the ninth step, a preliminary second dielectric layer is formed on the surface of the first dielectric layer 207, and then photolithography, dry etching, wet etching and other process steps are performed on the preliminary second dielectric layer to form a second dielectric layer 909. Fig.17 shown.

[0070] In the tenth step, photolithography, dry etching, wet etching and other process steps are performed on the second dielectric layer 909 to form the second dielectric layer 209. Fig.18 shown.

[0071] In the eleventh step, a source metal layer 210 is formed on the left side of the gate metal layer 208 and a drain metal layer 211 is formed on the right side thereof. Fig.19 shown.

[0072] Example 8 An exemplary Figure 3 The important steps of the method for forming the device structure embodiment are as follows: Figure 20-21 Shown: The process steps from the first step to the eighth step are similar to the process steps from the first step to the eighth step of Example 6. The difference is that the opening position of the second-step protective layer 915 of Example 8 is closer to the drain metal than the first opening range of the second-step protective layer 915 of Example 6. Fig. 20 shown.

[0073] Similar to Example 7, the first window opening range not only includes the range for forming the semiconductor layer 205 and the P-type semiconductor layer 206b, but also includes the range for forming the drain metal layer 211, which is closer to the drain location, so the formed semiconductor layer 205 and the P-type semiconductor layer 206b extend slightly toward the drain metal layer 211.

[0074] In the ninth step, a preliminary second dielectric layer is formed on the surface of the first dielectric layer 207, and then photolithography, dry etching, wet etching and other process steps are performed on the preliminary second dielectric layer to form a second dielectric layer 209. Fig. 20 The P-type semiconductor layer 206b and the semiconductor layer 205 thereunder are used as hard masks when etching the preliminary second dielectric layer.

[0075] In the tenth step, a source metal layer 210 is formed on the left side of the gate metal layer 208 and a drain metal layer 211 is formed on the right side thereof, as shown in FIG. Fig.21 shown.

[0076] Example 9 Another exemplary Figure 1 Device structure formation method such as Figure 22-Figure 24 Shown: The process steps from the first step to the second step are the same as the process steps from the first step to the second step in Example 6.

[0077] In the third step, a semiconductor layer 205 is formed at the first window position of the second-step protection layer 915 and on the surface of the barrier layer 103, and then a P-type semiconductor layer 206b is formed on the surface of the semiconductor layer 205. Fig. 22 shown.

[0078] In the fourth step, the two-step protective layer 915 is removed by wet etching, and then a three-step protective layer is formed on the barrier layer 103. Then, the three-step protective layer is subjected to photolithography, dry etching, wet etching and other process steps to form a patterned four-step protective layer 715, forming a second window position, such as Fig.23 shown.

[0079] In the fifth step, a P-type cap layer 206a is formed on the surface of the barrier layer 103 at the second window position of the four-step protection layer 715. Fig.24 shown.

[0080] The process steps of the sixth step are the same as those of the sixth step of Example 6, and all subsequent process steps are the same as those of Example 6.

[0081] In this embodiment, the P-type cap layer 206 a and the P-type semiconductor layer 206 b are separately formed using different process steps, and thus can be composed of different or the same materials, which provides more flexibility in optimizing device performance.

[0082] Example 10 Fig.25 The device structure of Example 4 Figure 4 AA' transverse cross-sectional view, in which the P-type semiconductor layer 206b is an integrated long strip.

[0083] A top view of a device structure embodiment of the present invention is shown in FIG. Fig.26 As shown, and Fig.25 The difference is that Fig.26 The P-type semiconductor layer 206b is composed of a series of independent squares (or rectangles). Fig.26 The total area of ​​the P-type semiconductor layer 206 b is smaller, and the number of hot electrons injected into the buffer layer 101 under the drain bias state is smaller, and the drain leakage current is also smaller.

[0084] for example, Figure 1 In the structure shown, the P-type semiconductor layer 206 b may be in the shape of an integrated long strip.

[0085] In the above structure, the required length, spacing and total area of ​​the P-type semiconductor layer 206 b can be obtained by adjusting the layout design of the second-step protection layer 915 , which has more design flexibility than the fourth embodiment in optimizing device performance.

[0086] Embodiment 11 A top view of a device structure embodiment of the present invention is shown in FIG. Fig. 27 As shown, and Fig.26 The difference is that Fig. 27 The P-type semiconductor layer 206 b is an independent circle (or an ellipse).

[0087] In the above structure, the circular or elliptical P-type semiconductor layer 206 b has no sharp corners, which reduces the peak electric field formed at the edge of the P-type semiconductor layer 206 b when the drain is biased, thereby reducing the number of hot electrons generated at this position.

[0088] for example, Figure 2In the structure shown, the P-type semiconductor layer 206 b may also be circular or elliptical, which can be adjusted according to actual needs.

[0089] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

Claims

1. A power semiconductor device, the device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a first dielectric layer above the barrier layer, a second dielectric layer above the first dielectric layer, a source metal layer and a drain metal layer at both sides of the device, the barrier layer and the channel layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer, a first semiconductor layer for forming an enhancement-mode device is provided between the barrier layer and the first dielectric layer, a first opening position is provided in the first dielectric layer above the first semiconductor layer, a gate metal layer is provided at the first opening position, the gate metal layer is separated from the source metal layer and the drain metal layer by the second dielectric layer, and characterized in that: A second structure is provided between the barrier layer and the first dielectric layer near the drain metal layer. The second structure includes a second semiconductor layer located above the barrier layer and a third semiconductor layer located above the second semiconductor layer for reducing the on-resistance of the device and improving stability. The third semiconductor layer is connected to the drain metal layer.

2. The power semiconductor device according to claim 1, characterized in that: The third semiconductor layer and the drain metal layer are connected at the periphery of the device.

3. The power semiconductor device according to claim 1, characterized in that: The side surfaces of the second semiconductor layer and the third semiconductor layer are adjacent to and connected to the drain metal layer.

4. The power semiconductor device according to claim 3, characterized in that: The side surfaces of the second semiconductor layer and the third semiconductor layer partially extend into the drain metal layer.

5. The power semiconductor device according to claim 1, characterized in that: The first dielectric layer above the third semiconductor layer is provided with a second opening position, the second opening position is provided with a dielectric layer opening, a drain field plate is also provided above the second dielectric layer, the drain field plate is connected to the drain metal layer, and the dielectric layer opening extends upward and is connected to the drain field plate.

6. The power semiconductor device according to claim 5, characterized in that: A source field plate connected to the source metal layer is provided above the second dielectric layer.

7. The power semiconductor device according to claim 1, characterized in that: The third semiconductor layer is in the shape of a strip, or one or more independent squares, rectangles, circles or ellipses.

8. The method for preparing a power semiconductor device according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a preliminary protective layer on the barrier layer, and then etch the preliminary protective layer to form a patterned second-step protective layer having a first window position; The third step is to form a second semiconductor layer on the surface of the barrier layer at the first window position of the second-step protective layer; Step 4: etching the two-step protective layer to form a three-step protective layer with a second window position; Step 5, forming a first semiconductor layer at the second window position of the three-step protective layer and on the surface of the barrier layer, and forming a third semiconductor layer on the surface of the second semiconductor layer; Step 6, removing the three-step protective layer, and then forming a preliminary first dielectric layer on the surface of the barrier layer, the first semiconductor layer and the third semiconductor layer; The seventh step is to etch the preliminary first dielectric layer to form a patterned first dielectric layer, and form a first opening position above the first semiconductor layer; The eighth step is to form a gate metal layer at the first opening position; The ninth step is to form a preliminary second dielectric layer on the upper surface, and then etch the preliminary second dielectric layer to form a patterned second dielectric layer; In the tenth step, a source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side.

9. The method for preparing a power semiconductor device according to claim 8, characterized in that: The method comprises the following steps: The process steps of the first step to the eighth step are the same as the process steps of claim 7, wherein the first window in the second step is close to the drain and the range is increased; Step 9, forming a preliminary second dielectric layer on the surface of the first dielectric layer, and then forming a second-step second dielectric layer on the preliminary second dielectric layer; Step 10, etching the second dielectric layer to form a second dielectric layer; In the eleventh step, a source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side.

10. The method for preparing a power semiconductor device according to claim 8, characterized in that: The method comprises the following steps: The process from the first step to the second step is the same as the process from the first step to the second step of claim 6; The third step is to form a second semiconductor layer at the first window position of the second-step protective layer and on the surface of the barrier layer, and then to form a first semiconductor layer on the surface of the second semiconductor layer; The fourth step is to remove the second-step protective layer, and then form a third-step protective layer on the barrier layer, and then etch the third-step protective layer to form a patterned fourth-step protective layer with a second window position; Step 5, forming a first semiconductor layer at the second window position of the four-step protective layer and on the surface of the barrier layer; The subsequent steps are the same as those of claim 6.

Images