Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and electronic equipment, the semiconductor device comprises a substrate, a channel layer stack part, a gate insulation layer, a surrounding gate and a source-drain function part, the channel layer stack part is formed on one side of the substrate and comprises a plurality of function layer groups arranged at intervals along the thickness direction of the substrate, and the gate insulation layer is formed on one side of the channel layer stack part; the functional layer group comprises a channel layer and at least one protective layer which are stacked in the thickness direction of the substrate, the length direction of the functional layer group is perpendicular to the thickness direction of the substrate, the functional layer group comprises a first region, a middle region and a second region which are arranged in the length direction, the protective layer is at least located in the middle region, and the channel layer is located in the first region, the middle region and the second region; the gate insulating layer surrounds the middle region in the direction around the length direction of the functional layer group; the surrounding type grid electrode surrounds the grid electrode insulating layer in the direction surrounding the length direction of the functional layer group. The performance of the semiconductor device provided by the invention is remarkably improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same, and an electronic device. Background Art

[0002] In the application process of high-mobility semiconductor devices (such as germanium and silicon-germanium as conductive channels), since the gate insulating layer (IL layer) is formed by oxidation, germanium oxide will be formed in the process of oxidizing the material of the conductive channel. Germanium oxide will cause the interface state density of the conductive channel to increase sharply, thereby reducing the performance of the semiconductor device and seriously limiting the development of high-mobility semiconductor devices. Summary of the invention

[0003] The purpose of this application is to at least solve the problem of low performance of semiconductor devices. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application provides a semiconductor device, comprising:

[0005] substrate;

[0006] a channel layer stack portion, formed on one side of the substrate, comprising a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate, the functional layer group comprising a channel layer and at least one protective layer stacked along the thickness direction of the substrate, the length direction of the functional layer group being perpendicular to the thickness direction of the substrate, the functional layer group comprising a first region, a middle region and a second region arranged along the length direction, the protective layer being at least located in the middle region, and the channel layer being located in the first region, the middle region and the second region;

[0007] a gate insulating layer, the gate insulating layer surrounding the middle region in a direction surrounding the length direction of the functional layer group;

[0008] a wraparound gate, the wraparound gate wrapping around the gate insulating layer in a direction around the length direction of the functional layer group;

[0009] The source-drain functional part includes a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on two opposite sides of the channel layer stack part along the length direction.

[0010] In the semiconductor device provided in the present application, a protective layer is formed between the channel layer and the gate insulating layer. The protective layer can prevent the surface of the channel layer from being oxidized and forming oxides during the formation of the gate insulating layer, thereby reducing the interface state density of the channel layer and reducing the subthreshold swing (SS) of the semiconductor device, thereby reducing the power consumption of the semiconductor device and improving the performance of the semiconductor device.

[0011] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:

[0012] providing a substrate;

[0013] A channel layer stack portion is formed on one side of the substrate, the channel layer stack portion comprises a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate, the functional layer group comprises a channel layer and at least one protective layer stacked along the thickness direction of the substrate, the length direction of the functional layer group is perpendicular to the thickness direction of the substrate, the functional layer group comprises a first region, a middle region and a second region arranged along the length direction, the protective layer is at least located in the middle region, and the channel layer is located in the first region, the middle region and the second region;

[0014] forming a gate insulating layer, the gate insulating layer surrounding the middle region in a direction surrounding the length direction of the functional layer group;

[0015] forming a wraparound gate, wherein the wraparound gate wraps around the gate insulating layer in a direction surrounding the length direction of the functional layer group;

[0016] A source-drain functional portion is formed, wherein the source-drain functional portion includes a source electrode and a drain electrode, and the source electrode and the drain electrode are located on two opposite sides of the channel layer stack portion along the length direction.

[0017] The third aspect of the present application also provides an electronic device, comprising at least one semiconductor device provided by the first aspect of the present application, and / or, comprising at least one semiconductor device prepared by the method for preparing a semiconductor device provided by the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0019] Figure 1 It is a schematic diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a partial structure of another semiconductor device provided in an embodiment of the present application;

[0021] Figure 3 It is a partial structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0022] Figure 4 is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0023] Figure 5 It is a schematic diagram of a formation process of stacked epitaxy in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0024] Figure 6 yes Figure 5 The main view;

[0025] Figure 7 It is a schematic diagram of a thinning process of a stacked epitaxial layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0026] Figure 8 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when a dummy gate is formed;

[0027] Fig. 9 It is a cross-sectional view of a method for preparing a semiconductor device provided in an embodiment of the present application when an inner sidewall is formed;

[0028] Fig.10 is a cross-sectional view of another method for preparing a semiconductor device provided in an embodiment of the present application when an inner sidewall is formed;

[0029] Fig.11 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when an outer side wall is formed;

[0030] Fig.12 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when a portion of the stacked epitaxy is removed;

[0031] Fig.13 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when a source electrode and a drain electrode are formed;

[0032] Fig.14 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when a dielectric layer is formed;

[0033] Fig.15 It is a front view of a method for preparing a semiconductor device provided in an embodiment of the present application when a dummy gate is removed;

[0034] Fig.16 It is a main view of a method for preparing a semiconductor device provided in an embodiment of the present application when a wraparound gate is formed.

[0035] The reference numerals are as follows:

[0036] 1. semiconductor device; 11. substrate; 12. channel layer stack; 120. functional layer group; 121. channel layer; 122. protective layer; x, length direction; A1, first area; A2, middle area; A3, second area; 13. gate insulating layer; 14. wraparound gate; 15. source-drain functional part; 151. source; 152. drain; 16. stacked epitaxy; 160. layer group to be patterned; 161. sacrificial layer; 162. protective material layer; B1, removal area; B2, reserved area; 17. dummy gate; y, second direction; 18. inner wall; Q, gap; 19. outer wall; 20. dielectric layer.

[0037] Specific implementation method

[0038] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0039] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0040] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0041] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0042] It has been found that in the application process of high-mobility semiconductor devices (such as germanium and silicon germanium as conductive channels), since the gate insulating layer (IL layer) is formed by oxidation, germanium oxide will be formed in the process of oxidizing the material of the conductive channel. The germanium oxide will cause the interface state density of the conductive channel to increase sharply, resulting in the deterioration of the subthreshold swing (SS) of the semiconductor device, thereby causing the power consumption of the semiconductor device to rise sharply, resulting in the performance of the semiconductor device to decrease. The current solution for the passivation of the interface of the high-mobility conductive channel in the industry is mainly: after forming germanium oxide in the IL layer, aluminum oxide is deposited as a passivation layer to passivate the conductive channel interface, but this method introduces aluminum oxide as a passivation layer while bringing about the threshold shift problem affected by Al, so the improvement effect on the performance of the semiconductor device is limited. Therefore, the present application provides a semiconductor device and a preparation method thereof to further improve the performance of the semiconductor device.

[0043] like Figure 1 and Figure 2As shown, according to an embodiment of the present application, a semiconductor device 1 is proposed, comprising a substrate 11, a channel layer stack 12, a gate insulating layer 13, a wraparound gate 14 and a source-drain functional portion 15. The channel layer stack 12 is formed on one side of the substrate 11, and comprises a plurality of functional layer groups 120 arranged at intervals along the thickness direction of the substrate 11. The functional layer group 120 comprises a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11. The length direction x of the functional layer group 120 is perpendicular to the thickness direction of the substrate 11. The functional layer group 120 comprises a first region A1, a middle region A2 and a second region A3 arranged along the length direction x. The protective layer 122 is at least located in the middle region A2, and the channel layer 121 is located in the first region A1, the middle region A2 and the second region A3. The gate insulating layer 13 wraps around the middle region A2 along the length direction x around the functional layer group 120. The wraparound gate 14 wraps around the gate insulating layer 13 along the length direction x around the functional layer group 120. The source-drain functional portion 15 includes a source 151 and a drain 152 . The source 151 and the drain 152 are located at two opposite sides of the channel layer stack portion 12 along the length direction x.

[0044] In the semiconductor device 1 provided in the present application, a protective layer 122 is formed between the channel layer 121 and the gate insulating layer 13. The protective layer 122 can prevent the surface of the channel layer 121 from being oxidized and forming oxides during the formation of the gate insulating layer 13, thereby reducing the interface state density of the channel layer 121 and reducing the subthreshold swing (SS) of the semiconductor device 1, thereby reducing the power consumption of the semiconductor device 1 and improving the performance of the semiconductor device 1.

[0045] Specifically, the semiconductor device 1 provided in the present application includes a full surround gate transistor (GAA), and the surround gate 14 surrounds the channel layer 121 along the direction of the length of the channel layer 121, thereby increasing the contact area between the surround gate 14 and the channel layer 121, and can better control the current flowing through the channel, thereby reducing leakage current, improving efficiency, and reducing power consumption. The surround gate 14 and the gate insulation layer 13 only surround the middle area A2, so the protection layer 122 is at least located in the middle area A2 to achieve isolation between the gate insulation layer 13 and the channel area. Figure 3 As shown, the protection layer 122 may also be located in the first area A1 and / or the second area A3, which is not particularly limited in the present application.

[0046] Specifically, the channel layer 121 may include four side surfaces along the circumference of its own length direction x, and the four side surfaces include a first surface and a second surface arranged along the thickness direction of the substrate 11, and a third surface and a fourth surface connected between the first surface and the second surface, and the third surface and the fourth surface are arranged opposite to each other. Among them, the area of ​​the first surface and the second surface is larger than that of the third surface and the fourth surface. Moreover, the first surface and the second surface are (100) surfaces, and the third surface and the fourth surface are (100) surfaces. The atoms of the (100) surface are less than those of the (110) surface, so the (100) surface is more easily oxidized.

[0047] In a feasible implementation manner, in the functional layer group 120 , the number of the protective layers 122 is two and they are respectively located on both sides of the channel layer 121 along the thickness direction of the substrate 11 .

[0048] In the above embodiment, since the two surfaces of the channel layer 121 arranged along the thickness direction of the substrate 11, namely the first surface and the second surface, are large in area and easier to be oxidized, two layers of protective layers 122 can be set in each functional layer group 120, wherein one layer of protective layer 122 contacts the first surface and at least covers a portion of the first surface located in the middle area A2, and the other layer of protective layer 122 contacts the second surface and at least covers a portion of the second surface located in the middle area A2, so that the area surrounded by the gate insulating layer 13 in the channel region is isolated from the gate insulating layer 13, thereby reducing the adverse effects on the channel region when forming the gate insulating layer 13, thereby improving the performance of the semiconductor device 1.

[0049] Specifically, since the third surface and the fourth surface are (100) surfaces, they are not easily oxidized, and the areas of the third surface and the fourth surface are relatively small, and the time for preparing the gate oxide layer is very short, therefore, the third surface and the fourth surface do not need to be provided with a protective layer 122, thereby reducing the difficulty of preparation and reducing the preparation cost.

[0050] In another feasible implementation, in order to simplify the manufacturing process, the protection layer 122 may be formed only on the first surface or the second surface of the channel layer 121 .

[0051] In a feasible implementation manner, the material of the protection layer 122 includes silicon.

[0052] In the above embodiment, the material of the gate insulating layer 13 may include silicon dioxide. Specifically, during the preparation process of the gate insulating layer 13, ozone may be introduced into deionized water at room temperature after the protective layer 122 is prepared, and the time is controlled to be within 20 seconds.

[0053] In a feasible implementation manner, the thickness of the protection layer 122 is in the range of 1 nm to 5 nm.

[0054] Specifically, the thickness of the protection layer 122 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0055] If the thickness of the protective layer 122 is too thin, it may cause protection failure. If the thickness of the protective layer 122 is too thick, it may increase the thickness of the semiconductor device 1. Controlling the thickness of the protective layer 122 within the range of 1nm-5nm can achieve both protection effect and thinness of the semiconductor device 1.

[0056] In a feasible implementation, the material of the channel layer 121 includes silicon germanium or germanium.

[0057] In the above embodiment, compared with the current mainstream silicon channel layer 121, the all-around gate transistor device with a channel layer 121 made of silicon germanium or germanium can alleviate the impact of stress engineering weakening caused by miniaturization and the influence of conductive crystal orientation changes on mobility, and further improve driving performance.

[0058] In a feasible implementation manner, the thickness of the channel layer 121 is 6 nm.

[0059] In the above embodiment, the thickness of the channel layer 121 is 6 nm to meet the thickness requirement of the channel layer 121 of a 3 nm node device.

[0060] The present application also provides a method for preparing a semiconductor device 1, such as Figure 5 As shown, including:

[0061] S200 , providing a substrate 11 .

[0062] Specifically, the material of the substrate 11 may include a silicon substrate 11 .

[0063] S400, a channel layer stack portion 12 is formed on one side of the substrate 11, the channel layer stack portion 12 includes a plurality of functional layer groups 120 arranged at intervals along the thickness direction of the substrate 11, the functional layer group 120 includes a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11, the length direction x of the functional layer group 120 is perpendicular to the thickness direction of the substrate 11, the functional layer group 120 includes a first area A1, a middle area A2 and a second area A3 arranged along the length direction x, the protective layer 122 is at least located in the middle area A2, and the channel layer 121 is located in the first area A1, the middle area A2 and the second area A3.

[0064] Specifically, adjacent functional layer groups 120 are spaced apart and provided with an accommodation space, and the accommodation space is used to accommodate the gate insulating layer 13 and the surrounding gate 14 .

[0065] S600 , forming a gate insulating layer 13 , wherein the gate insulating layer 13 surrounds the middle area A2 along a direction of a length direction x of the functional layer group 120 .

[0066] S800 , forming a wraparound gate 14 , wherein the wraparound gate 14 wraps around the gate insulating layer 13 along a length direction x of the functional layer group 120 .

[0067] S1000 , forming a source-drain functional portion 15 , the source-drain functional portion 15 including a source 151 and a drain 152 , the source 151 and the drain 152 are located on two opposite sides of the channel layer stack portion 12 along the length direction x.

[0068] Specifically, the channel layer 121 includes a first end and a second end along its own length direction x, the first end is located in the first area A1, and the second end is located in the second area A3, one of the source 151 and the drain 152 can contact the end surface of the first end, and the other can contact the end surface of the second end, thereby realizing the connection between the source 151, the drain 152 and the channel layer 121.

[0069] Specifically, when the semiconductor device 1 is a P-MOS tube, the material of the source 151 and the drain 152 can be selected from silicon germanium, and when the semiconductor device 1 is an N-MOS tube, the material of the source 151 and the drain 152 can be selected from silicon. The source 151 and the drain 152 can also be selected from other materials, which is not particularly limited in this application.

[0070] In the above preparation method, the channel layer stack portion 12 is formed first, and then the gate insulating layer 13 is formed. In the process of forming the channel layer stack portion 12, a protective layer 122 is formed on the surface of one side of the channel layer 121 close to and / or away from the substrate 11. In the subsequent process of forming the gate insulating layer 13, under the protective effect of the protective layer 122, the surface of the channel layer 121 is not easily oxidized to form oxide, thereby reducing the interface state density of the channel layer 121 and reducing the subthreshold swing (SS) of the semiconductor device 1, thereby reducing the power consumption of the semiconductor device 1 and improving the performance of the semiconductor device 1.

[0071] In a feasible implementation manner, forming the channel layer stack portion 12 on one side of the substrate 11 includes:

[0072] S401, such as Figure 6 As shown, a stacked epitaxial layer 16 is formed on one side of the substrate 11, and the stacked epitaxial layer 16 includes a plurality of channel layers 121 and a plurality of layer groups 160 to be patterned that are alternately arranged in a direction away from the substrate 11, and the layer groups 160 to be patterned include a sacrificial layer 161 and at least one protective material layer 162 that are stacked in a thickness direction of the substrate 11.

[0073] Specifically, the to-be-patterned layer group 160 includes a sacrificial layer 161 and a protective material layer 162 located on a side of the sacrificial layer 161 close to and / or away from the substrate 11. When the sacrificial layer 161 is adjacent to the protective material layer 162 only on a side close to or away from the substrate 11, the arrangement order of the sacrificial layer 161 and the protective material layer 162 in different functional layer groups 120 can be interchanged, and this application does not specifically limit this.

[0074] Specifically, the channel layer 121 is the channel layer 121 in the functional layer group 120 , and the protective material layer 162 is used to form the protective layer 122 . The protective material layer 162 is patterned to form the protective layer 122 , or the protective material layer 162 is not patterned and directly used as the protective layer 122 .

[0075] S402, such as Figure 7 As shown, both sides of the stacked epitaxy 16 along a first direction are thinned to form a removed area B1 and a retained area B2 , and the first direction is perpendicular to the thickness direction of the substrate 11 .

[0076] Specifically, the two sides along the first direction in the stacked epitaxy 16 represent the two sides located in the length direction x of the channel layer 121, wherein the two sides include a first side and a second side, and the arrangement direction of the first side and the second side is perpendicular to the first direction and perpendicular to the thickness direction of the substrate 11. In the specific preparation process, the stacked epitaxial outer layer needs to be thinned from both sides.

[0077] Specifically, while thinning the stacked epitaxial layer 16 , a shallow trench isolation structure can also be formed on the substrate 11 simultaneously to achieve electrical isolation of adjacent structures in the semiconductor device 1 .

[0078] S403, such as Figure 8 As shown, a dummy gate 17 is formed, which covers portions of the two side surfaces of the reserved area B2 perpendicular to the second direction y, and covers portions of the side surface of the reserved area B2 away from the substrate 11. The second direction y is perpendicular to the first direction and perpendicular to the thickness direction of the substrate 11.

[0079] Specifically, the dummy gate 17 is used to cover the position where the gate is to be formed to prevent other film layers from affecting the position. On the one hand, it is easy to prepare, and on the other hand, it can improve the preparation yield of the subsequent wrap-around gate 14 .

[0080] S404, such as Fig. 9 and Fig.10As shown, forming an inner sidewall 18 and a functional layer group 120 includes removing at least a portion of the sacrificial layer 161 in the layer group to be patterned 160 located on both sides of the dummy gate 17 along the first direction to form a gap Q; forming an inner sidewall 18 in the gap Q; removing the dummy gate 17, and removing a portion of the sacrificial layer 161 located between two adjacent inner sidewalls 18 along the first direction to form a plurality of functional layer groups 120 arranged at intervals.

[0081] Specifically, since the channel layer 121 and the to-be-patterned layer group 160 in the stacked epitaxy 16 are stacked in a direction away from the substrate 11 without being spaced apart, there is no position for subsequently forming the surrounding gate 14 in the stacked epitaxy 16. It is necessary to form a space for accommodating the surrounding gate 14 by removing the sacrificial layer 161 in the to-be-patterned layer group 160.

[0082] The sacrificial layer 161 can be removed in two steps. The first step is to remove the portions of the sacrificial layer 161 located on both sides of the dummy gate 17 along the first direction to form a gap Q, and the gap Q is used to form the inner sidewall 18. The second step is to remove the portions of the sacrificial layer 161 covered by the dummy gate 17 before the dummy gate 17 is removed after the dummy gate 17 is removed to release the channel layer 121. At this time, the portions of the protective material layer 162 covered by the dummy gate 17 before the dummy gate 17 is removed are retained, and a receiving space for receiving the gate insulating layer 13 and the surrounding gate 14 is formed at the original position of the sacrificial layer 161. The receiving space is located between adjacent channel layers 121. When the protective material layer 162 is provided on both the surface of the channel layer 121 close to the substrate 11 and the surface of the channel layer 121 away from the substrate 11, the above-mentioned receiving space is located between adjacent protective material layers 162.

[0083] Among them, the inner side wall 18 is used to block the etching solution or etching gas used to etch the sacrificial layer 161 when the sacrificial layer 161 is removed for the second time, that is, when the part of the sacrificial layer 161 originally covered by the dummy gate 17 is removed, so as to avoid the etching solution or etching gas continuing to flow along the first direction after the sacrificial layer 161 is completely removed during the etching process of the sacrificial layer 161, thereby damaging the source 151 and the drain 152.

[0084] After the sacrificial layer 161 is removed, the preparation of the functional layer group 120 is completed. The functional layer group 120 includes a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11. The length direction x of the functional layer group 120 is parallel to the first direction. The functional layer group 120 includes a first area A1, a middle area A2, and a second area A3 arranged along the first direction. The protective layer 122 is at least located in the middle area A2, and the channel layer 121 is located in the first area A1, the middle area A2, and the second area A3. Among them, the orthographic projections of the first area A1 and the second area A3 on the substrate 11 coincide with the orthographic projections of the gap Q and the inner sidewall 18 on the substrate 11, and the orthographic projection of the middle area A2 on the substrate 11 coincides with the orthographic projection of the accommodation space for accommodating the surround gate 14 on the substrate 11.

[0085] In the above embodiment, during the process of forming the gap Q, only the portions of the sacrificial layer 161 in the to-be-patterned layer group 160 located on both sides of the dummy gate 17 along the first direction may be removed, and the protective material layer 162 is not etched and directly serves as the protective layer 122. At this time, the protective layer 122 may be located in the first area A1, the middle area A2, and the second area A3.

[0086] In the above embodiment, during the process of forming the gap Q, the portions of the protective material layer 162 in the patterned layer group 160 located on both sides of the dummy gate 17 along the first direction can also be removed simultaneously to form the protective layer 122. At this time, the protective layer 122 is located in the middle area A2.

[0087] In a feasible implementation manner, the to-be-patterned layer group 160 includes a sacrificial layer 161 and protective material layers 162 stacked on both sides of the sacrificial layer 161 along the thickness direction of the substrate 11 .

[0088] In the above embodiment, the protection layer 122 can be provided on both the side of the channel layer 121 close to the substrate 11 and the side away from the substrate 11, so as to increase the protection effect on the channel and further improve the performance of the device.

[0089] In a feasible implementation manner, the thickness of the sacrificial layer 161 is in the range of 1 nm to 5 nm; and / or the thickness of the protective material layer 162 is in the range of 1 nm to 5 nm; and / or the thickness of the channel layer 121 is 6 nm.

[0090] Specifically, the thickness of the sacrificial layer 161 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0091] Specifically, the thickness of the protection material layer 162 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0092] If the thickness of the protective layer 122 is too thin, it may cause protection failure. If the thickness of the protective layer 122 is too thick, it may increase the thickness of the semiconductor device 1. Controlling the thickness of the protective layer 122 within the range of 1nm-5nm can achieve both protection effect and thinness of the semiconductor device 1.

[0093] In the above embodiment, the thickness of the channel layer 121 is 6 nm to meet the thickness requirement of the channel layer 121 of a 3 nm node device.

[0094] In a feasible implementation, the material of the sacrificial layer 161 includes one of germanium, germanium silicon, and zirconium dioxide.

[0095] In the above embodiment, the sacrificial layer 161 is made of a material that has a crystal structure similar to that of the film layer below and can be epitaxially grown. Specifically, when the lower material layer protects the material layer 162, the protective material layer 162 can be made of silicon, and the sacrificial layer 161 is made of a material that has a crystal structure similar to that of (100) silicon and can be epitaxially grown, and can be made of one of germanium, germanium silicon, and zirconium dioxide.

[0096] In a feasible implementation manner, during the process of removing the sacrificial layer 161 , a dry etching process or a wet etching process may be used for removal.

[0097] Specifically, when the sacrificial layer 161 is made of silicon germanium, a channel release solution may be used to perform etching to remove the sacrificial layer 161 . The channel etching solution is a mixture of acetic acid, hydrofluoric acid, and hydrogen peroxide.

[0098] In a possible implementation, Fig.11 As shown, after forming the dummy gate 17 and before forming the inner sidewall 18, the outer sidewall 19 is further formed, specifically including: forming the outer sidewalls 19 on two opposite sides of the dummy gate 17 along the first direction, and the inner sidewall 18 exposes two ends of the stacked epitaxial layer 16 arranged along the first direction.

[0099] In the above embodiment, the outer sidewall 19 is formed to define the position of the surrounding gate 14 to be formed after the dummy gate 17 is removed.

[0100] Also includes, such as Fig.12 As shown, the two ends of the epitaxial stack exposed by the outer sidewall 19 along the first direction are removed to form a source region and a drain region located on both sides of the stacked epitaxial 16 arranged along the first direction. This facilitates the subsequent formation of the source 151 and the drain 152 to contact the first area A1 and the second area A3 respectively. In a feasible embodiment, the step of forming the inner sidewall 18 in the gap Q includes:

[0101] Depositing an inner sidewall material layer, the orthographic projection of the inner sidewall material layer on the substrate 11 covers the dummy gate 17 and the outer sidewall 19 as well as the source region and the drain region, wherein the inner sidewall material layer wraps the surface of the outer sidewall 19 facing away from the dummy gate 17, and the inner sidewall material layer fills the gap Q;

[0102] The inner sidewall material layer is patterned to remove the portion of the inner sidewall material layer located in the source region and the drain region.

[0103] In the above embodiment, the material of the inner wall material layer and the outer wall 19 can be the same, both made of silicon nitride.

[0104] The deposited inner sidewall material layer prepared by depositing a whole layer is then etched to form an inner sidewall 18, wherein the portion of the inner sidewall material layer except for the portion located in the gap Q needs to be removed to expose the outer sidewall 19, the dummy gate 17, the source region, and the drain region to facilitate the preparation of subsequent film layers.

[0105] In a possible implementation, Fig.13 As shown, a source electrode 151 and a drain electrode 152 are formed in the source region and the drain region respectively, and the source electrode 151 and the drain electrode 152 are respectively in contact with two ends of the channel layer 121 along the first direction.

[0106] In the above embodiment, when forming the source 151 and the drain 152 , the source 151 epitaxial layer and the drain 152 epitaxial layer may be formed first, and then the source 151 epitaxial layer and the drain 152 epitaxial layer may be doped to form the source 151 and the drain 152 .

[0107] In a feasible implementation, it also includes:

[0108] like Fig.14 As shown, a dielectric layer 20 is formed, and the dielectric layer 20 covers the source 151 , the drain 152 , the inner sidewall 18 and the dummy gate 17 .

[0109] In the above embodiment, the dielectric layer 20 is used to planarize the top of the semiconductor device 1. During the preparation process, the dielectric material layer may be deposited first, and then the side of the dielectric material layer facing away from the substrate 11 may be polished by a chemical mechanical polishing process.

[0110] In the above implementation mode, if Fig.15 As shown, after forming the dielectric layer 20, the dummy gate 17 is removed. Fig.16 As shown, after removing the dummy gate 17, the sacrificial layer 161 is removed to form the gate insulating layer 13 and the surrounding gate 14. When removing the dummy gate 17, the portion of the dielectric layer 20 located on the side of the dummy gate 17 away from the substrate 11 is removed simultaneously.

[0111] The present application also provides an electronic device, which includes at least one semiconductor device 1 provided in the above embodiment, and / or includes at least one semiconductor device 1 prepared by the method for preparing the semiconductor device 1 provided in the above embodiment.

[0112] The performance of the semiconductor device in the electronic device is significantly improved, thereby significantly improving the performance of the electronic device, thereby improving the user experience.

[0113] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a channel layer stack portion, formed on one side of the substrate, comprising a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate, the functional layer group comprising a channel layer and at least one protective layer stacked along the thickness direction of the substrate, the length direction of the functional layer group being perpendicular to the thickness direction of the substrate, the functional layer group comprising a first region, a middle region and a second region arranged along the length direction, the protective layer being at least located in the middle region, and the channel layer being located in the first region, the middle region and the second region; a gate insulating layer, the gate insulating layer surrounding the middle region in a direction surrounding the length direction of the functional layer group; a wraparound gate, the wraparound gate wrapping around the gate insulating layer in a direction around the length direction of the functional layer group; The source-drain functional part includes a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on two opposite sides of the channel layer stack part along the length direction.

2. The semiconductor device according to claim 1, wherein: In the functional layer group, the number of the protective layers is two and they are respectively located on both sides of the channel layer along the thickness direction of the substrate.

3. The semiconductor device according to claim 1, wherein: The material of the channel layer includes germanium silicon or germanium, and / or the material of the protection layer includes silicon.

4. The semiconductor device according to claim 1, wherein: The thickness of the protection layer is in the range of 1 nm to 5 nm; the thickness of the channel layer is 6 nm.

5. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; A channel layer stack portion is formed on one side of the substrate, the channel layer stack portion comprises a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate, the functional layer group comprises a channel layer and at least one protective layer stacked along the thickness direction of the substrate, the length direction of the functional layer group is perpendicular to the thickness direction of the substrate, the functional layer group comprises a first region, a middle region and a second region arranged along the length direction, the protective layer is at least located in the middle region, and the channel layer is located in the first region, the middle region and the second region; forming a gate insulating layer, the gate insulating layer surrounding the middle region in a direction surrounding the length direction of the functional layer group; forming a wraparound gate, wherein the wraparound gate wraps around the gate insulating layer in a direction surrounding the length direction of the functional layer group; A source-drain functional portion is formed, wherein the source-drain functional portion includes a source electrode and a drain electrode, and the source electrode and the drain electrode are located on two opposite sides of the channel layer stack portion along the length direction.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The forming of a channel layer stack portion on one side of the substrate comprises: forming a stacked epitaxy on one side of the substrate, the stacked epitaxy comprising a plurality of channel layers and a plurality of to-be-patterned layer groups alternately arranged in a direction away from the substrate, the to-be-patterned layer groups comprising a sacrificial layer and at least one protective material layer stacked in a thickness direction of the substrate; Thinning both sides of the stacked epitaxy along a first direction to form a removal area and a retention area, wherein the first direction is perpendicular to the thickness direction of the substrate; forming a dummy gate, the dummy gate covering portions of both side surfaces of the reserved region perpendicular to a second direction, and covering a portion of a side surface of the reserved region away from the substrate, the second direction being perpendicular to the first direction and perpendicular to a thickness direction of the substrate; The inner side wall and the functional layer group are formed, including removing at least the portion of the sacrificial layer in the layer group to be patterned located on both sides of the dummy gate along the first direction to form a gap; forming an inner side wall in the gap; removing the dummy gate, and removing the portion of the sacrificial layer located between two adjacent inner side walls along the first direction to form a plurality of the functional layer groups arranged at intervals.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The layer group to be patterned includes a sacrificial layer and protective material layers stacked on both sides of the sacrificial layer along the thickness direction of the substrate.

8. The method for preparing a semiconductor device according to claim 6, characterized in that: The thickness of the sacrificial layer is in the range of 1 nm to 5 nm; and / or the thickness of the protective material layer is in the range of 1 nm to 5 nm; and / or the thickness of the channel layer is 6 nm.

9. The method for preparing a semiconductor device according to claim 6, characterized in that: The material of the sacrificial layer includes one of germanium, germanium silicon, and zirconium dioxide.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: After forming the dummy gate and before forming the inner sidewall, the method further includes forming an outer sidewall, specifically comprising: forming outer sidewalls on two opposite sides of the dummy gate along the first direction, respectively, and the inner sidewalls expose two ends of the stacked epitaxial layer arranged along the first direction; The method further includes removing two ends of the epitaxial stack exposed along the first direction through the outer sidewalls to form a source region and a drain region located on two sides of the stacked epitaxial layer arranged along the first direction.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The step of forming an inner side wall in the gap comprises: Depositing an inner sidewall material layer, the orthographic projection of the inner sidewall material layer on the substrate covers the dummy gate and the outer sidewall as well as the source region and the drain region, wherein the inner sidewall material layer wraps a surface of the outer sidewall facing away from the dummy gate, and the inner sidewall material layer fills the gap; The inner sidewall material layer is patterned to remove portions of the inner sidewall material layer located in the source region and the drain region.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The method further includes forming a source electrode and a drain electrode in the source region and the drain region, respectively, wherein the source electrode and the drain electrode are in contact with two ends of the channel layer along the first direction, respectively.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: Also includes: A dielectric layer is formed, wherein the dielectric layer covers the source, the drain, the inner sidewall and the dummy gate.

14. An electronic device, characterized in that: The electronic device comprises at least one semiconductor device according to any one of claims 1 to 4, and / or comprises at least one semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 5 to 13.

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