Si / SiC heterojunction structure and manufacturing method thereof
By using P-Si/N-SiC heterojunction and thermal oxidation to form a high-quality SiO2 gate oxide layer in Si/SiC heterojunction structure, the Si/SiC heterojunction device is solved due to lattice mismatch and The stack layer error defects caused by SiC surface state and other influences improve the performance and reliability of the device.
Patent Information
- Application Number
- CN202310946775.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
Due to the influence of lattice mismatch and SiC surface state, existing Si/SiC heterojunction devices have defects such as high density stack layer errors, which limit their applications in larger blocking voltages and higher temperatures.
P-Si/N-SiC heterojunction structure is adopted to form P-type doping through implantation/annealing or epitaxial processes, and the junction depth is controllable. Combined with thermal oxidation, a high-quality SiO2 gate oxide layer is formed to reduce the interfacial state density.
It effectively reduces the process difficulty of Si/SiC heterojunction, improves process quality, improves the performance and reliability of silicon carbide devices, and is suitable for applications with larger blocking voltages and higher temperatures.
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Figure CN119451196A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power devices, and in particular to a Si / SiC heterojunction structure and a manufacturing method thereof. Background Art
[0002] At present, silicon is the basic material for manufacturing most power devices. Silicon material has the advantages of simple preparation, mature process and low cost. However, due to the small bandgap width of silicon material, its application in larger blocking voltage and higher temperature is limited.
[0003] Silicon carbide materials have the advantages of large bandgap, low intrinsic carrier concentration, high critical electric field, high thermal conductivity and high saturation drift velocity, making them the preferred material for manufacturing high-voltage, high-temperature, high-frequency, high-power and radiation-resistant devices. However, the manufacturing of silicon carbide-based devices is not fully compatible with bulk silicon processes for the time being, and there is still a certain gap in doping, ohmic contact, gate oxide layer quality, etc.
[0004] The application of Si / SiC heterojunction devices can combine the advantages of mature silicon material technology and silicon carbide materials to improve the performance of devices; however, Si / SiC heterojunctions have defects such as high-density stacking faults due to lattice mismatch and SiC surface state. With the development of technologies such as molecular beam epitaxy (MBE), low-pressure chemical vapor deposition (LPCVD) and wafer bonding, the growth of high-quality SiC-based heterogeneous materials has made great progress, which has greatly promoted the rapid development of heterojunction devices. Summary of the invention
[0005] To overcome the deficiencies of the prior art, the present invention provides a Si / SiC heterostructure and a method for manufacturing the same, which avoids process difficulties such as high interface states of silicon carbide, reduces process difficulty, improves process quality, and enhances the performance and reliability of silicon carbide devices.
[0006] The present invention adopts the following technical solution:
[0007] The present invention provides a Si / SiC heterojunction structure, wherein the heterojunction forms the anode region of a diode, the P-type Si is located above the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers;
[0008] Or form the back emitter region of the insulated gate bipolar transistor IGBT, the P-type Si is located below the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers.
[0009] Furthermore, the structure is a P-Si / N-SiC heterojunction structure, the P-Si is located above the N-SiC, the P-type doping of the P-Si is formed by an injection / annealing or epitaxial process, and the junction depth is controllable.
[0010] Furthermore, the Si / SiC heterojunction forms the back emission region of the IGBT, the P-Si is located below the N-SiC, and the P-type doping of the P-Si is formed by an implantation / annealing or epitaxial process.
[0011] Furthermore, a Si / SiC heterojunction forms the front gate of the IGBT, where Si is located above the N-SiC. Si is formed using processes such as epitaxy, and the thickness and quality are controllable. Thermal oxidation is used to convert all Si into SiO2.
[0012] Furthermore, a Si / SiC heterojunction forms the front gate of the IGBT, where Si is located above the N-SiC. Si is formed using an epitaxial process with controllable thickness and quality. Thermal oxidation is used to partially convert Si into SiO2, and the N+ / P+ junction / P- junction of the IGBT is located in the N-Si; or part of the P well is placed in the SiC.
[0013] Furthermore, the Si / SiC heterojunction forms the P well contacting the P+ region on the front side of the IGBT, and the P+-Si is located in a local area above the N-SiC. The P+Si is formed by processes such as injection / annealing or epitaxy, and then etched, and subsequent processes and structures are completed in sequence to form the IGBT front side structure.
[0014] Furthermore, the SiC / Si heterojunction forms the substrate and drift region of the power device, and Si is located below the SiC, serving as a substrate or as part of the drift region.
[0015] Furthermore, the electric field strength in silicon is lower than the maximum breakdown field strength E of silicon material. max,Si .
[0016] The present invention also relates to a method for manufacturing a Si / SiC heterojunction structure, comprising the following steps:
[0017] Step 1, N-SiC material preparation;
[0018] Step 2, forming Si material on SiC by epitaxy or other processes;
[0019] Step 3, thermal oxidation to form a gate oxide layer;
[0020] Step 4, performing polycrystalline deposition and etching;
[0021] Step 5, forming a P-junction by implantation and pushing;
[0022] Step 6, implantation and activation to form N+ / P+ junction;
[0023] Step 7, deposition and etching of isolation layer on polycrystalline;
[0024] Step 8, metal deposition and etching;
[0025] Step 9: passivation deposition and etching.
[0026] Compared with the prior art, the technical solution of the present invention can achieve the following beneficial technical effects:
[0027] Compared with traditional silicon carbide structures, this patented structure is compatible with traditional silicon manufacturing processes, reduces process difficulty, improves process quality, reduces costs, and improves the performance and reliability of silicon carbide devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 Schematic diagram of the traditional silicon carbide structure of the present invention.
[0029] Figure 2 The anode region of the diode is formed by the 1-Si / SiC heterojunction according to the embodiment of the present invention.
[0030] Figure 3 The 2-Si / SiC heterojunction of the embodiment of the present invention forms the back emission region of the IGBT.
[0031] Figure 4 The 3-Si / SiC heterojunction of the embodiment of the present invention forms the front gate of the IGBT.
[0032] Figure 5 The front MOS structure of the IGBT is formed by the 4-Si / SiC heterojunction according to the embodiment of the present invention.
[0033] Figure 6 The P well contacts the P+ region on the front side of the IGBT formed by the 5-Si / SiC heterojunction of the embodiment of the present invention.
[0034] Figure 7 The 6-SiC / Si heterojunction of the embodiment of the present invention forms the substrate and drift region of the power device. DETAILED DESCRIPTION
[0035] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.
[0036] The method of the present invention is described in detail below with reference to specific embodiments.
[0037] A first aspect of the present invention provides a Si / SiC heterostructure.
[0038] The device structure of the present invention is as follows Figure 2 As shown, Figure 1Compared with the conventional structure shown in the figure, the conventional structure is a single silicon carbide material, and the present invention is a Si / SiC heterojunction material. This structure can have multiple deformations, such as the P-Si / N-SiC heterojunction can form the anode region of the diode, with the P-type Si located above the N-type SiC, and can also form the back emission region of the insulated gate bipolar transistor IGBT, with the P-type Si located below the N-type SiC. The heterojunction forms the anode region of the diode (the P-type Si is located above the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers), or forms the back emission region of the insulated gate bipolar transistor IGBT (the P-type Si is located below the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers). Si and SiC are semiconductor materials.
[0039] Specifically, in Example 1, the Si / SiC heterojunction forms the anode region of the diode, see Figure 2 . P-Si / N-SiC heterojunction structure, P-Si is located above N-SiC, and the P-type doping of P-Si is formed by injection / annealing or epitaxy. The junction depth is controllable and the activation rate is close to 100%. It avoids the risk of silicon carbide injection only forming a shallow junction and a low activation rate. In addition, compared with SiO2 / SiC, SiO2 / Si has a lower interface state density, which improves the reliability of the device.
[0040] Specifically, in Example 2, the Si / SiC heterojunction forms the back emission region of the IGBT, see Figure 3 . P-Si / N-SiC heterojunction structure, P-Si is located below N-SiC, and the P-type doping of P-Si is formed by injection / annealing or epitaxy. The junction depth is controllable, the doping morphology is controllable, and the activation rate is close to 100%. It avoids the problems of P-type silicon carbide being unable to achieve heavy doping and the high resistivity of P-type doping.
[0041] Specifically, in Example 3, the Si / SiC heterojunction forms the front gate of the IGBT, see Figure 4 . Si / N-SiC heterojunction structure, Si is located above N-SiC ( Figure 4 a), Si is formed by epitaxy and other processes, and the thickness and quality are controllable; then thermal oxidation is used to convert all Si into SiO2 ( Figure 4 b). The quality of the generated SiO2 is controllable and the interface state is low, which can avoid the problem of high interface state of conventional SiO2 / SiC, which causes threshold voltage drift.
[0042] Specifically, in Example 4, the Si / SiC heterojunction forms the front gate of the IGBT, see Figure 5 . Si / N-SiC heterojunction structure, Si is located above N-SiC ( Figure 5 a), Si is formed by epitaxy and other processes, and the thickness and quality are controllable; then thermal oxidation is used to convert Si into SiO2 ( Figure 5b), the N+ / P+ / P- junction of the IGBT is located in N-Si. The quality of the generated SiO2 is controllable, and the interface state is low, which can avoid the problem of high interface state of conventional SiO2 / SiC, which causes threshold voltage drift. It is also possible to place part of the P well in SiC ( Figure 5 c) By utilizing the high critical breakdown electric field of silicon carbide material, the blocking voltage of the device is increased.
[0043] Specifically, in Example 5, the Si / SiC heterojunction forms a P well contacting the P+ region on the front side of the IGBT, see Figure 6 . P+-Si / N-SiC heterojunction structure, P+-Si is located in the local area above N-SiC, and P+Si is implanted / annealed or epitaxially ( Figure 6 a), then etch and form, and complete the subsequent processes and structures in sequence to form the IGBT front structure ( Figure 6 b); It avoids the problem of low activation rate of P-type doping in silicon carbide and can significantly reduce the P-type contact resistivity of the silicon carbide structure.
[0044] Specifically, in Example 6, SiC / Si heterojunction forms the substrate and drift region of the power device, see Figure 7 Si is located below SiC, as a substrate or as part of the drift region; it should be noted that the electric field strength in silicon should be lower than the maximum breakdown field strength E of the silicon material. max,Si SiC is formed by epitaxy and other processes, and its thickness and quality are controllable. Replacing the SiC substrate / part of the drift region with Si can reduce costs.
[0045] Si / SiC heterojunction can also be extended to other silicon carbide structures, such as MOSFET, GTO, etc.
[0046] The invention also provides a method for manufacturing a Si / SiC heterostructure.
[0047] Specifically, in one embodiment of the present invention, the manufacturing method comprises the following steps:
[0048] 1. Preparation of N-SiC materials;
[0049] 2. Use epitaxy or other processes to form Si material on SiC, and the doping concentration and thickness are determined by the device blocking voltage;
[0050] 3. Thermal oxidation forms a gate oxide layer with a thickness of 0.05μm-0.15μm and a process temperature of 700℃-1200℃;
[0051] 4. Polycrystalline deposition and etching; polycrystalline thickness is 0.5μm-1.0μm, process temperature is 500℃-800℃;
[0052] 5. P-junction formation is usually formed by injection and push junction. The P-junction injection element is boron and other elements, the energy is 50KeV-100KeV, and the dose is 1E13 / cm 2 -1E14cm 2 The junction temperature is 1000℃-1250℃, and the junction time is 30-400min. The P-junction can also be formed by other processes;
[0053] 6. N+ / P+ formation, implantation plus activation or other processes; N+ implantation elements are phosphorus and other elements, the energy is 80KeV-150KeV, and the dose is 1E15 / cm 2 -1E16cm 2 The P+ implantation element is boron and other elements, the energy is 80KeV-150KeV, and the dose is 1E15 / cm 2 -1E16cm 2 .
[0054] 7. Deposition and etching of isolation layer on polycrystalline; the isolation layer is made of silicon oxide or silicon nitride and has a thickness of 0.5μm-1.5μm. The isolation layer can be etched by wet method, dry method or a combination of wet and dry method.
[0055] 8. Metal deposition and etching. The metal is made of aluminum or aluminum alloy, and metal etching can be done by wet or dry methods.
[0056] 9. Passivation deposition and etching. Passivation is a material such as silicon nitride or polyimide, or a multi-layer composite material.
[0057] Specifically, in another embodiment of the present invention, the manufacturing method comprises the following steps:
[0058] 1. Preparation of N-SiC materials;
[0059] 2. Use epitaxy or other processes to form P+Si material on SiC, and the doping concentration and thickness are determined by the ohmic contact of the device;
[0060] 3. P-SiC junction formation, implantation plus activation or other processes; the implanted element is aluminum or other elements, the implantation energy is 200KeV-1000KeV, and the dose is 1E13 / cm 2 -1E14cm 2 The activation temperature is 1500℃-2000℃ and the time is 30-200min.
[0061] 4. N+SiC junction formation, implantation plus activation or other processes; implantation element is aluminum or other elements, implantation energy is 20KeV-200KeV, and dose is 1E15 / cm 2 -1E16cm 2The activation temperature is 1500℃-2000℃ and the time is 30-200min.
[0062] 5. Gate oxide: formed by thermal oxidation or deposition processes; thickness is 0.03μm-0.10μm, process temperature is 800℃-1400℃;
[0063] 6. Polycrystalline deposition and etching; polycrystalline thickness is 0.5μm-1.0μm, process temperature is 500℃-800℃;
[0064] 7. Deposition and etching of isolation oxide layer on polycrystalline; the isolation layer is made of silicon oxide or silicon nitride and has a thickness of 0.5μm-1.5μm. The isolation layer can be etched by wet method, dry method or a combination of wet and dry method.
[0065] 8. Metal deposition and etching. The metal is aluminum or aluminum alloy or titanium / aluminum multilayer metal, etc. Metal etching can be done by wet or dry methods.
[0066] In summary, the present invention relates to a Si / SiC heterojunction structure and a method for manufacturing the same, wherein the heterojunction forms the anode region of a diode, the P-type Si is located above the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers; or forms the back-emitting region of an insulated gate bipolar transistor IGBT, the P-type Si is located below the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers. Compared with the traditional silicon carbide structure, the patented structure is compatible with the traditional silicon manufacturing process, reduces the process difficulty, improves the process quality, reduces the cost, and improves the performance and reliability of silicon carbide devices.
[0067] The above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.
Claims
1. A Si / SiC heterojunction structure, characterized in that: The heterojunction forms the anode region of the diode, the P-type Si is located above the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers; Or form the back emitter region of the insulated gate bipolar transistor IGBT, the P-type Si is located below the N-type SiC, and the Si / SiC heterojunction is composed of the above two layers.
2. The Si / SiC heterojunction structure according to claim 1, characterized in that: The structure is a P-Si / N-SiC heterojunction structure, the P-Si is located above the N-SiC, the P-type doping of the P-Si is formed by an injection / annealing or epitaxial process, and the junction depth is controllable.
3. The Si / SiC heterojunction structure according to claim 1, characterized in that: The Si / SiC heterojunction forms the back emission region of the IGBT, the P-Si is located below the N-SiC, and the P-type doping of the P-Si is formed by injection / annealing or epitaxial process.
4. The Si / SiC heterojunction structure according to claim 1, characterized in that: The Si / SiC heterojunction forms the front gate of the IGBT. Si is located above the N-SiC. Si is formed using processes such as epitaxy, and the thickness and quality are controllable. Thermal oxidation is used to convert all Si into SiO2.
5. The Si / SiC heterojunction structure according to claim 1, characterized in that: The Si / SiC heterojunction forms the front gate of the IGBT. The Si is located above the N-SiC. The Si is formed by an epitaxial process with controllable thickness and quality. Thermal oxidation is used to partially convert the Si into SiO2. The N+ / P+ junction / P- junction of the IGBT is located in the N-Si; or part of the P well is placed in the SiC.
6. The Si / SiC heterojunction structure according to claim 1, characterized in that: The Si / SiC heterojunction forms the P-well contacting the P+ region on the front side of the IGBT. The P+-Si is located in a local area above the N-SiC. The P+Si is formed by injection / annealing or epitaxy and then etching. Subsequent processes and structures are completed in sequence to form the front side structure of the IGBT.
7. The Si / SiC heterojunction structure according to claim 1, characterized in that: The SiC / Si heterojunction forms the substrate and drift region of the power device, and the Si is located below the SiC, serving as a substrate or as part of the drift region.
8. The Si / SiC heterojunction structure according to claim 7, characterized in that: The electric field strength in silicon is lower than the maximum breakdown field strength E of silicon material. max,Si .
9. A method for manufacturing a Si / SiC heterojunction structure, characterized in that: The steps include: Step 1, N-SiC material preparation; Step 2, forming Si material on SiC by epitaxy or other processes; Step 3, thermal oxidation to form a gate oxide layer; Step 4, performing polycrystalline deposition and etching; Step 5, forming a P-junction by implantation and pushing; Step 6, implantation and activation to form N+ / P+ junction; Step 7, deposition and etching of isolation layer on polycrystalline; Step 8, metal deposition and etching; Step 9: passivation deposition and etching.