Device containing multi-potential field plate structure and preparation method thereof

Abstract

The invention discloses a device containing a multi-potential field plate structure and a preparation method thereof, and the method comprises the following steps: preparing a basic structure, and carrying out the etching of a second dielectric layer of the basic structure, and forming a gate electrode hole; depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal; in the n layers of field plate metal, the thermal expansion coefficient of each layer of field plate metal is gradually increased from the nth layer to the second layer; etching the end part of the first layer of field plate metal; carrying out annealing treatment on the n layers of field plate metal, so that the end parts of the nth layer to the second layer of field plate metal are warped towards the direction far away from the second dielectric layer; and growing a third dielectric layer on the second dielectric layer, and etching the redundant third dielectric layer to form a field plate, thereby obtaining the device. According to the preparation method disclosed by the invention, the process is simplified, the device containing the multi-potential field plate structure is prepared, and the potential difference between the field plate and the two-dimensional electron gas below the field plate can be effectively controlled.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a device including a multi-potential field plate and a method for preparing the device. Background Art

[0002] At present, the single field plate structure of the planar channel structure of AlGaN / GaN HEMT in the industry uses gate field plates and source field plates. However, since the field plate potential is equal to the gate potential or the source potential, a large potential difference will be formed with the two-dimensional electron gas below the field plate, which is the main reason for device failure. The main reason is that the dielectric layer is easily subjected to high electric field strength, which can easily cause device reliability failure. At the same time, the high electric field strength causes the dielectric layer to capture charge and thus increase the dynamic resistance.

[0003] In order to solve the above problems, a HEMT (high electron mobility transistor) device with a multi-potential field plate structure is proposed, which can effectively control the potential difference between the field plate and the two-dimensional electron gas below, and solve the problem of dielectric layer breakdown reliability failure caused by high electric field and the problem of dielectric layer charge capture caused by high electric field strength. However, the planar channel structure of AlGaN / GaN HEMT introduces a multi-field plate structure from a single field plate structure, which causes many problems: in order to form a gradient multi-field plate, an additional 5 to 8 process steps are added, which increases the process complexity and processing cost; at the same time, too many process steps increase the risk of introducing defects in the process, which is not conducive to the reliability of the device. Summary of the invention

[0004] In view of this, in order to overcome the defects of the prior art, an object of the present invention is to provide a device containing a multi-potential field plate structure and a preparation method thereof, which can prepare a device containing a multi-potential field plate while avoiding excessive process steps.

[0005] In order to achieve the above object, the present invention provides a method for preparing a device containing a multi-potential field plate structure, comprising the following steps: Prepare a base structure and perform etching on the second dielectric layer of the base structure to form a gate electrode hole; n layers of metal are deposited and etched in the gate electrode hole to form n layers of field plate metal, wherein n is a positive integer greater than or equal to 3; the thermal expansion coefficient of each layer of the n layers of field plate metal gradually increases from the nth layer to the second layer; and it is ensured that the second to nth layers of field plate metal can be warped upward (in a direction away from the second dielectric layer) during annealing; Etching the end of the first layer of field plate metal; Annealing the n-layer field plate metal so that the end of the field plate metal from the n-th layer to the second layer is warped in a direction away from the second dielectric layer; A third dielectric layer is grown on the second dielectric layer and the redundant third dielectric layer is etched away to form a field plate, thereby obtaining the device having the multi-potential field plate structure.

[0006] The present invention deposits n layers of metal in the gate electrode hole and obtains n layers of field plate metal through etching, and then etches the end of the first layer of field plate metal located at the bottom, and then performs an annealing treatment to directly make the ends of the second to nth layers of field plate metal above the first layer of field plate metal warp in a direction away from the second dielectric layer at the same time to form an electric field gradient field plate, and finally obtains a device with a multi-potential field plate structure. Compared with the traditional manufacturing process of devices with a multi-potential field plate structure, the preparation method of the present invention can effectively reduce the process steps while preparing a device with a multi-potential field plate structure, so that the potential difference between the field plate and the two-dimensional electron gas below can be effectively controlled, and the problem of introducing defects caused by numerous process steps is avoided, which is beneficial to the reliability of the device.

[0007] According to some preferred implementation aspects of the present invention, the method for etching the end of the first layer of field plate metal is wet etching, and the first layer of field plate metal is a metal soluble in an alkaline solution.

[0008] According to some preferred implementation aspects of the present invention, in the step of depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal, the length of each layer of the n layers of field plate metal is the same.

[0009] According to some preferred implementation aspects of the present invention, the method for etching the end of the first layer of field plate metal comprises the following steps: Photoresist is applied to one end of the first field plate metal layer, and then an alkaline solution is used to corrode the other end of the first field plate metal layer, so that a first notch is formed at the other end of the first field plate metal layer.

[0010] According to some preferred implementation aspects of the present invention, the method for etching the end of the first layer of field plate metal comprises the following steps: First, one end of the first layer of field plate metal is coated with photoresist, and the other end of the first layer of field plate metal is corroded with an alkaline solution, so that a first gap is formed at the other end of the first layer of field plate metal; then, the end of the first layer of field plate metal having the first gap is coated with photoresist, and the end of the first layer of field plate metal away from the first gap is corroded with an alkaline solution, so that a second gap is formed at the end of the first layer of field plate metal away from the first gap.

[0011] According to some preferred implementation aspects of the present invention, the method for etching the end of the first layer of field plate metal comprises the following steps: An alkaline solution is used to simultaneously corrode both ends of the first layer of field plate metal, so that a first gap and a second gap are formed at both ends of the first layer of field plate metal respectively.

[0012] According to some preferred embodiments of the present invention, the length of the first notch is the same as or different from the length of the second notch.

[0013] According to some preferred implementation aspects of the present invention, the bottom surface of the end of the second field plate metal layer close to the first notch is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer is 10°-20°.

[0014] According to some preferred implementation aspects of the present invention, the bottom surface of the end of the second layer of field plate metal close to the first notch is a curved surface, and the central angle of the curved surface is 20° to 40°.

[0015] According to some preferred implementation aspects of the present invention, the bottom surface of the end of the second layer of field plate metal close to the first notch is a first inclined surface, the bottom surface of the end of the second layer of field plate metal close to the second notch is a second inclined surface, the angle between the first inclined surface and the top surface of the second dielectric layer is 10°~20°, and the angle between the second inclined surface and the top surface of the second dielectric layer is 10°~20°.

[0016] According to some preferred implementation aspects of the present invention, the bottom surface of the second field plate metal layer is a curved surface, and the central angle of the curved surface is 20° to 40°.

[0017] According to some preferred implementation aspects of the present invention, the length of the field plate metal remaining after the end of the first layer of field plate metal is etched accounts for 40% to 50% of the length of the end of the first layer of field plate metal before etching, so that the area of ​​the orthographic projection of the first notch or the first notch and the second notch on the second dielectric layer accounts for a percentage greater than or equal to 50% of the area of ​​the orthographic projection of the second layer of field plate metal to the nth layer of field plate metal on the second dielectric layer.

[0018] According to some preferred implementation aspects of the present invention, in the step of annealing the n-layer field plate metal, the annealing temperature is 380-500°C.

[0019] According to some preferred implementation aspects of the present invention, the basic structure includes, from bottom to top, a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer.

[0020] According to some preferred implementation aspects of the present invention, the method for preparing the base structure includes: performing nitride epitaxial growth on a substrate to form an epitaxial layer structure, and sequentially growing a first dielectric layer and a second dielectric layer on the epitaxial layer; Etching is performed on the epitaxial layer, the first dielectric layer and the second dielectric layer to form a source electrode hole and a drain electrode hole, and metal deposition and etching are performed in the source electrode hole and the drain electrode hole, and then annealing is performed to form ohmic contacts to form a source electrode and a drain electrode respectively.

[0021] The present invention also provides a device containing a multi-potential field plate structure prepared by the above-mentioned preparation method.

[0022] Due to the adoption of the above technical scheme, compared with the prior art, the benefits of the present invention are as follows: the preparation method of the device containing a multi-potential field plate structure of the present invention is to obtain n layers of field plate metal by depositing n layers of metal in the gate electrode hole and etching, and then etching the end of the first layer of field plate metal located at the bottom, and then through a single annealing treatment, the ends of the second to nth layers of field plate metal above the first layer of field plate metal can be directly warped in a direction away from the second dielectric layer at the same time to form an electric field gradient field plate, and finally a device containing a multi-potential field plate structure is obtained. Compared with the traditional manufacturing process of devices with a multi-potential field plate structure, the preparation method of the present invention can effectively reduce the process steps while preparing a device containing a multi-potential field plate structure, thereby effectively controlling the potential difference between the field plate and the two-dimensional electron gas below, and avoiding the problem of introducing defects caused by numerous process steps, which is beneficial to the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a cross-sectional schematic diagram after forming an epitaxial layer in the method for preparing the device in Embodiments 1 to 4 of the present invention; Figure 2 It is a cross-sectional schematic diagram of the device manufacturing method in Embodiment 1 to Embodiment 4 of the present invention after the first dielectric layer is formed; Figure 3 It is a cross-sectional schematic diagram of the device manufacturing method in Embodiment 1 to Embodiment 4 of the present invention after the second dielectric layer is formed; Figure 4 It is a cross-sectional schematic diagram after forming a source electrode hole and a drain electrode hole in the method for preparing the device in Embodiment 1 to Embodiment 4 of the present invention; Figure 5 It is a cross-sectional schematic diagram after forming a source electrode and a drain electrode in the method for preparing the device in Embodiments 1 to 4 of the present invention; Figure 6It is a cross-sectional schematic diagram of the device manufacturing method after the gate electrode hole is formed in the first to third embodiments of the present invention; Figure 7 It is a cross-sectional schematic diagram of the device manufacturing method in Embodiment 1 and Embodiment 2 of the present invention after forming three layers of field plate metal; Figure 8 It is a cross-sectional schematic diagram of the device after the first notch is formed in the method for preparing the device in Embodiment 1 and Embodiment 2 of the present invention; Fig. 9 It is a schematic cross-sectional view of one end of the third field plate metal layer and one end of the second field plate metal layer after being warped upwards in the method for preparing the device in the first embodiment of the present invention; Fig.10 Schematic diagram of the cross-sectional structure of a device containing a multi-potential field plate structure in Embodiment 1 of the present invention; Fig.11 It is a schematic diagram of the cross-sectional structure after one end of the third layer of field plate metal and one end of the second layer of field plate metal are warped upwards in the method for preparing the device in the second embodiment of the present invention; Fig.12 It is a schematic diagram of the cross-sectional structure of a device containing a multi-potential field plate structure in the second embodiment of the present invention; Fig.13 It is a cross-sectional schematic diagram after the first notch and the second notch are formed in the method for preparing the device in the third embodiment of the present invention; Fig.14 It is a schematic cross-sectional view of a method for manufacturing a device in Embodiment 3 of the present invention, in which one end of the third layer of field plate metal and both ends of the second layer of field plate metal are warped upward; Fig.15 Schematic diagram of the cross-sectional structure of a device containing a multi-potential field plate structure in Embodiment 3 of the present invention; Fig.16 It is a cross-sectional schematic diagram of a device after a gate electrode hole is formed in the method for preparing the device in the fourth embodiment of the present invention; Fig.17 It is a cross-sectional schematic diagram of the device manufacturing method in the fourth embodiment of the present invention after forming three layers of field plate metal; Fig.18 It is a cross-sectional schematic diagram after forming a first notch and a second notch in the method for preparing a device in Embodiment 4 of the present invention; Fig.19 It is a schematic cross-sectional view of a method for manufacturing a device in Embodiment 4 of the present invention, in which one end of a third layer of field plate metal and both ends of a second layer of field plate metal are warped upward; Fig. 20 Schematic diagram of the cross-sectional structure of a device containing a multi-potential field plate structure in Embodiment 4 of the present invention; In the accompanying drawings, substrate-1, epitaxial layer-2, drain electrode hole-21, source electrode hole-22, drain electrode-3, source electrode-4, first dielectric layer-5, second dielectric layer-6, gate electrode hole-61, third dielectric layer-7, first layer of field plate metal-81, second layer of field plate metal-82, third layer of field plate metal-83, first notch-Q1, second notch-Q2. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] The method for preparing a device containing a multi-potential field plate structure of the present invention comprises the following steps: Step 1: Select a conductive material as substrate 1, perform nitride epitaxial growth on substrate 1, and sequentially form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. Nitrides include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, etc. The nucleation layer, buffer layer, channel layer, and barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0027] The substrate 1 is one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, germanium or any other material capable of growing group III nitride materials.

[0028] Step 2: depositing one or more combinations of SiN, SiO2, SiON, and Al2O3 on the epitaxial layer 2 to form a first dielectric layer 5 for controlling a high-concentration two-dimensional electron gas channel.

[0029] Step three: deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 on the first dielectric layer 5 to form a second dielectric layer 6 to protect the first dielectric layer 5 from being damaged by the process.

[0030] Step 4: Etching is performed on the epitaxial layer 2, the first dielectric layer 5 and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, and ohmic metal deposition and etching are performed in the source electrode hole 22 and the drain electrode hole 21. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, and W to form an ohmic metal layer, and then annealing is performed to form an ohmic contact to form a source electrode 4 and a drain electrode 3, respectively.

[0031] Step five: etching is performed on the second dielectric layer 6 to form a gate electrode hole 61 .

[0032] Step six: deposit n layers of metal in the gate electrode hole 61 and etch away excess metal to form n layers of field plate metal, where n is a positive integer greater than or equal to 3; among the n layers of field plate metal, the thermal expansion coefficient of each layer of field plate metal gradually increases from the nth layer to the second layer.

[0033] Step seven: wet-etching the end of the first field plate metal layer 81 in the n-layer field plate metal to form a first notch Q1 and / or a second notch Q2.

[0034] Step eight: annealing the n-layer field plate metal to make the end of the n-th layer field plate metal to the second layer field plate metal 82 warp in a direction away from the second dielectric layer 6. The temperature of the annealing treatment is 380-500°C.

[0035] Step 9: growing one or more combinations of SiN, SiO2, SiON, Al2O3 on the second dielectric layer 6 to form a third dielectric layer 7, and etching away the redundant third dielectric layer 7 to form a field plate, thereby obtaining a device with a multi-potential field plate structure. The n-layer field plate metal serves as a conductive area, the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 serve as an electric field distribution area, and the n-layer field plate metal and the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 located directly below it form a field plate as a whole.

[0036] The device with multi-potential multi-field plate structure of the present invention comprises a drain electrode 3, a source electrode 4, an n-layer field plate metal, and a substrate 1, an epitaxial layer 2, a first dielectric layer 5, a second dielectric layer 6 and a third dielectric layer 7 arranged in sequence from bottom to top, wherein the drain electrode 3 and the source electrode 4 are both located in the epitaxial layer 2, the first dielectric layer 5, the second dielectric layer 6 and the third dielectric layer 7. The n-layer field plate metal is located in the second dielectric layer 6 and the third dielectric layer 7, the n-layer field plate metal is located above the second dielectric layer 6, and the n-layer field plate metal and the first dielectric layer 5, the second dielectric layer 6 and the third dielectric layer 7 located directly below it form a field plate structure as a whole; the field plate forms an electric field gradient from bottom to top, and among the n-layer field plate metal, the length of the first layer field plate metal 81 is less than the length of the remaining other layers of field plate metal, and the first layer field plate metal 81 is parallel to the second dielectric layer 6.

[0037] Furthermore, one end of the first layer of field plate metal 81 in the n-layer field plate metal has a first notch Q1, and the ends of the second to n-th layer of field plate metals close to the first notch Q1 are all inclined upward, and the bottom surface of the end of the second layer of field plate metal 82 close to the first notch Q1 is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer 6 is 10°~20°.

[0038] Furthermore, one end of the first layer of field plate metal 81 in the n-layer field plate metal has a first notch Q1, and the ends of the second layer of field plate metal 82 to the n-th layer of field plate metal close to the first notch Q1 all form a concave arc shape, and the bottom surface of the end of the second layer of field plate metal 82 close to the first notch Q1 is an arc surface, and the central angle of the arc surface is 20°~40°.

[0039] Further, one end of the first field plate metal 81 in the n-layer field plate metal has a first notch Q1, and the other end has a second notch Q2. The second field plate metal 82 to the end of the n-th field plate metal near the first notch Q1 are all inclined upward, and the bottom surface of the end of the second field plate metal 82 near the first notch Q1 is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer 6 is 10°~20°; the second field plate metal 82 to the end of the n-th field plate metal near the second notch Q2 are also inclined upward, and the bottom surface of the end of the second field plate metal 82 near the second notch Q2 is a second inclined surface, and the angle between the second inclined surface and the top surface of the second dielectric layer 6 is 10°~20°. Among them, the length of the first notch Q1 is the same as or different from the length of the second notch Q2. When the length of the first notch Q1 is equal to the length of the second notch Q2, the angles formed between the first inclined surface and the second inclined surface and the top surface of the second dielectric layer 6 are equal.

[0040] Furthermore, one end of the first layer of field plate metal 81 in the n-layer field plate metal has a first notch Q1, and the other end has a second notch Q2, the second layer of field plate metal 82 to the n-th layer of field plate metal form a concave arc as a whole, the bottom surface of the second layer of field plate metal 82 is an arc surface, and the central angle of the arc surface is 20°~40°.

[0041] Example 1 Preparation method of a device containing a multi-potential field plate structure This embodiment provides a method for preparing a device having a multi-potential field plate structure, which specifically comprises the following steps: Step 1: If Figure 1 As shown, silicon is selected as the substrate 1 for nitride epitaxial growth, and a nucleation layer, a buffer layer, a channel layer and a barrier layer are formed in sequence, and the nitride is GaN. The nucleation layer, the buffer layer, the channel layer and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0042] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD (metal organic chemical vapor deposition) to form a first dielectric layer 5, such as Figure 2 As shown, it is used to control the high-concentration two-dimensional electron gas channel.

[0043] Step 3: Deposit SiO2 on the first dielectric layer 5 to form a second dielectric layer 6, such as Figure 3 As shown, the first dielectric layer 5 is used to protect the first dielectric layer 5 from being damaged by the process.

[0044] Step 4: Etching is performed on the epitaxial layer 2, the first dielectric layer 5 and the second dielectric layer 6, such as Figure 4 As shown, a source electrode hole 22 and a drain electrode hole 21 are formed, and ohmic metal is deposited and etched in the source electrode hole 22 and the drain electrode hole 21, and then annealed to form an ohmic contact, and a source electrode 4 and a drain electrode 3 are formed respectively, as shown in FIG. Figure 5 shown.

[0045] Step 5: Etching is performed on the second dielectric layer 6 to form a gate electrode hole 61, such as Figure 6 shown.

[0046] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form a three-layer field plate metal, such as Figure 7 As shown, three layers of field plate metals are stacked in sequence, from bottom to top, namely: a first layer of field plate metal 81 , a second layer of field plate metal 82 , and a third layer of field plate metal 83 .

[0047] The thermal expansion coefficient of the third field plate metal 83 is greater than that of the second field plate metal 82. The thermal expansion coefficient of the third field plate metal 83 is 0~15×10 -6 / ℃, preferably 4×10 -6 ~11×10 -6 / ℃; the thermal expansion coefficient of the second field plate metal 82 is 20×10 -6 ~40×10 -6 / ℃, preferably 20×10 -6 ~25×10 -6 / ℃.

[0048] In this embodiment, the third field plate metal 83 is tungsten, with a thermal expansion coefficient of 4.5×10 -6 / ℃, thickness is 100nm, length is 10μm; the second field plate metal 82 is aluminum-copper alloy, thermal expansion coefficient is 20×10 -6 / ℃, thickness of 100nm, length of 10μm; the first field plate metal 81 is aluminum, thickness of 200nm, length of 10μm.

[0049] Step 7: Coat one end of the first field plate metal 81 of the three-layer field plate metal with photoresist, and then use alkaline solution tetramethylammonium hydroxide to corrode the other end of the first field plate metal 81, so that the other end of the first field plate metal 81 forms a first notch Q1, as shown in FIG. Figure 8 As shown, in this embodiment, the length of the remaining field plate metal after the end of the first layer of field plate metal 81 is etched accounts for 40% of the length of the end of the first layer of field plate metal 81 before etching.

[0050] Since ions cannot penetrate the photoresist at the location where the photoresist exists, the structure of one end of the first field plate metal 81 will not be damaged, thereby protecting it.

[0051] Step 8: Anneal the three-layer field plate metal at 400° C. for 30 seconds, so that the ends of the third layer field plate metal 83 and the second layer field plate metal 82 near the first notch Q1 are warped upwards. Fig. 9 shown.

[0052] Step 9: Using the SOD (Spin-On Dielectric) method, SiO2 is grown on the second dielectric layer 6 by spin coating and baking to form a third dielectric layer 7, and the redundant third dielectric layer 7 is etched away to obtain the following: Fig.10 In the device shown having a multi-potential field plate structure, the height of the field plate varies in a gradient.

[0053] In this embodiment, the bottom surface of the end of the second field plate metal layer 82 close to the first notch Q1 is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer 6 is 16°.

[0054] Example 2 Method for preparing a device containing a multi-potential field plate structure This embodiment provides a method for preparing a device having a multi-potential field plate structure, which specifically comprises the following steps: Step 1: If Figure 1 As shown, silicon is selected as the substrate 1 for nitride epitaxial growth, and a nucleation layer, a buffer layer, a channel layer and a barrier layer are formed in sequence, and the nitride is GaN. The nucleation layer, the buffer layer, the channel layer and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0055] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD to form a first dielectric layer 5, such as Figure 2 As shown, it is used to control the high-concentration two-dimensional electron gas channel.

[0056] Step 3: Deposit SiO2 on the first dielectric layer 5 to form a second dielectric layer 6, such as Figure 3As shown, the first dielectric layer 5 is used to protect the first dielectric layer 5 from being damaged by the process.

[0057] Step 4: Etching is performed on the epitaxial layer 2, the first dielectric layer 5 and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, such as Figure 4 As shown, ohmic metal deposition and etching are performed in the source electrode hole 22 and the drain electrode hole 21, and then annealing is performed to form ohmic contacts, thereby forming a source electrode 4 and a drain electrode 3, respectively. Figure 5 shown.

[0058] Step 5: Etching is performed on the second dielectric layer 6 to form a gate electrode hole 61, such as Figure 6 shown.

[0059] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form a three-layer field plate metal, such as Figure 7 As shown, three layers of field plate metals are stacked in sequence, from bottom to top, namely: a first layer of field plate metal 81 , a second layer of field plate metal 82 , and a third layer of field plate metal 83 .

[0060] The thermal expansion coefficient of the third field plate metal 83 is greater than that of the second field plate metal 82. The thermal expansion coefficient of the third field plate metal 83 is 0~15×10 -6 / ℃, preferably 4×10 -6 ~11×10 -6 / ℃; the thermal expansion coefficient of the second field plate metal 82 is 20×10 -6 ~40×10 -6 / ℃, preferably 20×10 -6 ~25×10 -6 / ℃.

[0061] In this embodiment, the third field plate metal 83 is titanium, with a thermal expansion coefficient of 10.8×10 -6 / ℃, thickness is 100nm, length is 10μm; the second field plate metal 82 is aluminum-magnesium alloy, thermal expansion coefficient is 24×10 -6 / ℃, thickness of 100nm, length of 10μm; the first field plate metal 81 is aluminum, thickness of 200nm, length of 10μm.

[0062] Step 7: Coat one end of the first field plate metal 81 of the three-layer field plate metal with photoresist, and then use alkaline solution tetramethylammonium hydroxide to corrode the other end of the first field plate metal 81, so that the other end of the first field plate metal 81 forms a first notch Q1, as shown in FIG. Figure 8 In this embodiment, the length of the remaining field plate metal after the end of the first layer of field plate metal 81 is etched accounts for 50% of the length of the end of the first layer of field plate metal 81 before etching.

[0063] Step 8: Anneal the three-layer field plate metal at 450° C. for 20 seconds, so that the ends of the third layer field plate metal 83 and the second layer field plate metal 82 near the first notch Q1 are warped upwards. Fig.11 shown.

[0064] Step 9: Using the SOD method, spin coating and baking are used to grow SiO2 on the second dielectric layer 6 to form a third dielectric layer 7, and the redundant third dielectric layer 7 is etched away to obtain the following: Fig.12 In the device shown having a multi-potential field plate structure, the height of the field plate varies in a gradient.

[0065] In this embodiment, the bottom surface of the end portion of the second layer of field plate metal 82 close to the first notch Q1 is an arc surface, and the central angle of the arc surface is 14°.

[0066] Example 3 Preparation method of a device containing a multi-potential field plate structure This embodiment provides a method for preparing a device having a multi-potential field plate structure, which specifically comprises the following steps: Step 1: If Figure 1 As shown, silicon is selected as the substrate 1 for nitride epitaxial growth, and a nucleation layer, a buffer layer, a channel layer and a barrier layer are formed in sequence, and the nitride is GaN. The nucleation layer, the buffer layer, the channel layer and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0067] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD to form a first dielectric layer 5, such as Figure 2 As shown, it is used to control the high-concentration two-dimensional electron gas channel.

[0068] Step 3: Deposit SiO2 on the first dielectric layer 5 to form a second dielectric layer 6, such as Figure 3 As shown, the first dielectric layer 5 is used to protect the first dielectric layer 5 from being damaged by the process.

[0069] Step 4: Etching is performed on the epitaxial layer 2, the first dielectric layer 5 and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, such as Figure 4 As shown, ohmic metal deposition and etching are performed in the source electrode hole 22 and the drain electrode hole 21, and then annealing is performed to form ohmic contacts, thereby forming a source electrode 4 and a drain electrode 3, respectively. Figure 5 shown.

[0070] Step 5: Etching is performed on the second dielectric layer 6 to form a gate electrode hole 61, such as Figure 6 shown.

[0071] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form a three-layer field plate metal, such as Figure 7 As shown, three layers of field plate metals are stacked in sequence, from bottom to top, namely: a first layer of field plate metal 81 , a second layer of field plate metal 82 , and a third layer of field plate metal 83 .

[0072] The thermal expansion coefficient of the third field plate metal 83 is greater than that of the second field plate metal 82. The thermal expansion coefficient of the third field plate metal 83 is 0~15×10 -6 / ℃, preferably 4×10 -6 ~11×10 -6 / ℃; the thermal expansion coefficient of the second field plate metal 82 is 20×10 -6 ~40×10 -6 / ℃, preferably 20×10 -6 ~25×10 -6 / ℃.

[0073] In this embodiment, the third field plate metal 83 is tungsten, with a thermal expansion coefficient of 4.5×10 -6 / ℃, thickness is 100nm, length is 10μm; the second field plate metal 82 is aluminum-copper alloy, thermal expansion coefficient is 20×10 -6 / ℃, thickness of 100nm, length of 10μm; the first field plate metal 81 is aluminum, thickness of 200nm, length of 10μm.

[0074] Step 7: first, photoresist is applied to one end of the first field plate metal 81 of the three-layer field plate metal, and the other end of the first field plate metal 81 is corroded by using an alkaline solution of tetramethylammonium hydroxide, so that a first gap Q1 is formed at the other end of the first field plate metal 81; then, photoresist is applied to the end of the first field plate metal 81 having the first gap Q1, and the end of the first field plate metal 81 away from the first gap Q1 is corroded by using an alkaline solution of methylammonium hydroxide, so that a second gap Q2 is formed at the end of the first field plate metal 81 away from the first gap Q1, as shown in FIG. Fig.13 In this embodiment, the length of the remaining field plate metal after the end of the first layer of field plate metal 81 is etched accounts for 40% of the length of the end of the first layer of field plate metal 81 before etching.

[0075] Step 8: Anneal the three-layer field plate metal at 400°C for 30 seconds, so that both ends of the third field plate metal 83 and the second field plate metal 82 near the first notch Q1 and the second notch Q2 are warped upwards. Fig.14 shown.

[0076] Step 9: Using the SOD method, spin coating and baking are used to grow SiO2 on the second dielectric layer 6 to form a third dielectric layer 7, and the redundant third dielectric layer 7 is etched away to obtain the following: Fig.15 In the device shown having a multi-potential field plate structure, the height of the field plate varies in a gradient.

[0077] In this embodiment, the length of the first notch Q1 is greater than the length of the second notch Q2, the bottom surface of the end of the second layer field plate metal 82 close to the first notch Q1 is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer 6 is 16°; the bottom surface of the end of the second layer field plate metal 82 close to the first notch Q1 is a second inclined surface, and the angle between the second inclined surface and the top surface of the second dielectric layer 6 is 14°.

[0078] Example 4 Preparation method of a device containing a multi-potential field plate structure This embodiment provides a method for preparing a device having a multi-potential field plate structure, which specifically comprises the following steps: Step 1: If Figure 1 As shown, silicon is selected as the substrate 1 for nitride epitaxial growth, and a nucleation layer, a buffer layer, a channel layer and a barrier layer are formed in sequence, and the nitride is GaN. The nucleation layer, the buffer layer, the channel layer and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0079] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD to form a first dielectric layer 5, such as Figure 2 As shown, it is used to control the high-concentration two-dimensional electron gas channel.

[0080] Step 3: Deposit SiO2 on the first dielectric layer 5 to form a second dielectric layer 6, such as Figure 3 As shown, the first dielectric layer 5 is used to protect the first dielectric layer 5 from being damaged by the process.

[0081] Step 4: Etching is performed on the epitaxial layer 2, the first dielectric layer 5 and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, such as Figure 4 As shown, ohmic metal deposition and etching are performed in the source electrode hole 22 and the drain electrode hole 21, and then annealing is performed to form ohmic contacts, thereby forming a source electrode 4 and a drain electrode 3, respectively. Figure 5 shown.

[0082] Step 5: Etching is performed on the second dielectric layer 6 to form a gate electrode hole 61, such as Fig.16 shown.

[0083] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form a three-layer field plate metal, such as Fig.17As shown, three layers of field plate metals are stacked in sequence, from bottom to top, namely: a first layer of field plate metal 81 , a second layer of field plate metal 82 , and a third layer of field plate metal 83 .

[0084] The thermal expansion coefficient of the third field plate metal 83 is greater than that of the second field plate metal 82. The thermal expansion coefficient of the third field plate metal 83 is 0~15×10 -6 / ℃, preferably 4×10 -6 ~11×10 -6 / ℃; the thermal expansion coefficient of the second field plate metal 82 is 20×10 -6 ~40×10 -6 / ℃, preferably 20×10 -6 ~25×10 -6 / ℃.

[0085] In this embodiment, the third field plate metal 83 is titanium, with a thermal expansion coefficient of 10.8×10 -6 / ℃, thickness is 100nm, length is 10μm; the second field plate metal 82 is aluminum-magnesium alloy, thermal expansion coefficient is 24×10 -6 / ℃, thickness of 100nm, length of 10μm; the first field plate metal 81 is aluminum, thickness of 200nm, length of 10μm.

[0086] Step 7: Use alkaline solution tetramethylammonium hydroxide to simultaneously corrode both ends of the first layer field plate metal 81, so that a first gap Q1 and a second gap Q2 are formed at both ends of the first layer field plate metal 81, such as Fig.18 In this embodiment, the length of the remaining field plate metal after the end of the first layer of field plate metal 81 is etched accounts for 50% of the length of the end of the first layer of field plate metal 81 before etching.

[0087] Step 8: Anneal the three-layer field plate metal at 450°C for 20 seconds, so that both ends of the third layer field plate metal 83 and the second layer field plate metal 82 near the first notch Q1 and the second notch Q2 are warped upwards. Fig.19 shown.

[0088] Step 9: Using the SOD method, spin coating and baking are used to grow SiO2 on the second dielectric layer 6 to form a third dielectric layer 7, and the redundant third dielectric layer 7 is etched away to obtain the following: Fig. 20 The device shown contains a three-layer multi-potential field plate structure, and the height of the field plate varies in a gradient.

[0089] In this embodiment, the length of the first notch Q1 is equal to the length of the second notch Q2 , and the bottom surface of the second layer of field plate metal 82 is an arc surface, and the central angle of the arc surface is 14°.

[0090] The method for preparing a device containing a multi-potential field plate structure of the present invention deposits n layers of metal in the gate electrode hole 61 and obtains n layers of field plate metal by etching, and then etches the end of the first layer of field plate metal 81 located at the bottom. Then, an annealing treatment is performed to directly make the ends of the second to nth layers of field plate metal above the first layer of field plate metal 81 warp in a direction away from the second dielectric layer 6 at the same time to form an electric field gradient field plate, and finally obtains a device containing a multi-potential field plate structure. Compared with the traditional field plate process, 5 to 8 steps are reduced, the process is simplified, and a device containing a multi-potential field plate structure is prepared, thereby being able to effectively control the potential difference between the field plate and the two-dimensional electron gas below, and avoiding the problem of introducing defects caused by numerous process steps, which is beneficial to the reliability of the device.

[0091] The above embodiments prepared by the method of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a device containing a multi-potential field plate structure, characterized in that: The steps include: Prepare a base structure and perform etching on the second dielectric layer of the base structure to form a gate electrode hole; Depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal, wherein n is a positive integer greater than or equal to 3; in the n layers of field plate metal, the thermal expansion coefficient of each layer of field plate metal gradually increases from the nth layer to the second layer; Etching the end of the first layer of field plate metal; Annealing the n-layer field plate metal so that the end of the field plate metal from the n-th layer to the second layer is warped in a direction away from the second dielectric layer; A third dielectric layer is grown on the second dielectric layer and the redundant third dielectric layer is etched away to form a field plate, thereby obtaining the device having the multi-potential field plate structure.

2. The preparation method according to claim 1, characterized in that: The method for etching the end of the first layer of field plate metal is wet etching, and the first layer of field plate metal is a metal soluble in an alkaline solution.

3. The preparation method according to claim 1, characterized in that: In the step of depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal, the length of each layer of the n layers of field plate metal is the same.

4. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: Photoresist is applied to one end of the first field plate metal layer, and then an alkaline solution is used to corrode the other end of the first field plate metal layer, so that a first notch is formed at the other end of the first field plate metal layer.

5. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: First, one end of the first layer of field plate metal is coated with photoresist, and the other end of the first layer of field plate metal is corroded with an alkaline solution, so that a first gap is formed at the other end of the first layer of field plate metal; then, the end of the first layer of field plate metal having the first gap is coated with photoresist, and the end of the first layer of field plate metal away from the first gap is corroded with an alkaline solution, so that a second gap is formed at the end of the first layer of field plate metal away from the first gap.

6. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: An alkaline solution is used to simultaneously corrode both ends of the first layer of field plate metal, so that a first gap and a second gap are formed at both ends of the first layer of field plate metal respectively.

7. The preparation method according to claim 5 or 6, characterized in that: The length of the first notch is the same as or different from the length of the second notch.

8. The preparation method according to claim 4, characterized in that: The bottom surface of the end of the second layer of field plate metal close to the first notch is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer is 10°-20°.

9. The preparation method according to claim 4, characterized in that: The bottom surface of the end of the second layer field plate metal close to the first notch is an arc surface, and the central angle of the arc surface is 20° to 40°.

10. The preparation method according to claim 5 or 6, characterized in that: The bottom surface of the end of the second layer of field plate metal close to the first notch is a first inclined surface, the bottom surface of the end of the second layer of field plate metal close to the second notch is a second inclined surface, the angle between the first inclined surface and the top surface of the second dielectric layer is 10°~20°, and the angle between the second inclined surface and the top surface of the second dielectric layer is 10°~20°.

11. The preparation method according to claim 5 or 6, characterized in that: The bottom surface of the second field plate metal layer is an arc surface, and the central angle of the arc surface is 20° to 40°.

12. The preparation method according to any one of claims 4 to 6, characterized in that: The length of the remaining field plate metal after the end of the first field plate metal is etched accounts for 40% to 50% of the length of the end of the first field plate metal before etching.

13. The preparation method according to claim 1, characterized in that: In the step of annealing the n-layer field plate metal, the annealing temperature is 380-500°C.

14. The preparation method according to claim 1, characterized in that: The basic structure comprises, from bottom to top, a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer.

15. The preparation method according to claim 14, characterized in that: The method for preparing the base structure comprises: performing nitride epitaxial growth on a substrate to form an epitaxial layer structure, and sequentially growing a first dielectric layer and a second dielectric layer on the epitaxial layer; Etching is performed on the epitaxial layer, the first dielectric layer and the second dielectric layer to form a source electrode hole and a drain electrode hole, and metal deposition and etching are performed in the source electrode hole and the drain electrode hole, and then annealing is performed to form ohmic contacts to form a source electrode and a drain electrode respectively.

16. A device containing a multi-potential field plate structure, characterized in that: Prepared by the preparation method according to any one of claims 1 to 15.

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