Planar gate power device and manufacturing method thereof

Abstract

The invention discloses a planar gate power device. A device unit comprises a drift region, a planar gate, a channel region, a source region and an anti-JFET region. The anti-JFET region is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, and the anti-JFET top layer region is located between the channel regions on the two sides of the plane gate. The doping concentration of the anti-JFET top layer region is smaller than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used for reducing stepping of the device. The higher doping concentration of the bottom region is used to reduce the specific on-resistance of the device. The first doping layer penetrates through the source region and the channel region, and the top region of the first doping layer is used for being in contact with the channel region and serving as a channel leading-out region for leading out the channel region; and the bottom region of the first doping layer is used for exhausting the bottom region of the anti-JFET, so that the breakdown voltage of the device is improved. The invention further discloses a manufacturing method of the planar gate power device. The on-resistance of the device can be reduced and the breakdown voltage of the device can be increased while the stepping of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a planar gate power device; the present invention also relates to a manufacturing method of the planar gate power device. Background Art

[0002] The most common gate structures of power devices are planar gate and trench gate. The trench gate has a higher channel density and lower on-resistance, but the trench etching process is complicated and the etching depth is difficult to control. In addition, the electric field strength at the bottom of the trench is strong, especially for SiC trench gate MOSFET, this problem becomes particularly prominent, bringing great difficulty to the design. Planar gate MOSFET has better reliability, but the device has a large step (Pitch). Pitch is the size of a device unit in the periodically arranged device units in the active area along the arrangement direction, for example, the sum of the width of the gate structure of the device unit and the spacing between the gate structures. Therefore, based on the planar gate MOSFET structure, if the Pitch can be reduced, the channel density will be increased.

[0003] like Figure 1 FIG. 1 is a schematic diagram of the structure of an existing planar gate MOSFET. Taking an N-type device as an example, the device unit structure of the existing planar gate MOSFET includes:

[0004] The heavily doped N-type substrate 1 is connected to the drain electrode composed of the back metal layer. In order to reduce the back diffusion of the substrate 1, an arsenic-doped substrate 1 is usually selected. In order to reduce the resistance of the substrate 1, it is hoped that the doping concentration of the substrate 1 is as high as possible and the thickness of the substrate 1 is as thin as possible.

[0005] The drift region 2 is composed of a semiconductor epitaxial layer formed on the substrate 1. The doping concentration and thickness of the drift region 2 determine the breakdown voltage of the device. The drift region 2 can be uniformly doped or variably doped.

[0006] The gate conductive material layer 6 is usually composed of N-type heavily doped polysilicon; a gate oxide layer 5 is spaced between the gate conductive material layer and the bottom semiconductor epitaxial layer, and the gate oxide layer 5 is usually SiO2; the thickness of the gate oxide layer 5 depends on the breakdown voltage of the device; the thicker the gate oxide layer 5, the higher the breakdown voltage.

[0007] A P-type channel region 3 is formed in the top region of the semiconductor epitaxial layer on both sides of the planar gate, and an N-type heavily doped source region 4 is formed in the surface region of the channel region 3 .

[0008] The top of the source region 4 is connected to the source electrode, i.e., the source metal, composed of the front metal layer 8, through a contact hole 9, i.e., a through hole (CT). The through hole corresponding to the source region 4 also passes through the source region 4 and contacts the channel region 3. The location of the through hole is in the middle of the platform region (Mesa) between the gate structures. In order to ensure that the through hole and the channel region 3 can form a good ohmic contact, a through hole injection is usually added below the through hole to form a heavily doped P-type layer 10. The through hole injection is usually the commonly used BF2, the injection energy is between 10keV and 50keV, and the injection dose is usually 1e14cm -2 ~5e15cm -2 The contact hole 9 passes through the interlayer film 7.

[0009] In the bottom area of ​​the planar gate, because the channel region 3 and the N-type drift region 2 will form a depletion region, this will make the conductive area between the channel region 3 in the bottom area of ​​the planar gate narrower. In order to reduce the width of the depletion region, an anti-JFET region 11 is usually added between the channel regions 3. The anti-JFET region 11 is a part of the drift region 2, and its function is to increase the surface doping concentration of the drift region 2. The formation of the anti-JFET region 11 can increase the surface doping concentration of the drift region 2 when it grows. The typical condition is that the surface doping concentration, i.e., the anti-JFET region 11, is 2 to 6 times higher than the drift region 2 in the body, i.e., the bottom of the anti-JFET region 11; however, this will bring difficulties to the design of the terminal.

[0010] The anti-JFET region 11 can also be formed by ion implantation, which is the current mainstream process. The impurity implanted in the anti-JFET region 11 is usually phosphorus, and the implantation dose is usually 1e12cm -2 ~1e13cm -2 The ion implantation (Implant) corresponding to the anti-JFET region 11 is also called Anti-JFET Implant.

[0011] Compared with trench gate MOSFET, planar gate MOSFET has larger Pitch and higher on-resistance. There are several reasons for this:

[0012] A. Planar gate MOSFET, the width of the channel region 3 will be affected by process fluctuations, where the width of the channel region 3 covered by the planar gate is the conductive channel length. We need to ensure that the width of the channel region 3 is still sufficient under the worst process conditions, so that the source and drain will not be directly connected, that is, there will be no penetration between the source region 4 and the drift region 2. Therefore, the width of the channel region 3 is determined by the corresponding width under the worst process conditions, so the design width of the channel region 3 must be larger in the end, which will increase the pitch.

[0013] B. It is usually hoped that the doping concentration of the anti-JFET region 11 is as high as possible, which will reduce the specific on-resistance. The higher the doping concentration of the anti-JFET region 11, the stronger the depletion capability of the channel region 3 will be, and the greater the impact on the width of the channel region 3 will be, and finally the ptich will inevitably increase. Therefore, there is a contradiction between the setting of the doping concentration of the anti-JFET region 11 to meet the requirements of reducing pitch and reducing the specific on-resistance. In addition, the high doping concentration of the anti-JFET region 11 will reduce the breakdown voltage of the device. Summary of the invention

[0014] The technical problem to be solved by the present invention is to provide a planar gate power device that can reduce the stepping of the device while reducing the on-resistance of the device and increasing the breakdown voltage of the device. To this end, the present invention also provides a method for manufacturing the planar gate power device.

[0015] In order to solve the above technical problems, the device unit of the planar gate power device provided by the present invention comprises:

[0016] A semiconductor epitaxial layer doped with a first conductivity type.

[0017] A planar gate is formed on the top surface of the semiconductor epitaxial layer.

[0018] A channel region doped with a second conductivity type is formed in the semiconductor epitaxial layer on both sides of the planar gate. The channel region also extends into the semiconductor epitaxial layer in the area covered by the planar gate. The surface of the channel region covered by the planar gate is used to form a conductive channel.

[0019] A source region heavily doped with a first conductivity type is formed in the surface area of ​​the channel region at both sides of the planar gate, and the source region and the side surfaces of the planar gate are self-aligned.

[0020] A side wall is formed on the side of the planar grid.

[0021] A first doped layer heavily doped with the second conductivity type is also formed in the semiconductor epitaxial layer on both sides of the planar gate, and the first doped layer is self-aligned with the side surface of the spacer.

[0022] An anti-JFET region doped with a first conductivity type is formed in the surface region of the semiconductor epitaxial layer, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region.

[0023] The anti-JFET region is divided into at least an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region.

[0024] The doping concentration of the anti-JFET top region is lower than that of the anti-JFET bottom region. The lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region to increase the effective length of the conductive channel and thereby reduce device stepping.

[0025] The higher doping concentration of the bottom region serves to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device.

[0026] The first doped layer passes through the source region and the channel region, and the top region of the first doped layer is used to contact the channel region and serve as a channel lead-out region for leading out the channel region; the bottom region of the first doped layer is used to deplete the anti-JFET bottom region, thereby increasing the breakdown voltage of the device.

[0027] A further improvement is that the channel region and the side surfaces of the planar gate are self-aligned, and the channel region is formed by angled ion implantation.

[0028] A further improvement is that the planar gate power device comprises an active region and a terminal region, and the device unit is located in the active region.

[0029] The anti-JFET region is composed of an ion implantation region formed in the active region.

[0030] The ion implantation of the anti-JFET region includes at least two times, the implantation energies of the ion implantations of the anti-JFET region are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

[0031] A further improvement is that the process conditions for ion implantation in the anti-JFET region include:

[0032] The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 .

[0033] The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

[0034] A further improvement is that the width of the sidewall is 0.2 μm to 0.6 μm.

[0035] A further improvement is that the number of times of ion implantation into the first doping layer is one time or two times or more.

[0036] A further improvement is that when the number of ion implantations of the first doping layer is a single implantation, the implantation energy of the ion implantations of the first doping layer is 50keV to 200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 .

[0037] When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV-80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation of the first doping layer has an implantation energy of 100keV to 400keV and an implantation dose of 1e12cm -2 ~1e14cm -2 .

[0038] A further improvement is that the ion implantation angle of the channel region is 30 degrees to 60 degrees.

[0039] The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

[0040] A further improvement is that the planar gate power device comprises a planar gate power MOSFET, and a drain region heavily doped with the first conductivity type is formed on the back side of the drift region.

[0041] A further improvement is that the material of the semiconductor epitaxial layer includes Si and SiC.

[0042] In order to solve the above technical problems, the present invention provides a method for manufacturing a planar gate power device, comprising the following steps:

[0043] A semiconductor epitaxial layer doped with a first conductivity type is provided.

[0044] An anti-JFET region doped with a first conductive type is formed in the surface area of ​​the semiconductor epitaxial layer in the active area, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region; the active area is the formation area of ​​the device unit.

[0045] A planar gate and a channel region doped with a second conductivity type are formed on the top surface of the semiconductor epitaxial layer; the channel region is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region also extends to the semiconductor epitaxial layer in the area covered by the planar gate, and the surface of the channel region covered by the planar gate is used to form a conductive channel.

[0046] A heavily doped source region of the first conductivity type is formed in the surface area of ​​the channel region on both sides of the planar gate under the condition of self-alignment of the side surfaces of the planar gate.

[0047] The source region is formed in the surface area of ​​the channel region at both sides of the planar gate and the side surfaces of the source region and the planar gate are self-aligned.

[0048] A side wall is formed on the side of the planar grid.

[0049] A first doped layer heavily doped with the second conductivity type is formed in the semiconductor epitaxial layer on both sides of the planar gate under a self-alignment condition.

[0050] The anti-JFET region is divided into at least an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region.

[0051] The doping concentration of the anti-JFET top region is lower than that of the anti-JFET bottom region. The lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region to increase the effective length of the conductive channel and thereby reduce device stepping.

[0052] The higher doping concentration of the bottom region serves to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device.

[0053] The first doped layer passes through the source region and the channel region, and the top region of the first doped layer is used to contact the channel region and serve as a channel lead-out region for leading out the channel region; the bottom region of the first doped layer is used to deplete the anti-JFET bottom region, thereby increasing the breakdown voltage of the device.

[0054] A further improvement is that the channel region is formed before or after the planar gate is formed.

[0055] When the channel region is formed after the planar gate is formed, the channel region is formed by angled ion implantation with the side surface of the planar gate as a self-alignment condition.

[0056] A further improvement is that the anti-JFET region is formed by ion implantation, the ion implantation of the anti-JFET region includes at least two times, the implantation energies of the ion implantations of the anti-JFET region are different and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

[0057] A further improvement is that the process conditions for ion implantation in the anti-JFET region include:

[0058] The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 .

[0059] The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

[0060] A further improvement is that the width of the sidewall is 0.2 μm to 0.6 μm.

[0061] A further improvement is that the number of times of ion implantation into the first doping layer is one time or two times or more.

[0062] A further improvement is that when the number of ion implantations of the first doping layer is a single implantation, the implantation energy of the ion implantations of the first doping layer is 50keV to 200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 .

[0063] When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV-80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation of the first doping layer has an implantation energy of 100keV to 400keV and an implantation dose of 1e12cm -2 ~1e14cm -2 .

[0064] A further improvement is that the ion implantation angle of the channel region is 30 degrees to 60 degrees.

[0065] The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

[0066] The present invention arranges the anti-JFET region in layers, and the doping concentration of the anti-JFET top region is arranged to be lower than the doping concentration of the anti-JFET bottom region, so that the anti-JFET effect can be achieved through the anti-JFET top region while avoiding the adverse effect of excessive doping of the JFET top region on the channel region, so that the depletion of the channel region by the anti-JFET region can be reduced, thereby increasing the effective length of the conductive channel, that is, under the condition that the stepping of the device remains unchanged, the effective length of the conductive channel will be increased, and under the condition that the effective length of the conductive channel remains unchanged, the stepping of the device can be reduced.

[0067] At the same time, the doping concentration of the anti-JFET bottom region of the present invention can be improved. Since the anti-JFET bottom region is located in the bottom area of ​​the channel region, improving the doping concentration of the anti-JFET bottom region will no longer have an adverse effect on the channel region. Therefore, the device's specific on-resistance can be reduced by increasing the doping concentration of the anti-JFET bottom region. Therefore, the present invention overcomes the contradiction in the prior art that the excessively high doping concentration of the anti-JFET region will have an adverse effect on the channel region, thereby affecting the stepping of the device, and the excessively low doping concentration of the anti-JFET region will have an adverse effect on the device's specific on-resistance, by performing a layered arrangement of the anti-JFET region. At the same time, the beneficial effects of reducing the stepping of the device and reducing the device's specific on-resistance can be obtained.

[0068] At the same time, since the anti-JFET region is also part of the drift region, the increase in the doping concentration of the anti-JFET bottom region will affect the withstand voltage of the device. The present invention sets a first doping layer, and utilizes the first doping layer to achieve depletion of the anti-JFET bottom region, so the breakdown voltage of the device can be kept unchanged or further increased; at the same time, the first doping layer also serves as a channel lead-out region, and the channel lead-out region can directly achieve ohmic contact with the contact hole at the top of the source region, so there is no need to add a second conductive type heavily doped ion implantation at the bottom of the contact hole opening after the contact hole opening is formed to form a contact hole injection region. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0070] Figure 1 It is a schematic diagram of the structure of an existing planar gate MOSFET;

[0071] Figure 2 is a schematic structural diagram of a planar gate power device according to an embodiment of the present invention;

[0072] Figure 3A-3D It is a schematic diagram of the device structure in each step of the manufacturing method of the planar gate power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0073] like Figure 2 , which is a schematic diagram of the structure of a planar gate power device according to an embodiment of the present invention; the device unit of the planar gate power device according to an embodiment of the present invention includes:

[0074] A semiconductor epitaxial layer 32 doped with a first conductivity type.

[0075] A planar gate is formed on the top surface of the semiconductor epitaxial layer 32. In the embodiment of the present invention, the plane includes a gate dielectric layer 35 and a gate conductive material layer 36 stacked in sequence. In some embodiments, the gate dielectric layer 35 is a gate oxide layer, and the gate conductive material layer 36 is a polysilicon gate.

[0076] A channel region 33 doped with the second conductivity type is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate. The channel region 33 also extends into the semiconductor epitaxial layer 32 in the area covered by the planar gate. The surface of the channel region 33 covered by the planar gate is used to form a conductive channel.

[0077] A heavily first conductive type doped source region 34 is formed in the surface region of the channel region 33 at both sides of the planar gate and the source region 34 is self-aligned with the side surface of the planar gate.

[0078] A spacer 42 is formed on the side of the planar gate. In some embodiments, the material of the spacer 42 includes silicon oxide, silicon nitride or silicon oxynitride.

[0079] A first doped layer 40 heavily doped with the second conductivity type is further formed in the semiconductor epitaxial layer 32 on both sides of the planar gate. The first doped layer 40 and the side surfaces of the spacer 42 are self-aligned.

[0080] An anti-JFET region 41 doped with the first conductivity type is formed in the surface region of the semiconductor epitaxial layer 32 . The semiconductor epitaxial layer 32 at the bottom of the anti-JFET region 41 serves as a drift region. The doping concentration of the anti-JFET region 41 is greater than that of the drift region.

[0081] The anti-JFET region 41 is divided into at least an anti-JFET top region and an anti-JFET bottom region. The anti-JFET top region is located between the channel regions 33 on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region 33 .

[0082] The doping concentration of the anti-JFET top region is lower than that of the anti-JFET bottom region. The lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region 33 to increase the effective length of the conductive channel and thereby reduce device stepping.

[0083] The higher doping concentration in the bottom region serves to increase the doping concentration of the entire anti-JFET region 41 and thereby reduce the specific on-resistance of the device.

[0084] The first doped layer 40 passes through the source region 34 and the channel region 33. The top region of the first doped layer 40 is used to contact the channel region 33 and serve as a channel lead-out region for leading out the channel region 33. The bottom region of the first doped layer 40 is used to counteract the depletion of the JFET bottom region, thereby increasing the breakdown voltage of the device.

[0085] In the embodiment of the present invention, the channel region 33 and the side of the planar gate are self-aligned, and the channel region 33 is formed by angled ion implantation. In this structure, the channel region 33 is formed after the planar gate is formed. In other embodiments, the ion implantation area of ​​the channel region 33 can also be defined by photolithography. In this case, the channel region 33 is formed before the planar gate formation process. In this structure, the implanted impurities in the channel region 33 will undergo more thermal processes, such as the thermal process of the gate dielectric layer 35 of the planar gate formation process such as thermal oxidation process. This structure is more suitable for the case where the material of the semiconductor epitaxial layer 32 is SiC, because the ion activation temperature of the SiC device is high, and the channel region 33 is formed before the planar gate, which is conducive to fully activating the channel region 33 using the planar gate formation process.

[0086] In the embodiment of the present invention, the planar gate power device includes an active region and a terminal region, and the device unit is located in the active region. Usually, the terminal region surrounds the peripheral side of the active region, and a guard ring dielectric layer is formed on the surface of the terminal region, and the guard ring dielectric layer usually uses field oxide.

[0087] The anti-JFET region 41 is composed of an ion implantation region formed in the active region.

[0088] The ion implantation of the anti-JFET region 41 includes at least two times. The implantation energies of the ion implantations of the anti-JFET region 41 are different and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

[0089] As an example, the process conditions for ion implantation of the anti-JFET region 41 include:

[0090] The first ion implantation of the anti-JFET region 41 has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 .

[0091] The second ion implantation of the anti-JFET region 41 has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

[0092] As an example, the width of the spacer 42 is 0.2 μm to 0.6 μm.

[0093] The number of ion implantation into the first doping layer 40 is one time or two times or more.

[0094] When the number of ion implantation of the first doping layer 40 is single, the implantation energy of the ion implantation of the first doping layer 40 is 50keV-200keV, and the implantation dose is 1e14cm -2 ~5e15cm-2 .

[0095] When the number of ion implantations of the first doping layer 40 is 2, the implantation energy of the first ion implantation of the first doping layer 40 is 30 keV to 80 keV, and the implantation dose is 5e14 cm -2 ~5e15cm -2 The second ion implantation energy of the first doping layer 40 is 100keV to 400keV, and the implantation dose is 1e12cm -2 ~1e14cm -2 .

[0096] As an example, the ion implantation angle of the channel region 33 is 30 degrees to 60 degrees.

[0097] As an example, the ion implantation of the source region 34 is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

[0098] In an embodiment of the present invention, the planar gate power device includes a planar gate power MOSFET, and a drain region heavily doped with a first conductivity type is formed on the back side of a drift region.

[0099] The semiconductor epitaxial layer 32 is formed on the surface of the semiconductor substrate 31. In some embodiments, the semiconductor substrate 31 is heavily doped with the first conductivity type, and the drain region is directly composed of the thinned semiconductor substrate 31; or, the drain region is formed by back ion implantation of the thinned semiconductor substrate 31 by heavily doping with the first conductivity type.

[0100] In the embodiment of the present invention, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are both Si. In other embodiments, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are both SiC.

[0101] In the embodiment of the present invention, the top of the source region 34 is also connected to the source electrode formed by the front metal layer 38 through a contact hole, that is, a through hole (CT) 39 that passes through the interlayer film 37. The through hole 39 at the top of the source region 34 also passes through the source region 34, and the channel region 33 forms an ohmic contact through the channel lead-out region of the first doping layer 40 and the through hole 39, and finally the channel region 33 and the source region 34 are connected to the source electrode at the same time. Figure 1 As shown, in the embodiment of the present invention, the channel lead-out region is directly composed of the first doping layer 40 , and does not need to be additionally formed at the bottom of the through hole 39 by ion implantation.

[0102] The embodiment of the present invention arranges the anti-JFET region 41 in layers, and the doping concentration of the anti-JFET top region is arranged to be lower than the doping concentration of the anti-JFET bottom region. In this way, the anti-JFET effect can be achieved through the anti-JFET top region while avoiding the adverse effect of excessive doping of the JFET top region on the channel region 33. In this way, the depletion of the channel region 33 by the anti-JFET region 41 can be reduced, thereby increasing the effective length of the conductive channel, that is, the effective length of the conductive channel can be increased under the condition that the stepping of the device remains unchanged, and the stepping of the device can be reduced under the condition that the effective length of the conductive channel remains unchanged.

[0103] At the same time, the doping concentration of the anti-JFET bottom region in the embodiment of the present invention can be improved. Since the anti-JFET bottom region is located in the bottom area of ​​the channel region 33, increasing the doping concentration of the anti-JFET bottom region will no longer have an adverse effect on the channel region 33. Therefore, the device's specific on-resistance can be reduced by increasing the doping concentration of the anti-JFET bottom region. Therefore, the embodiment of the present invention overcomes the contradiction in the prior art that the excessively high doping concentration of the anti-JFET region 41 will have an adverse effect on the channel region 33, thereby affecting the stepping of the device, and the excessively low doping concentration of the anti-JFET region 41 will have an adverse effect on the device's specific on-resistance, by performing a layered arrangement of the anti-JFET region 41. At the same time, the beneficial effects of reducing the stepping of the device and reducing the device's specific on-resistance can be obtained.

[0104] At the same time, since the anti-JFET region 41 is also part of the drift region, the increase in the doping concentration of the anti-JFET bottom region will affect the withstand voltage of the device. The embodiment of the present invention sets a first doping layer 40, and utilizes the first doping layer 40 to achieve depletion of the anti-JFET bottom region, so the breakdown voltage of the device can be kept unchanged or further increased; at the same time, the first doping layer 40 also serves as a channel lead-out region, and the channel lead-out region can directly achieve ohmic contact with the contact hole at the top of the source region 34, so there is no need to add a second conductive type heavily doped ion implantation at the bottom of the contact hole opening after the contact hole opening is formed to form a contact hole injection region.

[0105] like FIG. 3A to FIG. 3D , which is a schematic diagram of the device structure in each step of the method for manufacturing a planar gate power device according to an embodiment of the present invention; the method for manufacturing a planar gate power device according to an embodiment of the present invention comprises the following steps:

[0106] Step S101: Figure 3A As shown, a semiconductor epitaxial layer 32 doped with a first conductivity type is provided.

[0107] In the method of the embodiment of the present invention, the semiconductor epitaxial layer 32 is formed on the top surface of the semiconductor substrate 31 .

[0108] In the method of the embodiment of the present invention, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are both Si. In other embodiments, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 can also be SiC.

[0109] Step S102: Figure 3A As shown, an anti-JFET region 41 doped with a first conductive type is formed in the surface area of ​​the semiconductor epitaxial layer 32 in the active area, and the semiconductor epitaxial layer 32 at the bottom of the anti-JFET region 41 serves as a drift region. The doping concentration of the anti-JFET region 41 is greater than the doping concentration of the drift region; the active area is the formation area of ​​the device unit.

[0110] In the embodiment method of the present invention, the anti-JFET region 41 is divided into at least an anti-JFET top region and an anti-JFET bottom region. The anti-JFET top region is located between the channel regions 33 on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region 33.

[0111] The doping concentration of the anti-JFET top region is lower than that of the anti-JFET bottom region. The lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region 33 to increase the effective length of the conductive channel and thereby reduce device stepping.

[0112] The higher doping concentration in the bottom region serves to increase the doping concentration of the entire anti-JFET region 41 and thereby reduce the specific on-resistance of the device.

[0113] In the method of the embodiment of the present invention, the anti-JFET region 41 is formed by ion implantation, and the ion implantation of the anti-JFET region 41 is shown by the arrow line corresponding to the mark 101. The ion implantation of the anti-JFET region 41 includes at least two times, and the implantation energies of each ion implantation of the anti-JFET region 41 are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

[0114] As an example, the process conditions for ion implantation of the anti-JFET region 41 include:

[0115] The first ion implantation of the anti-JFET region 41 has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 .

[0116] The second ion implantation of the anti-JFET region 41 has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

[0117] As an example, taking an N-type device as an example, the implanted impurity of the ion implantation of the anti-JFET region 41 is phosphorus.

[0118] Step S103: Figure 3B As shown, a planar gate and a channel region 33 doped with a second conductive type are formed on the top surface of the semiconductor epitaxial layer 32; the channel region 33 is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate, and the channel region 33 also extends into the semiconductor epitaxial layer 32 in the area covered by the planar gate, and the surface of the channel region 33 covered by the planar gate is used to form a conductive channel.

[0119] In the method of the embodiment of the present invention, the channel region 33 is formed after the planar gate is formed, that is, the channel region 33 is formed after the gate dielectric layer 35 of the planar gate, such as the gate oxide layer, is formed and the gate conductive material layer 36 is etched. At this time, the formation area of ​​the channel region 33 is directly defined by the side self-alignment of the planar gate. In other embodiments, the channel region 33 can also be formed before the planar gate is formed; for SiC devices, the ion activation temperature is high, and the channel region 33 needs to be made before the planar gate, which is conducive to the activation of impurities in the channel region 33, but at this time, it is necessary to use photolithography to define the injection area of ​​the channel region 33 separately.

[0120] The channel region 33 is formed after the planar gate is formed by performing angled ion implantation with the side of the planar gate as a self-aligned condition. The ion implantation of the channel region 33 is indicated by the inclined arrow line corresponding to the mark 102 .

[0121] The planar gate includes sequentially forming a gate dielectric layer 35 and a gate conductive material layer 36, then forming a hard mask layer 103, patterning and etching the hard mask layer 103, and then etching the gate conductive material layer 36 and the gate dielectric layer 35 using the hard mask layer 103 as a mask to form a planar gate.

[0122] As an example, the ion implantation angle of the channel region 33 is 30 to 60 degrees. In order to ensure that the doping concentration of the channel region 33 in different directions is consistent, the wafer corresponding to the semiconductor substrate 31 also needs to be turned; usually 4 times, each time 90 degrees. Taking the N-type device as an example, the typical conditions for ion implantation in the channel region 33 are: the implanted impurity is boron, the implantation energy is between 60keV and 150keV, and the implantation dose is 5e12cm -2 ~2e13cm -2 The injection can be performed once or multiple times; if the injection is performed multiple times, it is more preferred that the injection energy is low and the dose is low; the injection energy is high and the dose is high.

[0123] The length of the conductive channel formed in the channel region 33, namely the channel length, is controlled by the injection angle and the injection energy. This is a self-alignment process that does not require photolithography, thus avoiding the influence of changes in photolithography accuracy on the channel length.

[0124] Step S104: Figure 3C As shown, a heavily doped source region 34 of the first conductivity type is formed in the surface area of ​​the channel region 33 on both sides of the planar gate under the condition of self-alignment of the side surfaces of the planar gate.

[0125] The source region 34 is formed in the surface area of ​​the channel region 33 on both sides of the planar gate and is self-aligned with the side surface of the planar gate.

[0126] In the method of the embodiment of the present invention, the ion implantation of the source region 34 is vertical implantation or angled implantation with an implantation angle of less than or equal to 7 degrees. The use of angled implantation with an implantation angle of less than or equal to 7 degrees can avoid the channeling effect during the implantation process. Taking an N-type device as an example, the typical conditions for the ion implantation of the source region 34 are that the implanted impurity is Arsenic, the implantation energy is between 30keV and 80keV, and the implantation dose is 1e15 cm -2 ~1e16 cm -2 between.

[0127] Step S105: Figure 3D As shown, a side wall 42 is formed on the side of the planar grid.

[0128] In the method of the embodiment of the present invention, the sidewall 42 is formed by first depositing a sidewall material layer and then fully etching the sidewall material layer, and the sidewall material layer retained on the side of the planar gate is used as the sidewall 42, and the sidewall 42 is self-aligned and formed on the side of the planar gate.

[0129] As an example, the width of the spacer 42 is 0.2 μm to 0.6 μm.

[0130] Step S106: Figure 3D As shown, a first doped layer 40 heavily doped with the second conductivity type is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate using the sidewalls 42 on both sides of the planar gate as a self-alignment condition. The ion implantation of the first doped layer 40 is marked with arrow lines corresponding to the mark 105.

[0131] The first doped layer 40 passes through the source region 34 and the channel region 33. The top region of the first doped layer 40 is used to contact the channel region 33 and serve as a channel lead-out region for leading out the channel region 33. The bottom region of the first doped layer 40 is used to counteract the depletion of the JFET bottom region, thereby increasing the breakdown voltage of the device.

[0132] In the method of the embodiment of the present invention, the number of ion implantations in the first doping layer 40 is one time or two times or more.

[0133] As an example, when the number of ion implantation of the first doping layer 40 is a single time, the implantation energy of the ion implantation of the first doping layer 40 is 50keV to 200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 .

[0134] As an example, when the number of ion implantations of the first doping layer 40 is 2, the implantation energy of the first ion implantation of the first doping layer 40 is 30 keV to 80 keV, and the implantation dose is 5e14 cm -2 ~5e15cm -2 The second ion implantation energy of the first doping layer 40 is 100keV to 400keV, and the implantation dose is 1e12cm -2 ~1e14cm -2 In order to better deplete the first doping layer 40 and the anti-JFET region 41 and reduce the electric field intensity on the surface of the gate dielectric layer 35, the high-energy implant of the first doping layer 40 can be performed by angled implantation.

[0135] As an example, taking an N-type device as an example, the implanted impurity of the ion implantation of the first doping layer 40 is Boron.

[0136] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A planar gate power device, characterized in that: The device unit includes: a semiconductor epitaxial layer doped with a first conductivity type; A planar gate is formed on the top surface of the semiconductor epitaxial layer; A channel region doped with a second conductivity type is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region also extends into the semiconductor epitaxial layer in the area covered by the planar gate, and the surface of the channel region covered by the planar gate is used to form a conductive channel; A heavily doped source region of the first conductivity type is formed in the surface area of ​​the channel region on both sides of the planar gate, and the source region and the side of the planar gate are self-aligned; A side wall is formed on the side of the planar grid; A first doped layer heavily doped with a second conductivity type is also formed in the semiconductor epitaxial layer on both sides of the planar gate, and the first doped layer is self-aligned with the side surface of the spacer; An anti-JFET region doped with a first conductive type is formed in a surface region of the semiconductor epitaxial layer, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region; The anti-JFET region is at least divided into an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region; The doping concentration of the anti-JFET top region is less than the doping concentration of the anti-JFET bottom region, and the lower doping concentration of the anti-JFET top region is used to reduce the depletion of the channel region, so as to increase the effective length of the conductive channel and thereby reduce the stepping of the device; The higher doping concentration of the bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device; The first doped layer passes through the source region and the channel region, and the top region of the first doped layer is used to contact the channel region and serve as a channel lead-out region for leading out the channel region; the bottom region of the first doped layer is used to deplete the anti-JFET bottom region, thereby increasing the breakdown voltage of the device.

2. The planar gate power device according to claim 1, characterized in that: The channel region and the side surface of the planar gate are self-aligned, and the channel region is formed by angled ion implantation.

3. The planar gate power device according to claim 2, characterized in that: The planar gate power device comprises an active region and a terminal region, wherein the device unit is located in the active region; The anti-JFET region is composed of an ion implantation region formed in the active region; The ion implantation of the anti-JFET region includes at least two times, the implantation energies of the ion implantations of the anti-JFET region are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

4. The planar gate power device according to claim 3, characterized in that: The process conditions of ion implantation in the anti-JFET region include: The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 ; The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

5. The planar gate power device according to claim 1, characterized in that: The width of the sidewall is 0.2 μm to 0.6 μm.

6. The planar gate power device according to claim 1, characterized in that: The number of ion implantation into the first doping layer is one time or two times or more.

7. The planar gate power device according to claim 6, characterized in that: When the number of ion implantations of the first doping layer is single, the implantation energy of the ion implantations of the first doping layer is 50keV-200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 ; When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV-80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation of the first doping layer has an implantation energy of 100keV to 400keV and an implantation dose of 1e12cm -2 ~1e14cm -2 .

8. The planar gate power device according to claim 1, characterized in that: The ion implantation angle of the channel region is 30 to 60 degrees; The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

9. The planar gate power device according to claim 1, characterized in that: The planar gate power device comprises a planar gate power MOSFET, wherein a drain region heavily doped with a first conductivity type is formed on the back side of the drift region.

10. The planar gate power device according to claim 1, characterized in that: The material of the semiconductor epitaxial layer includes Si and SiC.

11. A method for manufacturing a planar gate power device, characterized in that: The steps include: Providing a semiconductor epitaxial layer doped with a first conductivity type; An anti-JFET region doped with a first conductive type is formed in the surface region of the semiconductor epitaxial layer of the active region, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region; the active region is a formation region of a device unit; A planar gate and a second conductive type doped channel region are formed on the top surface of the semiconductor epitaxial layer; the channel region is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region also extends into the semiconductor epitaxial layer in the area covered by the planar gate, and the surface of the channel region covered by the planar gate is used to form a conductive channel; Forming heavily doped source regions of the first conductivity type in the surface areas of the channel regions on both sides of the planar gate using the side surfaces of both sides of the planar gate as a self-alignment condition; The source region is formed in the surface area of ​​the channel region on both sides of the planar gate and the side of the source region and the planar gate are self-aligned; A side wall is formed on the side of the planar grid; Forming a heavily doped first doped layer of the second conductivity type in the semiconductor epitaxial layer on both sides of the planar gate using the side surfaces of the spacers on both sides of the planar gate as a self-alignment condition; The anti-JFET region is at least divided into an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region; The doping concentration of the anti-JFET top region is less than the doping concentration of the anti-JFET bottom region, and the lower doping concentration of the anti-JFET top region is used to reduce the depletion of the channel region, so as to increase the effective length of the conductive channel and thereby reduce the stepping of the device; The higher doping concentration of the bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device; The first doped layer passes through the source region and the channel region, and the top region of the first doped layer is used to contact the channel region and serve as a channel lead-out region for leading out the channel region; the bottom region of the first doped layer is used to deplete the anti-JFET bottom region, thereby increasing the breakdown voltage of the device.

12. The method for manufacturing a planar gate power device according to claim 11, wherein: The channel region is formed before or after the planar gate is formed; When the channel region is formed after the planar gate is formed, the channel region is formed by angled ion implantation with the side surface of the planar gate as a self-alignment condition.

13. The method for manufacturing a planar gate power device according to claim 12, wherein: The anti-JFET region is formed by ion implantation. The ion implantation of the anti-JFET region includes at least two times. The implantation energies of the ion implantations of the anti-JFET region are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

14. The method for manufacturing a planar gate power device according to claim 13, wherein: The process conditions of ion implantation in the anti-JFET region include: The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 ; The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

15. The method for manufacturing a planar gate power device according to claim 11, wherein: The width of the sidewall is 0.2 μm to 0.6 μm.

16. The method for manufacturing a planar gate power device according to claim 11, wherein: The number of ion implantation into the first doping layer is one time or two times or more.

17. The method for manufacturing a planar gate power device according to claim 16, wherein: When the number of ion implantations of the first doping layer is single, the implantation energy of the ion implantations of the first doping layer is 50keV-200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 ; When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV-80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation of the first doping layer has an implantation energy of 100keV to 400keV and an implantation dose of 1e12cm -2 ~1e14cm -2 .

18. The method for manufacturing a planar gate power device according to claim 11, wherein: The ion implantation angle of the channel region is 30 to 60 degrees; The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

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