Sensing transistor with lower spread resistance

Abstract

The invention relates to a sensing transistor with lower spread resistance. Described examples include an integrated circuit (400) having a first (401c) and a second (401a, 401b, 401d, 401e) transistor. The first transistor (401C) includes a plurality of trenches extending into the semiconductor substrate and a plurality of source regions (406 '), each source region being located between a pair of adjacent trenches. A first source terminal (436) is connected to the plurality of source regions (406 '). The second transistor (401a, 401b, 401d, 401e) includes a central source region (406) located between a pair of the trenches and a second source terminal (440) connected to the central source region (406). The second source terminal (440) is conductively isolated from the first source terminal (436).

Description

Technical Field

[0001] The disclosed embodiments relate generally to power semiconductors, and more particularly to high capacity transistors. Background Art

[0002] Large capacity transistors can handle voltages of hundreds of volts and currents in excess of amperes. The measurement of operating current may involve a smaller proxy transistor located near the high current transistor. The accuracy of the value obtained from the proxy transistor is required to accurately reflect the current through the high current transistor. Summary of the invention

[0003] According to various examples, an integrated circuit includes first and second transistors. The first transistor has a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, wherein each source region is located between a pair of adjacent trenches. A first source terminal is connected to the plurality of source regions. The second transistor includes a central source region located between a pair of the trenches and a second source terminal connected to the central source region. The second source terminal is conductively isolated from the first source terminal.

[0004] Other examples include methods of making and using an integrated circuit including the first and second transistors as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a plan view of an example large-capacity transistor device.

[0006] Figure 2 is a side view of the baseline sense FET.

[0007] Figure 3 is a plan view of the baseline sense FET.

[0008] Figure 4 is a side view of an example sense FET of the present disclosure.

[0009] Figure 5A and 5B is a plan view of an example sense FET of the present disclosure.

[0010] Figures 6A to 6K (collectively referred to as "FIG. 6") is a side view of an example process of the present disclosure for fabricating an example sense FET.

[0011] Figure 7 is a schematic diagram of a circuit including a sense FET according to an example of the present disclosure.

[0012] Figure 8 is a flow chart of the process of making current measurements using a sense FET. DETAILED DESCRIPTION

[0013] In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0014] In this specification, the term "coupled" may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are "coupled." Also, as used herein, the terms "on" and "over" may include layers or other elements with intervening or additional elements between an element and the element that is "on" or "over."

[0015] Various disclosed methods and apparatus of the present disclosure may be advantageously applied to switching DC-DC converters and other embodiments where accurate sensing of high current drive transistors is beneficial. While such embodiments may be expected to provide improvements in performance, such as improved operating efficiency of such embodiments, no specific results are required unless expressly recited in a particular claim.

[0016] Figure 11 is a plan view of an example high current capacity transistor device 100 according to various examples of the present disclosure. Substrate 102 includes two high current or high power transistors, namely transistor 104 and transistor 106, which can act as high-side and low-side transistors of switching voltage converter circuits such as buck converters, respectively. In this example, substrate 102 acts as the drain of the transistor. Each of transistors 104 and 106 can be a vertical trench field effect transistor (FET), which includes thousands of vertical FET elements and therefore includes a considerable number of trenches. Each vertical FET element can be regarded as a separate active device and cooperates to act together as a single active device or transistor. Transistors 104 and 106 each have a control terminal, which in the case of the current example is a terminal connection to the gate electrode (not explicitly shown) of the FET. As further explained below, the trench is filled with a corresponding field plate to dissipate the local high electric field, which is conducive to high voltage operation. A gate is formed adjacent to the sidewall of the trench, and a source is formed at the top of the mesa between adjacent trenches. Among other control circuits, sense field effect transistors (FETs) 108 and sense FETs 112 are included at the periphery of transistors 104 and 106, respectively. Sense FETs 108, 112 may also each be a vertical trench FET, but include a smaller number of trenches than transistors 104, 106. In this case, sense FET 108 is used to sense the current in transistor 104, and sense FET 112 is used to sense the current in FET 106. Sense FETs 108 and sense FETs 112 are formed using the same processing steps as transistors 104 and transistors 106, so that their behavior is almost the same as these transistors on a smaller scale. Sense FETs 108, 112 may include only a few trenches and therefore have a drive current capacity that is a small fraction of the drive current capacity of transistors 104, 106. Sense FETs 108 , 112 may operate in parallel with transistors 104 , 106 , respectively, with the current through sense FETs 108 , 112 providing a proxy value representative of the current through transistors 104 , 106 .

[0017] Figure 22 is a side view of a baseline sense FET 200 that can be used in some baseline implementations. A dielectric isolation structure 204 surrounds the sense FET 200 to mitigate the effects of other devices in the substrate 202. In this example, the sense FET 200 has six trenches 201 that allow ten parallel transistors between adjacent pairs of trenches. That is, two transistors are formed on either wall between adjacent trenches. A source contact 240 contacts the source 206. A gate 228 (gate electrode) controls the channel region between adjacent pairs of trenches 201. The substrate 202 acts as a drain. Layer 208, layer 222 (including layer 220), and plug 232 electrically separate the source contact 240 from the gate 228 and the source 206, except where the source contact 240 extends into the source 206 and is connected to the source by means of a contact 234. The wider first field plate 218 and the narrower second field plate 216, which are coupled to a reference potential through a circuit node outside the diagrammatic view, help avoid local high field regions in the substrate 202. The first field plate 218 is separated from the substrate 202 by the first insulating layer (sidewall liner) 212. The second field plate 216 is separated from the substrate 202 by the first insulating layer 212 and the second insulating layer 214. The thickness of the insulating layer modulates the effect of the field plate along the length of the trench 201. Importantly, the resistor 250 affects the specific resistance of the transistor. In addition, at the end transistor, the resistor 252 provides a parallel resistance for the transistor at the end of a series of transistors in the sense FET 200. The resistor 252 can be collectively referred to as an "extended resistor".

[0018] In the case of transistor 104 ( Figure 1 ) in a primary transistor, thousands of trenches may be used. Therefore, in the primary transistor, the effect of edge resistance (such as resistor 252) is very small. However, the effect of edge resistance 252 on sense FET 200 is much greater. The purpose of sense FET 200 is to represent the behavior of the primary transistor so that when gate 228 and source 206 are coupled to the same input as the gate and source of the primary transistor, the current through the sense FET is as close to proportional as possible to the current through the primary transistor. This allows the current through the primary transistor to be monitored using a much lower current through sense FET 200. However, the effect of edge resistance 252 has a negative impact on the proportionality of the current through sense FET 200.

[0019] Figure 3 3 is a plan view of an example baseline sense FET 300 representing the baseline sense FET 200. In this example, the sense FET 300 is surrounded by a dielectric isolation structure 304. A gate terminal 342 contacts the gate 328 at a contact 336. In this figure, only one contact is labeled for clarity. A source terminal 340 contacts the source 306 via a contact 334.

[0020] Figure 4 401e. A dielectric isolation structure 404 surrounds the sense FET 400 to mitigate the effects of other devices in the substrate 402. In some examples, the isolation structure 404 is implemented by a shallow trench isolation (STI) structure or a deep trench isolation structure. In some other examples, the isolation structure 404 can be omitted. In this example, the sense FET 400 has a linear array 401 of active devices, for example, parallel vertical LDMOS transistors formed on adjacent pairs of walls between parallel trenches. That is, vertical transistors are formed at two walls between the trenches. In the example shown, there are five pairs of vertical LDMOS transistors 401a...401e. Transistor pair 401c is a sensing active device, and transistor pairs 401a, 401b, 401d and 401e are dummy active devices. In this context, “dummy active devices” means that such devices are operable to conduct current consistent with the transistor design, but such devices do not directly contribute to the current sensing function of the sense FET 400 .

[0021] Source contact 440 contacts source 406, and source contact 436 contacts source 406'. Thus, source contact 440 can serve as a current handling terminal with respect to transistor pairs (dummy source devices) 401a, 401b, 401d, and 401e, and source contact 436 can serve as a current handling terminal with respect to transistor pair 401c. Body region 407 extends from source 406, 406' approximately to the bottom of gate 428. Gate 428 controls the channel within body region 407. In this example, substrate 402 serves as the drain of sense FET 400 and the drain of a transistor such as transistor 104, so that the drains of both transistors can be connected to the same voltage node, such as the back side of the substrate, which serves as the current handling terminal of transistor 104, transistor pairs 401a, 401b, 401d, and 401e, and transistor pair 401c. Layer 408, layer 422 (including layer 420), and dielectric plug 432 electrically separate source contact 440 from gate 428 and source 406, and contact 436 from gate 428' and source 406', except where source contact 440 and source contact 436 are connected to source 406, 406' by means of contact 434. A wider first field plate 418 and a narrower second field plate 416 are coupled to a reference potential outside the diagrammatic view and help avoid local high field regions in substrate 402. First field plate 418 is separated from substrate 402 by a first insulating layer (sidewall dielectric) 412. Second field plate 416 is separated from substrate 402 by a first insulating layer 412 and a second insulating layer 414. The thickness of the insulating layers modulates the effect of the field plates along the length of the trenches in linear array 401. Importantly, separate source contacts 436 allow separate connections to the centermost transistor pair 401c, and therefore to a subset of the vertical LDMOS transistors. Source contacts 440 can then be connected to the source terminals of the primary transistors, so that the experienced edge resistance (spreading resistance) 252 ( Figure 2 ) are not used to measure current, thereby improving the accuracy of current measurement. In this example, source contact 440 contacts the same number of transistors on the opposite side of the center-most transistor, but other examples may not be the case. Resistor 450 represents the drain stray resistance experienced by transistor pair 401c, which is substantially direct between source 406' and drain D due to the shielding of transistor pairs 401a, 401b, 401d and 401e, e.g., low spreading resistance. In the absence of a dummy pattern surrounding transistor pair 401c used as a sense FET, the sense FET would be affected by the spreading resistance effect and its drain side resistance would be reduced, causing systematic errors in current sensing.

[0022] Figure 5Ais sensed by the sense FET 400 ( Figure 4 ) is a plan view of an example sense FET 500 illustrated in FIG. 5 . An optional dielectric isolation structure 504 surrounds the sense FET 500. A gate terminal 527 is connected to all gates 528, and therefore all gates 528 are connected to the same gate terminal. A source terminal 536 is coupled to a source 506' in the centermost inter-trench region by a contact 534'. The source 506' can be disconnected from a source 506 that is co-linear with the source 506'. The connection to the source terminal 536' is provided by a lead 538 via a through-hole 537, which is at a higher metallization level. The contact 534 connects a dummy source terminal 540 to the source 506, which is all sources that are not coupled to the source terminal 536. As previously described, for clarity, only one contact 534 is shown for each source 506. The transistor element connected to the dummy source terminal 540 can generally operate as a single transistor and can be considered a single transistor. In various instances, and as shown, dummy source terminal 540 completely surrounds source terminal 536. In some instances, and as shown, source terminal 536 is centrally located within dummy source terminal 540 such that dummy source terminal 540 extends approximately the same distance horizontally to the left and right of source terminal 536 as shown, and extends approximately the same distance vertically above and below source terminal 536 as shown. Source terminal 536 is coupled to sensing circuitry (not shown) to measure the sense FET current. Dummy source terminal 540 can be coupled to a dummy load (not shown) similar to the load provided by the sensing circuitry, or can be connected to the source terminal of the primary transistor being monitored. Thus, the current sensed by the sensing circuitry comes only from the centermost inter-trench transistor that is not affected by the spreading resistance, such as, for example, resistor 252 ( Figure 2 ) is shown. This provides a transistor of interest (e.g., transistor 104 ( Figure 1 ))A more accurately proportional sense FET 500.

[0023] Figure 5B is a plan view of another sense FET 502. The sense FET 502 is also composed of the sense FET 400 ( Figure 4) is illustrated. An optional dielectric isolation structure 504 surrounds the sense FET 502. Similar to the sense FET 500, the source terminal 536 (now referred to as the first source terminal 536) is coupled to the source 506' in the centermost inter-trench region only through the contact 534'. Unlike the sense FET 500, the second source terminal 539 is coupled to three source regions 506" through the contact 534": the centermost inter-trench region and two adjacent inter-trench regions. Lead 538 and via 537 provide connection to the source terminal 536. Lead 541 and via 542 provide connection to the source terminal 539. The transistor element connected to the source terminal 539 can generally operate as a single transistor and can be considered as a single transistor. Figure 5A Similarly, for clarity, only one contact 534, 534', 534" is labeled. A dummy source terminal 540 is coupled to all sources 506 that are not coupled to source terminal 536 or source terminal 539. Notably, source 506' coupled to first source terminal 536 and source 506" coupled to second source terminal 539 are separated from source 506 coupled to dummy source terminal 540. First source terminal 536 and second source terminal 539 can be coupled to sensing circuitry (not shown) to measure sense FET current. Source terminal 540 can be coupled to a dummy load (not shown) similar to the load provided by the sensing circuitry or to the source terminal of the primary transistor being monitored. Therefore, the current sensed by the sensing circuitry from the first source terminal 536 comes only from the centermost inter-trench transistor, which is not significantly affected (if at all) by the spreading resistance effect. In contrast, the current sensed by the sensing circuitry of the second source terminal 539 comes only from the three centermost source regions 506. Thus, the sense FET 502 essentially comprises two sense transistors with slightly different characteristics that can be mathematically combined or compared by the control circuitry (not shown). It can be determined experimentally what mathematical combination of the two sense transistors provides the same current as the primary transistor (e.g., transistor 104 ( Figure 1 )) the most accurate proportionality. This can provide the most accurate proportionality with the primary FET 104 ( Figure 1 ) is more accurately proportional to the sense FET 502.

[0024] Figure 5A and 5B The examples of FIG. 5 (collectively referred to as “FIG. 5”) are only two of many examples in which the sense FET may be configured. For example, the active sense element may be bounded by one to 100 dummy sources to minimize spreading resistance, with 4-5 dummy sources being optimal, depending on resistive edge effects and the area consumed by the overall layout. For clarity of the diagram, the configuration of FIG. 5 uses fewer dummy sources and only one or three active sources.

[0025] Figures 6A to 6K (collectively referred to as "FIG. 6") is a side view of an example process for manufacturing an example sense FET 600, which is representative of sense FETs 400, 500, 502, and other examples consistent with the present disclosure. It is worth noting that this process is also applicable to manufacturing primary FET 104 ( Figure 1 ) trench transistor. Using the same process to fabricate the sense FET and the main FET increases the probability that the current through the sense FET 600 is accurately proportional to the current through the primary FET 104 over the entire gate input range, thereby providing a Figure 1 ) for accurate sensing of current.

[0026] Fig. 6A A semiconductor substrate 602 is shown on which a silicon dioxide layer 608 is formed using thermal oxidation in steam at a temperature of 900° C. to a thickness of, for example, approximately 10 nm (in the range of 5 nm to 20 nm). Not shown, optional isolation structures such as isolation structure 404 ( Figure 4 ) as an example.

[0027] Figure 6B The sense FET 600 is shown after forming a trench 610. The trench 610 can be formed by etching the silicon dioxide layer 608 using a patterned mask. This patterned silicon dioxide layer 608 can be used as a mask (e.g., a hard mask) for etching the trench 610 into the substrate 602. In an example, reactive ion etching is used to form the trench 610. Thus, the source region 606 is divided into several source regions, each source region being located between a pair of adjacent trenches. Figure 6C The sense FET 600 is shown after forming a thermal silicon dioxide layer 612 to a thickness of 100 nm (range 50 nm to 150 nm), for example, by steam oxidation at a temperature of 900° C. Although the thermal silicon dioxide layer 612 is shown as being uniform, in some cases the thickness of the thermal silicon dioxide layer 612 will vary. A silicon dioxide layer 614 has been formed on the thermal silicon dioxide layer 612 to a thickness of 50 nm (range 30 nm to 80 nm), for example, using chemical vapor deposition (CVD).

[0028] exist Fig.6D In the embodiment, the trench 610 has been filled with a photoresist layer 616 extending above the trench. In the example, the photoresist layer 616 is spun on and provides a flat top surface. The photoresist layer 616 is then exposed so that the top portion of the photoresist layer 616 is developed and then removed. Fig. 6E. The remaining portion of the photoresist layer 616' is shown in . The remaining photoresist layer 616' can occupy 20-80% of the trench depth, depending on the time of photoresist exposure and the type of photoresist used. The height of the remaining photoresist layer 616' is selected to provide the desired height of the narrower field plate that will be formed in the trench later. The exposed portion of the silicon dioxide layer 614 is removed using a wet etch that is selective to CVD deposited oxide relative to thermal oxide. An example of this etch is a buffered hydrofluoric acid (HF) solution that is 10 parts 40% ammonium fluoride and one part 49% hydrofluoric acid, which is approximately twice as selective to CVD oxide as thermal oxide. Thereafter, the remaining photoresist layer 616 is removed by solvent and / or ashing.

[0029] like Fig. 6F As shown, a polysilicon layer has been deposited, planarized, and etched back to form field plates 618. Field plates 618 may be doped in-situ, for example with boron, to provide a desired conductivity. Figure 6G The sense FET 600 is shown after a silicon dioxide layer 620 and a gate oxide layer 622 have been formed, for example, by thermal oxidation. The thickness of the gate oxide layer 622 may be 5 nm (range 3.5 nm to 10 nm). Due to the faster oxidation of the doped polysilicon in the field plate 618, the silicon dioxide layer 620 is thicker than the gate oxide layer 622. A polysilicon layer 624 is then deposited by CVD to a thickness of 400 to 600 nm. The polysilicon layer 624 may be doped to a thickness of 1 to 5×10 18 Atom / cm 3 This dopant provides high electrical conductivity to the polysilicon layer 624.

[0030] like Figure 6H As shown, the polysilicon layer 624 is subjected to anisotropic reactive ion etching (RIE) so that all of the polysilicon layer 624 is removed except for the sidewall gate 628 (gate electrode). Double implantation 629 forms the body region 607 and the source region 606. The source region 606 can be formed by ion implantation of phosphorus ions at a density of 1×10 15 Atom / cm 2 (The range is 0.5×10 15 Atom / cm 2 Up to 2×10 15 Atom / cm 2 ) and the energy is 35 keV (range 30 keV to 40 keV). The body region 607 can be formed by ion implantation of boron atoms, 5×10 13 Atom / cm 2 (The range is 1×10 13 Atom / cm 2 Up to 1×1014 Atom / cm 2 ) and the energy is 60keV (range 55keV to 65keV). Fig.6I As shown, CVD can be used to deposit the silicon dioxide layer 632. Figure 6J As shown, silicon dioxide layer 632 is planarized and etched back so that the portion of silicon dioxide layer 632 above silicon dioxide layer 608 is approximately 200 nm thick. Using a patterned photoresist layer (not shown), an opening to silicon dioxide layer 608 in the inter-trench region is etched. Using patterned silicon dioxide layer 632, source contacts 634 are implanted, for example, using ion implantation of phosphorus ions at a density of 1×10 16 Atom / cm 2 (The range is 0.5×10 16 Atom / cm 2 Up to 2×10 16 Atom / cm 2 ) and the energy is 20 keV (range 15 keV to 25 keV). Using the patterned silicon dioxide layer 632 as a mask, an opening to the source contact 634 is etched, such as Figure 6K A layer of polysilicon is then deposited and patterned to form source leads 640 and 636 .

[0031] Figure 7 is a schematic diagram of an example circuit 700 that can use a sense FET according to an example of the present disclosure. In general, circuit 700 provides a high current capacity transistor having terminals S (source), G (gate), and D (drain). The gate of transistor 702 is connected to terminal G, the drain of transistor 702 is connected to terminal D via resistor 704 and resistor 706, and the source of transistor 702 is connected to terminal S via resistor 708. Transistor 702 is composed of transistor 104 ( Figure 1 ) is exemplified. The resistors 704, 706, 708 may be provided by the resistors of the semiconductor on which the circuit 700 is implemented (e.g., substrate 402 ( Figure 4 ) or provided by a diffused or polysilicon resistor formed in or over the substrate. Sense FET 710 has a gate connected to terminal G and a drain connected to a node between resistors 704, 706. Sense FET 710 may be exemplified by sense FETs 108, 400, 500, and 502.

[0032] In order to provide an accurate simulation of the current I through transistor 702, the sense FET 710 requires a source voltage that is the same as the source voltage applied at terminal S. However, the current through the sense FET 710 needs to be kept separate so that the current can be accurately sensed by the current sensor 712. To achieve this, the circuit 700 includes an operational amplifier 714, the positive input of which is coupled to terminal S. The high input impedance of the operational amplifier 714 means that the operational amplifier 714 has very little effect on the operation of the transistor 702. A negative feedback loop is provided to the negative input of the operational amplifier 714 via transistor 716. Any deviation from the voltage on terminal S at the source of the sense FET 710 causes the output voltage of the operational amplifier 714 to adjust the voltage on the gate of the transistor 716 to bring the voltage on the source of the sense FET 710 back into sync with the voltage on terminal S. Thus, the resulting current I sense represents the current through transistor 702.

[0033] Figure 8 is to use a sense FET (e.g., sense FET 400 ( Figure 4 ), sense FET 500 or sense FET 502 (FIG. 5)) to perform a primary transistor (e.g., transistor 104 ( Figure 1 )) is a flow chart of a process 800 for current measurement of a substrate. In step 802, a first group of active devices having a first control terminal is provided in or above a substrate, a first current handling terminal is provided at a first surface of the substrate, and a second current handling terminal is provided at a second surface of the substrate opposite to the first surface of the substrate. Step 804 is providing a second group of active devices in or above the substrate in a linear array, the second group of active devices having a second control terminal conductively coupled to the first control terminal, a third current handling terminal at the first surface of the substrate, and a fourth current handling terminal at the second surface of the substrate conductively coupled to the second current handling terminal.

[0034] Step 806 is to provide at least one dummy active device in the substrate at an end of the linear array, the at least one dummy active device having a third control terminal conductively coupled to the first control terminal, a fifth current handling terminal at the first surface of the substrate, and a sixth current handling terminal conductively coupled to the second current handling terminal at the second surface of the substrate. Step 808 is to provide a current monitor coupled to the third current handling terminal, and measure the current through the second group using the current monitor. Step 810 is to determine the current through the first group by multiplying the current by a fixed factor.

[0035] Modifications to the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. An integrated circuit, comprising: A first transistor comprising: a plurality of trenches extending into the semiconductor substrate; a plurality of source regions, each source region being located between a pair of adjacent trenches; as well as a first source terminal connected to the plurality of source regions; as well as A second transistor comprising: a central source region located between a pair of the trenches; and A second source terminal is connected to the central source region and is conductively isolated from the first source terminal. 2 . The integrated circuit of claim 1 , wherein the central source region is collinear with one of the plurality of source regions. 3 . The integrated circuit of claim 1 , wherein the first source terminal completely surrounds the second source terminal.

4. The integrated circuit of claim 1 , wherein the first transistor comprises a plurality of gate electrodes, each gate electrode being in a corresponding one of the plurality of trenches, and the second transistor comprises a pair of gate electrodes, each of the pair of gate electrodes being in a corresponding one of the pair of adjacent trenches, the plurality of gate electrodes and the pair of gate electrodes being connected to a same gate terminal. 5 . The integrated circuit of claim 1 , wherein a drain of the first transistor and a drain of the second transistor are connected in parallel to a same voltage node.

6. The integrated circuit of claim 1, wherein the second transistor comprises a plurality of the trenches.

7. The integrated circuit of claim 1 , wherein the central source region is a first central source region, and the integrated circuit further comprises: A third transistor comprising: a second central source region located between the pair of trenches; as well as A third source terminal is connected to the second central source region and is conductively isolated from the first source terminal and the second source terminal.

8. The integrated circuit of claim 7, wherein the first source terminal completely surrounds the second source terminal and completely surrounds the third source terminal.

9. The integrated circuit of claim 1, wherein the central source region is located between a first subset of the trenches and a second subset of the trenches, the first and second subsets having the same number of trenches.

10. The integrated circuit of claim 1, wherein the first transistor shields the second transistor from spreading resistance.

11. A method of forming an integrated circuit, comprising: A first transistor is formed in or over a semiconductor substrate, comprising: forming a plurality of trenches extending into the semiconductor substrate; forming a plurality of source regions, each source region being located between a pair of adjacent trenches; as well as connecting a first source terminal to the plurality of source regions; as well as forming a second transistor in or over the semiconductor substrate, comprising: forming a central source region between a pair of the trenches of the first transistor; as well as A second source terminal is connected to the central source region and is conductively isolated from the first source terminal. The method of claim 11 , wherein the central source region is collinear with one of the plurality of source regions. The method of claim 11 , wherein the first source terminal completely surrounds the second source terminal.

14. The method of claim 11 , wherein the first transistor comprises a plurality of gate electrodes, each gate electrode being in a corresponding one of the plurality of trenches, and the second transistor comprises a pair of gate electrodes, each of the pair of gate electrodes being in a corresponding one of the pair of adjacent trenches, the plurality of gate electrodes and the pair of gate electrodes being connected to the same gate terminal. 15 . The method of claim 11 , wherein a drain of the first transistor and a drain of the second transistor are connected in parallel to a same voltage node. The method of claim 11 , wherein the second transistor comprises a plurality of the trenches.

17. The method of claim 11, wherein the central source region is a first central source region, and the method further comprises forming a third transistor comprising: forming a second central source region between a pair of the trenches; and A third source terminal is formed that is connected to the second central source region and is conductively isolated from the first source terminal and the second source terminal.

18. The method of claim 17, wherein the first source terminal completely surrounds the second source terminal and completely surrounds the third source terminal.

19. The method of claim 11, wherein the central source region is located between a first subset of the trenches and a second subset of the trenches, the first and second subsets having the same number of trenches.

20. The method of claim 11, further comprising connecting a current monitor configured to sense current through the second transistor.

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