Pixel array substrate

Abstract

A pixel array substrate includes: a substrate; a plurality of data lines arranged on the substrate and arranged in a first direction; the gate lines are arranged on the substrate and arranged in a second direction, and the first direction and the second direction are staggered; the pixel structures are arranged on the substrate, each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to the corresponding data line and the corresponding gate line; one data line, the transparent conductive layer and one pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the data line and the pixel electrode of the pixel structure; the transparent conducting layer is provided with a plurality of openings and overlaps the pixel electrode of the pixel structure, and the pixel electrode of the pixel structure is provided with a plurality of slits and overlaps the openings of the transparent conducting layer.

Description

[0001] This application is a divisional application of an invention patent application whose applicant is AU Optronics Corporation, with an application date of July 1, 2021, application number 202110745303.6, and invention name “Pixel Array Substrate”. Technical Field

[0002] The invention relates to a pixel array substrate. Background Art

[0003] With the development of display technology, people's demands for display devices are no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people also expect display devices to have narrow borders or even no borders.

[0004] Generally speaking, a display device includes a plurality of pixel structures arranged in a display area, a data driving circuit arranged below the display area, and a gate driving circuit arranged on the left side, right side, or both sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the gate line extending in the horizontal direction must be electrically connected to the gate driving circuit through a switching line extending in the vertical direction. However, the switching line is interspersed between the plurality of pixel structures, and the signal change of the switching line is likely to affect the voltage of the pixel electrode, which is not conducive to the display quality of the display device. Summary of the invention

[0005] The invention provides a pixel array substrate with excellent characteristics.

[0006] The present invention provides another pixel array substrate with excellent characteristics.

[0007] A pixel array substrate according to an embodiment of the present invention comprises a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures, a plurality of transfer lines and a common line. A plurality of data lines are arranged on the substrate and arranged in a first direction. A plurality of gate lines are arranged on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to the corresponding data line and the corresponding gate line. A plurality of transfer lines are arranged on the substrate, electrically connected to the plurality of gate lines, and arranged in the first direction. A common line is arranged on the substrate, wherein the plurality of data lines and the common line are arranged in the first direction. A plurality of pixel structures comprise a first pixel structure, a plurality of data lines comprise a first data line electrically connected to the first pixel structure, and a plurality of transfer lines comprise a first transfer line. The first data line has a first portion, which is arranged outside the pixel electrode of the first pixel structure and is located beside the active element of the first pixel structure. Each pixel structure has a first side and a second side opposite to each other. In a top view of the pixel array substrate, the first transfer line is disposed on a first side of the active element of the first pixel structure, and the first portion of the first data line and the common line are disposed on a second side of the active element of the first pixel structure.

[0008] A pixel array substrate according to an embodiment of the present invention comprises a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. A plurality of data lines are arranged on the substrate and arranged in a first direction. A plurality of gate lines are arranged on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to the corresponding data line and the corresponding gate line. A plurality of transfer lines are arranged on the substrate, electrically connected to the plurality of gate lines, and arranged in the first direction. A plurality of transfer lines comprise a first transfer line. A plurality of pixel structures comprise a first pixel structure and a second pixel structure, which are respectively arranged on opposite sides of the first transfer line. A plurality of data lines comprise a first data line and a second data line, which are respectively electrically connected to the first pixel structure and the second pixel structure. The first data line has a first portion, which is arranged outside the pixel electrode of the first pixel structure and is located next to the active element of the first pixel structure. The second data line has a second portion, which is arranged outside the pixel electrode of the second pixel structure and is located next to the active element of the second pixel structure. In a top view of the pixel array substrate, a first portion of the first data line is disposed on a second side of the active element of the first pixel structure, and a first portion of the second data line is disposed on a first side of the active element of the second pixel structure.

[0009] In one embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the first portion of the first data line and the first switching line have a first distance in the first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

[0010] In one embodiment of the present invention, the above-mentioned multiple pixel structures also include a second pixel structure, the first pixel structure and the second pixel structure are arranged adjacent to each other and are arranged in a first direction; the multiple data lines also include a second data line electrically connected to the second pixel structure; the multiple adapter lines also include a second adapter line; the second data line has a first portion, which is arranged outside the pixel electrode of the second pixel structure and is located next to the active element of the second pixel structure; in a top view of the pixel array substrate, the common line and the first portion of the second data line are arranged on the first side of the active element of the second pixel structure, and the second adapter line is arranged on the second side of the active element of the second pixel structure.

[0011] In one embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the first portion of the second data line and the common line have a third distance in the first direction, the first portion of the second data line and the second switching line have a fourth distance in the first direction, and the fourth distance is greater than the third distance.

[0012] In one embodiment of the present invention, the above-mentioned multiple pixel structures also include a third pixel structure, and the first pixel structure, the second pixel structure and the third pixel structure are arranged in sequence in the first direction; the multiple data lines also include a third data line electrically connected to the third pixel structure; the multiple adapters also include a third adapter; the third data line has a first portion, which is arranged outside the pixel electrode of the third pixel structure and is located next to the active element of the third pixel structure. In the top view of the pixel array substrate, the second adapter and the first portion of the third data line are arranged on the first side of the active element of the third pixel structure, and the third adapter is arranged on the second side of the active element of the third pixel structure; or, in the top view of the pixel array substrate, the second adapter is arranged on the first side of the active element of the third pixel structure, and the first portion of the third data line and the third adapter are arranged on the second side of the active element of the third pixel structure.

[0013] In an embodiment of the present invention, the third pixel structure is used to display blue.

[0014] In one embodiment of the present invention, the pixel array substrate further comprises: a transparent conductive layer, wherein the data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the data line and the pixel electrode of the pixel structure. The transparent conductive layer has a plurality of openings overlapping the pixel electrode of the pixel structure.

[0015] A pixel array substrate according to an embodiment of the present invention comprises a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a transparent conductive layer. A plurality of data lines are arranged on the substrate and arranged in a first direction. A plurality of gate lines are arranged on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding gate line. The data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the data line and the pixel electrode of the pixel structure. The transparent conductive layer has a plurality of openings overlapping the pixel electrode of the pixel structure.

[0016] In an embodiment of the present invention, in the top view of the pixel array substrate, the plurality of openings of the transparent conductive layer are located on two opposite sides of the data line.

[0017] In one embodiment of the present invention, the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

[0018] In one embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of slits overlapping the plurality of openings of the transparent conductive layer.

[0019] In one embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the multiple slits of the pixel electrode are arranged in a first range, the multiple openings of the transparent conductive layer are arranged in a second range, the first range and the second range overlap, and the area of ​​the second range is smaller than the area of ​​the first range.

[0020] In one embodiment of the present invention, the pixel electrode of the above-mentioned pixel structure has a plurality of first branch portions, the plurality of first branch portions are separated from each other to define a plurality of slits, the first branch portions have a first line width, and two adjacent ones of the plurality of first branch portions have a first spacing; the transparent conductive layer has a plurality of second branch portions, the plurality of second branch portions are separated from each other to define a plurality of openings, the second branch portions have a second line width, and two adjacent ones of the plurality of second branch portions have a second spacing; the sum of the second line width and the second spacing of the transparent conductive layer is greater than the sum of the first line width and the first spacing of the pixel electrode.

[0021] In one embodiment of the present invention, the transparent conductive layer has a first solid portion overlapping the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining a plurality of openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

[0022] In one embodiment of the present invention, the above-mentioned multiple pixel structures also include a fourth pixel structure. The first pixel structure and the fourth pixel structure are respectively arranged on opposite sides of the first adapter line. The multiple data lines also include a fourth data line electrically connected to the fourth pixel structure. The fourth data line has a first portion, which is arranged outside the pixel electrode of the fourth pixel structure and is located next to the active element of the fourth pixel structure. In the top view of the pixel array substrate, the first portion of the first data line is arranged on the second side of the active element of the first pixel structure, and the first portion of the fourth data line is arranged on the first side of the active element of the fourth pixel structure.

[0023] In one embodiment of the present invention, the first pixel structure and the fourth pixel structure are used to display red and blue respectively.

[0024] In one embodiment of the present invention, the above-mentioned multiple pixel structures also include a fifth pixel structure and a sixth pixel structure. The fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are arranged in sequence in the first direction. The fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are used to display blue, red, green and blue respectively. The multiple data lines also include a fifth data line electrically connected to the fifth pixel structure. The fifth data line has a first portion, which is arranged outside the pixel electrode of the fifth pixel structure and is located next to the active element of the fifth pixel structure. The multiple data lines also include a sixth data line electrically connected to the sixth pixel structure. The sixth data line has a first portion, which is arranged outside the pixel electrode of the sixth pixel structure and is located next to the active element of the sixth pixel structure. In the top view of the pixel array substrate, the first portion of the fifth data line is arranged on the second side of the active element of the fifth pixel structure, and the first portion of the sixth data line is arranged on the first side of the active element of the sixth pixel structure.

[0025] In one embodiment of the present invention, the above-mentioned multiple pixel structures also include a fifth pixel structure. The fourth pixel structure, the first pixel structure and the fifth pixel structure are arranged in sequence in the first direction. The fourth pixel structure, the first pixel structure and the fifth pixel structure are used to display blue, red and green respectively. The multiple data lines also include a fifth data line electrically connected to the fifth pixel structure. The fifth data line has a first portion, which is arranged outside the pixel electrode of the fifth pixel structure and is located next to the active element of the sixth pixel structure. In the top view of the pixel array substrate, the first portion of the first data line is arranged on the second side of the active element of the first pixel structure, and the first portion of the fifth data line is arranged on the first side of the active element of the fifth pixel structure.

[0026] In an embodiment of the present invention, in the top view of the pixel array substrate, the edge of the solid portion of the transparent conductive layer and the edge of the data line have a minimum distance, and the minimum distance is greater than or equal to 5 μm and less than or equal to 8 μm.

[0027] In one embodiment of the present invention, the plurality of openings of the transparent conductive layer are arranged in a first direction.

[0028] In one embodiment of the present invention, the plurality of openings of the transparent conductive layer are arranged in the second direction.

[0029] In one embodiment of the present invention, the plurality of openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other.

[0030] In one embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of slits overlapping the plurality of openings of the transparent conductive layer; the plurality of slits are arranged in a fifth direction; and the fourth direction and the fifth direction are substantially the same.

[0031] In one embodiment of the present invention, the pixel electrode of the above-mentioned pixel structure has multiple slits overlapping the multiple openings of the transparent conductive layer; the multiple slits are arranged in the fifth direction; the fourth direction and the fifth direction include an angle θ, and 0°<θ≤90°.

[0032] In one embodiment of the present invention, the transparent conductive layer has a plurality of second branch portions which are interlaced with each other in a mesh shape to define a plurality of openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the present invention.

[0034] Figure 2 FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention.

[0035] Figure 3 FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention.

[0036] Figure 4 FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention.

[0037] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a display device 10 according to an embodiment of the present invention.

[0038] Figure 6 FIG. 1 is a schematic top view of a region of a pixel array substrate 100A according to an embodiment of the present invention.

[0039] Figure 7 FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention.

[0040] Figure 8FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention.

[0041] Fig. 9 FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention.

[0042] Fig.10 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention.

[0043] Fig.11 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention.

[0044] Fig.12 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention.

[0045] Fig.13 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention.

[0046] Fig.14 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention.

[0047] Fig.15 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention.

[0048] Fig.16 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention.

[0049] Fig.17 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention.

[0050] Fig.18 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention.

[0051] Fig.19 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention.

[0052] Fig. 20 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention.

[0053] Fig.21 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention.

[0054] Fig. 22 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention.

[0055] Fig.23 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention.

[0056] Fig.24 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention.

[0057] Fig.25 FIG. 1 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the present invention.

[0058] Fig.26 FIG. 1 is a schematic top view of a region of a pixel array substrate 100I according to an embodiment of the present invention.

[0059] Fig. 27 FIG. 1 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the present invention.

[0060] Description of reference numerals:

[0061] 10: Display device

[0062] 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J: Pixel array substrate

[0063] 110: Base

[0064] 120: Pixel structure

[0065] 120-1: First pixel structure

[0066] 120-2: Second pixel structure

[0067] 120-3: The third pixel structure

[0068] 120-4: The fourth pixel structure

[0069] 120-5: The fifth pixel structure

[0070] 120-6: Sixth pixel structure

[0071] 120-7: Seventh pixel structure

[0072] 120-8: Eighth pixel structure

[0073] 120-9: Ninth pixel structure

[0074] 120-10: Tenth pixel structure

[0075] 120-11: Eleventh pixel structure

[0076] 120-12: 12th pixel structure

[0077] 121: Active components

[0078] 121a: Source

[0079] 121b: Drain

[0080] 121c: Gate

[0081] 121d: Semiconductor pattern

[0082] 122: Pixel electrode

[0083] 122a: First Chief

[0084] 122b: Second main cadre

[0085] 122c: First branch

[0086] 122s, 122s-1, 122s-2, 122s-3, 122s-4: Slit

[0087] 130, 140, 170: Insulation layer

[0088] 140a: Through hole

[0089] 150: Transparent conductive layer

[0090] 151: First physical part

[0091] 151e, DLe: Edge

[0092] 152, 152-1, 152-2, 152-3, 152-4: Opening

[0093] 153, 153C-1, 153C-2: Second branch

[0094] 160: Color filter pattern layer

[0095] 200: Opposite substrate

[0096] 210: Base

[0097] 220: Common electrode

[0098] 300: Display medium

[0099] CL: Common Line

[0100] CL': common electrode

[0101] CL'-1: At least one first

[0102] CL'-2: At least a second part

[0103] D1: First distance

[0104] D2: Second distance

[0105] D3: The third distance

[0106] D4: The fourth distance

[0107] DL: Data Line

[0108] DL1: First data line

[0109] DL2: Second data line

[0110] DL3: The third data line

[0111] DL4 fourth data line

[0112] DL5: Fifth data line

[0113] DL6: Sixth data line

[0114] DLa: Part I

[0115] DLb: Part 2

[0116] d4: fourth direction

[0117] d5: fifth direction

[0118] GL: Gate Line

[0119] gl: adapter cable

[0120] gl1: first adapter cable

[0121] gl2: second adapter cable

[0122] gl3: The third adapter cable

[0123] L1: First line width

[0124] L2: Second line width

[0125] R: Alignment area

[0126] S1: First spacing

[0127] S2: Second spacing

[0128] RG1: First Range

[0129] RG2: Second Range

[0130] W: Minimum distance

[0131] x: first direction

[0132] y: Second direction

[0133] z: third direction

[0134] θ: Angle

[0135] Ι-Ι': section line DETAILED DESCRIPTION

[0136] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0137] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0138] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0139] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0140] Figure 1 FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the present invention.

[0141] Figure 2 FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention.

[0142] Figure 3FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention. Figure 3 Omit Figure 2 A transparent conductive layer 150 is provided.

[0143] Figure 4 FIG. 1 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the present invention. Figure 4 Omit Figure 2 A plurality of pixel electrodes 122 are provided.

[0144] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a display device 10 according to an embodiment of the present invention. Figure 5 correspond Figure 2 Section line Ι-Ι'.

[0145] Please refer to Figure 1 , Figure 2 and Figure 5 The display device 10 includes a pixel array substrate 100, an opposite substrate 200 relative to the pixel array substrate 100, and a display medium 300 disposed between the pixel array substrate 100 and the opposite substrate 200. For example, in this embodiment, the display medium 300 may be liquid crystal. However, the present invention is not limited thereto, and in other embodiments, the display medium 300 may also be a plurality of organic electroluminescent patterns, a plurality of micro light emitting diode elements, or other applicable materials.

[0146] The pixel array substrate 100 includes a substrate 110. The substrate 110 is used to carry multiple components of the pixel array substrate 100. For example, in this embodiment, the material of the substrate 110 may be glass. However, the present invention is not limited thereto, and according to other embodiments, the material of the substrate 110 may also be quartz, organic polymer, or opaque / reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.

[0147] The pixel array substrate 100 includes a plurality of data lines DL and a plurality of gate lines GL, which are disposed on a substrate 110. The plurality of data lines DL are arranged in a first direction x, and the plurality of gate lines GL are arranged in a second direction y, wherein the first direction x is interlaced with the second direction y. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the present invention is not limited thereto.

[0148] The data lines DL and the gate lines GL belong to different film layers. For example, in this embodiment, the gate lines GL may selectively belong to the first metal layer, and the data lines DL may selectively belong to the second metal layer, but the invention is not limited thereto.

[0149] Based on the consideration of conductivity, in the present embodiment, the data lines DL and the gate lines GL are made of metal materials. However, the present invention is not limited thereto, and according to other embodiments, the data lines DL and the gate lines GL may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0150] The pixel array substrate 100 further includes a plurality of pixel structures 120 disposed on the substrate 110. Each pixel structure 120 includes an active device 121 and a pixel electrode 122 electrically connected to the active device 121, and the active device 121 is electrically connected to a corresponding data line DL and a corresponding gate line GL.

[0151] For example, in this embodiment, the active element 121 includes a thin film transistor, which has a source 121a, a drain 121b, a gate 121c and a semiconductor pattern 121d. The insulating layer 130 is sandwiched between the gate 121c and the semiconductor pattern 121d. The source 121a and the drain 121b are respectively electrically connected to two different regions of the semiconductor pattern 121d. The source 121a is electrically connected to a corresponding data line DL, the gate 121c is electrically connected to a corresponding gate line GL, and the drain 121b is electrically connected to the pixel electrode 122.

[0152] Please refer to Figure 2 and Figure 3 In the present embodiment, the pixel electrode 122 may selectively have a plurality of slits 122s to define at least one alignment region R of the pixel structure 120. For example, in the present embodiment, the pixel electrode 122 may selectively include a first main stem 122a, a second main stem 122b, and a plurality of first branch portions 122c; the first main stem 122a and the second main stem 122b are interlaced to divide a plurality of alignment regions R; in the same alignment region R, a plurality of first branch portions 122c extend in the same direction and are separated from each other to define a plurality of slits 122s; but the present invention is not limited thereto.

[0153] In this embodiment, a sub-pixel region where the pixel electrode 122 is located may selectively include four alignment regions R. However, the present invention is not limited thereto, and in another embodiment, a sub-pixel region may also have other numbers (e.g., one, two, three, or more than five) of alignment regions R. In addition, in another embodiment, the pixel electrode 122 may not have the slit 122s.

[0154] Please refer to Figure 2 and Figure 5In this embodiment, the pixel array substrate 100 further includes a common line CL disposed on the substrate 110, wherein a plurality of data lines DL and the common line CL are arranged in the first direction x. The common line CL may partially overlap with the pixel electrode 122 to form a storage capacitor.

[0155] In this embodiment, the gate 121c and the gate line GL may selectively belong to the first metal layer, the source 121a, the drain 121b, the data line DL and the common line CL may selectively belong to the second metal layer, and the pixel array substrate 100 may further include an insulating layer 140 disposed on the second metal layer. The pixel electrode 122 may be disposed on the insulating layer 140 and electrically connected to the drain 121b of the thin film transistor through the through hole 140a of the insulating layer 140, but the present invention is not limited to this.

[0156] In the present embodiment, the pixel electrode 122 is, for example, light-transmitting, and the material of the light-transmitting pixel electrode 122 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above. It should be noted that the present invention does not limit the pixel electrode 122 to be light-transmitting; in other embodiments, the pixel electrode 122 may also be light-reflecting, or partially light-reflecting and partially light-transmitting.

[0157] Please refer to Figure 1 and Figure 2 The pixel array substrate 100 further includes a plurality of transfer lines gl disposed on the substrate 110 and arranged in the first direction x. The plurality of transfer lines gl arranged in the first direction x are electrically connected to the plurality of gate lines GL arranged in the second direction y, and are interspersed between the plurality of pixel structures 120.

[0158] For example, in this embodiment, the gate line GL may selectively belong to the first metal layer, and the switching line gl may selectively belong to the second metal layer. However, the present invention is not limited thereto, and in other embodiments, the switching line gl may also include multiple parts respectively belonging to the first metal layer and the second metal layer.

[0159] Please refer to Figure 2 , Figure 3 and Figure 4 The plurality of pixel structures 120 include a first pixel structure 120-1, the plurality of data lines DL include a first data line DL1 electrically connected to the first pixel structure 120-1, and the plurality of switching lines gl include a first switching line gl1. The first data line DL1 has a first portion DLa disposed outside the pixel electrode 122 of the first pixel structure 120-1 and located next to the active element 121 of the first pixel structure 120-1.

[0160] The active element 121 of each pixel structure 120 has a first side (for example but not limited to the left side) and a second side (for example but not limited to the right side) relative to each other. It is worth noting that in the top view of the pixel array substrate 100, the active element 121 of the first pixel structure 120-1 has a first side (for example but not limited to the left side) and a second side (for example but not limited to the right side) relative to each other, the first transfer line gl1 is arranged on the first side (for example but not limited to the left side) of the active element 121 of the first pixel structure 120-1, and the first part DLa of the first data line DL1 and the common line CL are arranged on the second side (for example but not limited to the right side) of the active element 121 of the first pixel structure 120-1. In other words, when a transfer line gl and a common line CL are respectively arranged on two opposite sides of a pixel structure 120, a part of the data line DL that bypasses the active element 121 (i.e., the first part DLa) is arranged closer to the common line CL and away from the transfer line gl. Therefore, the coupling capacitance between the data line DL and the switching line gl can be reduced, and the influence of the signal change of the switching line gl on the potential of the pixel electrode 122 can be reduced, thereby improving the display quality.

[0161] Please refer to Figure 2 In the top view of the pixel array substrate 100, the first portion DLa of the first data line DL1 and the first switching line gl1 have a first distance D1 in the first direction x, the first portion DLa of the first data line DL1 and the common line CL have a second distance D2 in the first direction x, and the first distance D1 is greater than the second distance D2.

[0162] Please refer to Figure 2 In this embodiment, the plurality of pixel structures 120 further include a second pixel structure 120-2, the first pixel structure 120-1 and the second pixel structure 120-2 are adjacently arranged and arranged in the first direction x; the plurality of data lines DL further include a second data line DL2 electrically connected to the second pixel structure 120-2; the plurality of switching lines gl further include a second switching line gl2; the second data line DL2 has a first portion DLa, which is arranged outside the pixel electrode 122 of the second pixel structure 120-2 and is located next to the active element 121 of the second pixel structure 120-2.

[0163] In the top view of the pixel array substrate 100, the active element 121 of the second pixel structure 120-2 has a first side (for example but not limited to: the left side) and a second side (for example but not limited to: the right side) relative to each other, the common line CL and the first portion DLa of the second data line DL2 are arranged on the first side (for example but not limited to: the left side) of the active element 121 of the second pixel structure 120-2, and the second transfer line gl2 is arranged on the second side (for example but not limited to: the right side) of the active element 121 of the second pixel structure 120-2. In other words, when a common line CL and a transfer line gl are respectively arranged on two opposite sides of a pixel structure 120, a portion of the data line DL that bypasses the active element 121 (i.e., the first portion DLa) is arranged closer to the common line CL and away from the transfer line gl. Therefore, the coupling capacitance between the data line DL and the transfer line gl can be reduced, and the influence of the signal change of the transfer line gl on the potential of the pixel electrode 122 can be reduced, thereby improving the display quality.

[0164] In the top view of the pixel array substrate 100, the first portion DLa of the second data line DL2 and the common line CL have a third distance D3 in the first direction x, and the first portion DLa of the second data line DL2 and the second switching line gl2 have a fourth distance D4 in the first direction x, and the fourth distance D4 is greater than the third distance D3.

[0165] Please refer to Figure 2 In the present embodiment, the plurality of pixel structures 120 further include a third pixel structure 120-3, and the first pixel structure 120-1, the second pixel structure 120-2 and the third pixel structure 120-3 are arranged in sequence in the first direction x; there are no other pixel structures 120 between the first pixel structure 120-1, the second pixel structure 120-2 and the third pixel structure 120-3; the plurality of data lines DL further include a third data line DL3 electrically connected to the third pixel structure 120-3; the plurality of switching lines gl further include a third switching line gl3; the third data line DL3 has a first portion DLa, which is arranged outside the pixel electrode 122 of the third pixel structure 120-3 and is located next to the active element 121 of the third pixel structure 120-3.

[0166] In the top view of the pixel array substrate 100, the active element 121 of the third pixel structure 120-3 has a first side (for example but not limited to the left side) and a second side (for example but not limited to the right side) opposite to each other, the second transfer line gl2 and the first portion DLa of the third data line DL3 are arranged on the first side (for example but not limited to the left side) of the active element 121 of the third pixel structure 120-3, and the third transfer line gl3 is arranged on the second side (for example but not limited to the right side) of the active element 121 of the third pixel structure 120-3. When transfer lines gl are arranged on both opposite sides of a pixel structure 120, a portion of the data line DL that bypasses the active element 121 (i.e., the first portion DLa) can be arbitrarily arranged at a location closer to one of the transfer lines gl.

[0167] In the present embodiment, the third pixel structure 120-3 is used to display blue. In other words, the pixel structure 120 having the adapter lines gl on both sides thereof is preferably used to display blue. Therefore, the adverse effect of the adapter lines gl on the display quality can be reduced. In addition, in the present embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are used to display red and green, respectively, for example, but the present invention is not limited thereto.

[0168] Please refer to Figure 2 , Figure 4 and Figure 5 In this embodiment, the pixel array substrate 100 further includes a transparent conductive layer 150, wherein the data line DL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in a third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the data line DL and the pixel electrode 122 of the pixel structure 120. In addition, in this embodiment, the common line CL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in a third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the common line CL and the pixel electrode 122 of the pixel structure 120.

[0169] In short, in this embodiment, the transparent conductive layer 150 is arranged between the film layer to which the pixel electrode 122 belongs and the second metal layer to create a shielding effect on the components of the second metal layer (such as but not limited to: the adapter wire gl); therefore, the adverse effects of the signals of the components of the second metal layer (such as but not limited to: the adapter wire gl) on the pixel electrode 122 can be reduced, thereby improving the display quality.

[0170] In this embodiment, the potential of the transparent conductive layer 150 and the potential of the common line CL may be substantially equal. In this embodiment, the opposite substrate 200 may selectively include a common electrode 220 (shown in FIG. 2 ) disposed on the substrate 210 in addition to the substrate 210. Figure 5), the common electrode 220 overlaps the plurality of pixel electrodes 122 of the plurality of pixel structures 120, and the display medium 300 is disposed between the common electrode 220 and the plurality of pixel electrodes 122. The potential difference between the common electrode 220 and each pixel electrode 122 can be used to drive the display medium 300, thereby enabling the display device 10 to display images. In this embodiment, the potential of the transparent conductive layer 150 of the pixel array substrate 100 and the potential of the common electrode 220 of the opposite substrate 200 can be substantially equal, but the present invention is not limited thereto.

[0171] In this embodiment, the pixel array substrate 100 may optionally further include a color filter pattern layer 160 (indicated at Figure 5 ), wherein the color filter pattern layer 160 is disposed on the insulating layer 140, and the transparent conductive layer 150 is disposed on the color filter pattern layer 160; the pixel array substrate 100 also includes an insulating layer 170, the insulating layer 170 is disposed on the transparent conductive layer 150, and the pixel electrode 122 is disposed on the insulating layer 170.

[0172] Please refer to Figure 2 and Figure 4 It is worth noting that in this embodiment, the transparent conductive layer 150 may have a plurality of openings 152, which overlap the pixel electrode 122 of the pixel structure 120. The plurality of openings 152 of the transparent conductive layer 150 helps to reduce the interference of the transparent conductive layer 150 with the electric field formed by the pixel electrode 122, thereby increasing the liquid crystal efficiency and improving the transmittance of the display device 10.

[0173] In the present embodiment, the transparent conductive layer 150 has a first solid portion 151 overlapping the data line DL; in the top view of the pixel array substrate 100, the first solid portion 151 of the transparent conductive layer 150 has an edge 151e defining a plurality of openings 152, and the edge 151e of the first solid portion 151 of the transparent conductive layer 150 is located outside the data line DL. In other words, although the transparent conductive layer 150 has a plurality of openings 152, the first solid portion 151 of the transparent conductive layer 150 still well shields the second portion DLb overlapping the data line DL and the pixel electrode 122.

[0174] For example, in this embodiment, in the top view of the pixel array substrate 100, the edge 151e of the first solid portion 151 of the transparent conductive layer 150 and the edge DLe of the data line DL have a minimum distance W, and the minimum distance W is greater than or equal to 5μm and less than or equal to 8μm, but the present invention is not limited thereto.

[0175] Please refer to Figure 2 , Figure 3 and Figure 4In the present embodiment, in the top view of the pixel array substrate 100, the plurality of slits 122s of the pixel electrode 122 are disposed in the first range RG1, the plurality of openings 152 of the transparent conductive layer 150 are disposed in the second range RG2, the first range RG1 and the second range RG2 overlap, and the area of ​​the second range RG2 is smaller than the area of ​​the first range RG1.

[0176] In the present embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of first branch portions 122c, the plurality of first branch portions 122c are separated from each other to define a plurality of slits 122s, a first branch portion 122c has a first line width L1, and two adjacent first branch portions 122c have a first spacing S1; the transparent conductive layer 150 has a plurality of second branch portions 153, the plurality of second branch portions 153 are separated from each other to define a plurality of openings 152, a second branch portion 153 has a second line width L2, and two adjacent second branch portions 153 have a second spacing S2; the sum of the second line width L2 and the second spacing S2 of the transparent conductive layer 150 is greater than the sum of the first line width L1 and the first spacing S1 of the pixel electrode 122.

[0177] In the present embodiment, in the top view of the pixel array substrate 100, the plurality of openings 152 of the transparent conductive layer 150 are located at opposite sides of the data line DL. In the present embodiment, the plurality of slits 122s of the pixel electrode 122 include a plurality of slits 122s-1, a plurality of slits 122s-2, a plurality of slits 122s-3, and a plurality of slits 122s-4, which are respectively disposed in a plurality of alignment regions R divided by the first trunk 122a and the second trunk 122b of the pixel electrode 122; the plurality of openings 152 of the transparent conductive layer 150 may include a plurality of openings 152-1, a plurality of openings 152-2, a plurality of openings 152-3, and a plurality of openings 152-4, which are respectively overlapped with the plurality of slits 122s-1, a plurality of slits 122s-2, a plurality of slits 122s-3, and a plurality of slits 122s-4 of the pixel electrode 122.

[0178] In this embodiment, the plurality of openings 152-1, 152-2, 152-3 or 152-4 of the transparent conductive layer 150 may be arranged in the first direction x. In this embodiment, the plurality of openings 152 of the transparent conductive layer 150 may extend in the second direction y. In other words, in this embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be straight openings. However, the present invention is not limited thereto, and in other embodiments, the plurality of openings 152 may also be in other shapes and / or arranged in other ways, which will be described below with reference to other figures.

[0179] It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0180] Figure 6 FIG. 1 is a schematic top view of a region of a pixel array substrate 100A according to an embodiment of the present invention.

[0181] Figure 6 The pixel array substrate 100A and Figure 2 The pixel array substrate 100 is similar to the pixel array substrate 100 of FIG. 1 , and the difference between the two is that: Figure 2 In the embodiment, the first portion DLa of the third data line DL3 is disposed on a first side (for example but not limited to: the left side) of the active element 121 of the third pixel structure 120-3; Figure 6 In the embodiment, the first portion DLa of the third data line DL3 is disposed on the second side (for example but not limited to: the right side) of the active device 121 of the third pixel structure 120 - 3 .

[0182] Figure 7 FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention.

[0183] Figure 8 FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention. Figure 8 Omit Figure 7 A transparent conductive layer 150 is provided.

[0184] Fig. 9 FIG. 1 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the present invention. Fig. 9 Omit Figure 7 The pixel electrode 122 is formed by a plurality of electrodes.

[0185] Figures 7 to 9 The pixel array substrate 100B and Figures 2 to 4 The pixel array substrate 100 of the embodiment of the present invention is similar to that of the embodiment of the present invention, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two embodiments of the present invention are different.

[0186] Please refer to Figures 7 to 9 Specifically, in this embodiment, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the second direction y. Each opening 152 of the transparent conductive layer 150 may extend in the first direction x. In other words, in this embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be a plurality of lateral openings.

[0187] Fig.10 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention.

[0188] Fig.11 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention. Fig.11 Omit Fig.10 A transparent conductive layer 150 is provided.

[0189] Fig.12 FIG. 1 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the present invention. Fig.12 Omit Fig.10 The pixel electrode 122 is formed by a plurality of electrodes.

[0190] Figures 10 to 12 The pixel array substrate 100C and Figures 2 to 4 The pixel array substrate 100 of the embodiment of the present invention is similar to that of the embodiment of the present invention, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two embodiments of the present invention are different.

[0191] Please refer to Figures 10 to 12 Specifically, in this embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1, 153C-2, which are interlaced with each other in a mesh shape to define a plurality of openings 152 (indicated at Fig.12 ). Furthermore, in the present embodiment, the plurality of second branch portions 153C-1, 153C-2 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 that are staggered with each other, wherein the plurality of second branch portions 153C-1 may be selectively parallel to the second portion DLb of the data line DL, and the plurality of second branch portions 153C-1 may be selectively perpendicular to the second portion DLb of the data line DL.

[0192] Fig.13 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention.

[0193] Fig.14 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention. Fig.14 Omit Fig.13 A transparent conductive layer 150 is provided.

[0194] Fig.15 FIG. 1 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the present invention. Fig.15 Omit Fig.13 The pixel electrode 122 is formed by a plurality of electrodes.

[0195] Figures 13 to 15 The pixel array substrate 100D and Figures 2 to 4 The pixel array substrate 100 of the embodiment of the present invention is similar to that of the embodiment of the present invention, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two embodiments of the present invention are different.

[0196] Please refer to Figures 13 to 15 Specifically, in this embodiment, a plurality of data lines DL are arranged in a first direction x, a plurality of gate lines GL are arranged in a second direction y, a plurality of openings 152 of the transparent conductive layer 150 are arranged in a fourth direction d4, and the first direction x, the second direction y and the fourth direction d4 are different from each other.

[0197] Furthermore, in this embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of slits 122s, the plurality of slits 122s of the pixel electrode 122 overlap with the plurality of openings 152 of the transparent conductive layer 150, the plurality of slits 122s of the pixel electrode 122 are arranged in a fifth direction d5, the plurality of openings 152 of the transparent conductive layer 150 are arranged in a fourth direction d4, and the fourth direction d4 is substantially the same as the fifth direction d5.

[0198] Fig.16 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention.

[0199] Fig.17 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention. Fig.17 Omit Fig.16 A transparent conductive layer 150 is provided.

[0200] Fig.18 FIG. 1 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the present invention. Fig.18 Omit Fig.16 The pixel electrode 122 is formed by a plurality of electrodes.

[0201] Figures 16 to 18 The pixel array substrate 100E and Figures 13 to 15 The pixel array substrate 100D is similar to the pixel array substrate 100D, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two are different.

[0202] Please refer to Figures 16 to 18 Specifically, in this embodiment, the multiple slits 122s of the pixel electrode 122 are arranged in the fifth direction d5, the multiple openings 152 of the transparent conductive layer 150 are arranged in the fourth direction d4, and the fourth direction d4 and the fifth direction d5 form an angle θ, and 0°<θ≤90°.

[0203] Fig.19 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention.

[0204] Fig. 20 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention. Fig. 20 Omit Fig.19 A transparent conductive layer 150 is provided.

[0205] Fig.21 FIG. 1 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the present invention. Fig.21 Omit Fig.19 The pixel electrode 122 is formed by a plurality of electrodes.

[0206] Figures 19 to 21 The pixel array substrate 100F and Figures 10 to 12 The pixel array substrate 100 of the embodiment of the present invention is similar to that of the embodiment of the present invention, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two embodiments of the present invention are different.

[0207] Please refer to Figures 19 to 21 Similarly, in this embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1, 153C-2 (indicated at Fig.21 ), interlaced with each other in a mesh shape to define a plurality of openings 152; the plurality of second branch portions 153C-1 and 153C-2 of the transparent conductive layer 150 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 interlaced with each other. Figures 10 to 12 In this embodiment, the second branch portions 153C-1 are neither parallel nor perpendicular to the second portion DLb of the data line DL, and the second branch portions 153C-2 are neither parallel nor perpendicular to the second portion DLb of the data line DL. In short, in this embodiment, the second branch portions 153C-1 and 153C-2 of the transparent conductive layer 150 can be interwoven into a mesh pattern arranged obliquely.

[0208] Fig. 22 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention.

[0209] Fig.23 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention. Fig.23 Omit Fig. 22 A transparent conductive layer 150 is provided.

[0210] Fig.24 FIG. 1 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the present invention. Fig.24 Omit Fig. 22 The pixel electrode 122 is formed by a plurality of electrodes.

[0211] Figure 22 to Figure 24 The pixel array substrate 100G and Figures 2 to 4 The pixel array substrate 100 of the embodiment of the present invention is similar to that of the embodiment of the present invention, and the main difference between the two is that the openings 152 of the transparent conductive layer 150 of the two embodiments of the present invention are different.

[0212] Please refer to Figure 22 to Figure 24In the present embodiment, the transparent conductive layer 150 does not have the opening 152 of the aforementioned pixel array substrate 100 , and the entity of the transparent conductive layer 150 may overlap with the pixel electrode 122 .

[0213] Fig.25 FIG. 1 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the present invention. Fig.25 The pixel array substrate 100H and Figure 2 The main differences between the two are described below. For the same or similar points between the two, please refer to the above description and will not be repeated here.

[0214] Please refer to Fig.25 In this embodiment, the plurality of pixel structures 120 further include a fourth pixel structure 120-4; the first pixel structure 120-1 and the fourth pixel structure 120-4 are respectively disposed on opposite sides of the first transfer line gl1; the plurality of data lines DL further include a fourth data line DL4 electrically connected to the fourth pixel structure 120-4; the fourth data line DL4 has a first portion DLa, disposed outside the pixel electrode 122 of the fourth pixel structure 120-4, and located next to the active element 121 of the fourth pixel structure 120-4. In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the first data line DL1 is disposed on the second side (for example but not limited to: the right side) of the active element 121 of the first pixel structure 120-1, and the first portion DLa of the fourth data line DL4 is disposed on the first side (for example but not limited to: the right side) of the active element 121 of the fourth pixel structure 120-4. That is, in this embodiment, two pixel structures 120 are adjacent to the same switching line gl and are respectively located on opposite sides of the same switching line gl, and the two first portions DLa of the two data lines DL respectively electrically connected to the two pixel structures 120 are both arranged away from the switching line gl.

[0215] Please refer to Fig.25 In this embodiment, the first pixel structure 120-1 and the fourth pixel structure 120-4 are used to display red and blue respectively. That is, in the top view of the pixel array substrate 100, a transfer line gl is disposed between the plurality of pixel structures 120 used to display red and blue respectively.

[0216] Please refer to Fig.25In the present embodiment, the plurality of pixel structures 120 further include a fifth pixel structure 120-5, a sixth pixel structure 120-6, a seventh pixel structure 120-7 and an eighth pixel structure 120-8. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5 and the sixth pixel structure 120-6 are arranged in sequence in the first direction x. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5 and the sixth pixel structure 120-6 are used to display red, green, blue, red, green and blue respectively. The plurality of data lines DL further include a fifth data line DL5 electrically connected to the fifth pixel structure 120-5. The fifth data line DL5 has a first portion DLa, is disposed outside the pixel electrode 122 of the fifth pixel structure 120-5, and is located next to the active device 121 of the fifth pixel structure 120-5. The plurality of data lines DL also include a sixth data line DL6 electrically connected to the sixth pixel structure 120-6. The sixth data line DL6 has a first portion DLa, is disposed outside the pixel electrode 122 of the sixth pixel structure 120-6, and is located next to the active device 121 of the sixth pixel structure 120-6.

[0217] In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the fifth data line DL5 is disposed on the second side (for example but not limited to the right side) of the active element 121 of the fifth pixel structure 120-5, and the first portion DLa of the sixth data line DL6 is disposed on the first side (for example but not limited to the left side) of the active element 121 of the sixth pixel structure 120-6. In other words, the two first portions DLa of the two data lines DL electrically connected to the two pixel structures 120 for displaying green and blue, respectively, are disposed adjacent to each other.

[0218] Fig.26 FIG. 1 is a schematic top view of a region of a pixel array substrate 100I according to an embodiment of the present invention. Fig.26 The pixel array substrate 100I and Fig.25 The pixel array substrate 100H is similar to the pixel array substrate 100H, and the difference between the two is that: Fig.26 In the top view of the pixel array substrate 100I, the first portion DLa of the first data line DL1 is disposed on the second side (for example but not limited to the right side) of the active element 121 of the first pixel structure 120-1, and the first portion DLa of the fifth data line DL5 is disposed on the first side (for example but not limited to the left side) of the active element 121 of the fifth pixel structure 120-5. That is, Fig.26 In the embodiment of FIG. 1 , two first portions DLa of two data lines DL respectively electrically connected to two pixel structures 120 for displaying red and green are disposed adjacent to each other.

[0219] Fig. 27 FIG. 1 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the present invention. Fig. 27 The pixel array substrate 100J and Figure 2 The main differences between the two are described below. For the same or similar points between the two, please refer to the above description and will not be repeated here.

[0220] Please refer to Fig. 27 In the present embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are respectively disposed on opposite sides of the first transition line gl1. The plurality of data lines DL include a first data line DL1 and a second data line DL2, which are respectively electrically connected to the first pixel structure 120-1 and the second pixel structure 120-2. The first data line DL1 has a first portion DLa, which is disposed outside the pixel electrode 122 of the first pixel structure 120-1 and is located next to the active element 121 of the first pixel structure 120-1. The second data line DL2 has a first portion DLa, which is disposed outside the pixel electrode 122 of the second pixel structure 120-2 and is located next to the active element 121 of the second pixel structure 120-2.

[0221] In particular, in the top view of the pixel array substrate 100J, the first transfer line gl1 is disposed on the first side (for example but not limited to: the left side) of the active element 121 of the first pixel structure 120-1, the first portion DLa of the first data line DL1 is disposed on the second side (for example but not limited to: the right side) of the active element 121 of the first pixel structure 120-1, the first transfer line gl1 is disposed on the second side (for example but not limited to: the right side) of the active element 121 of the second pixel structure 120-2, and the first portion DLa of the second data line DL2 is disposed on the first side (for example but not limited to: the left side) of the active element 121 of the second pixel structure 120-2. That is, in the present embodiment, there are two pixel structures 120 adjacent to the same transfer line g1 and respectively located on opposite sides of the same transfer line g1, and the two first portions DLa of the two data lines DL respectively electrically connected to the two pixel structures 120 are both disposed away from the transfer line gl.

[0222] Please refer to Fig. 27In the present embodiment, the plurality of pixel structures 120 further include a ninth pixel structure 120-9, a tenth pixel structure 120-10, an eleventh pixel structure 120-11 and a twelfth pixel structure 120-12. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9 and the tenth pixel structure 120-10 are arranged in sequence in the first direction x. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9 and the tenth pixel structure 120-10 can be used to display red, green, blue, red, green and blue, respectively.

[0223] also, Fig. 27 The pixel array substrate 100J does not include Figure 2 The common line CL of the pixel array substrate 100 includes a common electrode CL'. Fig. 27 In this embodiment, the common electrode CL' includes at least one first portion CL'-1, and the at least one first portion CL'-1 of the common electrode CL' is arranged with the gate line GL in the second direction y, and the at least one first portion CL'-1 of the common electrode CL' partially overlaps with the pixel electrode 122. In this embodiment, the common electrode CL' also includes at least one second portion CL'-2, and the at least one second portion CL'-2 of the common electrode CL' is arranged with the data line DL in the first direction x, and the at least one second portion CL'-2 of the common electrode CL' partially overlaps with the pixel electrode 122. Furthermore, Fig. 27 The pixel array substrate 100J may not include Figure 2 The transparent conductive layer 150 of the pixel array substrate 100 is formed.

Claims

1. A pixel array substrate, comprising: a base; A plurality of data lines are disposed on the substrate and arranged in a first direction; A plurality of gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction; A plurality of pixel structures are disposed on the substrate, wherein each of the pixel structures comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding gate line; as well as a transparent conductive layer, wherein the data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the data line and the pixel electrode of the pixel structure; The transparent conductive layer has a plurality of openings overlapping the pixel electrode of the pixel structure, wherein the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer.

2. The pixel array substrate as described in claim 1 further includes a common line, wherein the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in the third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the common line and the pixel electrode of the pixel structure.

3. The pixel array substrate as described in claim 1, wherein in a top view of the pixel array substrate, the slits of the pixel electrode are arranged in a first range, the openings of the transparent conductive layer are arranged in a second range, the first range and the second range overlap, and the area of ​​the second range is smaller than the area of ​​the first range.

4. The pixel array substrate as described in claim 1, wherein the pixel electrode of the pixel structure has a plurality of first branch portions, the first branch portions are separated from each other to define the slits, the first branch portions have a first line width, and two adjacent ones of the first branch portions have a first spacing; the transparent conductive layer has a plurality of second branch portions, the second branch portions are separated from each other to define the openings, the second branch portions have a second line width, and two adjacent ones of the second branch portions have a second spacing; the sum of the second line width and the second spacing of the transparent conductive layer is greater than the sum of the first line width and the first spacing of the pixel electrode.

5. The pixel array substrate as described in claim 1, wherein the transparent conductive layer has a first solid portion overlapping the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining the openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line. 6 . The pixel array substrate as claimed in claim 1 , wherein the openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other. 7 . The pixel array substrate as claimed in claim 6 , wherein the slits are arranged in a fifth direction; an angle θ is formed between the fourth direction and the fifth direction, and 0°<θ≤90°. 8 . The pixel array substrate as claimed in claim 1 , wherein in a top view of the pixel array substrate, an edge of the solid portion of the transparent conductive layer and an edge of the data line have a minimum distance, and the minimum distance is greater than or equal to 5 μm and less than or equal to 8 μm. 9 . The pixel array substrate as claimed in claim 4 , wherein the second branch portions are staggered with each other to form a mesh shape. 10 . The pixel array substrate as claimed in claim 2 , wherein a potential of the transparent conductive layer is substantially equal to a potential of the common line.

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