Power device integrated with high-robustness ESD (Electro-Static Discharge) protection structure and preparation method

Abstract

The invention discloses a power device integrated with a high-robustness ESD (Electro-Static Discharge) protection structure and a preparation method, and relates to the field of semiconductor devices. The power device comprises a first conductive type substrate, an active region prepared in a central region of the substrate, a terminal protection region surrounding the active region, and at least one ESD protection structure prepared in the terminal protection region, the ESD protection structure is in ohmic contact with first electrode metal used for forming a first electrode and second electrode metal used for forming a second electrode above the substrate, so that the ESD protection structure is connected in series between the first electrode and the second electrode; and two current discharge passages are formed based on the ESD protection structure and are used for discharging ESD current. The device has relatively good ESD current discharge capability and relatively low switching loss.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a power device with an integrated high-robustness ESD protection structure and a preparation method thereof. Background Art

[0002] Integrated circuit products will accumulate charges during the manufacturing, testing, packaging, storage, and transportation process. When the pin of the product is grounded, the current generated by the pin discharging the charge reaches the ampere level. In the absence of an ESD (Electro-Static Discharge) protection structure, the high voltage generated instantly will cause the device to break down and fail. At the same time, a large amount of heat will cause the silicon material and aluminum near the pin to reach the melting point and dissolve each other, resulting in lattice mismatch, metal connection line breakage, and ultimately product failure. Therefore, the design of the ESD protection structure in chip design is directly related to the functional stability of the chip and is extremely important.

[0003] Figure 8 A cross-sectional view of a power device with a traditional ESD protection structure is shown. As shown in the figure, the traditional ESD protection structure uses a group of alternating N-type and P-type polysilicon to form a Zener diode group. When the diode is reverse biased, very little current flows from the cathode to the anode. When the reverse bias exceeds the reverse breakdown voltage, the reverse current suddenly increases. As the reverse bias increases, regardless of the current flowing through the diode, the diode will form a constant voltage region, thereby achieving a voltage stabilization state. However, as the application scenarios of power devices become more and more complex, the requirements for the chip's ability to resist ESD are becoming higher and higher, especially for the communications field. When advanced processes are carried out, the failure current of the traditional ESD protection structure per unit width is also deteriorating. Therefore, how to improve the robustness of the ESD protection structure through a better electrostatic protection design, thereby improving the reliability of power devices, is an urgent problem to be solved. Summary of the invention

[0004] In view of the above problems and technical requirements, the inventors have proposed a power device with an integrated high-robustness ESD protection structure and a preparation method thereof. The technical solution of the present invention is as follows:

[0005] A power device with an integrated high-robustness ESD protection structure comprises a first conductive type substrate, an active region prepared in the center of the substrate, a terminal protection region surrounding the active region, and at least one ESD protection structure prepared in the terminal protection region, wherein:

[0006] The ESD protection structure is in ohmic contact with a first electrode metal for forming a first electrode and a second electrode metal for forming a second electrode above the substrate, so as to connect the ESD protection structure in series between the first electrode and the second electrode;

[0007] Two current discharge paths are formed based on the ESD protection structure to discharge the ESD current.

[0008] A further technical solution is that the ESD protection structure includes a first polysilicon group, a second polysilicon group, an N-type body region and a P-type body region, wherein:

[0009] The N-type body region and the P-type body region are in contact and are both located in the substrate corresponding to the terminal protection area;

[0010] The first polysilicon group at least includes an N-type first polysilicon body, an N-type second polysilicon body, and a P-type first polysilicon body, wherein the P-type first polysilicon body is located between the N-type first polysilicon body and the N-type second polysilicon body, and contacts the N-type first polysilicon body and the N-type second polysilicon body;

[0011] The second polysilicon group at least includes an N-type third polysilicon body, an N-type fourth polysilicon body, and a P-type second polysilicon body, wherein the P-type second polysilicon body is located between the N-type third polysilicon body and the N-type fourth polysilicon body, and contacts the N-type third polysilicon body and the N-type fourth polysilicon body;

[0012] The P-type first polysilicon body is in contact with the N-type body region, the N-type third polysilicon body is in contact with the P-type body region, and the N-type first polysilicon body, the N-type second polysilicon body, the N-type fourth polysilicon body and the P-type second polysilicon body are isolated from the N-type body region and the P-type body region by an isolation oxide layer;

[0013] The N-type first polysilicon body is in ohmic contact with the first electrode metal, the N-type second polysilicon body is electrically connected to the N-type third polysilicon body, and the N-type fourth polysilicon body is in ohmic contact with the second electrode metal.

[0014] A further technical solution is that the N-type first polysilicon body, the P-type first polysilicon body and the N-type second polysilicon body are arranged in sequence along a first direction above the substrate and correspond to the N-type body region, wherein:

[0015] The P-type first polysilicon body extends from the substrate to the N-type body region, and the extension depth of the P-type first polysilicon body in the N-type body region is not greater than the junction depth of the N-type body region. The first direction is perpendicular to the substrate thickness direction.

[0016] A further technical solution is that the N-type third polysilicon body, the P-type second polysilicon body and the N-type fourth polysilicon body are arranged in sequence along a first direction above the substrate and correspond to the P-type body region, wherein:

[0017] The N-type third polysilicon body extends from the substrate to the P-type body region, and the extension depth of the N-type third polysilicon body in the P-type body region is not greater than the junction depth of the P-type body region. The first direction is perpendicular to the substrate thickness direction.

[0018] A further technical solution is that the active area includes a plurality of planar cells distributed in parallel;

[0019] The planar cell comprises a planar gate unit prepared on a substrate, wherein the planar gate unit comprises a planar gate oxide layer and a planar gate polysilicon group, and the planar gate polysilicon group is insulated and isolated from the substrate by the planar gate oxide layer;

[0020] The planar gate polysilicon group is in ohmic contact with a second electrode metal for forming a second electrode above the substrate, and the planar gate polysilicon group includes a plurality of alternately arranged N-type planar gate polysilicon bodies and P-type planar gate polysilicon bodies.

[0021] A further technical solution is that the planar gate polysilicon group includes four N-type planar gate polysilicon bodies and three P-type planar gate polysilicon bodies, and the N-type planar gate polysilicon bodies and the P-type planar gate polysilicon bodies are alternately arranged along a first direction, and the first direction is perpendicular to the substrate thickness direction;

[0022] The three P-type planar gate polysilicon bodies are respectively located between two adjacent N-type planar gate polysilicon bodies, and any P-type planar gate polysilicon body is in contact with the N-type planar gate polysilicon bodies adjacent to the two sides.

[0023] A further technical solution is that a second conductive type base region is disposed on both sides of the planar gate unit, and a first conductive type source region and a second conductive type source region are disposed in the second conductive type base region;

[0024] The second conductive type base region and the first conductive type source region both overlap with the planar gate unit, and the first conductive type source region in the same second conductive type base region contacts the second conductive type source region;

[0025] The first conductive type source region and the second conductive type source region are both in ohmic contact with a first electrode metal used to form a first electrode.

[0026] A further technical solution is that the doping concentration of the first conductive type source region is greater than the doping concentration of the substrate, and the doping concentration of the second conductive type source region is greater than the doping concentration of the second conductive type base region.

[0027] A further technical solution is that the second conductive type base region located at the edge of the active region extends from the active region to the terminal protection region;

[0028] The N-type body region and the P-type body region are both arranged in the second conductive type base region extending into the terminal protection.

[0029] A method for preparing a power device with an integrated high-robustness ESD protection structure, used for preparing the above-mentioned power device, the method for preparing the power device comprising:

[0030] Providing a substrate of a first conductivity type, and preparing at least one ESD protection structure in a terminal protection area of ​​the substrate;

[0031] The ESD protection structure is in ohmic contact with a first electrode metal for forming a first electrode and a second electrode metal for forming a second electrode above the substrate, so as to connect the ESD protection structure in series between the first electrode and the second electrode;

[0032] Two current discharge paths are formed based on the ESD protection structure to discharge the ESD current.

[0033] In the above-mentioned "first conductivity type" and "second conductivity type", for N-type power devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0034] The beneficial technical effects of the present invention are:

[0035] The present invention is provided with a highly robust ESD protection structure in the terminal protection zone, and two current discharge paths are formed based on the ESD protection structure, thereby increasing the ESD current discharge capacity of the device, enhancing the robustness of the ESD protection structure, and reducing the loss when discharging the ESD current, which is very beneficial for advanced highly robust ESD protection engineering. At the same time, the present invention also uses polysilicon of different conductivity types to form a planar gate polysilicon group to reduce input capacitance and reduce switching losses of power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a cross-sectional view of an embodiment of a power device with an integrated high-robustness ESD protection structure provided by the present invention.

[0037] Figure 2 Schematic diagram of the structure of the gate-drain capacitor in one embodiment of the present invention.

[0038] Figure 3 Schematic diagram of an equivalent circuit of a gate-drain capacitor in an embodiment of the present invention.

[0039] Figure 4-Figure 7 1 is a cross-sectional view of the process steps of an embodiment of a method for preparing a power device with an integrated high-robustness ESD protection structure provided by the present invention, wherein:

[0040] Figure 4 It is a cross-sectional view of an embodiment after the first filling groove and the second filling groove are prepared in the present invention.

[0041] Figure 5 It is a cross-sectional view of an embodiment of the present invention in which a P-type base region is prepared.

[0042] Figure 6 It is a cross-sectional view of an embodiment of the present invention after the insulating dielectric layer is prepared.

[0043] Figure 7 It is a cross-sectional view of an embodiment of the present invention after preparing the first electrode metal, the connecting metal and the second electrode metal.

[0044] Figure 8 It is a cross-sectional view of a power device with a traditional ESD protection structure.

[0045] Reference numerals: 1-substrate, 2-N-type body region, 3-P-type body region, 41-N-type first polysilicon body, 42-N-type second polysilicon body, 43-N-type third polysilicon body, 44-N-type fourth polysilicon, 51-P-type first polysilicon, 52-P-type second polysilicon, 6-P-type base region, 7-P-type source region, 8-N-type source region, 9-planar gate oxide layer, 10-isolation oxide layer, 11-protective layer, 12-insulating dielectric layer, 13-first electrode metal, 14-connection metal, 15-second electrode metal, 16-N-type planar gate polysilicon body, 17-P-type planar gate polysilicon body. 18-first contact hole, 19-second contact hole, 20-third contact hole, 21-fourth contact hole, 22-fifth contact hole. DETAILED DESCRIPTION

[0046] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0047] The present invention provides a power device with an integrated high-robustness ESD protection structure. Taking the first conductivity type as N-type as an example, in one embodiment of the present invention, the power device with an integrated high-robustness ESD protection structure comprises an N-type substrate 1, an active area prepared in the central area of ​​the substrate 1, a terminal protection area surrounding the active area, and at least one ESD protection structure prepared in the terminal protection area, wherein:

[0048] The ESD protection structure is in ohmic contact with a first electrode metal for forming a first electrode and a second electrode metal for forming a second electrode above the substrate 1, so as to connect the ESD protection structure in series between the first electrode and the second electrode;

[0049] Two current discharge paths are formed based on the ESD protection structure to discharge the ESD current.

[0050] Specifically, for a power device, it generally includes an active area located in the central area of ​​the substrate 1 and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art, and the specific structure in the terminal protection area can refer to the following implementation. The substrate 1 can be made of existing commonly used materials, such as silicon substrates, silicon carbide substrates, etc., to meet application requirements. The substrate 1 generally has a front side and a back side corresponding to the front side, and the ESD protection structure is prepared on the front side of the substrate 1 corresponding to the terminal protection area.

[0051] Generally, for a power device, the front electrode arranged on the front side of its substrate 1 includes a first electrode and a second electrode, and the back side of the substrate 1 is also provided with a back metal for forming a third electrode. Specifically, according to different settings of the back side structure of the substrate 1, the power device can form a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type device or an IGBT (Insulated Gate Bipolar Transistor) type device. For a MOSFET type device, the first electrode of the power device is the source, the second electrode is the gate, and the third electrode is the drain; for an IGBT type device, the first electrode of the power device is the emitter, the second electrode is the gate, and the third electrode is the collector.

[0052] In this embodiment, the first electrode metal 13 used to form the first electrode and the second electrode metal 15 used to form the second electrode are simultaneously in ohmic contact with the ESD protection structure to form two current discharge paths between the first electrode and the second electrode of the power device based on the ESD protection structure, which are used to discharge the ESD current so that the power device has anti-ESD performance. The traditional ESD protection structure can generally only form one current discharge path. Compared with the traditional ESD protection structure, the ESD protection structure provided by the present invention can form two current discharge paths, which increases the ESD current discharge capacity of the device, enhances the robustness of the ESD protection structure, and reduces the loss when discharging the ESD current, which is very beneficial for advanced high-robust ESD protection engineering. The specific implementation form of the ESD protection structure can refer to the following description.

[0053] Furthermore, the ESD protection structure includes a first polysilicon group, a second polysilicon group, an N-type body region 2 and a P-type body region 3, wherein:

[0054] The N-type body region 2 and the P-type body region 3 are in contact with each other and are both located in the substrate 1 corresponding to the terminal protection area; the first polysilicon group at least includes an N-type first polysilicon body 41, an N-type second polysilicon body 42 and a P-type first polysilicon body 51, and the P-type first polysilicon body 51 is located between the N-type first polysilicon body 41 and the N-type second polysilicon body 42, and is in contact with the N-type first polysilicon body 41 and the N-type second polysilicon body 42;

[0055] The second polysilicon group at least includes an N-type third polysilicon body 43, an N-type fourth polysilicon body 44, and a P-type second polysilicon body 52, wherein the P-type second polysilicon body 52 is located between the N-type third polysilicon body 43 and the N-type fourth polysilicon body 44, and contacts the N-type third polysilicon body 43 and the N-type fourth polysilicon body 44;

[0056] The P-type first polysilicon body 51 is in contact with the N-type body region 2, the N-type third polysilicon body 43 is in contact with the P-type body region 3, and the N-type first polysilicon body 41, the N-type second polysilicon body 42, the N-type fourth polysilicon body 44 and the P-type second polysilicon body 52 are isolated from the N-type body region 2 and the P-type body region 3 by the isolation oxide layer 10;

[0057] The N-type first polysilicon body 41 is in ohmic contact with the first electrode metal 13 , the N-type second polysilicon body 42 is electrically connected to the N-type third polysilicon body 43 , and the N-type fourth polysilicon body 44 is in ohmic contact with the second electrode metal 15 .

[0058] Specifically, the N-type second polysilicon body 42 and the N-type third polysilicon body are both in ohmic contact with the connection metal 14 disposed above the substrate 1 , so as to be electrically connected to each other through the connection metal 14 . Figure 1 Taking MOSFET as an example, the specific form of ESD protection structure is shown. Figure 1 As shown, the N-type first polysilicon body 41, the P-type first polysilicon body 51 and the N-type second polysilicon body 42 in this embodiment are arranged on the front side of the substrate 1 corresponding to the terminal protection area, and are arranged in sequence along the first direction above the substrate 1, and correspond to the N-type body region 51, wherein the P-type first polysilicon body 51 extends vertically from the front side of the substrate 1 to the N-type body region 2, and the extension depth of the P-type first polysilicon body 51 in the N-type body region 2 is not greater than the junction depth of the N-type body region 2. The N-type first polysilicon body 41 and the N-type second polysilicon body 42 are isolated from the N-type body region 2 by the isolation oxide layer 10 on the front side of the substrate 1. The doping concentration of the N-type body region 2 is greater than the doping concentration of the N-type substrate 1.

[0059] Similarly, the N-type third polysilicon body 43, the P-type second polysilicon body 52 and the N-type fourth polysilicon body 44 are also arranged on the front side of the substrate 1 corresponding to the terminal protection area, and are arranged in sequence along the first direction above the substrate 2, and correspond to the P-type body region 3, wherein the N-type third polysilicon body 43 extends vertically from the upper side of the substrate 1 to the P-type body region 3, and the extension depth of the N-type third polysilicon body 43 in the P-type body region 3 is not greater than the junction depth of the P-type body region 3, and the first direction is perpendicular to the thickness direction of the substrate 1. The P-type second polysilicon body 52 and the N-type fourth polysilicon body 44 are isolated from the P-type body region 3 by the isolation oxide layer 10 on the front side of the substrate 1. In a specific implementation, the N-type first polysilicon body 41, the P-type first polysilicon body 51 and the N-type second polysilicon body 42 in the first polysilicon group, and the N-type third polysilicon body 43, the P-type second polysilicon body 52 and the N-type fourth polysilicon body 44 in the second polysilicon group can be arranged in the substrate 1, or can be stacked along the thickness direction of the substrate 1 to further reduce the area of ​​the ESD protection structure. At the same time, the N-type polysilicon body and the P-type polysilicon body that can be in contact with each other in the first polysilicon group and the second polysilicon group can be the minimum repeating unit, and the number of polysilicon bodies in the ESD protection structure is increased under the condition that the conductive types of adjacent polysilicon bodies in the formed polysilicon group are different. In a specific implementation, the number of polysilicon bodies in the ESD protection structure can be selected according to actual needs, specifically to meet the ESD resistance requirements of the power device.

[0060] The specific principle of the ESD protection structure forming two current paths is: when an ESD pulse comes and no avalanche breakdown occurs in the N-type body region 2 and the P-type body region 3, the ESD current pulse can discharge the forward ESD current through the diode group formed by the N-type first polysilicon body 41-P-type first polysilicon body 51-N-type second polysilicon body 42-N-type third polysilicon body 43-P-type second polysilicon body 52-N-type fourth polysilicon body 44, and the diode group formed by the N-type first polysilicon body 41-P-type first polysilicon body 51-N-type body region 2-P-type body region 3-N-type third polysilicon body 43-P-type second polysilicon body 52-N-type fourth polysilicon body 44.

[0061] When the ESD pulse is higher than the avalanche breakdown voltage of the N-type body region 2 and the P-type body region 3, an avalanche breakdown occurs in the N-type body region 2 and the P-type body region 3, and the breakdown current generates a large number of electron-hole pairs. The generated electrons and holes form a voltage drop on the well resistance of the N-type body region 2 and the P-type body region 3. When the voltage drop exceeds a certain value, the PNP transistor formed by the P-type first polysilicon body 51-N-type body region 2-P-type body region 3 and the NPN transistor formed by the N-type body region 2-P-type body region 3-N-type third polysilicon body 43 are turned on at the same time and form positive feedback. Under the gain of the positive feedback effect, a strong conductivity modulation effect occurs in the N-type body region 2 and the P-type body region 3, presenting a negative differential resistance state and entering a low resistance state, which is equivalent to forming an SCR (Silicon Diode) in the N-type body region 2 and the P-type body region 3. The diode group formed by the first N-type polysilicon body 41-the first P-type polysilicon body 51-the second N-type polysilicon body 42-the third N-type polysilicon body 43-the second P-type polysilicon body 52-the fourth N-type polysilicon body 44 discharges the ESD current together, thereby increasing the forward and reverse ESD current discharge capabilities of the device and enhancing the robustness of the ESD protection structure. At the same time, since the first polysilicon group corresponds to the N-type body region 1 and the second polysilicon group corresponds to the P-type body region 2, the robustness of the ESD protection structure can be improved while keeping the chip area occupied by the ESD protection structure unchanged.

[0062] Furthermore, the active region includes a plurality of planar cells distributed in parallel;

[0063] The planar cell includes a planar gate unit prepared on a substrate 1, wherein the planar gate unit includes a planar gate oxide layer 9 and a planar gate polysilicon group, and the planar gate polysilicon group is insulated and isolated from the substrate 1 by the planar gate oxide layer 9;

[0064] The planar gate polysilicon group is in ohmic contact with a second electrode metal 15 for forming a second electrode on the substrate 1 , and the planar gate polysilicon group includes a plurality of alternately arranged N-type planar gate polysilicon bodies 16 and P-type planar gate polysilicon bodies 17 .

[0065] Specifically, a P-type base region 6 is disposed on both sides of the planar gate unit, and an N-type source region 8 and a P-type source region 7 are disposed in the P-type base region 6. The P-type base region 6 and the N-type source region 8 overlap with the planar gate unit, and the N-type source region 8 in the same P-type base region 6 contacts the P-type source region 7, and the N-type source region 8 and the P-type source region 7 are in ohmic contact with the first electrode metal 13 used to form the first electrode. The P-type base region 6 and the N-type source region 8 overlap with the planar gate unit, specifically referring to the projection of the P-type base region 6 and the N-type source region 8 onto the planar gate unit, and the projection of the P-type base region 6 and the N-type source region 8 overlaps with the planar gate unit.

[0066] In one embodiment of the present invention, the planar gate polysilicon group includes four N-type planar gate polysilicon bodies 16 and three P-type planar gate polysilicon bodies 17, and the N-type planar gate polysilicon bodies 16 and the P-type planar gate polysilicon bodies 17 are alternately arranged along a first direction, and the first direction is perpendicular to the thickness direction of the substrate 1; the three P-type planar gate polysilicon bodies 17 are respectively located between two adjacent N-type planar gate polysilicon bodies 16, and any P-type planar gate polysilicon body 17 is in contact with the N-type planar gate polysilicon bodies 16 adjacent to both sides. The planar gate polysilicon group is in ohmic contact with the second electrode metal 15 for forming the second electrode above the substrate 1, that is, at least one N-type planar gate polysilicon body 16 or P-type planar gate polysilicon body 17 in the planar gate polysilicon group is in ohmic contact with the second electrode metal 15 for forming the second electrode above the substrate 1. In specific implementation, the number of N-type planar gate polysilicon bodies 16 and P-type planar gate polysilicon bodies 17 in the planar gate polysilicon group can be selected according to actual needs.

[0067] Generally, the doping concentration of the N-type source region 8 is greater than the doping concentration of the substrate 1, and the doping concentration of the P-type source region 7 is greater than the doping concentration of the P-type base region 6. In this embodiment, the junction depth of the P-type source region 7 is greater than the junction depth of the N-type source region 8. At the same time, in order to facilitate process preparation, the P-type base region 6 located at the edge of the active region extends from the active region to the terminal protection area, and the N-type body region 2 and the P-type body region 3 are both arranged in the P-type base region 6 extending to the terminal protection area, and the doping concentration of the P-type body region 3 is greater than the doping concentration of the P-type base region 6.

[0068] For ease of explanation, Figure 1 The P-type base region 6 and the N-type source region 8 on the left side of the planar gate unit are used as the first P-type base region and the first N-type source region, and the P-type base region 6 and the N-type source region 8 on the right side of the planar gate unit are used as the second P-type base region and the second N-type source region. In this embodiment, the first-order N-type planar gate polysilicon body 16 overlaps with the first N-type source region from left to right in the planar gate polysilicon group, the first-order P-type planar gate polysilicon body 17 overlaps with the first P-type base region, the third-order N-type planar gate polysilicon body 16 and the P-type planar gate polysilicon body 17 overlap with the second P-type base region, and the fourth-order N-type planar gate polysilicon body 16 overlaps with the second N-type source region. The definition of the overlap is the same as the definition of the overlap between the N-type source region 8 and the planar gate unit, which will not be repeated here.

[0069] There is a barrier region at the junction of the PN junction formed in the planar gate polysilicon group. The voltage change at both ends of the PN junction causes the change in the amount of charge accumulated in this region, thereby showing the capacitance effect. Taking a MOSFET type device as an example, the planar gate polysilicon group formed by alternating N-type planar gate polysilicon bodies 16 and P-type planar gate polysilicon bodies 17 can improve the original gate-drain capacitance of the power device into multiple capacitors connected in parallel and then in series, greatly reducing the size of the gate-drain capacitance to reduce the input capacitance and reduce the switching loss of the power device.

[0070] Specifically, Figure 2 and Figure 3 The schematic diagram and the schematic diagram of the circuit of the gate-drain capacitor in the present embodiment are shown respectively. As shown in the figure, the gate-drain capacitor includes a diode junction capacitor and a gate capacitor connected in series. The diode junction capacitor includes a first diode junction capacitor C1, a second diode junction capacitor C2, a third diode junction capacitor C3, a fourth diode junction capacitor C4, a fifth diode junction capacitor C5 and a sixth diode junction capacitor C6 connected in parallel. The gate capacitor includes a capacitor Cgd1 formed by the first-order P-type planar gate polysilicon body 17 and the first P-type base region in the planar gate polysilicon group from left to right, with the planar gate oxide layer 9 as the medium, a capacitor Cgd2 formed by the second-order N-type planar gate polysilicon body 16 and the N-type substrate 1, a capacitor Cgd3 formed by the second-order P-type planar gate polysilicon body 17 and the N-type substrate 1, a capacitor Cgd4 formed by the third-order N-type planar gate polysilicon body 16 and the second P-type base region, and a capacitor Cgd5 formed by the third-order P-type planar gate polysilicon body 17 and the second P-type base region. The gate capacitor also includes a junction capacitor Cgd6 between the first P-type base region and the N-type substrate 1, and a junction capacitor Cgd7 between the second P-type base region and the N-type substrate 1. Capacitor Cgd4 is connected in parallel with capacitor Cgd5 and then connected in series with capacitor Cgd7, and connected in parallel with capacitor Cgd2 and capacitor Cgd3. Capacitor Cgd1 is connected in series with capacitor Cgd6 and then connected in parallel with capacitor Cgd2 and capacitor Cgd3. The overall gate-drain capacitance is smaller than the original gate-drain capacitance, thereby reducing the input capacitance of the device.

[0071] For the above-mentioned power device with integrated high robustness ESD protection structure, the present invention provides a method for preparing the power device, and the method for preparing the power device comprises:

[0072] An N-type substrate 1 is provided, and at least one ESD protection structure is prepared in a terminal protection zone of the substrate 1; the ESD protection structure is in ohmic contact with a first electrode metal 13 for forming a first electrode and a second electrode metal 15 for forming a second electrode above the substrate 1, so as to connect the ESD protection structure in series between the first electrode and the second electrode; two current discharge paths are formed based on the ESD protection structure for discharging ESD current.

[0073] Specifically, Figures 4 to 7 Taking a MOSFET device as an example, an embodiment of the process steps of the above-mentioned integrated high-robustness ESD protection structure power device is shown. The process steps are specifically described below using an ESD protection structure and a cell as examples:

[0074] like Figure 4 As shown, an N-type substrate 1 is provided, an active region located in the center region of the substrate 1 and a terminal protection region surrounding the active region are prepared, an oxide layer is grown on the front side of the substrate 1 and an injection window is obtained by wet etching in the terminal protection region, and N-type doping ions and P-type doping ions are respectively injected into the terminal protection region of the substrate 1 using the injection window, and high-temperature annealing is performed to prepare an N-type body region 2 and a P-type body region 3. In specific implementation, the process conditions of the ion implantation and high-temperature annealing can be selected according to actual needs to meet the preparation requirements of the N-type body region 2 and the P-type body region 3. An oxide layer is grown on the front side of the substrate 1 to prepare a planar gate oxide layer 9 and an isolation oxide layer 10, N-type polysilicon is deposited on the substrate 1 on which the planar gate oxide layer 9 and the isolation oxide layer 10 are prepared, and the deposited polysilicon is photoetched to prepare an N-type planar gate polysilicon body 16 in the planar gate polysilicon group, an N-type first polysilicon body 41 and an N-type second polysilicon body 42 in the first polysilicon group, and an N-type fourth polysilicon 44 in the second polysilicon group. At the same time, a first filling groove is prepared in the N-type body region 2, and a second filling groove is prepared in the P-type body region 3.

[0075] like Figure 5 As shown, polysilicon is deposited on the front side of the substrate 1, in the first filling groove and the second filling groove, and etched using a photomask, and N-type ions or P-type ions are doped accordingly to prepare a P-type planar gate polysilicon body 17 in the planar gate polysilicon group, a P-type first polysilicon body 51 partially filled in the first filling groove in the first polysilicon group, a P-type second polysilicon body 52 in the second polysilicon group, and an N-type third polysilicon body 43 partially filled in the second filling groove. P-type doping ions are implanted in the active area and the terminal protection area, and high-temperature annealing is performed to prepare a P-type base region 6. In specific implementation, the process conditions of the P-type ion implantation and high-temperature annealing can be selected according to actual needs to meet the preparation requirements of the P-type base region 6.

[0076] like Figure 6As shown, a layer of silicon nitride with a thickness of 1200 angstroms is deposited on the front of the substrate 1 as a protective layer 11 for ion implantation, and the protective layer covers the planar gate polysilicon group, the first polysilicon group and the second polysilicon group. An implantation window is etched on the front of the substrate 1 and N-type doping ions are implanted. The N-type source region 8 is prepared by annealing at 950 degrees. An insulating dielectric is deposited on the front of the substrate 1 to form an insulating dielectric layer 12, and a first contact hole 18, a second contact hole 19, a third contact hole 20, a fourth contact hole 21 and a fifth contact hole 22 are etched on the insulating dielectric layer 12, wherein the first contact hole 18 is located above the P-type base region 6 in the active region, the second contact hole 19 is located above the N-type first polysilicon body 41, the third contact hole 20 is located above the N-type second polysilicon body 42, the fourth contact hole 21 is located above the N-type third polysilicon body 43, and the fifth contact hole 22 is located above the fourth N-type polysilicon body 44. P-type doping ions are implanted into the P-type base region 6 in the active region through the first contact hole 18 , and high-temperature annealing is performed to form a P-type source region 7 . The P-type source region 7 is in contact with the N-type source region 8 .

[0077] like Figure 7 As shown, metal is deposited and patterned on the insulating dielectric layer 12 to form a first electrode metal 13, a connection metal 14 and a second electrode metal 15. The first electrode metal 13 is filled in the first contact hole 18 and the second contact hole 19 at the same time, and the P-type source region 7 and the N-type source region 8 are in ohmic contact with the first electrode metal 13 through the metal filled in the first contact hole 18. The N-type first polysilicon body 41 is in ohmic contact with the first electrode metal 13 through the metal filled in the second contact hole 19. The connection metal 14 is filled in the third contact hole 20 and the fourth contact hole 21 at the same time, the N-type second polysilicon body 42 is in ohmic contact with the connection metal 14 through the metal filled in the third contact hole 20, and the N-type third polysilicon body 43 is in ohmic contact with the connection metal 14 through the metal filled in the fourth contact hole 21. The second electrode metal 15 is filled in the fifth contact hole 22 at the same time, and the N-type fourth polysilicon body 44 is in ohmic contact with the second electrode metal 15 through the metal filled in the fifth contact hole 22. The planar gate polysilicon group also makes ohmic contact with the second electrode metal 15 (not shown in the figure), and the manner in which the planar gate polysilicon group makes ohmic contact with the second electrode metal 15 can be the same as that in the prior art.

[0078] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0079] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A power device with integrated high robustness ESD protection structure, characterized in that: It comprises a first conductive type substrate, an active area prepared in the central area of ​​the substrate, a terminal protection area surrounding the active area, and at least one ESD protection structure prepared in the terminal protection area, wherein: The ESD protection structure is in ohmic contact with a first electrode metal for forming a first electrode and a second electrode metal for forming a second electrode above the substrate, so as to connect the ESD protection structure in series between the first electrode and the second electrode; Two current discharge paths are formed based on the ESD protection structure to discharge the ESD current.

2. The power device with integrated high robustness ESD protection structure according to claim 1, characterized in that: The ESD protection structure includes a first polysilicon group, a second polysilicon group, an N-type body region and a P-type body region, wherein: The N-type body region and the P-type body region are in contact and are both located in the substrate corresponding to the terminal protection area; The first polysilicon group at least includes an N-type first polysilicon body, an N-type second polysilicon body, and a P-type first polysilicon body, wherein the P-type first polysilicon body is located between the N-type first polysilicon body and the N-type second polysilicon body, and contacts the N-type first polysilicon body and the N-type second polysilicon body; The second polysilicon group at least includes an N-type third polysilicon body, an N-type fourth polysilicon body, and a P-type second polysilicon body, wherein the P-type second polysilicon body is located between the N-type third polysilicon body and the N-type fourth polysilicon body, and contacts the N-type third polysilicon body and the N-type fourth polysilicon body; The P-type first polysilicon body is in contact with the N-type body region, the N-type third polysilicon body is in contact with the P-type body region, and the N-type first polysilicon body, the N-type second polysilicon body, the N-type fourth polysilicon body and the P-type second polysilicon body are isolated from the N-type body region and the P-type body region by an isolation oxide layer; The N-type first polysilicon body is in ohmic contact with the first electrode metal, the N-type second polysilicon body is electrically connected to the N-type third polysilicon body, and the N-type fourth polysilicon body is in ohmic contact with the second electrode metal.

3. The power device with integrated high robustness ESD protection structure according to claim 2, characterized in that: The N-type first polysilicon body, the P-type first polysilicon body and the N-type second polysilicon body are arranged in sequence along a first direction above the substrate and correspond to the N-type body region, wherein: The P-type first polysilicon body extends from the substrate to the N-type body region, and the extension depth of the P-type first polysilicon body in the N-type body region is not greater than the junction depth of the N-type body region. The first direction is perpendicular to the substrate thickness direction.

4. The power device with integrated high robustness ESD protection structure according to claim 2, characterized in that: The N-type third polysilicon body, the P-type second polysilicon body and the N-type fourth polysilicon body are arranged in sequence along the first direction above the substrate and correspond to the P-type body region, wherein: The N-type third polysilicon body extends from the substrate to the P-type body region, and the extension depth of the N-type third polysilicon body in the P-type body region is not greater than the junction depth of the P-type body region. The first direction is perpendicular to the substrate thickness direction.

5. The power device with integrated high robustness ESD protection structure according to claim 1, characterized in that: The active region includes a plurality of planar cells distributed in parallel; The planar cell comprises a planar gate unit prepared on a substrate, wherein the planar gate unit comprises a planar gate oxide layer and a planar gate polysilicon group, and the planar gate polysilicon group is insulated and isolated from the substrate by the planar gate oxide layer; The planar gate polysilicon group is in ohmic contact with a second electrode metal for forming a second electrode above the substrate, and the planar gate polysilicon group includes a plurality of alternately arranged N-type planar gate polysilicon bodies and P-type planar gate polysilicon bodies.

6. The power device with integrated high robustness ESD protection structure according to claim 5, characterized in that: The planar gate polysilicon group includes four N-type planar gate polysilicon bodies and three P-type planar gate polysilicon bodies, and the N-type planar gate polysilicon bodies and the P-type planar gate polysilicon bodies are alternately arranged along a first direction, and the first direction is perpendicular to the substrate thickness direction; The three P-type planar gate polysilicon bodies are respectively located between two adjacent N-type planar gate polysilicon bodies, and any P-type planar gate polysilicon body is in contact with the N-type planar gate polysilicon bodies adjacent to the two sides.

7. The power device with integrated high robustness ESD protection structure according to claim 5, characterized in that: A second conductive type base region is disposed on both sides of the planar gate unit, and a first conductive type source region and a second conductive type source region are disposed in the second conductive type base region; The second conductive type base region and the first conductive type source region both overlap with the planar gate unit, and the first conductive type source region in the same second conductive type base region contacts the second conductive type source region; The first conductive type source region and the second conductive type source region are both in ohmic contact with a first electrode metal used to form a first electrode.

8. The power device with integrated high robustness ESD protection structure according to claim 7, characterized in that: The doping concentration of the first conductive type source region is greater than the doping concentration of the substrate, and the doping concentration of the second conductive type source region is greater than the doping concentration of the second conductive type base region.

9. The power device with integrated high robustness ESD protection structure according to claim 7, characterized in that: The second conductive type base region located at the edge of the active region extends from the active region to the terminal protection region; The N-type body region and the P-type body region are both arranged in the second conductive type base region extending into the terminal protection.

10. A method for preparing a power device with an integrated high-robustness ESD protection structure, characterized in that: Used to prepare the power device according to any one of claims 1 to 9, the method for preparing the power device comprising: Providing a substrate of a first conductivity type, and preparing at least one ESD protection structure in a terminal protection area of ​​the substrate; The ESD protection structure is in ohmic contact with a first electrode metal for forming a first electrode and a second electrode metal for forming a second electrode above the substrate, so as to connect the ESD protection structure in series between the first electrode and the second electrode; Two current discharge paths are formed based on the ESD protection structure to discharge the ESD current.

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