Integrated chip and forming method thereof

Abstract

A waveguide light detector includes a plate on a substrate, first and second contact portions protruding upwardly from the plate, and a ridge protruding upwardly from the plate between the first and second contact portions. The first semiconductor layer is on the substrate and includes a first doped region in the first contact portion, a second doped region in the plate between the first contact portion and the ridge, third and sixth doped regions in the ridge, a fourth doped region in the second contact portion, a fifth doped region in the plate between the second contact portion and the ridge, the first intrinsic region is arranged between the sixth doped region and the third doped region; and the second intrinsic region is arranged between the sixth doped region and the fifth doped region. A second semiconductor layer is on the first intrinsic region and between the sixth and third doped regions.

Description

Technical Field

[0001] The invention relates to an integrated chip and a forming method thereof. Background Art

[0002] Optical waveguides are often used as components in integrated optical circuits. Optical waveguides are used to confine and guide light from a first point on an integrated chip (IC) to a second point on the IC with minimal attenuation. Many modern optical waveguides are formed using semiconductors. Semiconductor waveguides can include optical converters or optical couplers for optically coupling optical fibers to semiconductor waveguides. Many integrated optical circuits include light detectors, such as avalanche photodiodes (APDs). Summary of the invention

[0003] The present application provides an integrated chip including a substrate and a waveguide light detector on the substrate. The waveguide light detector includes a plate portion extending laterally on the substrate, a first contact portion protruding upward from the plate portion, a second contact portion protruding upward from the plate portion and laterally spaced apart from the first contact portion, and a ridge portion protruding upward from the plate portion between the first contact portion and the second contact portion. A first semiconductor layer including a first semiconductor on the substrate. The first semiconductor layer has a first sidewall, a second sidewall, a first top surface, and a second top surface that partially define a ridge portion of the waveguide light detector. The first semiconductor layer includes a first doping region having a first doping type and in the first contact portion, a second doping region having the first doping type in the plate portion laterally between the first contact portion and the ridge portion, a third doping region having the first doping type in the ridge portion, a fourth doping region having a second doping type different from the first doping type in the second contact portion, a fifth doping region having the second doping type in the plate portion laterally between the second contact portion and the ridge portion, a sixth doping region in the ridge portion, and a first intrinsic region laterally between the sixth doping region and the third doping region. The second semiconductor layer is above the first intrinsic region and laterally between the sixth doped region and the third doped region. The second semiconductor layer includes a second semiconductor different from the first semiconductor. The second semiconductor layer has a first sidewall, a second sidewall, and a top surface, further defining a ridge portion of the waveguide light detector. The sixth doped region has a first doping type. The first semiconductor layer further includes a second intrinsic region laterally between the sixth doped region and the fifth doped region.

[0004] The present application provides an integrated chip including a substrate, a first semiconductor layer above the substrate, and a second semiconductor layer above the substrate. The first semiconductor layer includes a first semiconductor. The second semiconductor layer includes a second semiconductor different from the first semiconductor. The first semiconductor layer is between the second semiconductor layer and the substrate. The first semiconductor layer includes a first intrinsic region, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a sixth doped region, and a second intrinsic region. The first intrinsic region is located directly below the second semiconductor layer. The first doped region is laterally spaced apart from the first intrinsic region and the second semiconductor layer in a first direction. The first doped region has a first doping type and a first doping concentration. The second doped region is laterally between the first doped region and the first intrinsic region. The second doped region has a first doping type and a second doping concentration less than the first doping concentration. The third doped region is laterally between the second doped region and the first intrinsic region. The third doped region is next to the first intrinsic region, directly below the second semiconductor layer, and extends upward along the first sidewall of the second semiconductor layer. The third doped region has a first doping type and a third doping concentration less than the second doping concentration. The fourth doped region is laterally spaced apart from the first intrinsic region and the second semiconductor layer in a second direction opposite to the first direction. The fourth doping region has a second doping type different from the first doping type and a fourth doping concentration. The fifth doping region is laterally between the fourth doping region and the first intrinsic region. The fifth doping region has a second doping type and a fifth doping concentration less than the fourth doping concentration. The sixth doping region is laterally between the fifth doping region and the first intrinsic region. The sixth doping region is next to the first intrinsic region, directly below the second semiconductor layer, and extends upward along the second side wall of the second semiconductor layer. The sixth doping region has the first doping type and a sixth doping concentration less than the second doping concentration. The second intrinsic region is laterally between the sixth doping region and the fifth doping region.

[0005] The present application provides a method for forming an integrated chip. A first semiconductor layer is formed on a substrate. The first semiconductor layer includes a first semiconductor. The first semiconductor layer is etched to form a waveguide, the waveguide including a ridge portion, a first contact portion and a second contact portion spaced laterally above a plate portion. The ridge portion is defined by a first sidewall, a second sidewall and a top surface of the first semiconductor layer. A first doping region is formed in the first semiconductor layer and is spaced laterally from the ridge portion in a first direction. The first doping region doping type has a first doping type and a first doping concentration. A second doping region is laterally formed in the first semiconductor layer between the ridge portion and the first doping region. The second doping region has a first doping type and a second doping concentration less than the first doping concentration. A third doping region and a sixth doping region are formed in the first semiconductor layer at the ridge portion. The first intrinsic region in the first semiconductor layer is between the third doping region and the sixth doping region. The third doping region and the sixth doping region have a first doping type and a third doping concentration less than the second doping concentration. A fourth doping region is formed in the first semiconductor layer and is spaced laterally from the ridge portion in a second direction opposite to the first direction. The fourth doping region has a second doping type different from the first doping type and a fourth doping concentration. A fifth doping region is formed in the first semiconductor layer and laterally between the fourth doping region and the ridge portion. The fifth doping region has a second doping type and a fifth doping concentration that is less than the fourth doping concentration. The second intrinsic region in the first semiconductor layer is between the fifth doping region and the sixth doping region. The ridge portion is etched between the third doping region and the sixth doping region to form a third recess in the ridge portion. The third recess is defined by a third sidewall, a fourth sidewall, and an upper surface of the first semiconductor layer. The third doping region extends along the third sidewall and the upper surface of the first semiconductor layer. The sixth doping region extends along the fourth sidewall and the upper surface of the first semiconductor layer. The first intrinsic region extends along the upper surface of the first semiconductor layer. The second semiconductor layer is formed in the third recess, on the upper surface of the first semiconductor layer, and between the third sidewall and the fourth sidewall of the first semiconductor layer. The second semiconductor layer includes a second semiconductor that is different from the first semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated chips including waveguide light detectors are shown.

[0008] Figure 2 Shows Figure 1 Top view of some embodiments of a waveguide light detector.

[0009] Figure 3Shows Figure 1 A three-dimensional view of some embodiments of an integrated chip including a waveguide and a waveguide light detector.

[0010] Figure 4-6 A top view of some embodiments of an integrated chip is shown, in which waveguide light detectors are arranged along various waveguides.

[0011] Figure 7-18 Shows Figure 1 Cross-sectional views of various embodiments of waveguide light detectors.

[0012] Figure 19-32 Cross-sectional views of some embodiments of methods for forming an integrated chip including a waveguide light detector are shown.

[0013] Fig.33 A flow chart illustrating some embodiments of a method for forming an integrated chip including a waveguide light detector. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of a first feature on or above a second feature may include an embodiment in which the first and second features are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] The integrated chip includes a semiconductor waveguide and a waveguide photodetector (e.g., an avalanche photodiode (APD) or the like) disposed along the waveguide. The waveguide photodetector is configured to convert an optical signal (e.g., optical radiation) propagating through the waveguide into an electrical signal (e.g., an electric current). The waveguide photodetector is formed of a first semiconductor layer and a second semiconductor layer overlying the first semiconductor layer. The second semiconductor layer forms an absorption region of the waveguide photodetector. The absorption region is configured to absorb photons propagating through the waveguide. The first semiconductor layer includes an intrinsic region directly below the second semiconductor layer, a first doped region having a first doping type (e.g., p-type doping) on ​​a first side of the intrinsic region, and a second doped region having a second doping type (e.g., n-type doping) different from the first doping type on a second side of the intrinsic region.

[0017] A challenge with waveguide photodetectors is that the responsivity (e.g., the ratio of photocurrent generated per incident optical power) of a waveguide photodetector may be low. Therefore, a signal propagating through a waveguide may require increasing the optical power of the waveguide photodetector to generate a large amount of photocurrent (e.g., greater than 100 microamps, greater than 200 microamps, or some other suitable value).

[0018] In various embodiments of the present disclosure, the waveguide light detector further includes a charge region and an intrinsic multiplication region to improve the responsivity of the waveguide light detector. For example, the charge region located at the second side of the intrinsic region and between the intrinsic region and the second doped region has a first doping type (e.g., p-type). In addition, the intrinsic multiplication region is located between the charge region and the second doped region.

[0019] By including a charge region and an intrinsic multiplication region in a waveguide photodetector, carrier multiplication in the photodetector can be increased. By increasing carrier multiplication, the amount of photocurrent generated by the waveguide photodetector in response to an incident light signal can be increased without increasing the optical power of the incident light signal. Thus, the optical power of the light signal transmitted through the optical waveguide and detected by the waveguide photodetector can be reduced.

[0020] Figure 1 A cross-sectional view 100 of some embodiments of an integrated chip including a waveguide light detector 101 is shown. Figure 2 Shows Figure 1 200 of some embodiments of waveguide light detector 101. In some embodiments, for example, Figure 2 The section line A-A' is obtained Figure 1 A cross-sectional view 100 is provided.

[0021] The first semiconductor layer 104 is on the substrate 102. The second semiconductor layer 106 is between the first sidewall 104a and the second sidewall 104b of the first semiconductor layer 104 and on the first upper surface 104c of the first semiconductor layer 104. The first semiconductor layer 104 includes a first semiconductor (e.g., silicon or some other suitable semiconductor), and the second semiconductor layer 106 includes a second semiconductor different from the first semiconductor (e.g., germanium or some other suitable semiconductor). The first semiconductor layer 104 includes a first intrinsic region 108, a first doped region 110, a second doped region 112, a third doped region 114, a fourth doped region 116, a fifth doped region 118, a sixth doped region 120, and a second intrinsic region 122. The first intrinsic region 108, the first doped region 110, the second doped region 112, the third doped region 114, the fourth doped region 116, the fifth doped region 118, the sixth doped region 120, the second intrinsic region 122, and the second semiconductor layer 106 form a waveguide light detector 101.

[0022] The first intrinsic region 108 is directly below the second semiconductor layer 106. The first doped region 110 is laterally spaced apart from the first intrinsic region 108 and the second semiconductor layer 106 in the first direction 103. In some embodiments, the first doped region 110 forms an anode of the waveguide light detector 101. The first doped region 110 has a first doping type (e.g., p-type) and a first doping concentration. The second doped region 112 is laterally between the first doped region 110 and the first intrinsic region 108. The second doped region 112 has a first doping type and a second doping concentration less than the first doping concentration. The third doped region 114 is laterally between the second doped region 112 and the first intrinsic region 108. The third doped region 114 is directly below and beside the second semiconductor layer 106. For example, the third doped region 114 extends along the bottom surface 106a of the second semiconductor layer 106 and the first sidewall 106b of the second semiconductor layer 106. The third doped region 114 has the first doping type and a third doping concentration less than the second doping concentration.

[0023] The fourth doped region 116 is laterally spaced apart from the first intrinsic region 108 and the second semiconductor layer 106 in a second direction 105 opposite to the first direction 103. In some embodiments, the fourth doped region 116 forms a cathode of the waveguide light detector 101. The fourth doped region 116 has a second doping type (e.g., n-type) different from the first doping type and a fourth doping concentration. The fifth doped region 118 is laterally between the fourth doped region 116 and the first intrinsic region 108. The fifth doped region 118 has a second doping type and a fifth doping concentration less than the fourth doping concentration. The sixth doped region 120 (e.g., a charge region of the waveguide light detector 101) is laterally between the fifth doped region 118 and the first intrinsic region 108. The sixth doped region 120 is directly below and beside the second semiconductor layer 106. For example, the sixth doped region 120 extends along the bottom surface 106a of the second semiconductor layer 106 and the second sidewall 106c of the second semiconductor layer 106. The sixth doping region 120 has the first doping type and a sixth doping concentration that is less than the second doping concentration. A second intrinsic region 122 (eg, a multiplication region of the waveguide light detector 101 ) is laterally between the sixth doping region 120 and the fifth doping region 118 .

[0024] The waveguide light detector 101 includes a plate portion 124, a ridge portion 126, and a first contact portion 128 and a second contact portion 130. The plate portion 124 of the waveguide light detector 101 is defined by the bottom surface 104d, the second upper surface 104e, and the third upper surface 104f of the first semiconductor layer 104. The ridge portion 126 of the waveguide light detector 101 is defined by the third sidewall 104g of the first semiconductor layer 104, the fourth sidewall 104h of the first semiconductor layer 104, the first top surface 104i of the first semiconductor layer 104, the second top surface 104j of the first semiconductor layer 104, the upper portion of the first sidewall 106b of the second semiconductor layer 106, the upper portion of the second sidewall 106c of the second semiconductor layer 106, and the top surface 106d of the second semiconductor layer 106. The first contact portion 128 is defined by the third top surface 104k and the fifth sidewall 104m of the first semiconductor layer 104. The second contact portion 130 is defined by the fourth top surface 104 n and the sixth sidewall 104 p of the first semiconductor layer 104 .

[0025] The second semiconductor layer 106 forms an absorption region of the waveguide photodetector 101. Photons propagating along the ridge portion 126 can be absorbed by the second semiconductor layer 106. When photons are absorbed in the waveguide photodetector 101, electron-hole pairs are formed. The electric field in the waveguide photodetector 101 accelerates these charge carriers toward their corresponding electrodes (e.g., anode and cathode), thereby generating a photocurrent. By including the sixth doped region 120 (e.g., charge region) and the second intrinsic region 122 (e.g., multiplication region), the electric field in the waveguide photodetector 101 can be increased. More specifically, a high electric field is generated at the second intrinsic region 122. This high electric field further accelerates the charge carriers. These highly accelerated charge carriers can have high enough energy to excite additional charge carriers, thereby increasing the photocurrent. Therefore, by increasing the electric field in the waveguide light detector 101 through the sixth doped region 120 (e.g., charge region) and the second intrinsic region 122 (e.g., multiplication region), the amount of photocurrent generated by the waveguide light detector 101 can be increased, thereby increasing the responsivity of the waveguide light detector 101.

[0026] In some embodiments, the second intrinsic region 122 is adjacent to the ridge portion 126. For example, the sixth doped region 120 and the second intrinsic region 122 intersect at an interface directly below the sidewall 104h of the first semiconductor layer 104.

[0027] The first upper surface 104c of the first semiconductor layer 104 and the bottom surface 106a of the second semiconductor layer 106 are disposed at a first height on the substrate 102. The second upper surface 104e and the third upper surface 104f of the first semiconductor layer 104 are disposed at a second height greater than the first height on the substrate 102. The first top surface 104i, the second top surface 104j, the third top surface 104k, and the fourth top surface 104n are disposed at a third height greater than the second height on the substrate 102. The top surface 106d of the second semiconductor layer 106 is disposed at a fourth height greater than the third height on the substrate 102.

[0028] The dielectric cap 132 is on the ridge portion 126 of the waveguide light detector 101. The dielectric cap 132 covers the first top surface 104i of the first semiconductor layer 104, the second top surface 104j of the first semiconductor layer 104, and the top surface 106d of the second semiconductor layer 106. The dielectric cap 132 protects the second semiconductor layer 106. In some embodiments, the dielectric cap 132 includes silicon nitride or some other suitable dielectric.

[0029] A dielectric layer 134 is disposed on the waveguide light detector 101 and the dielectric cap 132. The dielectric layer 134 includes a different dielectric than the dielectric cap 132. For example, in some embodiments, the dielectric layer 134 includes silicon dioxide or some other suitable dielectric. A first contact 136 extends from a first metal line 138 through the dielectric layer 134 to the first contact portion 128 (and the first doped region 110 in the first contact portion 128) of the waveguide light detector 101. A second contact 140 extends from a second metal line 142 through the dielectric layer 134 to the second contact portion 130 (and the fourth doped region 116 in the second contact portion 130) of the waveguide light detector 101.

[0030] In some embodiments, the first doping type is p-type and the second doping type is n-type. In some other embodiments, the first doping type is n-type and the second doping type is p-type. In some embodiments, the dopant concentration of the first doping region 110 and the fourth doping region 116 ranges from 10 19 cm -3 Up to 10 22 cm -3 , 10 20 cm -3 Up to 10 21 cm -3 Or some other suitable range. In some embodiments, the dopant concentration of the second doping region 112 and the fifth doping region 118 ranges from 10 18 cm -3 Up to 10 20 cm -3 , 10 19 cm -3 Up to 10 20 cm -3 or some other suitable range. In some embodiments, the dopant concentrations of the third doping region 114 and the sixth doping region 120 are substantially equal. In some embodiments, the dopant concentrations of the third doping region 114 and the sixth doping region 120 range from 10 16 cm -3 Up to 10 19 cm -3 , 10 16 cm -3 Up to 10 18 cm -3 or some other appropriate range.

[0031] In some embodiments, the height of the ridge portion 126 ranges from about 50 to 500 nanometers, 70-200 nanometers, or some other suitable range. In some embodiments, the width of the ridge portion 126 ranges from about 100 to 700 nanometers, 200 to 500 nanometers, or some other suitable range. In some embodiments, the width of the second intrinsic region 122 ranges from about 5 to 200 nanometers, 10 to 100 nanometers, or some other suitable range. In some embodiments, the width of the fifth doped region 118 and the second doped region 112 ranges from about 5 to 200 nanometers, 10 to 100 nanometers, or some other suitable range.

[0032] In some embodiments, substrate 102 is or includes a semiconductor (e.g., silicon or the like), a semiconductor-on-insulator (SOI) substrate, a dielectric layer, a buried dielectric layer on a base semiconductor layer, or some other suitable substrate. For clarity of the underlying layers, Figure 2 The dielectric layer 134 is not shown in the top view 200 of FIG.

[0033] Figure 3 The waveguide 302 and Figure 1 A three-dimensional view 300 of some embodiments of an integrated chip of the waveguide light detector 101 is shown.

[0034] The photons travel along waveguide 302 (e.g., as shown by line 304) to waveguide light detector 101 where they are absorbed and converted into photocurrent. In some embodiments, waveguide 302 is formed of first semiconductor layer 104. Waveguide light detector 101 is formed of first semiconductor layer 104 and second semiconductor layer 106. First semiconductor layer 104 forms ridge portion 126 and slab portion 124 in waveguide 302. Second semiconductor layer 106 further forms a ridge portion in waveguide light detector 101.

[0035] The dielectric cap 132 is shown as semi-transparent and is not shown in the illustration to clearly illustrate the underlying layers. Figure 3 Dielectric layer 134 , contacts 136 , 140 , and metal lines 138 , 142 are not shown in three-dimensional view 300 .

[0036] Figure 4-6 Top views 400-600 of some embodiments of integrated chips are shown, wherein waveguide light detectors 101 are disposed along various waveguides.

[0037] In some embodiments (e.g., Figure 4 400), the waveguide light detector 101 is arranged along the linear waveguide 402. In some embodiments (e.g., as Figure 5500), the waveguide light detector 101 has a dual-port configuration, wherein two waveguides 502, 504 are coupled to the waveguide light detector 101 at opposite ends of the waveguide light detector 101. In some embodiments (e.g., Figure 6 As shown in the top view 600 of the device, the waveguide light detector 101 is integrated with a micro-ring resonator / modulator 602.

[0038] Figure 7-14 Shows Figure 1 Cross-sectional views 700 - 1400 of various embodiments of the waveguide light detector 101 are shown.

[0039] In some embodiments (e.g., Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , the second intrinsic region 122 is laterally spaced apart from the ridge portion 126 of the waveguide light detector 101 (e.g., spaced apart from the sidewall 104h of the first semiconductor layer 104) by a first non-zero distance 706. For example, the sixth doped region 120 and the second intrinsic region 122 intersect at an interface, which is laterally spaced apart from the sidewall 104h of the first semiconductor layer 104. In some embodiments, the substrate 102 includes a base semiconductor layer 702 and an insulator layer 704 (e.g., a buried oxide (BOX) layer) on the base semiconductor layer 702.

[0040] In some embodiments, a distance 708 between a first side of the first intrinsic region 108 and a side of the first sidewall 106 b of the second semiconductor layer 106 ranges from about 0 micrometers to about 1 micrometer, 0.25 micrometers to about 0.75 micrometers, or some other range. In some embodiments, a distance 710 between a second side of the first intrinsic region 108 and a side of the second sidewall 106 c of the second semiconductor layer 106 ranges from about 0 micrometers to about 1 micrometer, 0.25 micrometers to about 0.75 micrometers, or some other range.

[0041] In some embodiments (e.g., Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , the second intrinsic region 122 is in the ridge portion 126 of the waveguide light detector 101. For example, the second intrinsic region 122 extends from the bottom surface 104d of the first semiconductor layer 104 to the second top surface 104j along one side of the sixth doping region 120. In addition, the second intrinsic region 122 extends along the fourth sidewall 104h of the first semiconductor layer 104 and the second top surface 104j.

[0042] In some embodiments (e.g., Fig. 9As shown in the cross-sectional view 900 of FIG. 1 , the second intrinsic region 122 is in both the ridge portion 126 and the plate portion 124. For example, the second intrinsic region 122 extends along the fourth sidewall 104h and the second top surface 104j of the first semiconductor layer 104, and further extends along the third upper surface 104f of the first semiconductor layer 104.

[0043] In some embodiments (e.g., Fig.10 As shown in the cross-sectional view 1000 of the embodiment of the present invention, the sidewalls (e.g., 104a, 104b, 104g, 104h, 104m, 104p) of the first semiconductor layer 104 are inclined. In addition, the second intrinsic region 122 extends along the lower portion of the fourth sidewall 104h, and the sixth doped region 120 extends along the upper portion of the fourth sidewall 104h.

[0044] In some embodiments (e.g., Fig.11 As shown in the cross-sectional view 1100 of the waveguide light detector 101, the sixth doped region 120 extends from the second top surface 104j into the first semiconductor layer 104, but does not reach the bottom surface 104d of the first semiconductor layer 104. Therefore, the first intrinsic region 108 and the second intrinsic region 122 are connected below the sixth doped region 120 (e.g., forming a common intrinsic region). In some embodiments, the sixth doped region 120 (and the third doped region 114) are balloon-shaped in the plate portion 124 of the waveguide light detector 101 (e.g., below the upper surfaces 104e, 104f of the first semiconductor layer 104).

[0045] In some embodiments (e.g., Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the fifth doped region 118 and the sixth doped region 120 intersect at the interface below the second intrinsic region 122. Therefore, the second intrinsic region 122 is in the first semiconductor layer 104 along the third upper surface 104f of the first semiconductor layer 104, but does not extend to the bottom surface 104d of the first semiconductor layer 104.

[0046] In some embodiments (e.g., Fig.13 1300 ), the first semiconductor layer 104 has a plurality of intrinsic regions laterally spaced apart from the first intrinsic region 108. For example, in some embodiments, the first semiconductor layer 104 includes a third intrinsic region 1302 laterally between the second intrinsic region 122 and the fifth doping region 118. In addition, the first semiconductor layer 104 includes a seventh doping region 1304 laterally between the second intrinsic region 122 and the third intrinsic region 1302. In some embodiments, the seventh doping region 1304 has a first doping type (e.g., p-type). In some embodiments, the width of the third intrinsic region 1302 is different from the width of the second intrinsic region 122, and the width of the seventh doping region 1304 is different from the width of the sixth doping region 120.

[0047] In some embodiments (e.g., Fig.14 1400), the second intrinsic region 122 includes a semiconductor different from the first semiconductor layer 104. In some such embodiments, the second intrinsic region 122 is optionally referred to as a third semiconductor layer 1402 including an intrinsic semiconductor different from the semiconductor of the first semiconductor layer 104. The third semiconductor layer 1402 is between the seventh sidewall 104q and the eighth sidewall 104r of the first semiconductor layer 104. The top surface 1402a of the third semiconductor layer 1402 is approximately coplanar with the third upper surface 104f of the first semiconductor layer 104.

[0048] Figure 15-18 Shows Figure 1 1500-1800 of various embodiments of the waveguide light detector 101, wherein the third intrinsic region 1502 is between the second doped region 112 and the third doped region 114. By including the third intrinsic region 1502 in the waveguide light detector 101, the charge carrier multiplication can be further increased. Therefore, the responsivity of the waveguide light detector 101 can be further increased.

[0049] In some embodiments (e.g., Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , the third intrinsic region 1502 is adjacent to the ridge portion 126. For example, the third doped region 114 and the third intrinsic region 1502 intersect at an interface directly below the sidewall 104g of the first semiconductor layer 104.

[0050] In some embodiments (e.g., Fig.16 1600), the third intrinsic region 1502 is laterally spaced apart from the ridge portion 126. In some embodiments, the second intrinsic region 122 and the third intrinsic region 1502 are spaced apart from the ridge portion 126 by different distances. For example, the second intrinsic region 122 is laterally spaced apart from the fourth sidewall 104h of the first semiconductor layer 104 by a first distance 1602, and the third intrinsic region 1502 is laterally spaced apart from the third sidewall 104g of the first semiconductor layer 104 by a second distance 1604 that is different from the first distance 1602. In addition, in some embodiments, the second intrinsic region 122 and the third intrinsic region 1502 have different widths.

[0051] In some embodiments (e.g., Fig.17 1700), the third intrinsic region 1502 is in both the ridge portion 126 and the plate portion 124. For example, the third intrinsic region 1502 extends along the third sidewall 104g and the first top surface 104i of the first semiconductor layer 104, and further extends along the second upper surface 104e of the first semiconductor layer 104.

[0052] In some embodiments (e.g., Fig.18 1800), the first semiconductor layer 104 includes a different number of intrinsic regions on each side of the ridge portion 126. For example, the first semiconductor layer 104 includes two intrinsic regions (the second intrinsic region 122 and the fourth intrinsic region 1802, with the seventh doping region 1804 in between) laterally between the fifth doping region 118 and the sixth doping region 120, and the first semiconductor layer 104 includes one intrinsic region (the third intrinsic region 1502) laterally between the second doping region 112 and the third doping region 114.

[0053] Figure 19-32 Cross-sectional views 1900-3200 of some embodiments of methods for forming an integrated chip including a waveguide light detector 101 are shown. Figure 19-32 is described with respect to a method, but it should be understood that Figure 19-32 The structure disclosed in is not limited to such a method, but may exist alone as a structure independent of the method.

[0054] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the insulator layer 704 is formed on the base semiconductor layer 702, and the first semiconductor layer 104 is formed on the insulator layer 704. In some embodiments, the base semiconductor layer 702 and the first semiconductor layer 104 include silicon or some other suitable material. In some embodiments, the insulator layer 704 includes silicon dioxide or some other suitable material. In some embodiments, the base semiconductor layer 702, the insulator layer 704, and the first semiconductor layer 104 can be provided as an SOI substrate.

[0055] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , the first semiconductor layer 104 is etched to form a waveguide 2002 including a ridge portion 126 and contact portions 128, 130 on the plate portion 124. A first recess 2004 in the first semiconductor layer 104 between the ridge portion 126 and the first contact portion 128 and a second recess 2006 in the first semiconductor layer 104 between the ridge portion 126 and the second contact portion 130 are formed by etching. The ridge portion 126 is directly between the first recess 2004 and the second recess 2006. The ridge portion 126 is defined by the sidewalls 104g, 104h and the top surface 104s of the first semiconductor layer 104. The first contact portion 128 is defined by the sidewalls 104m and the top surface 104k of the first semiconductor layer 104. The second contact portion 130 is defined by the sidewalls 104p and the top surface 104n of the first semiconductor layer 104. The plate portion 124 is at least partially defined by the upper surfaces 104 e , 104 f of the first semiconductor layer 104 .

[0056] In some embodiments, a mask layer 2008 is formed on the first semiconductor layer 104 and etching is performed according to the mask layer 2008. In some embodiments, etching includes a dry etching process, such as a reactive ion etching process, a plasma etching process, an ion beam etching (IBE) process, or some other suitable process. In some embodiments, the mask layer 2008 is or includes a photoresist layer, a hard mask layer, or some other suitable layer.

[0057] Figure 21-25 Cross-sectional views 2100 - 2500 of some embodiments of methods for forming first doped region 110 , second doped region 112 , third doped region 114 , fourth doped region 116 , fifth doped region 118 , and sixth doped region 120 in first semiconductor layer 104 to form waveguide light detector 101 along waveguide 2002 are shown.

[0058] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 2 , the third doping region 114 and the sixth doping region 120 are formed in the first semiconductor layer 104 in the ridge portion 126. The third doping region 114 and the sixth doping region 120 are laterally spaced apart, with the first intrinsic region 108 located therebetween. The third intrinsic region 1502 is on a first side of the ridge portion 126, and the second intrinsic region 122 is on a second side of the ridge portion 126.

[0059] The third doping region 114 and the sixth doping region 120 have a first doping type (eg, p-type). The doping concentrations of the third doping region 114 and the sixth doping region 120 are substantially equal. In some embodiments, the doping concentrations of the third doping region 114 and the sixth doping region 120 range from 10 16 cm -3 Up to 10 19 cm -3 , 10 16 cm -3 Up to 10 18 cm -3 or some other appropriate range.

[0060] In some embodiments, the third doping region 114 and the sixth doping region 120 are formed in the first semiconductor layer 104 by an ion implantation process or some other suitable process. In some embodiments, a mask layer 2102 is formed on the first semiconductor layer 104, and the third doping region 114 and the sixth doping region 120 are formed in the first semiconductor layer 104 according to the mask layer 2102. In some embodiments, the mask layer 2102 is or includes a photoresist layer or some other suitable layer. In some embodiments, the third doping region 114 and the sixth doping region 120 are formed together by a common doping process.

[0061] like Fig. 22As shown in the cross-sectional view 2200 of FIG. 2 , the second doped region 112 is formed in the first semiconductor layer 104 in the plate portion 124. In some embodiments, the second doped region 112 is laterally spaced apart from the third doped region 114, with the third intrinsic region 1502 located therebetween. In some other embodiments, the second doped region 112 is formed adjacent to the third doped region 114.

[0062] The second doping region 112 has a first doping type. The doping concentration of the second doping region 112 is greater than the doping concentrations of the third doping region 114 and the sixth doping region 120. In some embodiments, the doping concentration of the second doping region 112 ranges from 10 18 cm -3 Up to 10 20 cm -3 , 10 19 cm -3 Up to 10 20 cm -3 or some other appropriate range.

[0063] In some embodiments, the second doped region 112 is formed in the first semiconductor layer 104 by an ion implantation process or some other suitable process. In some embodiments, a mask layer 2202 is formed on the first semiconductor layer 104 and the second doped region 112 is formed in the first semiconductor layer 104 according to the mask layer 2202. In some embodiments, the mask layer 2202 is or includes a photoresist layer or some other suitable layer.

[0064] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 23 , the first doped region 110 is formed in the first semiconductor layer 104 in the first contact portion 128 . In some embodiments, the first doped region 110 is laterally adjacent to the second doped region 112 .

[0065] The first doping region 110 has a first doping type. The doping concentration of the first doping region 110 is greater than the doping concentration of the second doping region 112. In some embodiments, the doping concentration of the first doping region 110 ranges from 10 19 cm -3 Up to 10 22 cm -3 , 10 20 cm -3 Up to 10 21 cm -3 or some other appropriate range.

[0066] In some embodiments, the first doped region 110 is formed in the first semiconductor layer 104 by an ion implantation process or some other suitable process. In some embodiments, a mask layer 2302 is formed on the first semiconductor layer 104 and the first doped region 110 is formed in the first semiconductor layer 104 according to the mask layer 2302. In some embodiments, the mask layer 2302 is or includes a photoresist layer or some other suitable layer.

[0067] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , the fifth doping region 118 is formed in the first semiconductor layer 104 in the plate portion 124. The fifth doping region 118 is laterally spaced apart from the sixth doping region 120, with the second intrinsic region 122 located therebetween.

[0068] The fifth doping region 118 has a second doping type (eg, n-type) different from the first doping type. The doping concentration of the fifth doping region 118 is greater than the doping concentrations of the third doping region 114 and the sixth doping region 120. In some embodiments, the doping concentration of the fifth doping region 118 ranges from 10 18 cm -3 Up to 10 20 cm -3 , 10 19 cm -3 Up to 10 20 cm -3 or some other appropriate range.

[0069] In some embodiments, the fifth doped region 118 is formed in the first semiconductor layer 104 by an ion implantation process or some other suitable process. In some embodiments, a mask layer 2402 is formed on the first semiconductor layer 104 and the fifth doped region 118 is formed in the first semiconductor layer 104 according to the mask layer 2402. In some embodiments, the mask layer 2402 is or includes a photoresist layer or some other suitable layer.

[0070] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25 , the fourth doping region 116 is formed in the first semiconductor layer 104 in the second contact portion 130 . In some embodiments, the fourth doping region 116 is laterally adjacent to the fifth doping region 118 .

[0071] The fourth doping region 116 has the second doping type. The doping concentration of the fourth doping region 116 is greater than the doping concentration of the fifth doping region 118. In some embodiments, the doping concentration of the fourth doping region 116 ranges from 10 19 cm -3 Up to 10 22 cm -3 , 10 20 cm -3 Up to 10 21cm -3 or some other appropriate range.

[0072] In some embodiments, the fourth doped region 116 is formed in the first semiconductor layer 104 by an ion implantation process or some other suitable process. In some embodiments, a mask layer 2502 is formed on the first semiconductor layer 104 and the fourth doped region 116 is formed in the first semiconductor layer 104 according to the mask layer 2502. In some embodiments, the mask layer 2502 is or includes a photoresist layer or some other suitable layer.

[0073] although Figure 21-25 The third doping region 114 and the sixth doping region 120 are shown to be formed first, followed by the second doping region 112, the first doping region 110, the fifth doping region 118, and the fourth doping region 116, but it should be understood that in some other embodiments, the doping regions can be formed in a different order. For example, in some embodiments, the third doping region 114 and the sixth doping region 120 are alternately formed after the first doping region 110, the second doping region 112, the fourth doping region 116, and the fifth doping region 118.

[0074] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 1 , the first semiconductor layer 104 is etched to form a third recess 2602 in the ridge portion 126. The etching extends to the third doped region 114, the sixth doped region 120, and the first intrinsic region 108. The third recess 2602 is defined by the sidewalls 104a, 104b and the upper surface 104c of the first semiconductor layer 104. The third recess 2602 is directly above the first intrinsic region 108, the third doped region 114, and the sixth doped region 120. The third recess 2602 is directly between the third doped region 114 and the sixth doped region 120. The third recess divides the top surface 104s into top surfaces 104i, 104j. In some embodiments, the third recess 2602 extends into the first semiconductor layer 104 to below the upper surfaces 104e, 104f of the first semiconductor layer 104 (for example, the upper surface 104c is below the upper surfaces 104e, 104f).

[0075] In some embodiments, a mask layer 2604 is formed on the first semiconductor layer 104 and etching is performed according to the mask layer 2604. In some embodiments, etching includes a dry etching process, such as a reactive ion etching process, a plasma etching process, an ion beam etching process, or some other suitable process. In some embodiments, the mask layer 2604 is or includes a photoresist layer, a hard mask layer, or some other suitable layer.

[0076] Fig. 27 The method for applying the method to the third recess (eg, Fig.26 A cross-sectional view 2700 of some embodiments of a method of forming a second semiconductor layer 106 in 2602 of FIG. Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , the barrier layer 2702 is formed on the first semiconductor layer 104 but not in the third recess (eg, Fig.26 2602), so that the second semiconductor layer 106 can be selectively deposited in the third recess (for example, Fig.26 2602).

[0077] Figure 28-29 The method for applying the method to the third recess (eg, Fig.26 Cross-sectional views 2800-2900 of some other embodiments of the method of forming the second semiconductor layer 106 in 2602). Fig.28 As shown in the cross-sectional view 2800, the second semiconductor layer 106 is deposited in the third recess (eg, Fig.26 2602) and on the first semiconductor layer 104. Fig.29 As shown in the cross-sectional view 2900 of FIG. 29 , the second semiconductor layer 106 is etched according to the mask layer 2902 to remove a portion of the second semiconductor layer 106 from a portion of the first semiconductor layer 104, so that the second semiconductor layer 106 remains in the third recess (eg, Fig.26 2602).

[0078] The second semiconductor layer 106 fills the third recess (eg, Fig.26 The second semiconductor layer 106 further forms a ridge portion 126 of the waveguide light detector 101 (together with the first semiconductor layer 104). The second semiconductor layer 106 forms an absorption region of the waveguide light detector 101. The second semiconductor layer 106 includes a different semiconductor than the first semiconductor layer 104. For example, in some embodiments, the second semiconductor layer 106 includes germanium or some other suitable material. In some embodiments, the second semiconductor layer 106 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0079] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 1 , a dielectric cap layer 3002 is formed covering the first semiconductor layer 104 and the second semiconductor layer 106. In some embodiments, the dielectric cap layer 3002 includes silicon nitride or some other suitable material. In some embodiments, the dielectric cap layer 3002 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0080] like Fig.31 As shown in cross-sectional view 3100 of FIG. 1 , etching the dielectric cap layer (eg, Fig.303002) to form a dielectric cap 132 on the ridge portion 126 of the dielectric cap layer. In some embodiments, a mask layer 3102 is formed on the dielectric cap layer at the ridge portion 126, and etching is performed according to the mask layer 3102. In some embodiments, etching includes a dry etching process, such as a reactive ion etching process, a plasma etching process, an ion beam etching process, or some other suitable process. In some embodiments, the mask layer 3102 is or includes a photoresist layer, a hard mask layer, or some other suitable layer.

[0081] like Fig.32 As shown in the cross-sectional view 3200 of FIG. 32A , a dielectric layer 134 is formed on the waveguide light detector 101. In addition, contacts 136 and 140 are formed in the dielectric layer 134 and contact the first doped region 110 and the fourth doped region 116, respectively. In addition, metal lines 138 and 142 are formed above the contacts 136 and 140, respectively. In some embodiments, the dielectric layer 134 includes silicon dioxide or some other suitable material. In some embodiments, the dielectric layer 134 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the contacts 136 and 140 and the metal lines 138 and 142 are formed in the dielectric layer 134 by etching the dielectric layer 134 and depositing a metal on the dielectric layer 134 after etching.

[0082] Fig.33 A flow chart of some embodiments of a method 3300 for forming an integrated chip including a waveguide light detector is shown. Although the method 3300 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions described herein may be performed in one or more separate actions and / or stages.

[0083] At block 3302, a first semiconductor layer, an insulator layer, and a base semiconductor layer are provided. The insulator layer is on the base semiconductor layer. The first semiconductor layer is on the insulator layer. Fig.19 A cross-sectional view 1900 corresponding to some embodiments of block 3302 is shown.

[0084] At block 3304, the first semiconductor layer is etched to form a waveguide having a ridge portion and a contact portion on a plate portion. The ridge portion protrudes upward from the plate portion at the center of the waveguide. The contact portion protrudes upward from the plate portion on opposite sides of the ridge portion along an outer edge of the waveguide. Fig. 20 A cross-sectional view 2000 corresponding to some embodiments of block 3304 is shown.

[0085] At block 3306, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, and a sixth doped region are formed in the first semiconductor layer such that a first intrinsic region and a second intrinsic region remain in the first semiconductor layer between the doped regions. The first doped region and the fourth doped region are respectively formed in contact portions of the waveguide. The second doped region and the fifth doped region are formed in the slab portion on opposite sides of the ridge portion. The third doped region and the sixth doped region are formed in the ridge portion with the first intrinsic region therebetween. The second intrinsic region is located in the slab portion laterally between the fifth doped region and the sixth doped region. The doped regions are formed in the first semiconductor layer partially along the waveguide to form a waveguide light detector. The sixth doped region forms a charge region of the waveguide light detector. The second intrinsic region forms a multiplication region of the waveguide light detector. Figure 21-25 Cross-sectional views 2100-2500 of some embodiments corresponding to block 3306 are shown.

[0086] At block 3308, a ridge portion of the first semiconductor layer is etched to form a recess in the ridge portion. The recess is directly between the third doped region and the sixth doped region and directly above the first intrinsic region. Fig.26 A cross-sectional view 2600 corresponding to some embodiments of block 3308 is shown.

[0087] At block 3310, a second semiconductor layer is formed in the recess to further form a ridge portion. The second semiconductor layer further forms a waveguide light detector. For example, the second semiconductor layer forms an absorption region of the waveguide light detector. Figure 27-29 Cross-sectional views 2700-2900 corresponding to some embodiments of block 3310 are shown.

[0088] At block 3312, a dielectric cap is formed on the ridge portion. The dielectric cap covers a top surface of the second semiconductor layer and a top surface of the first semiconductor layer. Figure 30-31 Cross-sectional views 3000-3100 of some embodiments corresponding to block 3312 are shown.

[0089] At block 3314, a dielectric layer is formed on the waveguide and a contact is formed in contact with the contact portion. Fig.29 A cross-sectional view 3200 corresponding to some embodiments of block 3314 is shown.

[0090] Therefore, the present disclosure relates to an integrated chip including a waveguide light detector, a waveguide light detector including a charge region and an intrinsic multiplication region to improve the responsivity of the waveguide light detector.

[0091] Thus, in some embodiments, the present disclosure relates to an integrated chip including a substrate and a waveguide light detector on the substrate. The waveguide light detector includes a plate portion extending laterally on the substrate, a first contact portion protruding upward from the plate portion, a second contact portion protruding upward from the plate portion and laterally spaced apart from the first contact portion, and a ridge portion protruding upward from the plate portion between the first contact portion and the second contact portion. A first semiconductor layer including a first semiconductor on the substrate. The first semiconductor layer has a first sidewall, a second sidewall, a first top surface, and a second top surface that partially define a ridge portion of the waveguide light detector. The first semiconductor layer includes a first doped region having a first doping type and in the first contact portion, a second doped region having the first doping type in the plate portion laterally between the first contact portion and the ridge portion, a third doped region having the first doping type in the ridge portion, a fourth doped region having a second doping type different from the first doping type in the second contact portion, a fifth doped region having the second doping type in the plate portion laterally between the second contact portion and the ridge portion, a sixth doped region in the ridge portion, and a first intrinsic region laterally between the sixth doped region and the third doped region. The second semiconductor layer is above the first intrinsic region and laterally between the sixth doped region and the third doped region. The second semiconductor layer includes a second semiconductor different from the first semiconductor. The second semiconductor layer has a first sidewall, a second sidewall, and a top surface, further defining a ridge portion of the waveguide light detector. The sixth doped region has a first doping type. The first semiconductor layer further includes a second intrinsic region laterally between the sixth doped region and the fifth doped region.

[0092] In some embodiments, the first semiconductor layer further includes a third intrinsic region laterally between the second doped region and the third doped region. In some embodiments, the sixth doped region and the second intrinsic region intersect at an interface directly below the second sidewall of the first semiconductor layer. In some embodiments, the sixth doped region and the second intrinsic region intersect at an interface laterally spaced apart from the second sidewall of the first semiconductor layer toward the second contact portion. In some embodiments, the first semiconductor layer has an upper surface of a plate portion that partially defines a waveguide light detector, wherein the second intrinsic region is in the ridge portion and the plate portion, and wherein the second intrinsic region extends along the second sidewall and the upper surface of the first semiconductor layer. In some embodiments, the integrated chip further includes a dielectric cap covering a first top surface of the first semiconductor layer, a second top surface of the first semiconductor layer, an upper portion of the first sidewall of the second semiconductor layer, an upper portion of the second sidewall of the second semiconductor layer, and a top surface of the second semiconductor layer. In some embodiments, the first semiconductor layer has a bottom surface that partially defines a plate portion of the waveguide light detector, a first top surface, and a second top surface, wherein a top surface of the second semiconductor layer is above the first top surface and the second top surface of the first semiconductor layer, and wherein a bottom surface of the second semiconductor layer is lower than the first top surface and the second top surface of the first semiconductor layer.

[0093] In other embodiments, the disclosure relates to an integrated chip including a substrate, a first semiconductor layer above the substrate, and a second semiconductor layer above the substrate. The first semiconductor layer includes a first semiconductor. The second semiconductor layer includes a second semiconductor different from the first semiconductor. The first semiconductor layer is between the second semiconductor layer and the substrate. The first semiconductor layer includes a first intrinsic region, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a sixth doped region, and a second intrinsic region. The first intrinsic region is located directly below the second semiconductor layer. The first doped region is laterally spaced apart from the first intrinsic region and the second semiconductor layer in a first direction. The first doped region has a first doping type and a first doping concentration. The second doped region is laterally between the first doped region and the first intrinsic region. The second doped region has a first doping type and a second doping concentration less than the first doping concentration. The third doped region is laterally between the second doped region and the first intrinsic region. The third doped region is next to the first intrinsic region, directly below the second semiconductor layer, and extends upward along a first sidewall of the second semiconductor layer. The third doped region has a first doping type and a third doping concentration less than the second doping concentration. The fourth doped region is laterally spaced apart from the first intrinsic region and the second semiconductor layer in a second direction opposite to the first direction. The fourth doping region has a second doping type different from the first doping type and a fourth doping concentration. The fifth doping region is laterally between the fourth doping region and the first intrinsic region. The fifth doping region has a second doping type and a fifth doping concentration less than the fourth doping concentration. The sixth doping region is laterally between the fifth doping region and the first intrinsic region. The sixth doping region is next to the first intrinsic region, directly below the second semiconductor layer, and extends upward along the second side wall of the second semiconductor layer. The sixth doping region has the first doping type and a sixth doping concentration less than the second doping concentration. The second intrinsic region is laterally between the sixth doping region and the fifth doping region.

[0094] In some embodiments, the first semiconductor layer further includes a third intrinsic region laterally between the second doping region and the third doping region. In some embodiments, the first semiconductor layer further includes a third intrinsic region laterally between the second intrinsic region and the fifth doping region; and a seventh doping region laterally between the second intrinsic region and the third intrinsic region. In some embodiments, the first semiconductor layer further includes a fourth intrinsic region laterally between the second doping region and the third doping region. In some embodiments, the first intrinsic region and the second intrinsic region are connected below the sixth doping region. In some embodiments, the fifth doping region and the sixth doping region intersect at an interface directly below the second intrinsic region. In some embodiments, the second intrinsic region includes a third semiconductor that is different from the first semiconductor.

[0095] In some further embodiments, the disclosure relates to a method for forming an integrated chip. A first semiconductor layer is formed on a substrate. The first semiconductor layer includes a first semiconductor. The first semiconductor layer is etched to form a waveguide, the waveguide including a ridge portion, a first contact portion, and a second contact portion spaced laterally above the plate portion. The ridge portion is defined by a first sidewall, a second sidewall, and a top surface of the first semiconductor layer. A first doped region is formed in the first semiconductor layer and is spaced laterally from the ridge portion in a first direction. The first doped region doping type has a first doping type and a first doping concentration. A second doped region is laterally formed in the first semiconductor layer between the ridge portion and the first doped region. The second doped region has a first doping type and a second doping concentration less than the first doping concentration. A third doped region and a sixth doped region are formed in the first semiconductor layer at the ridge portion. The first intrinsic region in the first semiconductor layer is between the third doped region and the sixth doped region. The third doped region and the sixth doped region have a first doping type and a third doping concentration less than the second doping concentration. A fourth doped region is formed in the first semiconductor layer and is spaced laterally from the ridge portion in a second direction opposite to the first direction. The fourth doped region has a second doping type different from the first doping type and a fourth doping concentration. A fifth doping region is formed in the first semiconductor layer and laterally between the fourth doping region and the ridge portion. The fifth doping region has a second doping type and a fifth doping concentration that is less than the fourth doping concentration. The second intrinsic region in the first semiconductor layer is between the fifth doping region and the sixth doping region. The ridge portion is etched between the third doping region and the sixth doping region to form a third recess in the ridge portion. The third recess is defined by a third sidewall, a fourth sidewall, and an upper surface of the first semiconductor layer. The third doping region extends along the third sidewall and the upper surface of the first semiconductor layer. The sixth doping region extends along the fourth sidewall and the upper surface of the first semiconductor layer. The first intrinsic region extends along the upper surface of the first semiconductor layer. The second semiconductor layer is formed in the third recess, on the upper surface of the first semiconductor layer, and between the third sidewall and the fourth sidewall of the first semiconductor layer. The second semiconductor layer includes a second semiconductor that is different from the first semiconductor.

[0096] In some embodiments, the third intrinsic region in the first semiconductor layer is between the second doping region and the third doping region. In some embodiments, the second semiconductor layer in the third recess includes forming a barrier layer on the first semiconductor layer on the opposite side of the third recess, and depositing the second semiconductor layer in the third recess according to the position of the barrier layer. In some embodiments, forming the second semiconductor layer in the third recess includes depositing the second semiconductor layer on the first semiconductor layer and in the third recess, and etching the second semiconductor layer to remove the second semiconductor layer from the first semiconductor layer on the opposite side of the third recess. In some embodiments, the etching of the ridge portion extends into the top surface of the first semiconductor layer and removes a portion of the third doping region, a portion of the sixth doping region, and a portion of the first intrinsic region. In some embodiments, the third doping region and the sixth doping region are formed by a common doping process.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, characterized in that: include: substrate; a waveguide light detector on the substrate, the waveguide light detector comprising a plate portion extending laterally on the substrate, a first contact portion projecting upwardly from the plate portion, a second contact portion projecting upwardly from the plate portion and laterally spaced apart from the first contact portion, and a ridge portion projecting upwardly from the plate portion between the first contact portion and the second contact portion; a first semiconductor layer, comprising a first semiconductor on the substrate, the first semiconductor layer having a first sidewall, a second sidewall, a first top surface, and a second top surface partially defining the ridge portion of the waveguide light detector, the first semiconductor layer comprising a first doped region having a first doping type in the first contact portion, a second doped region having the first doping type in the slab portion laterally between the first contact portion and the ridge portion, a third doped region having the first doping type in the ridge portion, a fourth doped region having a second doping type different from the first doping type in the second contact portion, a fifth doped region having the second doping type in the slab portion laterally between the second contact portion and the ridge portion, a sixth doped region in the ridge portion, and a first intrinsic region laterally between the sixth doped region and the third doped region; as well as a second semiconductor layer on the first intrinsic region and laterally between the sixth doped region and the third doped region, the second semiconductor layer comprising a second semiconductor different from the first semiconductor, the second semiconductor layer having a first sidewall, a second sidewall, and a top surface further defining the ridge portion of the waveguide light detector, The sixth doping region has the first doping type, and the first semiconductor layer further includes a second intrinsic region laterally between the sixth doping region and the fifth doping region.

2. The integrated chip according to claim 1, characterized in that: The first semiconductor layer further includes a third intrinsic region laterally between the second doped region and the third doped region. 3 . The integrated chip according to claim 1 , wherein the sixth doped region and the second intrinsic region intersect at an interface directly below the second sidewall of the first semiconductor layer.

4. The integrated chip according to claim 1, characterized in that: The sixth doped region and the second intrinsic region intersect at an interface, and the interface is laterally spaced apart from the second sidewall of the first semiconductor layer toward the second contact portion.

5. The integrated chip according to claim 1, characterized in that: Also includes: A dielectric cap covers the first top surface of the first semiconductor layer, the second top surface of the first semiconductor layer, an upper portion of the first sidewall of the second semiconductor layer, an upper portion of the second sidewall of the second semiconductor layer, and the top surface of the second semiconductor layer.

6. An integrated chip, characterized in that: include: substrate; A first semiconductor layer and a second semiconductor layer on the substrate, the first semiconductor layer including a first semiconductor, the second semiconductor layer including a second semiconductor different from the first semiconductor, the first semiconductor layer being between the second semiconductor layer and the substrate, the first semiconductor layer including: a first intrinsic region directly below the second semiconductor layer; a first doped region laterally spaced apart from the first intrinsic region and the second semiconductor layer in a first direction, the first doped region having a first doping type and a first doping concentration; a second doping region laterally between the first doping region and the first intrinsic region, the second doping region having the first doping type and a second doping concentration less than the first doping concentration; a third doping region laterally disposed between the second doping region and the first intrinsic region, the third doping region being beside the first intrinsic region, directly below the second semiconductor layer, and extending upward along a first sidewall of the second semiconductor layer, the third doping region having the first doping type and a third doping concentration less than the second doping concentration; a fourth doping region laterally spaced apart from the first intrinsic region and the second semiconductor layer in a second direction opposite to the first direction, the fourth doping region having a second doping type different from the first doping type and a fourth doping concentration; a fifth doping region laterally between the fourth doping region and the first intrinsic region, the fifth doping region having the second doping type and a fifth doping concentration less than the fourth doping concentration; a sixth doping region laterally disposed between the fifth doping region and the first intrinsic region, the sixth doping region being beside the first intrinsic region, directly below the second semiconductor layer, and extending upward along a second sidewall of the second semiconductor layer, the sixth doping region having the first doping type and a sixth doping concentration less than the second doping concentration; and A second intrinsic region is laterally disposed between the sixth doping region and the fifth doping region.

7. The integrated chip according to claim 6, characterized in that: The first semiconductor layer further comprises: a third intrinsic region laterally between the second intrinsic region and the fifth doped region; and A seventh doped region is laterally disposed between the second intrinsic region and the third intrinsic region.

8. The integrated chip according to claim 6, characterized in that: The first intrinsic region and the second intrinsic region are connected below the sixth doping region.

9. The integrated chip according to claim 6, characterized in that: The fifth doping region and the sixth doping region intersect at an interface directly below the second intrinsic region.

10. A method for forming an integrated chip, characterized in that: The method comprises: forming a first semiconductor layer on a substrate, wherein the first semiconductor layer comprises a first semiconductor; etching the first semiconductor layer to form a waveguide including a ridge portion, a first contact portion, and a second contact portion laterally spaced apart above the slab portion, the ridge portion being defined by a first sidewall, a second sidewall, and a top surface of the first semiconductor layer; forming a first doped region in the first semiconductor layer and laterally spaced apart from the ridge portion in a first direction, the first doped region having a first doping type and a first doping concentration; forming a second doped region in the first semiconductor layer laterally between the first doped regions in the ridge portion, the second doped region having the first doping type and a second doping concentration less than the first doping concentration; forming a third doping region and a sixth doping region in the first semiconductor layer at the ridge portion, wherein a first intrinsic region of the first semiconductor layer is between the third doping region and the sixth doping region, and the third doping region and the sixth doping region have the first doping type and a third doping concentration less than the second doping concentration; forming a fourth doping region in the first semiconductor layer and laterally spaced apart from the ridge portion in a second direction opposite to the first direction, the fourth doping region having a second doping type different from the first doping type and a fourth doping concentration; forming a fifth doping region in the first semiconductor layer and laterally between the fourth doping region and the ridge portion, the fifth doping region having the second doping type and a fifth doping concentration less than the fourth doping concentration, wherein the second intrinsic region of the first semiconductor layer is between the fifth doping region and the sixth doping region; etching the ridge portion between the third doping region and the sixth doping region to form a third recess in the ridge portion, wherein the third recess is defined by a third sidewall, a fourth sidewall, and an upper surface of the first semiconductor layer, wherein the third doping region extends along the third sidewall and the upper surface of the first semiconductor layer, the sixth doping region extends along the fourth sidewall and the upper surface of the first semiconductor layer, and the first intrinsic region extends along the upper surface of the first semiconductor layer; and A second semiconductor layer is formed in the third recess, on the upper surface of the first semiconductor layer, and between the third sidewall and the fourth sidewall of the first semiconductor layer, the second semiconductor layer including a second semiconductor different from the first semiconductor.

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