Light detection device

Abstract

An image pickup device according to an embodiment includes a first substrate, a second substrate, a wiring, and a trench. The first substrate includes pixels each having a photodiode and a floating diffusion that holds a charge converted by the photodiode. And a second substrate including a pixel circuit for reading a pixel signal according to a charge held by the floating diffusion in a pixel, the second substrate being stacked on the first substrate. The wiring passes through the first substrate and the second substrate in a stacking direction, and establishes an electrical connection between the floating diffusion in the first substrate and the amplification transistor in the pixel circuit of the second substrate. And a trench formed at least in the second substrate so as to extend in parallel with the wiring, the trench having a depth equal to or greater than a thickness of a semiconductor layer in the second substrate.

Description

[0001] This application is a divisional application of patent application No. 202080034711.4, with application date of June 26, 2020 and invention name of “Camera Device”. Technical Field

[0002] The present invention relates to a camera device. Background Art

[0003] In the related art, miniaturization of the area per pixel of an image pickup device having a two-dimensional structure has been achieved by introducing fine processing and increasing the mounting density. In recent years, in order to achieve further miniaturization of the image pickup device and high density of pixels, an image pickup device having a three-dimensional structure has been developed. In an image pickup device having a three-dimensional structure, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are stacked on each other.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Publication No. 2010-245506 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] Incidentally, in an image pickup device having a three-dimensional structure, in the case of stacking three layers of semiconductor chips, it is impossible to bond all semiconductor substrates between the surfaces on the front surface side. In the case of randomly stacking three layers of semiconductor substrates, there is a possibility that the chip size increases or the miniaturization of the area per pixel is hindered due to the structure in which the semiconductor substrates are electrically connected to each other. Therefore, it is desirable to provide an image pickup device having a three-layer structure that has the same chip size as before and does not hinder the miniaturization of the area per pixel.

[0009] In addition, without limiting the three-layer structure, the imaging device uses a connection via as an FD wiring to connect the floating diffusion in the pixel and the gate of the amplifier transistor of the pixel circuit. In fine pixels, the area of ​​the connection via of the FD wiring is about 45%. Therefore, since the effective area of ​​the pixel circuit is reduced, the layout area of ​​the amplifier transistor cannot be expanded.

[0010] Solutions to technical problems

[0011] In order to solve the above problems, the camera device according to the embodiment includes a first substrate, a second substrate, wiring and a groove. The first substrate includes a pixel having a photodiode and a floating diffusion portion that holds the charge converted by the photodiode. The second substrate includes a pixel circuit that reads a pixel signal according to the charge held in the floating diffusion portion of the pixel, and is stacked on the first substrate. The wiring penetrates the first substrate and the second substrate in the stacking direction, and electrically connects the floating diffusion portion in the first substrate to an amplifying transistor in the pixel circuit of the second substrate. The groove is formed at least in the second substrate, extends parallel to the wiring, and has a depth equal to or greater than the thickness of the semiconductor layer in the second substrate.

[0012] Advantageous Effects of the Invention

[0013] By reducing the parasitic capacitance of wiring, the charge-voltage conversion efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing an example of a functional configuration of an image pickup apparatus according to an embodiment of the present invention.

[0015] Figure 2 It shows Figure 1 A schematic plan view of the schematic configuration of the imaging device shown.

[0016] Figure 3 It shows that along Figure 2 A schematic diagram of the cross-sectional structure along line III-III' is shown.

[0017] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0018] Figure 5 is a diagram showing an example of a connection state between a plurality of pixel sharing units and a plurality of vertical signal lines.

[0019] Figure 6 It shows Figure 3 A schematic cross-sectional view showing an example of a specific configuration of the imaging device shown.

[0020] Fig. 7A It shows Figure 6 A schematic diagram showing an example of a planar configuration of a main portion of the first substrate is shown.

[0021] Figure 7B is shown together with the pad portion Fig. 7A A schematic diagram of a planar structure showing the main parts of a first substrate.

[0022] Figure 8 It shows Figure 6 Schematic diagram of an example of a planar structure of the second substrate (semiconductor layer) shown.

[0023] Fig. 9 is a diagram showing the main parts of the pixel circuit and the first substrate together with Figure 6 Schematic diagram of an example of a planar configuration of the first wiring layer shown.

[0024] Fig.10 It shows Figure 6 Schematic diagram of an example of a planar configuration of a first wiring layer and a second wiring layer shown.

[0025] Fig.11 It shows Figure 6 Schematic diagram of an example of a planar configuration of a second wiring layer and a third wiring layer shown.

[0026] Fig.12 It shows Figure 6 A schematic diagram showing an example of a planar configuration of a third wiring layer and a fourth wiring layer.

[0027] Fig.13 It is used to illustrate Figure 3 A schematic diagram of the path of the input signal of the camera device is shown.

[0028] Fig.14 It is used to illustrate Figure 3 Schematic diagram of the signal path of the pixel signal of the camera device shown.

[0029] Fig.15 It shows Figure 8 Schematic diagram of a modification of the planar structure of the second substrate (semiconductor layer) shown.

[0030] Fig.16 is a diagram showing the main part of the first wiring layer and the first substrate together with Fig.15 A schematic diagram of the planar construction of the pixel circuit shown.

[0031] Fig.17 is shown together with the second wiring layer Fig.16 Schematic diagram of an example of a planar configuration of the first wiring layer shown.

[0032] Fig.18 is shown together with the third wiring layer Fig.17 Schematic diagram of an example of a planar configuration of the second wiring layer shown.

[0033] Fig.19 is shown together with the fourth wiring layer Fig.18 Schematic diagram of an example of a planar configuration of the third wiring layer shown.

[0034] Fig. 20 It shows Fig. 7A Schematic diagram of a modified example of the planar structure of the first substrate shown.

[0035] Fig.21 is shown stacked in Fig. 20 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0036] Fig. 22 is shown together with the first wiring layer Fig.21 Schematic diagram of an example of a planar configuration of a pixel circuit shown together.

[0037] Fig.23 is shown together with the second wiring layer Fig. 22 Schematic diagram of an example of a planar configuration of the first wiring layer shown.

[0038] Fig.24 is shown together with the third wiring layer Fig.23 Schematic diagram of an example of a planar configuration of the second wiring layer shown.

[0039] Fig.25 is shown together with the fourth wiring layer Fig.24 Schematic diagram of an example of a planar configuration of the third wiring layer shown.

[0040] Fig.26 It shows Fig. 20 FIG. 4 is a schematic diagram of another example of the planar structure of the first substrate shown.

[0041] Fig. 27 is shown stacked in Fig.26 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0042] Fig.28 is shown together with the first wiring layer Fig. 27 Schematic diagram of an example of a planar configuration of a pixel circuit shown together.

[0043] Fig.29 is shown together with the second wiring layer Fig.28 Schematic diagram of an example of a planar configuration of the first wiring layer shown.

[0044] Fig.30 is shown together with the third wiring layer Fig.29 Schematic diagram of an example of a planar configuration of the second wiring layer shown.

[0045] Fig.31 is shown together with the fourth wiring layer Fig.30Schematic diagram of an example of a planar configuration of the third wiring layer shown.

[0046] Fig.32 It shows Figure 3 A schematic cross-sectional view of another example of the imaging device shown.

[0047] Fig.33 It is used to illustrate Fig.32 A schematic diagram of the path of the input signal of the camera device is shown.

[0048] Fig.34 It is used to illustrate Fig.32 Schematic diagram of the signal path of the pixel signal of the camera device shown.

[0049] Fig.35 It shows Figure 6 A schematic cross-sectional view of another example of the imaging device shown.

[0050] Fig.36 It shows Figure 4 FIG. 1 is a diagram of another example of an equivalent circuit shown.

[0051] Fig.37 It shows Fig. 7A Schematic plan view of another example of a pixel isolation portion shown in FIG.

[0052] Fig.38 is an equivalent circuit diagram showing a configuration example of a pixel sharing unit in the image pickup device of the 2-1st embodiment.

[0053] Fig.39 : is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the 2-1st embodiment.

[0054] Fig.40 is a schematic diagram showing an example of a stacked structure of a first substrate and a second substrate.

[0055] Fig.41 is a schematic diagram showing an example of the arrangement configuration of the trenches T1 on the surface of the second substrate.

[0056] Fig.42 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T2 on the surface of the second substrate.

[0057] Fig.43 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T3 on the surface of the second substrate.

[0058] Fig.44 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T4 on the surface of the second substrate.

[0059] Fig.45 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate according to the 2-2 embodiment.

[0060] Fig.46A is a schematic diagram showing an example of the arrangement configuration of the trenches T5 on the surface of the second substrate.

[0061] Fig.46B is a schematic diagram showing an example of the arrangement configuration of the trenches T10 on the surface of the second substrate.

[0062] Fig.46C is a schematic diagram showing an example of the arrangement configuration of the trenches T11 on the surface of the second substrate.

[0063] Fig.46D 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T12 on the surface of the second substrate.

[0064] Fig.46E 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T13 on the surface of the second substrate.

[0065] Fig.46F 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T14 on the surface of the second substrate.

[0066] Figure 46G 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T15 on the surface of the second substrate.

[0067] Figure 46H 2 is a schematic diagram showing an example of the arrangement configuration of the trenches T16 on the surface of the second substrate.

[0068] Fig.47 is a schematic diagram showing an example of a schematic cross-sectional shape of the trench T5 .

[0069] Fig.48A : is an equivalent circuit diagram showing a configuration example of a pixel sharing unit of the image pickup device according to the second-third embodiment.

[0070] Fig.48B : is an equivalent circuit diagram showing another example of the configuration of the pixel sharing unit of the image pickup device according to the second-third embodiment.

[0071] Fig.49 : is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the second-third embodiment.

[0072] Fig.50A : is an equivalent circuit diagram showing an example of the configuration of a plurality of pixel circuits of the second substrate of the 3-1st embodiment.

[0073] Fig.50B is a schematic block diagram of the column signal processing unit of the first aspect.

[0074] Fig.50C is a schematic block diagram of the column signal processing unit of the second aspect.

[0075] Fig.50D is an explanatory diagram of a first configuration example of a comparator.

[0076] Fig.50E is an explanatory diagram of a second configuration example of a comparator.

[0077] Fig.50F is an explanatory diagram of a third configuration example of a comparator.

[0078] Figure 50G is a schematic block diagram of the column signal processing unit of the third aspect.

[0079] Figure 50H It is an explanatory diagram of a configuration example of a comparator according to the third aspect.

[0080] Fig.50I is a schematic block diagram of the column signal processing unit of the fourth aspect.

[0081] Fig.50J This is an explanatory diagram of a configuration example of a pre-circuit.

[0082] Fig.51 : is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the 3-1st embodiment.

[0083] Fig.52 is a schematic diagram showing an example of a planar configuration of a pixel circuit.

[0084] Fig.53 The FD wiring FDL and the shield wiring SL2 are shown in FIG. Fig.52 Schematic diagram of an example of a planar configuration in which the front surface of a pixel circuit is overlapped.

[0085] Fig.54 : is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the 3-2nd embodiment.

[0086] Fig.55 : is an equivalent circuit diagram showing a configuration example of a plurality of pixel circuits of the second substrate of the 3-3 embodiment.

[0087] Fig.56 : is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit of a global shutter mode imaging device according to the third-fourth embodiment.

[0088] Fig.57 : is an equivalent circuit diagram showing a configuration example of a pixel sharing unit of a memory hold type global shutter mode imaging device according to the third to fifth embodiments.

[0089] Fig.58 : is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to the above-described embodiment and its modified example.

[0090] Fig.59 It shows Fig.58 A diagram showing an example of an imaging process of the imaging system shown.

[0091] Fig.60 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0092] Fig.61 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0093] Fig.62 is a diagram showing a schematic configuration of an endoscopic surgery system.

[0094] Fig.63 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Specific implementation plan

[0095] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same parts are denoted by the same reference numerals, and redundant description will be omitted.

[0096] Hereinafter, a scheme for implementing the present invention will be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.

[0097] 1. First embodiment (imaging device having a three-substrate stacked structure)

[0098] 2. First Modification (First Example of Planar Structure)

[0099] 3. Second Modification (Second Example of Planar Structure)

[0100] 4. Third Modification (Third Example of Planar Structure)

[0101] 5. Fourth Modification Example (Example in which the Contact Section Between Substrates is Provided at the Center of the Pixel Array Section)

[0102] 6. Fifth Modification (Example Including Planar Transfer Transistor)

[0103] 7. Sixth Modification Example (Example in which one pixel is connected to one pixel circuit)

[0104] 8. Seventh Modification Example (Structural Example of Pixel Isolation Section)

[0105] 9. Second Implementation Method

[0106] 9.1 Issues to be solved by the second implementation plan

[0107] 9.2 Overview of the Second Implementation Plan

[0108] 9.3 Specific example of implementation plan 2-1

[0109] 9.3.1 Structure of Implementation Plan 2-1

[0110] 9.3.2 Operation and Effect of Implementation Plan 2-1

[0111] 9.3.3 Variation of Implementation Example 2-1

[0112] 9.4 Specific example of implementation plan 2-2

[0113] 9.4.1 Structure of Implementation Plan 2-2

[0114] 9.4.2 Operation and Effect of Implementation Plan 2-2

[0115] 9.5 Specific examples of implementation plans 2-3

[0116] 9.5.1 Construction of the 2nd and 3rd Implementation Plan

[0117] 9.5.2 Operation and Effect of Implementation Plan 2-3

[0118] 10. Implementation Method 3

[0119] 10.1 Issues to be solved by the third implementation plan

[0120] 10.2 Overview of the Third Implementation Plan

[0121] 10.3 Specific example of implementation plan 3-1

[0122] 10.3.1 Structure of Implementation Plan 3-1

[0123] 10.3.2 Operation and Effect of Implementation Plan 3-1

[0124] 10.4 Specific example of implementation plan 3-2

[0125] 10.4.1 Structure of Implementation Plan 3-2

[0126] 10.4.2 Operation and Effect of Implementation Plan 3-2

[0127] 10.5 Specific examples of implementation plan 3-3

[0128] 10.5.1 Construction of Implementation Plan 3-3

[0129] 10.5.2 Operation and Effect of Implementation Plan 3-3

[0130] 10.6 Specific examples of implementation plans 3-4

[0131] 10.6.1 Construction of Implementation Scheme 3-4

[0132] 10.6.2 Operation and Effect of Implementation Plan 3-4

[0133] 10.7 Specific examples of implementation plans 3-5

[0134] 10.7.1 Construction of Implementation Plans 3-5

[0135] 10.7.2 Operation and Effect of Implementation Plans 3-5

[0136] 11. Application example (camera system)

[0137] 12. Application Examples

[0138] <1. First Implementation Method>

[0139] [Functional Configuration of the Image Capture Device 1]

[0140] Figure 1 : is a block diagram showing an example of the functional configuration of an image pickup apparatus (image pickup apparatus 1 ) according to an embodiment of the present invention.

[0141] For example, Figure 1 The imaging device 1 includes an input unit 510A, a row driving unit 520, a timing control unit 530, a pixel array section 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0142] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel common unit 539 including a plurality of pixels is a repeating unit, and the pixel common unit 539 is repeatedly arranged in an array consisting of a row direction and a column direction. In this specification, for convenience, the row direction may be referred to as the H direction, and the column direction perpendicular to the row direction may be referred to as the V direction. Figure 1 In the example of FIG. 5 , one pixel sharing unit 539 includes four pixels (pixel 541A, pixel 541B, pixel 541C, and pixel 541D). Each of the pixel 541A, pixel 541B, pixel 541C, and pixel 541D has a photodiode PD (described later). Figure 6 ). The pixel sharing unit 539 is a pixel sharing circuit (described later). Figure 4210). In other words, one pixel circuit (pixel circuit 210 described later) is set for every 4 pixels (pixel 541A, pixel 541B, pixel 541C, pixel 541D). The pixel circuit operates in a time-sharing manner so as to sequentially read the pixel signals of each of the pixels 541A, pixel 541B, pixel 541C, and pixel 541D. For example, the pixels 541A, pixel 541B, pixel 541C, and pixel 541D are arranged in 2 rows × 2 columns. In the pixel array section 540, a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column read lines) 543 are provided together with the pixels 541A, pixel 541B, pixel 541C, and pixel 541D. The row drive signal line 542 drives the pixels 541 in the pixel array section 540 that are arranged side by side in the row direction and included in each of the plurality of pixel sharing units 539. In the pixel sharing unit 539, the pixels arranged side by side in the row direction are driven. Figure 4 As will be described in detail later, the pixel common unit 539 is provided with a plurality of transistors. In order to drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel common unit 539. The pixel common unit 539 is connected to a vertical signal line (column read line) 543. A pixel signal is read from each of the pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539 through the vertical signal line (column read line) 543.

[0143] The row driving unit 520 includes, for example, a row address control unit (in other words, a row decoder unit) that determines the position of a row for driving pixels and a row driving circuit unit that generates signals for driving pixels 541A, 541B, 541C, and 541D.

[0144] The column signal processing unit 550 includes, for example, a load circuit unit connected to the vertical signal line 543 and forming a source follower circuit with the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D (the pixel common unit 539). The column signal processing unit 550 may have an amplifying circuit unit that amplifies a signal read from the pixel common unit 539 through the vertical signal line 543. The column signal processing unit 550 may have a noise processing unit. In the noise processing unit, for example, a system noise level is removed from a signal read by the pixel common unit 539 as a result of photoelectric conversion.

[0145] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the analog signal after noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with the reference signal to be compared. In the counter unit, the time is measured until the comparison result of the comparator unit is inverted. The column signal processing unit 550 may include a horizontal scanning circuit unit that performs control to scan the read column.

[0146] The timing control unit 530 supplies a signal for controlling timing to the row driving unit 520 and the column signal processing unit 550 based on a reference clock signal or a timing control signal input to the device.

[0147] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion (in other words, data obtained as a result of the image pickup operation of the image pickup device 1). The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0148] An example of the signal processing performed in the image signal processing unit 560 is a tone curve correction process that gives a lot of grayscale when the AD-converted image data is data obtained by imaging a dark subject, and reduces the grayscale when the AD-converted image data is data obtained by imaging a bright subject. In this case, it is desirable to store the characteristic data of the tone curve in advance in the data holding unit of the image signal processing unit 560 based on the tone curve whose grayscale of the image data is corrected.

[0149] The input unit 510A is used, for example, to input a reference clock signal, a timing control signal, feature data, etc. from outside the device to the camera device 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, etc. The feature data is, for example, to be stored in a data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude variation unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0150] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is used to input the signal input to the input terminal 511 into the camera device 1. In the input amplitude variation unit 513, the amplitude of the signal acquired by the input circuit unit 512 is changed to an amplitude that can be easily used in the camera device 1. In the input data conversion circuit unit 514, the arrangement of the data string of the input data is changed. The input data conversion circuit unit 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. In the input unit 510A, the input amplitude variation unit 513 and the input data conversion circuit unit 514 may not be provided. The power supply unit supplies power set to various voltages required inside the camera device 1 based on the power supplied to the camera device 1 from the outside.

[0151] When the camera 1 is connected to an external storage device, the input unit 510A may be provided with a storage interface circuit that receives data from the external storage device. Examples of the external storage device include flash memory, SRAM, and DRAM.

[0152] The output unit 510B outputs the image data to the outside of the device. The image data is, for example, image data captured by the camera 1, image data subjected to signal processing by the image signal processing unit 560, etc. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0153] The output data conversion circuit unit 515 includes, for example, a parallel-to-serial conversion circuit, and in the output data conversion circuit unit 515, a parallel signal used inside the image pickup device 1 is converted into a serial signal. The output amplitude changing unit 516 changes the amplitude of the signal used inside the image pickup device 1. The signal with the changed amplitude can be easily used in an external device connected to the outside of the image pickup device 1. The output circuit unit 517 is a circuit that outputs data from the inside of the image pickup device 1 to the outside of the device, and the wiring outside the image pickup device 1 connected to the output terminal 518 is driven by the output circuit unit 517. At the output terminal 518, data is output from the image pickup device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude changing unit 516 may not be provided.

[0154] When the camera 1 is connected to an external storage device, the output unit 510B may be provided with a storage interface circuit that outputs data to the external storage device. Examples of the external storage device include flash memory, SRAM, DRAM, and the like.

[0155] [Schematic Configuration of Image Pickup Device 1]

[0156] Figure 2 and Figure 3 There is shown an example of a schematic configuration of the image pickup device 1. The image pickup device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 2 The planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300 is schematically shown, and Figure 3 The cross-sectional configuration of the first substrate 100 , the second substrate 200 , and the third substrate 300 stacked on each other is schematically shown. Figure 3 Corresponding to along Figure 2 The cross-sectional structure taken along the line III-III' shown. The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film surrounding the wiring is referred to as a wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence, and a semiconductor layer 100S, a wiring layer 100T, a semiconductor layer 200S, a wiring layer 200T, a wiring layer 300T, and a semiconductor layer 300S are arranged in sequence along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 3 The arrow shown shows the incident direction of the light L on the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "lower", "lower side", "below", and the side opposite to the light incident side may be referred to as "upper", "upper side", and "above". In addition, in this specification, for convenience, in a substrate including a semiconductor layer and a wiring layer, the side of the substrate close to the wiring layer may be referred to as the front, and the side of the substrate close to the semiconductor layer may be referred to as the back. The description of the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light enters from the back side of a first substrate 100 having a photodiode.

[0157] The pixel array section 540 and the pixel common unit 539 included in the pixel array section 540 are constituted using both the first substrate 100 and the second substrate 200. In the first substrate 100, a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539 are provided. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). In the second substrate 200, a pixel circuit (pixel circuit 210 described later) included in the pixel common unit 539 is provided. The pixel circuit reads the pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C, and 541D through the transfer transistor, or resets the photodiode. In addition to the pixel circuit, the second substrate 200 also has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also has a power supply line 544 extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row driving unit 520 is, for example, disposed in a region in which a portion of the row driving unit 520 overlaps with the pixel array section 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter, referred to as the stacking direction). More specifically, the row driving unit 520 is disposed in a region in which the row driving unit 520 overlaps with a portion of the pixel array section 540 near the end in the H direction in the stacking direction ( Figure 2 ). For example, the column signal processing unit 550 is disposed in a region in which a portion of the column signal processing unit 550 overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing unit 550 is disposed in a region in which the column signal processing unit 550 overlaps with a portion of the pixel array section 540 near an end in the V direction in the stacking direction ( Figure 2 ). Although not shown, the input unit 510A and the output unit 510B may be provided in a portion other than the third substrate 300, and may be provided on the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be provided on the rear side (light incident surface) of the first substrate 100. Note that, as another name, the pixel circuit provided on the second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel reading circuit, or a reading circuit. In this specification, the term "pixel circuit" is used.

[0158] The first substrate 100 and the second substrate 200 are connected to each other by, for example, through electrodes (described later). Figure 6 The through-electrodes 120E, 121E) are electrically connected. For example, the second substrate 200 and the third substrate 300 are electrically connected through the contact portion 201, the contact portion 202, the contact portion 301 and the contact portion 302. The contact portion 201 and the contact portion 202 are arranged on the second substrate 200, and the contact portion 301 and the contact portion 302 are arranged on the third substrate 300. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact area 201R in which a plurality of contact portions 201 are arranged and a contact area 202R in which a plurality of contact portions 202 are arranged. The third substrate 300 has a contact area 301R in which a plurality of contact portions 301 are arranged and a contact area 302R in which a plurality of contact portions 302 are arranged. The contact area 201R and the contact area 301R are arranged along the stacking direction ( Figure 3 ) is disposed between the pixel array section 540 and the row drive unit 520. In other words, for example, the contact region 201R and the contact region 301R are disposed in a region where the row drive unit 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction or in a region near the region where the row drive unit 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction. For example, the contact region 201R and the contact region 301R are disposed at the ends of such a region in the H direction ( Figure 2 In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a portion of the row drive unit 520 (specifically, an end portion of the row drive unit 520 in the H direction) ( Figure 2 and Figure 3 ). For example, the contact portion 201 and the contact portion 301 connect the row driving unit 520 provided on the third substrate 300 to the row driving signal line 542 provided on the second substrate 200. For example, the contact portion 201 and the contact portion 301 can connect the input unit 510A provided on the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS described later). The contact region 202R and the contact region 302R are provided between the pixel array portion 540 and the column signal processing unit 550 in the stacking direction ( Figure 3 ). In other words, for example, the contact region 202R and the contact region 302R are provided in a region where the column signal processing unit 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction or in a region near the region where the column signal processing unit 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction. For example, the contact region 202R and the contact region 302R are arranged at the end of such a region in the V direction ( Figure 2In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the column signal processing unit 550 (specifically, an end portion of the column signal processing unit 550 in the V direction) ( Figure 2 and Figure 3 ). For example, the contact portion 202 and the contact portion 302 are used to connect a pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion of a photodiode) output from each of the plurality of pixel common units 539 included in the pixel array portion 540 to a column signal processing unit 550 provided on the third substrate 300. The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0159] Figure 3 is an example of a cross-sectional view of the camera device 1 as described above. The first substrate 100, the second substrate 200 and the third substrate 300 are electrically connected by the wiring layer 100T, the wiring layer 200T and the wiring layer 300T. For example, the camera device 1 has an electrical connection portion that electrically connects the second substrate 200 to the third substrate 300. Specifically, the contact portion 201, the contact portion 202, the contact portion 301 and the contact portion 302 are formed by electrodes formed by a conductive material. For example, the conductive material is formed by a metal material such as copper (Cu), aluminum (Al) or gold (Au). For example, the contact area 201R, the contact area 202R, the contact area 301R and the contact area 302R electrically connect the second substrate to the third substrate by directly bonding the wiring formed as the electrode, and enable input and / or output of signals between the second substrate 200 and the third substrate 300.

[0160] The electrical connection portion that electrically connects the second substrate 200 to the third substrate 300 may be disposed at a desired position. Figure 3 In the contact region 201R, the contact region 202R, the contact region 301R, and the contact region 302R, the electrical connection portion may be provided in a region overlapping with the pixel array portion 540 in the stacking direction. In addition, the electrical connection portion may be provided in a region not overlapping with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region overlapping with a peripheral portion arranged outside the pixel array portion 540 in the stacking direction.

[0161] The first substrate 100 and the second substrate 200 are provided with, for example, a connection hole portion H1 and a connection hole portion H2. The connection hole portion H1 and the connection hole portion H2 penetrate the first substrate 100 and the second substrate 200 ( Figure 3 The connection hole portion H1 and the connection hole portion H2 are provided outside the pixel array portion 540 (or a portion overlapping with the pixel array portion 540) ( Figure 2). For example, the connection hole portion H1 is arranged on the outside of the pixel array portion 540 in the H direction, and the connection hole portion H2 is arranged on the outside of the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input unit 510A provided in the third substrate 300, and the connection hole portion H2 reaches the output unit 510B provided in the third substrate 300. The connection hole portion H1 and the connection hole portion H2 may be hollow or at least partially contain a conductive material. For example, a bonding wire is connected to an electrode formed as the input unit 510A and / or the output unit 510B. Alternatively, an electrode formed as the input unit 510A and / or the output unit 510B is connected to a conductive material provided in the connection hole portion H1 and the connection hole portion H2. The conductive material provided in the connection hole portion H1 and the connection hole portion H2 may be embedded in a part or all of the connection hole portion H1 and the connection hole portion H2, and the conductive material may be formed on the side walls of the connection hole portion H1 and the connection hole portion H2.

[0162] exist Figure 3 In the embodiment, the input unit 510A and the output unit 510B are arranged in the third substrate 300, but the present invention is not limited thereto. For example, by transmitting the signal of the third substrate 300 to the second substrate 200 through the wiring layer 200T and the wiring layer 300T, the input unit 510A and / or the output unit 510B can be arranged in the second substrate 200. Similarly, by transmitting the signal of the second substrate 200 to the first substrate 1000 through the wiring layer 100T and the wiring layer 200T, the input unit 510A and / or the output unit 510B can be arranged in the first substrate 100.

[0163] Figure 4 5 is an equivalent circuit diagram showing a configuration example of a pixel common unit 539. The pixel common unit 539 includes a plurality of pixels 541 ( Figure 4 541A, pixel 541B, pixel 541C, and pixel 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210 are shown. The pixel circuit 210 includes, for example, four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, by operating one pixel circuit 210 in a time-sharing manner, the pixel sharing unit 539 sequentially outputs the pixel signals of the four pixels 541 (pixel 541A, pixel 541B, pixel 541C, and pixel 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The state in which one pixel circuit 210 is connected to a plurality of pixels 541, and the pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time-sharing manner is referred to as "a plurality of pixels 541 share one pixel circuit 210".

[0164] Pixel 541A, pixel 541B, pixel 541C, and pixel 541D have the same components. Hereinafter, in order to distinguish the components of pixel 541A, pixel 541B, pixel 541C, and pixel 541D from each other, identification number 1 is assigned to the end of the reference numeral of the component of pixel 541A, identification number 2 is assigned to the end of the reference numeral of the component of pixel 541B, identification number 3 is assigned to the end of the reference numeral of the component of pixel 541C, and identification number 4 is assigned to the end of the reference numeral of the component of pixel 541D. In the case where it is not necessary to distinguish the components of pixel 541A, pixel 541B, pixel 541C, and pixel 541D from each other, the identification numbers at the end of the reference numerals of the components of pixel 541A, pixel 541B, pixel 541C, and pixel 541D are omitted.

[0165] Pixel 541A, pixel 541B, pixel 541C, and pixel 541D have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion portion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates charges according to the amount of light received. The transfer transistor TR (transfer transistor TR1, transfer transistor TR2, transfer transistor TR3, and transfer transistor TR4) is, for example, an n-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion portion FD, and the gate is electrically connected to a drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel common unit 539 (refer to Figure 1 ). The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1, floating diffusion FD2, floating diffusion FD3, and floating diffusion FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding device for temporarily holding the charge transferred from the photodiode PD, and is a charge-voltage conversion device for generating a voltage according to the amount of charge.

[0166] The four floating diffusions FD (floating diffusion FD1, floating diffusion FD2, floating diffusion FD3, and floating diffusion FD4) included in one pixel sharing unit 539 are electrically connected to each other, and are electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of the multiple row drive signal lines 542 connected to one pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of the multiple row drive signal lines 542 connected to one pixel sharing unit 539. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel common unit 539 .

[0167] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and is provided from the semiconductor layer (described later) to the floating diffusion FD. Figure 6 The front surface of the semiconductor layer 100S) extends to reach the Figure 6 The depth of the PD shown. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a voltage signal as a pixel signal according to the level of the charge retained in the floating diffusion FD. The amplifier transistor AMP is connected to the vertical signal line 543 through the selection transistor SEL. The amplifier transistor AMP is connected to the load circuit unit of the column signal processing unit 550 connected to the vertical signal line 543 (refer to Figure 1 ) constitutes a source follower. When the selection transistor is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion portion FD to the column signal processing unit 550 through the vertical signal line 543. For example, the reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are N-type MOS transistors.

[0168] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion of the floating diffusion FD. Generally, when photographing in a dark place, the pixel signal is small. When the capacitance (FD capacitance C) of the floating diffusion FD is large when the charge-voltage conversion is performed based on Q=CV, V becomes smaller when it is converted to voltage by the amplifier transistor AMP. On the other hand, since the pixel signal in the bright place becomes larger, the floating diffusion FD cannot receive the charge of the photodiode PD unless the FD capacitance C is large. In addition, the FD capacitance C needs to be large so that V does not become too large when it is converted to voltage by the amplifier transistor AMP (in other words, V becomes smaller). In view of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, thereby increasing the entire FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C decreases. In this way, by turning on and off the FD conversion gain switching transistor FDG, the FD capacitance C is made variable, and the conversion efficiency can be switched. For example, the FD conversion gain switching transistor FDG is an N-type MOS transistor.

[0169] Note that a configuration in which the FD conversion gain switching transistor FDG is not provided is also feasible. In this case, for example, the pixel circuit 210 includes three transistors, such as an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210, for example, has at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0170] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (refer to Figure 1 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that although not shown, the number of pixels 541 that share one pixel circuit 210 may not be four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0171] Figure 5 543. For example, four pixel sharing units 539 arranged in the column direction are divided into four groups, and the vertical signal lines 543 are connected to the four groups, respectively. Figure 5An example is shown in which each of the four groups has one pixel common unit 539, but each of the four groups may include a plurality of pixel common units 539. As described above, in the image pickup device 1, a plurality of pixel common units 539 arranged in the column direction may be divided into a plurality of groups, each group including one or more pixel common units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each group, and pixel signals may be read from each group at the same time. Alternatively, in the image pickup device 1, one vertical signal line 543 may be connected to a plurality of pixel common units 539 arranged in the column direction. In this case, pixel signals are sequentially read from a plurality of pixel common units 539 connected to one vertical signal line 543 in a time-division manner.

[0172] [Specific Structure of the Image Capture Device 1]

[0173] Figure 6 An example of a cross-sectional configuration in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the image pickup device 1 is shown. For ease of understanding, Figure 6 The positional relationship of the components is schematically shown and may be different from the actual cross section. In the camera device 1, the first substrate 100, the second substrate 200 and the third substrate 300 are stacked in this order. The camera device 1 also has a light receiving lens 401 on the rear side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. For example, the light receiving lens 401 is provided in each of the pixel 541A, the pixel 541B, the pixel 541C and the pixel 541D. The camera device 1 is, for example, a back-illuminated camera device. The camera device 1 includes a pixel array portion 540 arranged in a central portion and a peripheral portion 540B arranged outside the pixel array portion 540.

[0174] The first substrate 100 has an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T in order from the light receiving lens 401 side. The semiconductor layer 100S is formed of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the front surface (the surface on the wiring layer 100T side) and its vicinity, and has an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0175] Fig. 7A An example of a planar configuration of the first substrate 100 is shown. Fig. 7A The planar structure of the pixel isolation portion 117, the photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100 is mainly shown. Fig. 7A Together with Figure 6 The structure of the first substrate 100 will be described together.

[0176] The floating diffusion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion FD includes an n-type semiconductor region provided in the p-well layer 115. The floating diffusion FD (floating diffusion FD1, floating diffusion FD2, floating diffusion FD3, and floating diffusion FD4) of each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D is provided, for example, in the pixel common unit 539 ( Fig. 7A ) are close to each other in the central part of the pixel common unit 539. Although the details will be described later, the four floating diffusions (floating diffusion FD1, floating diffusion FD2, floating diffusion FD3 and floating diffusion FD4) included in the pixel common unit 539 are electrically connected to each other by an electrical connection means (pad portion 120 described later) of the first substrate 100 (more specifically, in the wiring layer 100T). In addition, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) by electrical means (through electrode 120E described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG by the electrical means.

[0177] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged away from the floating diffusion FD. For example, in the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end of each pixel in the V direction ( Fig. 7A ). The VSS contact region 118 includes, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is supplied to the semiconductor layer 100S.

[0178] The transfer transistor TR is provided in the first substrate 100 together with the photodiode PD, the floating diffusion FD, and the VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end of the vertical portion TGa is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transmission failure of the pixel signal hardly occurs, and the efficiency of reading the pixel signal can be improved.

[0179] The horizontal portion TGb of the transfer gate TG extends in the H direction from a position facing the vertical portion TGa toward, for example, the central portion of the pixel sharing unit 539 ( Fig. 7A ). Therefore, the position of the through electrode (through electrode TGV described later) reaching the transfer gate TG in the H direction can be made close to the position of the through electrode (through electrode 120E, through electrode 121E described later) connected to the floating diffusion FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel common units 539 provided in the first substrate 100 have the same configuration ( Fig. 7A ).

[0180] In the semiconductor layer 100S, a pixel isolation portion 117 is provided to isolate the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D from each other. The pixel isolation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel isolation portion 117 is provided to separate the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D from each other, and the pixel isolation portion 117 has, for example, a grid-like planar shape ( Fig. 7A and Figure 7B). For example, the pixel isolation unit 117 electrically and optically isolates the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D from each other. The pixel isolation unit 117, for example, includes a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A. The insulating film 117B is disposed between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is formed, for example, of silicon oxide (SiO). The pixel isolation unit 117, for example, has a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel isolation unit 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S can be used. The pixel isolation unit 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial area of ​​the semiconductor layer 100S.

[0181] For example, in the semiconductor layer 100S, a first pinning region 113 and a second pinning region 116 are provided. The first pinning region 113 is provided near the rear surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side of the pixel isolation portion 117, specifically, between the pixel isolation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed, for example, of a p-type semiconductor region.

[0182] The fixed charge film 112 having negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. The first pinning region 113 of the hole accumulation layer is formed at the interface on the light receiving surface (rear) side of the semiconductor layer 100S by the electric field induced by the fixed charge film 112. Therefore, the dark current generated due to the interface state on the light receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is formed, for example, of an insulating film having negative fixed charge. Examples of the material of the insulating film having negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0183] The light shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light shielding film 117A may be provided continuously with the light shielding film 117A constituting the pixel isolation portion 117. The light shielding film 117A between the fixed charge film 112 and the insulating film 111 may be selectively provided, for example, at a position facing the pixel isolation portion 117 in the semiconductor layer 100S. The insulating film 111 is provided to cover the light shielding film 117A. The insulating film 111 is formed of, for example, silicon oxide.

[0184] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, a pad portion 120 and a pad portion 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in order from the semiconductor layer 100S side. For example, the horizontal portion TGb of the transmission gate TG is provided in the wiring layer 100T. The interlayer insulating film 119 is provided on the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is formed of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above description, and may be a configuration including wiring and an insulating film.

[0185] Figure 7B The pad portion 120 and the pad portion 121 are shown together with Fig. 7A The pad portion 120 and the pad portion 121 are provided in a selected region on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of each pixel 541A, pixel 541B, pixel 541C, and pixel 541D. For example, for each pixel common unit 539 ( Figure 7B ), the pad portion 120 is arranged in the center portion of the pixel sharing unit 539 in a plan view. The pad portion 120 is provided across the pixel isolation portion 117, and is arranged to overlap at least a portion of each of the floating diffusion portion FD1, the floating diffusion portion FD2, the floating diffusion portion FD3, and the floating diffusion portion FD4 ( Figure 6 and 7B ). Specifically, the pad portion 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of the shared pixel circuit 210 and at least a portion of the pixel isolation portion 117 formed between the plurality of photodiodes PD (photodiode PD1, photodiode PD2, photodiode PD3, photodiode PD4) of the shared pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100s. The interlayer insulating film 119 is provided with a connection through hole 120C for electrically connecting the pad portion 120 to the floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4. The connection through hole 120C is provided in each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D. For example, by embedding a part of the pad portion 120 in the connection through hole 120C, the pad portion 120 is electrically connected to the floating diffusion FD1 , the floating diffusion FD2 , the floating diffusion FD3 , and the floating diffusion FD4 .

[0186] The pad portion 121 is used to connect the plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 and the VSS contact regions 118 provided in the pixels 541A and 541B of another pixel sharing unit 539 are electrically connected through the pad portion 121, and the one pixel sharing unit 539 and the other pixel sharing unit 539 are adjacent in the V direction. For example, the pad portion 121 is provided to cross the pixel isolation portion 117, and is arranged to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100s. The interlayer insulating film 119 is provided with a connection through hole 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection through hole 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, the pad portion 121 and the VSS contact region 118 are electrically connected by embedding a portion of the pad portion 121 in the connection through hole 121C. For example, the pad portion 120 and the pad portion 121 of each of the plurality of pixel sharing units 539 arranged in the V direction are arranged at approximately the same position in the H direction ( Figure 7B ).

[0187] By providing the pad portion 120, the wiring for connection from each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifier transistor AMP) can be reduced in the entire chip. Similarly, by providing the pad portion 121, the wiring for supplying a potential to each VSS contact region 118 can be reduced in the entire chip. Therefore, it is possible to reduce the area of ​​the entire chip, suppress electrical interference between wirings of miniaturized pixels, and / or reduce costs by reducing the number of components.

[0188] The pad portion 120 and the pad portion 121 may be disposed at desired positions of the first substrate 100 and the second substrate 200. Specifically, the pad portion 120 and the pad portion 121 may be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200s. In the case where the pad portion 120 and the pad portion 121 are disposed in the wiring layer 100T, the pad portion 120 and the pad portion 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portion 120 and the pad portion 121 may be directly connected to at least a portion of each of the floating diffusion portion FD and / or the VSS contact region 118. Furthermore, connection vias 120C and 121C may be provided respectively from the floating diffusion FD and / or the VSS contact region 118 connected to the pad portion 120 and the pad portion 121, and the pad portion 120 and the pad portion 121 may be provided at positions required by the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0189] In particular, in the case where the pad portion 120 and the pad portion 121 are provided in the wiring layer 100T, the wiring for connecting to the floating diffusion portion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200s can be reduced. Therefore, in the second substrate 200 formed with the pixel circuit 210, the area of ​​the insulating region 212 for forming the through wiring connecting the floating diffusion portion FD to the pixel circuit 210 can be reduced. Thus, a large area of ​​the second substrate 200 formed with the pixel circuit 210 can be ensured. By ensuring the area of ​​the pixel circuit 210, a large pixel transistor can be formed, and it helps to improve the image quality by noise reduction and the like.

[0190] In particular, when the pixel isolation portion 117 adopts the FTI structure, since the floating diffusion portion FD and / or the VSS contact area 118 are preferably set in each pixel 541, the wiring connecting the first substrate 100 to the second substrate 200 can be greatly reduced by using the structure of the pad portion 120 and the pad portion 121.

[0191] In addition, if Figure 7B As shown, for example, a pad portion 120 connecting a plurality of floating diffusion portions FD and a pad portion 121 connecting a plurality of VSS contact regions 118 are alternately arranged in a straight line in the V direction. In addition, the pad portion 120 and the pad portion 121 are formed at a position surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion portions FD. Therefore, in the first substrate 100 in which a plurality of elements are formed, elements other than the floating diffusion portion FD and the VSS contact region 118 can be freely arranged, and the layout efficiency of the entire chip can be improved. In addition, the symmetry of the layout of the elements formed in each pixel common unit 539 is ensured, and the difference in the characteristics of each pixel 541 can be suppressed.

[0192] The pad portion 120 and the pad portion 121 are formed of, for example, polysilicon (Poly Si), more specifically, doped polysilicon doped with impurities. The pad portion 120 and the pad portion 121 are preferably formed of a conductive material having high heat resistance such as polysilicon, tungsten (W), titanium (Ti) or titanium nitride (TiN). Therefore, the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason will be explained below. Note that in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0193] Here, it is also conceivable to form the pixel circuit 210 on the second substrate 200 and then bond the second substrate 200 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on each of the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 200 (the front surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded to each other, at the same time, the electrodes for electrical connection formed on the front surface of the first substrate 100 and the front surface of the second substrate 200, respectively, contact each other. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the structure of the imaging device 1 using the second manufacturing method, for example, it is possible to manufacture using an appropriate process according to the structure of each of the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

[0194] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded to each other, an alignment error may occur due to the manufacturing equipment used for bonding. In addition, the size of the first substrate 100 and the second substrate 200 is, for example, about tens of centimeters in diameter, but when the first substrate 100 and the second substrate 200 are bonded to each other, there is the possibility that the expansion and contraction of the substrate occurs in the microscopic area of ​​the corresponding parts of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrate is caused by a slight offset when the substrate and the substrate are in contact with each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, the position of the electrode for electrical connection formed on the front surface of the first substrate 100 and the front surface of the second substrate 200, respectively, may have an error. In the second manufacturing method, even if such an error occurs, it is preferred to take measures to make the electrodes of the first substrate 100 and the second substrate 200 contact each other. Specifically, in view of the above-mentioned error, at least one of the electrodes in the first substrate 100 and the second substrate 200 is increased, preferably both. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the front surface of the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) is larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 to the front surface in the thickness direction.

[0195] On the other hand, the pad portion 120 and the pad portion 121 are formed of a conductive material having heat resistance, so that the first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded to each other. In this case, the second substrate 200 is in a state where patterns such as active elements and wiring layers constituting the pixel circuit 210 are not formed. Since the second substrate 200 is in a state before pattern formation, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, the bonding error does not cause an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded. For example, when forming a pattern on the second substrate, in an exposure device for forming a pattern, the pattern is formed while setting the pattern formed on the first substrate as an alignment target. For the above reasons, in the process of manufacturing the image pickup device 1 by the first manufacturing method, an error in the bonding position between the first substrate 100 and the second substrate 200 does not cause a problem. For the same reason, in the process of manufacturing the image pickup device 1 by the first manufacturing method, an error due to expansion and contraction of the substrate occurring in the second manufacturing method does not cause a problem.

[0196] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded in this manner, an active element is formed on the second substrate 200. Then, the through electrodes 120E and 121E and the through electrodes TGV ( Figure 6 ). In the formation of the through-electrode 120E, the through-electrode 121E, and the through-electrode TGV, for example, a pattern of the through-electrode is formed from above the second substrate 200 using reduced projection exposure performed by an exposure device. Since the reduced exposure projection is used, even if an alignment error occurs between the second substrate 200 and the exposure device, the size of the error in the second substrate 200 is only a fraction of the error of the second manufacturing method (the inverse of the magnification of the reduced exposure projection). Therefore, by adopting the configuration of the image pickup device 1 using the first manufacturing method, it is easy to align the elements formed on each of the first substrate 100 and the second substrate 200, and it is possible to manufacture an image pickup device with high quality and high performance.

[0197] The image pickup device 1 manufactured using the first manufacturing method has different features from the image pickup device manufactured by the second manufacturing method. Specifically, in the image pickup device 1 manufactured by the first manufacturing method, for example, the through electrode 120E, the through electrode 121E, and the through electrode TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrode 120E, the through electrode 121E, and the through electrode TGV have a conical shape, the through electrode 120E, the through electrode 121E, and the through electrode TGV have a conical shape with a constant inclination. In the image pickup device 1 including such a through electrode 120E, the through electrode 121E, and the through electrode TGV, it is easy to miniaturize the pixel 541.

[0198] Here, when the image pickup device 1 is manufactured by the first manufacturing method, since active elements are formed on the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded to each other, the first substrate 100 is also affected by the heat treatment required to form the active elements. Therefore, as described above, a conductive material with high heat resistance is preferably used for the pad portion 120 and the pad portion 121 provided on the first substrate 100. For example, the pad portion 120 and the pad portion 121 are preferably formed of a material having a higher melting point (i.e., higher heat resistance) than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad portion 120 and the pad portion 121. Therefore, the image pickup device 1 can be manufactured using the first manufacturing method.

[0199] For example, the passivation film 122 is disposed over the entire front surface of the semiconductor layer 100S to cover the pad portion 120 and the pad portion 121 ( Figure 6 ). The passivation film 122 is formed of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portion 120 and the pad portion 121, and the passivation film 122 is sandwiched between the interlayer insulating film 123 and the pad portion 120 and the pad portion 121. For example, the interlayer insulating film 123 is arranged above the entire front surface of the semiconductor layer 100S. The interlayer insulating film 123 is formed of, for example, a silicon oxide (SiO) film. The bonding film 124 is arranged on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is arranged on the entire main surface of the first substrate 100. The bonding film 124 is formed of, for example, a silicon nitride film.

[0200] The light receiving lens 401 faces the semiconductor layer 100S, for example, with the fixed charge film 112 and the insulating film 111 sandwiched therebetween ( Figure 6 ). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D.

[0201] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S is formed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 20 is provided with a pixel circuit 210 arranged for each pixel common unit 539. The pixel circuit 210 is, for example, provided on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 so that the rear surface side (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate. That is, the second substrate 200 is bonded to the first substrate 100 in a face-to-back manner.

[0202] Figures 8 to 12 An example of a planar configuration of the second substrate 200 is schematically shown. Figure 8 The configuration of the pixel circuit 210 provided near the front surface of the semiconductor layer 200S is shown. Fig. 9 The configurations of the wiring layer 200T (specifically, a first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each portion of the first substrate 100 are schematically shown. Figures 10 to 12 An example of a planar configuration of the wiring layer 200T is shown. Figures 8 to 12 Together with Figure 6The structure of the second substrate 200 is described together. Figure 8 and Fig. 9 , the outer shape of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dotted line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping with the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dashed line. In the portion overlapping with the gate electrode of the amplifier transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 212 are both set on one side in the trench width direction.

[0203] The second substrate 200 is provided with an insulating region 212 separating the semiconductor layer 200S and an element isolation region 213 ( Figure 6 ). For example, the through-electrode 120E and the through-electrode 121E and the through-electrode TGV (through-electrode TGV1, through-electrode TGV2, through-electrode TGV3, and through-electrode TGV4) of the two pixel common units 539 connected to two pixel circuits 210 adjacent in the H direction are arranged in the insulating region 212 provided between the two pixel circuits 210 ( Fig. 9 ).

[0204] The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 200S ( Figure 6 ). The semiconductor layer 200S is divided by the insulating region 212. The through-electrodes 120E and 121E and the through-electrode TGV are arranged in the insulating region 212. The insulating region 212 is formed of, for example, silicon oxide.

[0205] The through-electrode 120E and the through-electrode 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through-electrode 120E and the through-electrode 121E are connected to the wirings (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later) of the wiring layer 200T. The through-electrode 120E and the through-electrode 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends of the through-electrode 120E and the through-electrode 121E are connected to the pad portion 120 and the pad portion 121 ( Figure 6). The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion portion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the VSS contact area 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0206] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and the lower end of the through electrode TGV is connected to the transmission gate TG( Figure 6 ). This through electrode TGV is used to electrically connect the transfer gate TG (transfer gate TG1, transfer gate TG2, transfer gate TG3, and transfer gate TG4) of each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D to the wiring of the wiring layer 200T (a part of the row drive signal line 542, specifically, the wiring TRG1, the wiring TRG2, the wiring TRG3, and the wiring TRG4 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and the drive signal is transmitted to the respective transfer transistors TR (transfer transistor TR1, transfer transistor TR2, transfer transistor TR3, and transfer transistor TR4).

[0207] The insulating region 212 is a region for insulating the through-electrodes 120E and 121E and the through-electrodes TGV (which are used to electrically connect the first substrate 100 to the second substrate 200) from the semiconductor layer 200S. For example, the through-electrodes 120E and 121E and the through-electrodes TGV (through-electrode TGV1, through-electrode TGV2, through-electrode TGV3, and through-electrode TGV4) connected to two pixel circuits 210 adjacent in the H direction are arranged in the insulating region 212 provided between the two pixel circuits 210 (pixel common unit 539). For example, the insulating region 212 is provided to extend in the V direction ( Figure 8 and Fig. 9 Here, by designing the arrangement of the horizontal portion TGb of the transfer gate TG, the through electrode TGV is arranged so that the position of the through electrode TGV in the H direction is closer to the positions of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa ( Fig. 7A and 9). For example, the through electrode TGV is arranged at approximately the same position as the through electrode 120E and the through electrode 121E in the H direction. Therefore, the through electrode 120E and the through electrode 121E and the through electrode TGV can be jointly arranged in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to arrange the horizontal portion TGb only in the area overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and, for example, the through electrode TGV is arranged in the approximately central part of the H direction and the V direction of each pixel 541. In this case, the position of the through electrode TGV in the H direction greatly deviates from the position of the through electrode 120E and the through electrode 121E in the H direction. For example, an insulating region 212 is arranged around the through electrode TGV and the through electrode 120E and the through electrode 121E to electrically insulate the through electrode TGV and the through electrode 120E and the through electrode 121E from the adjacent semiconductor layer 200S. In the case where the position of the through electrode TGV in the H direction is greatly separated from the position of the through electrode 120E and the through electrode 121E in the H direction, it is necessary to independently provide the insulating region 212 around each of the through electrode 120E, the through electrode 121E, and the through electrode TGV. Therefore, the semiconductor layer 200S is finely divided. In contrast, the layout in which the through electrode 120E and the through electrode 121E and the through electrode TGV are jointly arranged in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. Therefore, a large area of ​​the semiconductor element formation region of the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0208] As reference Figure 4 As described above, the pixel sharing unit 539 has the following structure: wherein the floating diffusion portions FD respectively provided in the plurality of pixels 541 are electrically connected, and the plurality of pixels 541 share one pixel circuit 210. The floating diffusion portion FD is electrically connected via the pad portion 120 provided on the first substrate 100 ( Figure 6 and Figure 7B). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via a through electrode 120E. As another structural example, it is also conceivable to provide an electrical connection portion between the floating diffusion portions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes respectively connected to the floating diffusion portion FD1, the floating diffusion portion FD2, the floating diffusion portion FD3 and the floating diffusion portion FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S is increased, and the insulating region 212 that insulates the periphery of these through electrodes is increased. In contrast, in the structure in which the pad portion 120 is provided on the first substrate 100 ( Figure 6 and Figure 7B ), the number of through electrodes can be reduced, and the insulating region 212 can be reduced. Therefore, a large area of ​​the semiconductor element formation region of the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0209] The element isolation region 213 is arranged on the front surface side of the semiconductor layer 200S. The element isolation region 213 has a shallow trench isolation (STI) structure. In the element isolation region 213, the semiconductor layer 200S is excavated in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the excavated portion. The insulating film is formed of silicon oxide, for example. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (the deep part of the semiconductor layer 200S).

[0210] Here, refer to Fig. 7A , Figure 7B and Figure 8 , the difference between the outer shape of the pixel common unit 539 on the first substrate 100 (the outer shape in the substrate plane direction) and the outer shape of the pixel common unit 539 on the second substrate 200 will be described.

[0211] In the image pickup device 1, the pixel common unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel common unit 539 provided on the first substrate 100 is different from the outer shape of the pixel common unit 539 provided on the second substrate 200.

[0212] exist Fig. 7A and Figure 7B, the outlines of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D are shown by a single-dot chain line, and the outer shape of the pixel common unit 539 is shown by a bold line. For example, the pixel common unit 539 of the first substrate 100 includes two pixels 541 (pixel 541A and pixel 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixel 541A and pixel 541C) arranged adjacent to each other in the V direction. That is, the pixel common unit 539 of the first substrate 100 includes four pixels 541 of adjacent 2 rows×2 columns, and the pixel common unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array section 540, these pixel common units 539 are arranged adjacent to each other at a two-pixel pitch (a pitch corresponding to the two pixels 541) in the H direction and at a two-pixel pitch (a pitch corresponding to the two pixels 541) in the V direction.

[0213] exist Figure 8 and Fig. 9 , the outlines of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D are shown by a single-dot chain line, and the outer shape of the pixel common unit 539 is shown by a bold line. For example, the outer shape of the pixel common unit 539 of the second substrate 200 is smaller than the outer shape of the pixel common unit 539 of the first substrate 100 in the H direction, and is larger than the outer shape of the pixel common unit 539 of the first substrate 100 in the V direction. For example, the pixel common unit 539 of the second substrate 200 is formed in a size (area) corresponding to one pixel in the H direction, and is formed in a size corresponding to four pixels in the V direction. That is, the pixel common unit 539 of the second substrate 200 is formed in a size corresponding to the pixels arranged in adjacent 1 row×4 columns, and the pixel common unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0214] For example, in each pixel circuit 210, a selection transistor SEL, an amplification transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG are arranged in this order in the V direction ( Figure 8 By setting the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, four transistors (select transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) can be arranged side by side in one direction ( Figure 8 Therefore, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared in a substantially square shape (refer to the later described Fig.21) The formation area of ​​each pixel circuit 210 is set. In this case, two transistors are arranged along one direction, and it is difficult to share the drain of the amplifier transistor AMP and the drain of the reset transistor RST in one diffusion area. Therefore, by setting the formation area of ​​the pixel circuit 210 in a substantially rectangular shape, it is easy to arrange four transistors close to each other, and the formation area of ​​the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, the formation area of ​​the amplifier transistor AMP can be increased, and noise can be suppressed.

[0215] In addition to the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the front surface of the semiconductor layer 200S, for example. The VSS contact region 218 includes, for example, a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) through the wiring of the wiring layer 200T and the through electrode 121E. For example, the VSS contact region 218 is provided at a position adjacent to the source of the FD conversion gain switching transistor FDG, and the element isolation region 213 is sandwiched between the VSS contact region 218 and the source ( Figure 8 ).

[0216] Next, we will refer to Figure 7B and Figure 8 The positional relationship between the pixel common unit 539 disposed on the first substrate 100 and the pixel common unit 539 disposed on the second substrate 200 is described. For example, one pixel common unit 539 (for example, Figure 7B ) is connected to one pixel common unit 539 (for example, Figure 8 For example, the other pixel common unit 539 (eg, Figure 7B The lower side of the paper) is connected to the other pixel common unit 539 (for example, Figure 8 on the right side of the paper).

[0217] For example, of the two pixel common units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel common unit 539 is substantially equal to the layout obtained by inverting the internal layout of the other pixel common unit 539 in the V direction and the H direction. Hereinafter, the effect obtained by this layout will be described.

[0218] In the two pixel sharing units 539 arranged in the V direction on the first substrate 100, each pad portion 120 is provided at the central portion of the outer shape of the pixel sharing unit 539, that is, at the pixel sharing unit 539 in the V direction and the H direction ( Figure 7B ) in the center part. On the other hand, since the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular shape in the V direction as described above, for example, the amplifier transistor AMP connected to the pad portion 120 is arranged at a position offset upward in the paper from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layout of two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, the distance between the amplifier transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper of FIG. 7 ) becomes relatively short. However, the distance between the amplifier transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper of FIG. 7 ) becomes longer. Therefore, the wiring area required for the connection between the amplifier transistor AMP and the pad portion 120 is increased, and the wiring layout of the pixel sharing unit 539 may become complicated. This may affect the miniaturization of the imaging device 1.

[0219] On the other hand, the internal layout of the two pixel common units 539 arranged in the H direction on the second substrate 200 is reversed at least in the V direction, so that the distance between the amplifier transistor AMP and the pad portion 120 of both the two pixel common units 539 can be shortened. Therefore, compared with a configuration in which the internal layout of the two pixel common units 539 arranged in the H direction on the second substrate 200 is the same, it is easy to miniaturize the image pickup device 1. Note that the planar layout of the plurality of pixel common units 539 on the second substrate 200 is reversed in the V direction. Figure 8 The range shown is bilaterally symmetrical, but includes the Fig. 9 The layout of the first wiring layer W1 shown is bilaterally asymmetrical.

[0220] In addition, preferably, the internal layout of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 is also reversed in the H direction. The reason will be explained below. Fig. 9As shown, each of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 is connected to the pad portion 120 and the pad portion 121 of the first substrate 100. For example, the pad portion 120 and the pad portion 121 are arranged at the central portion in the H direction of the two pixel sharing units 539 (between the two pixel sharing units 539 arranged in the H direction), and the two pixel sharing units 539 are arranged in the H direction on the second substrate 200. Therefore, the internal layout of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 is also reversed in the H direction, so that the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portion 120 and the pad portion 121 can be reduced. That is, it is easier to miniaturize the image pickup device 1.

[0221] In addition, the position of the outline of the pixel common unit 539 of the second substrate 200 may not be aligned with the position of any outline of the pixel common unit 539 of the first substrate 100. For example, one pixel common unit 539 (e.g., Fig. 9 On the left side of the paper), on one side in the V direction (for example, Fig. 9 The outline of the pixel sharing unit 539 (eg, the upper side of the paper) is arranged on the corresponding pixel sharing unit 539 of the first substrate 100. Figure 7B In addition, the other pixel common unit 539 (for example, Fig. 9 On the right side of the paper), on the other side in the V direction (for example, Fig. 9 The outline of the corresponding pixel sharing unit 539 (eg, Fig. 9 As described above, by mutually arranging the pixel common unit 539 of the second substrate 200 and the pixel common unit 539 of the first substrate 100, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0222] In addition, the positions of the contours of the plurality of pixel sharing units 539 of the second substrate 200 may not be aligned. For example, two pixel sharing units 539 arranged in the H direction on the second substrate 200 are arranged so that the positions of the contours in the V direction are offset. Therefore, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the camera device 1.

[0223] Will refer to Figure 7B and Fig. 9The pixel common unit 539 in the pixel array section 540 is described as being repeatedly arranged. The pixel common unit 539 of the first substrate 100 has a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction ( Figure 7B ). For example, in the pixel array portion 540 of the first substrate 100, pixel sharing units 539 having a size corresponding to four pixels 541 are repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (corresponding to a pitch of two pixels 541) and at a two-pixel pitch in the V direction (corresponding to a pitch of two pixels 541). Alternatively, in the pixel array portion 540 of the first substrate 100, pairs of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction may be provided. In the pixel array portion 540 of the first substrate 100, pairs of pixel sharing units 539 are repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (corresponding to a pitch of two pixels 541) and at a four-pixel pitch in the V direction (corresponding to a pitch of four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Fig. 9 ). For example, in the pixel array portion 540 of the second substrate 200, pairs of pixel sharing units 539 are provided, and each pair of pixel sharing units 539 includes two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction, and are arranged to be offset in the V direction. In the pixel array portion 540 of the second substrate 200, a plurality of pairs of pixel sharing units 539 are repeatedly arranged adjacent to each other without gaps in the H direction at a two-pixel pitch (corresponding to the pitch of two pixels 541) and in the V direction at a four-pixel pitch (corresponding to the pitch of four pixels 541). This arrangement of the pixel sharing units 539 makes it possible to arrange the pixel sharing units 539 without gaps. Therefore, it is easy to miniaturize the imaging device 1.

[0224] Preferably, the amplifying transistor AMP has a Fin type ( Figure 6 ) and other three-dimensional structures. Therefore, the size of the effective gate width is increased, and noise can be suppressed. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplifier transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0225] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221, for example, contacts the front surface of the semiconductor layer 200S and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of each of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4) are isolated by the interlayer insulating film 222. The interlayer insulating film 222 is formed, for example, of silicon oxide.

[0226] In the wiring layer 200T, for example, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, the fourth wiring layer W4, and the contact portion 201 and the contact portion 202 are sequentially provided from the semiconductor layer 200S side, and they are insulated from each other by the interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection portions are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3 or the fourth wiring layer W4 and the lower layer thereof. The connection portion is a portion in which a conductive material is embedded in a connection hole provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection portion 218V is provided to connect the first wiring layer W1 and the VSS contact area 218. For example, the hole diameter of the connection portion connecting the element of the second substrate 200 is different from the hole diameter of the through electrode 120E and the through electrode 121E and the through electrode TGV. Specifically, preferably, the aperture of the connection hole connecting the element of the second substrate 200 is smaller than the aperture of the through-electrode 120E, the through-electrode 121E, and the through-electrode TGV. The reason will be explained below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through-electrode 120E, the through-electrode 121E, and the through-electrode TGV. Therefore, in the connection portion, the connection hole can be easily filled with a conductive material compared to the through-electrode 120E, the through-electrode 121E, and the through-electrode TGV. By making the aperture of the connection portion smaller than the aperture of the through-electrode 120E, the through-electrode 121E, and the through-electrode TGV, it is easy to miniaturize the camera device 1.

[0227] For example, the through electrode 120E is connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG through the first wiring layer W1 (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). The first wiring layer W1, for example, connects the through electrode 121E to the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S with the VSS contact region 118 of the semiconductor layer 100S.

[0228] Next, we will refer to Figures 10 to 12 The planar structure of the wiring layer 200T will be described. Fig.10 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Fig.11 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Fig.12 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0229] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Fig.11 ). These wirings correspond to the reference Figure 4 The plurality of row drive signal lines 542 described. Wiring TRG1, wiring TRG2, wiring TRG3 and wiring TRG4 are used to transmit drive signals to transmission gate TG1, transmission gate TG2, transmission gate TG3 and transmission gate TG4, respectively. Wiring TRG1, wiring TRG2, wiring TRG3 and wiring TRG4 are respectively connected to transmission gate TG1, transmission gate TG2, transmission gate TG3 and transmission gate TG4 through the second wiring layer W2, the first wiring layer W1 and the through electrode 120E. Wiring SELL is used to transmit a drive signal to the gate of the selection transistor SEL, wiring RSTL line is used to transmit a drive signal to the gate of the reset transistor RST, and wiring FDGL is used to transmit a drive signal to the gate of the FD conversion gain switching transistor FDG. Wiring SELL, wiring RSTL and wiring FDGL are respectively connected to the gates of the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG through the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0230] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 ( Fig.12 ). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0231] The contact portion 201 and the contact portion 202 may be disposed at a position overlapping with the pixel array portion 540 in a plan view (eg, Figure 3 ), or may be provided in the peripheral portion 540B outside the pixel array portion 540 (for example, Figure 6 ). The contact portion 201 and the contact portion 202 are provided on the front surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portion 201 and the contact portion 202 are formed of, for example, a metal such as copper (Cu) and aluminum (Al). The contact portion 201 and the contact portion 202 are exposed on the front surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portion 201 and the contact portion 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding between the second substrate 200 and the third substrate 300.

[0232] Figure 6 2 shows an example of a peripheral circuit disposed in the peripheral portion 540B of the second substrate 200. The peripheral circuit may include a portion of the row driving unit 520, a portion of the column signal processing unit 550, etc. Figure 3 As shown, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200 , and the connection hole portion H1 and the connection hole portion H2 may be arranged near the pixel array portion 540 .

[0233] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in sequence from the second substrate 200 side. For example, the front surface of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S is formed by a silicon substrate. A circuit is arranged in a portion of the front surface side of the semiconductor layer 300S. Specifically, for example, at least a portion of the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is arranged in a portion of the front surface side of the semiconductor layer 300S. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200, for example, includes an interlayer insulating film, a plurality of wiring layers isolated by the interlayer insulating film, and contact portions 301 and 302. The contact portion 301 and the contact portion 302 are exposed on the front surface (surface on the second substrate 200 side) of the wiring layer 300T, and the contact portion 301 contacts the contact portion 201 of the second substrate 200, and the contact portion 302 contacts the contact portion 202 of the second substrate 200. The contact portion 301 and the contact portion 302 are electrically connected to the circuit formed in the semiconductor layer 300S (for example, at least one of the input unit 510A, the row driving unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B). For example, the contact portion 301 and the contact portion 302 are formed of a metal such as copper (Cu) and aluminum (Al). For example, the external terminal TA is connected to the input unit 510A through the connection hole portion H1, and the external terminal TB is connected to the output unit 510B through the connection hole portion H2.

[0234] Here, features of the image pickup device 1 will be described.

[0235] In general, an image pickup device mainly includes a photodiode and a pixel circuit. Here, when the area of ​​the photodiode increases, the charge generated due to photoelectric conversion increases, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and the image pickup device can output better image data (image information). On the other hand, when the size of the transistor included in the pixel circuit (particularly, the size of the amplifying transistor) increases, the noise generated in the pixel circuit decreases, thereby improving the S / N ratio of the image pickup signal, and the image pickup device can output better image data (image information).

[0236] However, in an image pickup device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased in a limited area of ​​the semiconductor substrate, the size of the transistor included in the pixel circuit is reduced. In addition, if the size of the transistor included in the pixel circuit is increased, the area of ​​the photodiode is reduced.

[0237] In order to solve these problems, for example, the image pickup device 1 of the present embodiment adopts a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, within the limited area of ​​the semiconductor substrate, it is possible to make the area of ​​the photodiode PD as large as possible, and to make the size of the transistor included in the pixel circuit 210 as large as possible. Therefore, the S / N ratio of the pixel signal can be improved, and the image pickup device 1 can output better image data (image information).

[0238] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD, a plurality of wirings connected to the one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to ensure a large area of ​​the semiconductor substrate 200 on which the pixel circuit 210 is formed, for example, a connection wiring that connects a plurality of extended wirings to each other and integrates the plurality of extended wirings into one may be formed. Similarly, for a plurality of wirings extending from the VSS contact region 118, a connection wiring that connects a plurality of extended wirings to each other and integrates the plurality of extended wirings into one may be formed.

[0239] For example, when a connection wiring that connects a plurality of wirings extending from the floating diffusion FD of each of the plurality of pixels 541 to each other is formed in the semiconductor substrate 200 in which the pixel circuit 210 is formed, the area for forming the transistors included in the pixel circuit 210 can be reduced. Similarly, when a connection wiring that connects and integrates a plurality of wirings extending from the VSS contact region 118 of each of the plurality of pixels 541 is formed in the semiconductor substrate 200 in which the pixel circuit 210 is formed, the area for forming the transistors included in the pixel circuit 210 can be reduced.

[0240] In order to solve these problems, for example, the camera device 1 of the present embodiment may have a structure in which a plurality of pixels 541 share a pixel circuit 210, the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD, and the first substrate 100 is provided with a connecting wiring that connects the floating diffusion portions FD of the plurality of pixels 541 to each other and integrates them into one, and a connecting wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other and integrates them into one.

[0241] Here, for example, when the above-mentioned second manufacturing method is used as a connection wiring for connecting the floating diffusion portions FD of a plurality of pixels 541 to each other and integrating them into one and connecting the VSS contact regions 118 included in the plurality of pixels 541 to each other and integrating them into one on the first substrate 100, the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, and an image pickup device with high quality and high performance can be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, in the case of using the second manufacturing method, an electrode connected to the floating diffusion portion FD and an electrode connected to the VSS contact region 118 are respectively provided on the front surface of the first substrate 100 and the front surface of the second substrate 200, which are the bonding boundary surfaces of the first substrate 100 and the second substrate 200. In addition, even if a positional deviation occurs between the electrodes provided on the front surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together, it is preferable to expand the electrodes formed on the front surfaces of the two substrates so that the electrodes formed on the front surfaces of the two substrates are in contact with each other. In this case, it is conceivable that it will become difficult to arrange electrodes in a limited area of ​​each pixel included in the image pickup device 1 .

[0242] In order to solve the problem that a large electrode is required at the bonding boundary surface of the first substrate 100 and the second substrate 200, for example, in the image pickup device 1 of the present embodiment, the above-mentioned first manufacturing method can be used as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, it is easy to align the elements formed on the first substrate 100 and the second substrate 200, and it is possible to manufacture a high-quality and high-performance image pickup device. In addition, it is possible to set a unique structure generated by using this manufacturing method (i.e., a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence), in other words, to set a structure in which the first substrate 100 and the second substrate 200 are stacked face to back, and to set a through electrode 120E and a through electrode 121E that penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S of the second substrate 200 and reach the front surface of the semiconductor layer 100S of the first substrate 100.

[0243] In a structure in which the first substrate 100 is provided with connection wiring that connects the floating diffusion portions FD of a plurality of pixels 541 to one another and integrates the floating diffusion portions FD into one, and connection wiring that connects the VSS contact areas 118 of a plurality of pixels 541 to one another and integrates the VSS contact areas 118 into one, when the structure is stacked with the second substrate 200 using the first manufacturing method and a pixel circuit 210 is formed on the second substrate 200, there is a possibility that heat treatment required when forming active elements included in the pixel circuit 210 affects the connection wiring formed on the first substrate 100.

[0244] Therefore, in order to solve the problem of the influence of the heat treatment when forming the active element on the connection wiring, it is desirable that in the image pickup device 1 of the present embodiment, a conductive material having high heat resistance is used for the connection wiring that connects the floating diffusion portions FD of the plurality of pixels 541 to each other and integrates the floating diffusion portions FD into one and the connection wiring that connects the VSS contact regions 118 of the plurality of pixels 541 to each other and integrates the VSS contact regions 118 into one. Specifically, as the conductive material having high heat resistance, a material having a melting point higher than the melting point of at least a part of the wiring material included in the wiring layer 200T of the second substrate 200 can be used.

[0245] As described above, for example, the image pickup device 1 according to the embodiment includes: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked in a face-to-back manner (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100, and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which the through-electrode 120E and the through-electrode 121E are provided which penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S of the second substrate 200 and reach the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusion portion F included in the plurality of pixels 541 is connected to the floating diffusion portion F D A structure in which the connecting wiring that connects the floating diffusion portions FD to each other and integrates the floating diffusion portions FD into one, and the connecting wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other and integrates the VSS contact areas 118 into one are formed of a conductive material having high heat resistance, so that without providing a large electrode at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 can be provided with a connecting wiring that connects the floating diffusion portions FD included in the plurality of pixels 541 to each other and integrates the floating diffusion portions FD into one, and a connecting wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other and integrates the VSS contact areas 118 into one.

[0246] [Operation of the Image Capture Device 1]

[0247] Next, we will refer to Fig.13 and Fig.14 The operation of the imaging device 1 will be described. Fig.13 and 14 By adding arrows indicating the paths of the individual signals to Figure 3 Obtained by Fig.13 In FIG. 1 , arrows are used to show the paths of input signals input from the outside to the image pickup device 1 and the power supply potential and reference potential. Fig.14 , a signal path of a pixel signal output from the image pickup device 1 to the outside is shown by an arrow. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the image pickup device 1 through the input unit 510A is transmitted to the row drive unit 520 of the third substrate 300, and the row drive unit 520 generates a row drive signal. The row drive signal is transmitted to the second substrate 200 through the contact portion 301 and the contact portion 201. In addition, the row drive signal reaches each pixel common unit 539 of the pixel array portion 540 through the row drive signal line 542 of the wiring layer 200T. Among the row drive signals reaching the pixel common unit 539 of the second substrate 200, the drive signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 through the through electrode TGV, and drives the pixels 541A, 541B, 541C, and 541D ( Fig.13 ). In addition, the power supply potential and the reference potential supplied from the outside of the image pickup device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 through the contact portion 301 and the contact portion 201, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D of the first substrate 100 through the through electrode 121E. On the other hand, the pixel signal photoelectrically converted by the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200 of each pixel common unit 539 through the through electrode 120E. The pixel signal based on the above-mentioned pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 through the vertical signal line 543 and the contact portion 202 and the contact portion 302. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300 and then output to the outside through the output unit 510B.

[0248] [Effect]

[0249] In the present embodiment, the pixel 541A, the pixel 541B, the pixel 541C and the pixel 541D (the pixel common unit 539) and the pixel circuit 210 are arranged on different substrates (the first substrate 100 and the second substrate 200). Therefore, compared with the case where the pixel 541A, the pixel 541B, the pixel 541C and the pixel 541D and the pixel circuit 210 are formed on the same substrate, the area of ​​the pixel 541A, the pixel 541B, the pixel 541C and the pixel 541D and the pixel circuit 210 can be expanded. Therefore, it is possible to increase the amount of pixel signals obtained by photoelectric conversion, and reduce the transistor noise of the pixel circuit 210. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the camera 1 can output better pixel data (image information). In addition, the camera 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the camera 1 can be reduced). The camera 1 can increase the number of pixels per unit area by reducing the pixel size, and can output high-quality images.

[0250] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through the through electrode 120E and the through electrode 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting the first substrate 100 and the second substrate 200 by through wiring (for example, through silicon via (TSV)) penetrating the semiconductor layer can be considered. Compared with these methods, by providing the through electrode 120E and the through electrode 121E in the insulating region 212, the area required for connection between the first substrate 100 and the second substrate 200 can be reduced. Therefore, the pixel size can be reduced, and the imaging device 1 can be further miniaturized. In addition, by further reducing the area of ​​each pixel, the resolution can be further improved. When it is not necessary to reduce the chip size, the formation area of ​​the pixel 541A, the pixel 541B, the pixel 541C and the pixel 541D and the pixel circuit 210 can be expanded. Thereby, the pixel signal amount obtained by photoelectric conversion can be increased, and the noise of the transistor included in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the image pickup device 1 can output better pixel data (image information).

[0251] In addition, in the camera device 1, the pixel circuit 210 and the column signal processing unit 550 and the image signal processing unit 560 are arranged on different substrates (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210, the column signal processing unit 550 and the image signal processing unit 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the area of ​​the column signal processing unit 550 and the image signal processing unit 560 can be expanded. Therefore, the noise generated by the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be installed through the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the camera device 1 can output better pixel data (image information).

[0252] In addition, in the image pickup device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing unit 550 and the image signal processing unit 560 are provided on the third substrate 300. In addition, the contact portions 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the layout of the contact portions 201, 202, 301, and 302 can be freely arranged without being disturbed by the layout of various wirings arranged in the pixel array. Therefore, the contact portions 201, 202, 301, and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. For example, by using the contact portions 201, 202, 301, and 302, the column signal processing unit 550 and the image signal processing unit 560 have a higher degree of freedom in layout. Therefore, noise generated by the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be installed through the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the camera 1 can output better pixel data (image information).

[0253] In addition, in the image pickup device 1, the pixel isolation portion 117 penetrates the semiconductor layer 100S. Therefore, even if the distance between adjacent pixels (pixel 541A, pixel 541B, pixel 541C, and pixel 541D) is shortened due to the miniaturization of each pixel area, color mixing between the pixels 541A, pixel 541B, pixel 541C, and pixel 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the image pickup device 1 can output better pixel data (image information).

[0254] In addition, in the image pickup device 1, the pixel circuit 210 is provided for each pixel common unit 539. Therefore, compared with the case where the pixel circuit 210 is provided in each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D, the formation area of ​​the transistors (amplifier transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 can be expanded. For example, by increasing the formation area of ​​the amplifier transistor AMP, noise can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the image pickup device 1 can output better pixel data (image information).

[0255] Furthermore, in the image pickup device 1, a pad portion 120 electrically connecting the floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of four pixels (pixel 541A, pixel 541B, pixel 541C, and pixel 541D) is provided on the first substrate 100. Therefore, compared with the case where the pad portion 120 is provided on the second substrate 200, the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, by reducing the insulating region 212, the formation area of ​​the transistor (semiconductor layer 200S) constituting the pixel circuit 210 can be ensured with a sufficient size. Therefore, the noise of the transistor included in the pixel circuit 210 can be reduced, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0256] Hereinafter, a modification of the image pickup device 1 according to the above-described embodiment will be described. In the following modification, the same reference numerals are given to the same configuration as the above-described embodiment.

[0257] <2. First Modification>

[0258] Figures 15 to 19 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.15 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and is similar to that described in the above embodiment. Figure 8 Corresponding. Fig.16 The configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100 is schematically shown, and is similar to that described in the above embodiment. Fig. 9 Corresponding. Fig.17 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and is similar to that described in the above embodiment. Fig.10 Corresponding. Fig.18An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and is similar to that described in the above embodiment. Fig.11 Corresponding. Fig.19 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and is similar to that described in the above embodiment. Fig.12 Corresponding.

[0259] In this variation, if Fig.16 As shown, in the two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (for example, the right side of the paper) is obtained by inverting the internal layout of the other pixel sharing unit 539 (for example, the left side of the paper) only in the H direction. In addition, the deviation between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 in the V direction is greater than the deviation described in the above embodiment ( Fig. 9 ). In this way, by increasing the deviation in the V direction, the distance between the amplifier transistor AMP of the other pixel sharing unit 539 and the pad portion 120 connected thereto (the pad portion 120 of the other pixel sharing unit 539 (lower side of the paper) of the two pixel sharing units 539 arranged in the V direction shown in FIG. 7) can be reduced. Using this layout, Figures 15 to 19 The first modification of the imaging device 1 shown in the figure can make the area of ​​the two pixel sharing units 539 arranged in the H direction the same as the area of ​​the pixel sharing unit 539 of the second substrate 200 described in the above embodiment, without reversing the plane layout of the two pixel sharing units 539 in the V direction. Note that the plane layout of the pixel sharing unit 539 of the first substrate 100 is different from the plane layout described in the above embodiment ( Fig. 7A and Figure 7B ). Therefore, the image pickup device 1 of this modification can obtain the same effect as the image pickup device 1 described in the above embodiment. The arrangement of the pixel common unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0260] <3. Second Modification>

[0261] Figure 20 to Figure 25 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig. 20 The planar structure of the first substrate 100 is schematically shown and is similar to that described in the above embodiment. Fig. 7A Corresponding. Fig.21 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and is similar to that described in the above embodiment. Figure 8 Corresponding. Fig. 22The configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100 is schematically shown, and is similar to that described in the above embodiment. Fig. 9 Corresponding. Fig.23 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and is similar to that described in the above embodiment. Fig.10 Corresponding. Fig.24 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and is similar to that described in the above embodiment. Fig.11 Corresponding. Fig.25 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and is similar to that described in the above embodiment. Fig.12 Corresponding.

[0262] In this modification, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Fig.21 In this respect, the planar configuration of the imaging device 1 of this modification example is different from the planar configuration of the imaging device 1 described in the above-mentioned embodiment.

[0263] For example, as described in the above embodiment, the pixel common unit 539 of the first substrate 100 is formed on a pixel region of 2 rows×2 columns and has a substantially square planar shape ( Fig. 20 ). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C of one pixel column extend in a direction from a position overlapping with the vertical portion TGa toward the center portion of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541A and 541C and in a direction toward the center portion of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D of the other pixel column extend in a direction from a position overlapping with the vertical portion TGa toward the outer edges of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541B and 541D and in a direction toward the outside of the pixel sharing unit 539). The pad portion 120 connected to the floating diffusion portion FD is provided at the central portion of the pixel sharing unit 539 (the central portion of the pixel sharing unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact region 118 is provided at least in the H direction (in the V direction) of the pixel sharing unit 539. Fig. 20 In the H direction and the V direction) at the end.

[0264] As another arrangement example, it is also conceivable to set the horizontal part TGb of the transfer gate TG1, the transfer gate TG2, the transfer gate TG3 and the transfer gate TG4 only in the area facing the vertical part TGa. At this time, as described in the above embodiment, the semiconductor layer 200S is likely to be subdivided. Therefore, it is difficult to form a large transistor of the pixel circuit 210. On the other hand, when the horizontal part TGb of the transfer gate TG1, the transfer gate TG2, the transfer gate TG3 and the transfer gate TG4 extends in the H direction from the position overlapping with the vertical part TGa as described in the above modification, the width of the semiconductor layer 200S can be increased as described in the above embodiment. Specifically, the position of the through electrode TGV1 and the through electrode TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be arranged at a position close to the through electrode 120E in the H direction, and the position of the through electrode TGV2 and the through electrode TGV4 connected to the transfer gate TG2 and the transfer gate TG4 in the H direction can be arranged at a position close to the through electrode 121E in the H direction. Therefore, as described in the above embodiment, the width (the size in the H direction) of the semiconductor layer 200S extending along the V direction can be increased. Therefore, it is possible to increase the size of the transistor of the pixel circuit 210, in particular, the size of the amplifier transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the image pickup device 1 can output better pixel data (image information).

[0265] The pixel sharing unit 539 of the second substrate 200 has, for example, substantially the same size as the pixel sharing unit 539 of the first substrate 100 in the H direction and the V direction, and is, for example, arranged on an area corresponding to a pixel area of ​​approximately 2 rows × 2 columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction. Via the insulating region 212, one semiconductor layer 200S in which the selection transistor SEL and the amplifier transistor AMP are provided and one semiconductor layer 200S in which the FD conversion gain switching transistor FDG and the reset transistor RST are provided are arranged in the H direction. The insulating region 212 extends in the V direction ( Fig.21 ).

[0266] Here, we will refer to Fig.21 and Fig. 22 The appearance of the pixel sharing unit 539 of the second substrate 200 is described. For example, Fig. 20 The pixel sharing unit 539 of the first substrate 100 shown is connected to one side ( Fig. 22The amplifying transistor AMP and the selecting transistor SEL arranged on the left side of the paper, and the other side ( Fig. 22 The outer shape of the pixel common unit 539 of the second substrate 200 including the amplifying transistor AMP, the selecting transistor SEL, the FD conversion gain switching transistor FDG and the reset transistor RST is determined by the following four outer edges.

[0267] The first outer edge is one end of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP in the V direction ( Fig. 22 The first outer edge is set at the amplifying transistor AMP included in the pixel sharing unit 539 and at one side ( Fig. 22 The first outer edge is between the selection transistor SEL included in the adjacent pixel sharing unit 539 (on the upper side of the paper). More specifically, the first outer edge is set at the central part of the element isolation region 213 in the V direction between the amplifier transistor AMP and the selection transistor SEL. The second outer edge is the other end ( Fig. 22 The second outer edge is set at the lower end of the paper of the selection transistor SEL included in the pixel sharing unit 539 and the other side ( Fig. 22 The third outer edge is the other end (in the V direction) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. Fig. 22 The third outer edge is set at the lower end of the paper of the FD conversion gain switching transistor FDG included in the pixel sharing unit 539 and the other end ( Fig. 22 The third outer edge is between the reset transistor RST included in the adjacent pixel sharing unit 539 (the lower side of the paper). More specifically, the third outer edge is set at the central part of the element isolation region 213 in the V direction between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is one end ( Fig. 22 The fourth outer edge is set at the reset transistor RST included in the pixel sharing unit 539 and the side ( Fig. 22More specifically, the fourth outer edge is set at the center portion in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0268] In the outer shape of the pixel common unit 539 of the second substrate 200 including such a first outer edge, a second outer edge, a third outer edge, and a fourth outer edge, the third outer edge and the fourth outer edge are arranged to be offset to one side relative to the first outer edge and the second outer edge in the V direction (in other words, offset to one side in the V direction). By using such a layout, the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close to the pad portion 120 as possible. Therefore, the area of ​​the wiring connecting the amplifier transistor AMP and the FD conversion gain switching transistor FDG to the pad portion 120 is reduced, and the image pickup device 1 can be easily miniaturized. Note that the VSS contact area 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplifier transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, a plurality of pixel circuits 210 have the same arrangement.

[0269] The image pickup device 1 including such a second substrate 200 can also obtain the same effects as those described in the above embodiment. The arrangement of the pixel common unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0270] <4. Third Modification>

[0271] Figure 26 to Figure 31 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.26 The planar structure of the first substrate 100 is schematically shown and is similar to that described in the above embodiment. Figure 7B Corresponding. Fig. 27 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and is similar to that described in the above embodiment. Figure 8 Corresponding. Fig.28 The configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100 is schematically shown, and is similar to that described in the above embodiment. Fig. 9 Corresponding. Fig.29 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and is similar to that described in the above embodiment. Fig.10 Corresponding. Fig.30An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and is similar to that described in the above embodiment. Fig.11 Corresponding. Fig.31 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and is similar to that described in the above embodiment. Fig.12 Corresponding.

[0272] In this modification, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( Fig.28 ). That is, the configuration corresponds roughly to the configuration obtained by rotating Fig.21 The structure is obtained by the planar structure of the imaging device 1 shown in FIG.

[0273] For example, as described in the above embodiment, the pixel common unit 539 of the first substrate 100 is formed on a pixel region of 2 rows×2 columns and has a substantially square planar shape ( Fig.26 ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B of one pixel row extend in the V direction toward the center portion of the pixel sharing unit 539, and the transfer gates TG3 and TG4 of the pixels 541C and 541D of another pixel row extend in the V direction toward the outside of the pixel sharing unit 539. The pad portion 120 connected to the floating diffusion portion FD is provided in the center portion of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at least in the V direction ( Fig.26 In this case, the positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 in the V direction are close to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 in the V direction are close to the position of the through electrode 121E in the V direction ( Fig.28 ). Therefore, due to the same reason as described in the above embodiment, the width of the semiconductor layer 200S extending along the H direction (the dimension in the V direction) can be increased. Therefore, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0274] In each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged at a position adjacent to the selection transistor SEL in the V direction, and the insulating region 212 is sandwiched between the selection transistor SEL and the reset transistor RST ( Fig. 27). The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the H direction. The VSS contact region 218 is provided in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction ( Fig.30 ), and the fourth wiring layer W4 extends along the V direction ( Fig.31 ).

[0275] The image pickup device 1 including such a second substrate 200 can also obtain the same effect as described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification. For example, the semiconductor layer 200S described in the above embodiment and the first modification can extend along the H direction.

[0276] <5. Fourth Modification>

[0277] Fig.32 A modified example of the cross-sectional configuration of the image pickup device 1 according to the above-described embodiment is schematically shown. Fig.32 Corresponding to the above-mentioned embodiment Figure 3 In this modification, in addition to the contact portions 201, 202, 301, and 302, the image pickup device 1 has contact portions 203, 204, 303, and 304 at a position facing the center portion of the pixel array portion 540. The image pickup device 1 of this modification is different from the image pickup device 1 described in the above embodiment in this respect.

[0278] The contact portion 203 and the contact portion 204 are provided on the second substrate 200 and exposed on the bonding surface with the third substrate 300. The contact portion 303 and the contact portion 304 are provided on the third substrate 300 and exposed on the bonding surface with the second substrate 200. The contact portion 203 contacts the contact portion 303, and the contact portion 204 contacts the contact portion 304. That is, in the imaging device 1, in addition to the contact portion 201, the contact portion 202, the contact portion 301, and the contact portion 302, the second substrate 200 and the third substrate 300 are connected by the contact portion 203, the contact portion 204, the contact portion 303, and the contact portion 304.

[0279] Next, we will refer to Fig.33 and Fig.34 The operation of the imaging device 1 will be described. Fig.33 In FIG. 1 , arrows are used to show the paths of input signals input from the outside to the image pickup device 1 and the power supply potential and reference potential. Fig.34, a signal path of a pixel signal output from the image pickup device 1 to the outside is shown by an arrow. For example, an input signal input to the image pickup device is transmitted to the row driving unit 520 of the third substrate 300 through the input unit 510A, and the row driving unit 520 generates a row driving signal. The row driving signal is transmitted to the second substrate 200 through the contact portion 303 and the contact portion 203. In addition, the row driving signal reaches each pixel common unit 539 of the pixel array portion 540 through the row driving signal line 542 of the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, the driving signal other than the driving signal of the transmission gate TG is input to the pixel circuit 210, and drives each transistor included in the pixel circuit 210. The driving signal of the transmission gate TG is input to the transmission gate TG1, the transmission gate TG2, the transmission gate TG3, and the transmission gate TG4 of the first substrate 100 through the through electrode TGV, and drives the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D. In addition, the power supply potential and the reference potential supplied from the outside of the image pickup device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 through the contact portion 303 and the contact portion 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring of the wiring layer 200T. The reference potential is also supplied to the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D of the first substrate 100 through the through electrode 121E. On the other hand, for each pixel common unit 539, the pixel signal photoelectrically converted by the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200. The pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 through the vertical signal line 543 and the contact portion 204 and the contact portion 304. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300 and then output to the outside through the output unit 510B.

[0280] The image pickup device 1 including such contact portions 203, 204, 303, and 304 can also obtain the same effects as described in the above embodiment. The positions, number, etc. of the contacts can be changed according to the design of the circuits of the third substrate 300 to which the wiring is connected through the contacts 303 and 304.

[0281] <6. Fifth Modification>

[0282] Fig.35 A modified example of the cross-sectional configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.35 Corresponding to the above-mentioned embodiment Figure 6In this modification, a transfer transistor TR having a planar structure is provided on the first substrate 100. The image pickup device 1 of this modification is different from the image pickup device 1 described in the above embodiment in this respect.

[0283] In the transfer transistor TR, the transfer gate TG is composed of only the horizontal portion TGb. In other words, the transfer gate TG does not have the vertical portion TGa, and is disposed to face the semiconductor layer 100S.

[0284] The image pickup device 1 including the transfer transistor TR having such a planar structure can also obtain the same effects as those described in the above-mentioned embodiment. In addition, it is conceivable that, compared with the case where the vertical transfer gate TG is provided on the first substrate, by providing the planar transfer gate TG on the first substrate 100, the photodiode PD can be formed closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation signal amount (Qs). In addition, it is conceivable that, compared with the method of forming the vertical transfer gate TG on the first substrate 100, in the method of forming the planar transfer gate TG on the first substrate 100, the number of manufacturing steps is small and the photodiode PD is less likely to be adversely affected by the manufacturing steps.

[0285] <7. Sixth Modification>

[0286] Fig.36 A modification example of the pixel circuit of the image pickup device 1 according to the above-described embodiment is shown. Fig.36 Corresponding to the above-mentioned embodiment Figure 4 In this modification, the pixel circuit 210 is provided for each pixel (pixel 541A). That is, a plurality of pixels do not share the pixel circuit 210. The image pickup device 1 of this modification is different from the image pickup device 1 described in the above embodiment in this respect.

[0287] The imaging device 1 of this variation is similar to the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the imaging device 1 according to this variation can also obtain the same effect as described in the above embodiment.

[0288] <8. Seventh Modification>

[0289] Fig.37A variation of the planar structure of the pixel isolation section 117 described in the above embodiment is shown. A gap is provided in the pixel isolation section 117 surrounding each of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D. That is, the pixel isolation section 117 may not surround the entire periphery of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D. For example, the gap in the pixel isolation section 117 is provided near the pad section 120 and the pad section 121 (refer to Figure 7B ).

[0290] In the above-mentioned embodiment, it has been described that the pixel isolation portion 117 has a structure that penetrates the semiconductor layer 100S (see Figure 6 ), but the pixel isolation part 117 may have other structures besides the FTI structure. For example, the pixel isolation part 117 may be provided so as not to completely penetrate the semiconductor layer 100S, and may have a so-called deep trench isolation (DTI) structure.

[0291] <9. Second Implementation Plan>

[0292] <9.1 Issues to be Solved by the Second Implementation Plan>

[0293] However, the floating diffusion FD in the pixel 541 and the gate of the amplifier transistor AMP in the pixel circuit 210 are connected through a connection through hole as the FD wiring FDL. In the fine pixel, the area of ​​the connection through hole of the FD wiring FDL is about 45%. Therefore, since the effective area of ​​the pixel circuit 210 is reduced, the layout area of ​​the amplifier transistor AMP cannot be expanded.

[0294] In addition, the capacitance between the FD wiring FDL and the gate of the amplifier transistor AMP and the capacitance between other connection through holes extending in parallel with the connection through hole of the FD wiring FDL (such as the TG wiring TGL or the VSS wiring VSS) overlap with the capacitance of the floating diffusion FD. Therefore, the FD capacitance is increased, the charge-voltage conversion efficiency is reduced, and the read noise cannot be reduced.

[0295] <9.2 Overview of the Second Implementation Plan>

[0296] Therefore, the camera device has a first substrate, a second substrate, wiring and a groove. The first substrate has a pixel including a photodiode and a floating diffusion portion that holds the charge converted by the photodiode. The second substrate includes a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion portion of the pixel, and is stacked on the first substrate. The wiring penetrates the first substrate and the second substrate in the stacking direction, and electrically connects the floating diffusion portion of the first substrate to the amplifying transistor in the pixel circuit of the second substrate. A groove is formed in at least the second substrate, the groove extending parallel to the wiring and having a depth equal to or greater than the thickness of the semiconductor layer in the second substrate.

[0297] In the imaging device, a groove extending parallel to a wiring that electrically connects a floating diffusion in a first substrate to an amplifier transistor in a pixel circuit of the second substrate is formed in the second substrate at a depth equal to or greater than the thickness of a semiconductor layer of the second substrate, thereby reducing the parasitic capacitance of the wiring and improving the charge-voltage conversion efficiency.

[0298] <9.3 Specific example of implementation plan 2-1>

[0299] <9.3.1 Structure of Implementation Plan 2-1>

[0300] Fig.38 1 is an equivalent circuit diagram showing a configuration example of a pixel common unit 539 of an image pickup device 1 of a 2-1 embodiment. The image pickup device 1 has a structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked. The first substrate 100 has a pixel 541 that performs photoelectric conversion. The second substrate 200 has a pixel circuit 210A that reads a pixel signal based on a charge output from the pixel 541. The third substrate 300 has a processing circuit that detects a pixel signal. The pixel common unit 539 has a pixel 541 and a pixel circuit 210A. The pixel 541 has four photodiodes PD, four transfer transistors TR that transfer charges converted by each photodiode PD, and a floating diffusion FD that holds the charges transferred by the transfer transistor TR.

[0301] The pixel circuit 210A includes, for example, a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, a power supply line VDD, and a vertical signal line (VSL) 543. The reset transistor RST resets the voltage of the floating diffusion FD to a predetermined potential. The amplifier transistor AMP generates a voltage signal as a pixel signal according to the level of the charge retained in the floating diffusion FD. The selection transistor SEL controls the connection between the drain of the amplifier transistor AMP and the vertical signal line 543. The floating diffusion FD of the first substrate 100 is electrically connected to the gate of the amplifier transistor AMP of the pixel circuit 210A of the second substrate 200 through the FD wiring FDL.

[0302] The vertical signal line 543 electrically connects each pixel circuit 210A to a column signal processing unit 550 of a processing circuit arranged on the third substrate 300. Then, the column signal processing unit 550 detects a pixel signal appearing in the vertical signal line 543 from each pixel circuit 210A.

[0303] The image pickup device 1 has an FD wiring FDL that connects the floating diffusion FD of the pixel 541 of the first substrate 100 to the gate of the amplifier transistor AMP of the pixel circuit 210A of the second substrate 200. The FD wiring FDL is formed as a connection through hole between the first substrate 100 and the second substrate 200. The image pickup device 1 has a trench T formed in the second substrate 200 on the side closer to the first substrate 100 to extend in parallel with the FD wiring FDL. The trench T is in a state in which, for example, a conductive substance is embedded.

[0304] The source of the amplifier transistor AMP in the pixel circuit 210A of the second substrate 200 is connected to the shield wiring SL made of a conductive substance embedded in the trench T to have the same potential. By reducing the parasitic capacitance between the FD wiring FDL and the shield wiring SL to (1-(SF gain)) times, the capacitance of the FD wiring FDL can be reduced to improve the charge-voltage conversion efficiency.

[0305] Fig.39 1 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate 100 and a second substrate 200 of the second embodiment. The wiring layer 100T between the semiconductor layer 100S in the first substrate 100 and the second substrate 200 is made of, for example, SiO 2 The first substrate 100 and the second substrate 200 are electrically connected to each other through the through wiring.

[0306] The through wiring includes a TG wiring TGL electrically connected to the gate (transfer gate TG) of the transfer transistor TR of the pixel 541, and an FD wiring FDL connecting the gate of the amplifier transistor AMP of the pixel circuit 210A to the connection pad of the floating diffusion FD. The trench T is formed between the TG wiring TGL and the FD wiring FDL in the wiring layer 100T. Note that the depth of the trench T is equal to or greater than the thickness of the Si substrate of the second substrate 200, and is within a range that does not affect the floating diffusion FD formed in the first substrate 100. The shielding wiring SL is formed of, for example, a conductive material such as doped polysilicon or metal embedded in the trench T.

[0307] Fig.401 is a schematic diagram showing an example of a stacking structure of a first substrate 100 and a second substrate 200. When the shielding wiring SL (groove T) is observed from the front surface (stack surface) of the wiring layer 100T, as shown in the figure, on the stacking surface of the wiring layer 100T, the shielding wiring SL is formed into a circular shape centered on the FD wiring FDL. That is, a groove T extending parallel to the FD wiring FDL is formed on the stacking surface of the wiring layer 100T, so that the FD wiring FDL and the TG wiring TGL extending parallel to the FD wiring FDL are electrically separated from each other, and the FD wiring FDL is enclosed in a circular shape on the stacking surface.

[0308] <9.3.2 Operation and Effect of Implementation Plan 2-1>

[0309] In the camera device 1 of the 2-1st embodiment, the shielding wiring SL extends in parallel with the FD wiring FDL that penetrates and connects the first substrate 100 and the second substrate 200. In addition, in the camera device 1, the source of the amplifier transistor AMP of the pixel circuit 210A of the second substrate 200 and the shielding wiring SL are electrically connected to have the same potential. Therefore, since the parasitic capacitance between the FD wiring FDL and the shielding wiring SL is reduced to (1-(SF gain)) times, the capacitance of the FD wiring FDL can be reduced to improve the charge-voltage conversion efficiency. In addition, even in the case where one FD wiring FDL extends in parallel with two TG wirings TGL, the shielding wiring SL is arranged between each FD wiring FDL and the TG wiring TGL and between the FD wiring FDL and another FD wiring FDL. Therefore, by reducing the parasitic capacitance of the FD wiring FDL, the charge-voltage conversion efficiency can be improved.

[0310] <9.3.3 Variation of Implementation Example 2-1>

[0311] Furthermore, the case where the shield wiring SL is formed in a circular shape centered on the FD wiring FDL when the shield wiring SL is viewed from the front surface (stacked surface) of the wiring layer 100T has been exemplified, but the present invention is not limited thereto and may be appropriately modified. Fig.41 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T1 on the surface of the second substrate 200 . Fig.42 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T2 on the surface of the second substrate 200. For example, in the case where the shielding wiring SL is observed from the front surface (stacked surface) of the wiring layer, it can be used Fig.41 The parallel plate groove T1 shown, or can be used Fig.42 The rectangular groove T2 shown may be modified appropriately.

[0312] Fig.432 is a schematic diagram showing an example of the arrangement configuration of the trenches T3 on the surface of the second substrate 200. In addition, the trenches T may be arranged at positions that electrically separate the FD wiring FDL and the TG wiring TGL from each other, and for example, relative to Fig.43 The FD wiring FDL shown in the figure may be arranged in a trench T3 having a length greater than the width of the FD wiring FDL. Fig.44 2 is a schematic diagram showing an example of the arrangement of the grooves T4 on the surface of the second substrate 200. Fig.44 In the case where the TG wiring TGL is arranged on the diagonal line of the FD wiring FDL shown, the trench T4 may be arranged on the diagonal line of the FD wiring FDL between the FD wiring FDL and the TG wiring TGL, and may be appropriately deformed.

[0313] In the imaging device 1 of the 2-1st embodiment, the case where the shielding wiring SL in which the groove T in which the conductive material is embedded is formed in the wiring layer 100T has been exemplified. However, a hollow groove T may be formed in the wiring layer 100T as the shielding wiring SL without embedding the conductive material in the groove T, and may be appropriately deformed.

[0314] Note that as the selected pixel 541, for example, a pixel 541 selected on a row basis among one or more pixels 541 arranged in the row direction has been exemplified. However, the unselected pixel 541 may be any pixel 541 other than the selected pixel 541, and may be appropriately deformed.

[0315] As the selected pixel 541 , the pixel 541 selected on a row basis has been exemplified, but, for example, the pixel 541 may be selected on a column basis among one to a plurality of pixels 541 arranged in the column direction, and may be appropriately modified.

[0316] The pixel 541 includes, for example, a total of four photodiodes PD of 2×2, but may be appropriately modified as long as the pixel 541 includes one or more photodiodes PD without being limited to four photodiodes PD.

[0317] <9.4 Specific example of implementation plan 2-2>

[0318] <9.4.1 Structure of Implementation Plan 2-2>

[0319] In the image pickup device 1 of the 2-1st embodiment, the case where the groove T is arranged between one FD wiring FDL and the TG wiring TGL has been exemplified. However, the groove T may be arranged between four FD wirings FDL and the TG wiring TGL, and its embodiment will be described below as the 2-2nd embodiment. The same components as those of the 2-1st embodiment are denoted by the same reference numerals, and redundant descriptions of the components and operations will be omitted.

[0320] Fig.45 is a schematic cross-sectional view showing an example of a stacked structure of the first substrate 100 and the second substrate 200 of the 2-2nd embodiment. The wiring layer 100T has a first FD wiring FDL1 , a second FD wiring FDL2 , a first TG wiring TGL1 , and a second TG wiring TGL2 .

[0321] The wiring layer 100T includes a first trench T51, a second trench T52, and a third trench T53. The first trench T51 is formed between the first TG wiring TGL1 and the first FD wiring FDL1, and electrically isolates the first FD wiring FDL1 from the first TG wiring TGL1. The second trench T52 is formed between the second TG wiring TGL2 and the second FD wiring FDL2, and electrically separates the second TG wiring TGL2 from the second FD wiring FDL2. The third trench T53 is formed between the first FD wiring FDL1 and the second FD wiring FDL2, and electrically separates the first FD wiring FDL1 from the second FD wiring FDL2.

[0322] Fig.46A 1 is a schematic diagram showing an example of the arrangement configuration of the grooves T5 on the surface of the second substrate 200. When the grooves T5 are viewed from the front surface (stacked surface) of the wiring layer 100T, as shown in FIG. Fig.46A As shown, the trench T5 includes a first trench T51, a second trench T52, a third trench T53, a fourth trench T54, and a fifth trench T55. The first trench T51 electrically separates the first FD wiring FDL1 from the first TG wiring TGL1, and electrically separates the third FD wiring FDL3 from the third TG wiring TGL3. The third trench T53 electrically separates the first FD wiring FDL1 from the second FD wiring FDL2, and electrically separates the third FD wiring FDL3 from the fourth FD wiring FDL4. The second trench T52 electrically separates the second FD wiring FDL2 from the second TG wiring TGL2, and electrically separates the fourth FD wiring FDL4 from the fourth TG wiring TGL4. Fig.47 2 is a schematic diagram showing an example of a schematic cross-sectional shape of the trench T5. Fig.47 As shown, the hole size on the front surface (second substrate 200) side may be larger than the hole size on the rear surface (first substrate 100) side, and may be appropriately deformed.

[0323] The arrangement of the grooves T can be appropriately modified, and can be as follows FIG. 46B to FIG. 46H shown. Fig.46B is a schematic diagram showing an example of the arrangement of the grooves T10 on the surface of the second substrate 200. The L-shaped grooves T10 may be arranged at Fig.46BThe trench T10 electrically separates the first FD wiring FDL1 from the first TG wiring TGL1, the first FD wiring FDL1 from the second TG wiring TGL2, the first FD wiring FDL1 from the third TG wiring TGL3, and the first FD wiring FDL1 from the fourth TG wiring TGL4.

[0324] Fig.46C 2 is a schematic diagram showing an example of the arrangement of the grooves T11 on the surface of the second substrate 200. Fig.46C As shown, each of the FD wirings FDL1 to FDL4 may be surrounded by a grid-shaped trench T11. The trench electrically separates the FD wiring FDL from adjacent FD wirings FDL and from adjacent TG wirings TGL. Fig.46D 2 is a schematic diagram showing an example of the arrangement of the grooves T12 on the surface of the second substrate 200. Fig.46D As shown, each of the FD wirings FDL1 to FDL4 can be surrounded by the grid-shaped trench T12. At the same time, the shielding of the cross-shaped intersection T12A of the trench T12 is omitted. Therefore, it goes without saying that the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and it is possible to avoid the situation where the processing depth of the intersection becomes deeper during the trench processing.

[0325] Fig.46E 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T13 on the surface of the second substrate 200 . Fig.46E The trench T13 shown has a cross trench T131 and a diagonal trench T132. The cross trench T131 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T132 electrically separates the FD wiring FDL from the TG wiring TGL on the diagonal line thereof. Fig.46F 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T14 on the surface of the second substrate 200 . Fig.46F The trench T14 shown has a cross trench T141 and a diagonal trench T142. The cross trench T141 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T142 electrically separates the FD wiring FDL from the TG wiring TGL on the diagonal line thereof.

[0326] Figure 46G 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T15 on the surface of the second substrate 200 . Figure 46GThe groove T15 shown has a cross groove T151 and a diagonal groove T152. The cross groove T151 electrically separates the adjacent FD wirings FDL from each other. The diagonal groove T152 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal. At the same time, the shielding of the cross-shaped intersection T151A of the cross groove T151 is omitted. Therefore, it goes without saying that the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and the processing depth of the intersection T151A can be avoided from becoming deeper during the groove processing.

[0327] Figure 46H 2 is a schematic diagram showing an example of the arrangement configuration of the grooves T16 on the surface of the second substrate 200 . Figure 46H The trench T16 shown has a cross trench T161 and a diagonal trench T162. The cross trench T161 electrically separates the adjacent FD wirings FDL from each other. The diagonal trench T162 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal. At the same time, the shielding of the cross-shaped intersection T161A of the cross trench T161 is omitted. Therefore, it goes without saying that the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and the processing depth of the intersection T161A can be avoided from becoming deeper during the trench processing.

[0328] <9.4.2 Operation and Effect of Implementation Plan 2-2>

[0329] Even in the case where the four FD wirings FDL1 to FDL4 extend in parallel with the four TG wirings TGL1 to TGL4, a trench T5 is arranged to electrically isolate each FD wiring FDL from the TG wiring TGL and to electrically separate the FD wiring FDL from other FD wirings FDL. Therefore, by reducing the capacitance of the FD wiring FDL, the charge-voltage conversion efficiency can be improved.

[0330] In the imaging device 1 of the 2-1st embodiment, the case where the shield wiring SL composed of the groove T in which the conductive material is embedded is arranged in the wiring layer 100T has been exemplified. However, the material embedded in the groove T is not limited to the conductive material, and may be a gas, for example, and its embodiment will be described below as the 2-3rd embodiment.

[0331] <9.5 Specific examples of implementation schemes 2-3>

[0332] <9.5.1 Structure of Implementation Scheme 2-3>

[0333] Fig.48A is an equivalent circuit diagram showing a configuration example of a pixel sharing unit 539 in the image pickup device 1 of the second-third embodiment, and Fig.49 1 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate 100 and a second substrate 200 of the second-third embodiment. The imaging device 1 has an FD wiring FDL penetrating and connecting a wiring layer 100T between a semiconductor layer 100S in the first substrate 100 and the second substrate 200, and a trench T6 extending parallel to the FD wiring FDL formed on the second substrate 200 near the first substrate 100.

[0334] The trench T6 is filled and sealed with a gas having a low relative dielectric constant (εs) such as air (1.00054), N2 (1.00057), He (1.00052), or Ar (1.00007) to form the shield wiring SL1. 2 The air gap with a relative dielectric constant of 3.9 can reduce the FD capacitance to improve the charge-voltage conversion efficiency.

[0335] In the image pickup device 1 of the second-third embodiment, since the trench T6 filled with a gas having a low relative dielectric constant is arranged between the FD wiring FDL and the TG wiring TGL, the parasitic capacitance of the FD wiring FDL is reduced, thereby improving the charge-voltage conversion efficiency.

[0336] Note that the case where the trench T6 is sealed with a gas having a low dielectric constant has been exemplified, but the trench T6 may be filled with an insulating film material having a low dielectric constant (Low-k) and may be appropriately modified.

[0337] In addition, it has been exemplified that the depth of the trench T6 is set to be greater than the depth of the SiO 2 The case where the depth is deeper and is set to a depth within a range that does not affect the floating diffusion portion FD of the first substrate 100. However, the depth is not limited thereto, and may be set to Fig.49 The depth of the trench T6 of the shield wiring SL1 shown in FIG. 1 is 0, and can be appropriately modified. In addition, for the wiring layer 100T, for example, SiO 2 For the wiring layer 100T, however, for example, a material having a lower content than SiO 2 The insulating film material has a dielectric constant (Low-k) and can be deformed appropriately.

[0338] <9.5.2 Operation and Effect of Implementation Plan 2-3>

[0339] In the image pickup device 1 of the second-third embodiment, even in the case where one FD wiring FDL extends in parallel with two TG wirings TGL, a shield wiring SL1 is arranged to electrically separate each FD wiring FDL from the TG wiring TGL and to electrically separate the FD wiring FDL from other FD wirings FDL. Therefore, by reducing the parasitic capacitance of the FD wiring FDL, it is possible to improve the charge-voltage conversion efficiency.

[0340] Fig.48B : is an equivalent circuit diagram showing another example of the configuration of the pixel sharing unit of the image pickup device according to the second-third embodiment.

[0341] Fig.48B The pixel sharing unit and Fig.48A The pixel sharing unit is different in that the back gate of the amplifying transistor AMP is connected to the source of the amplifying transistor AMP.

[0342] Therefore, since the gate-source voltage Vgs of the amplifier transistor AMP is lowered, the potential of the reset level appearing in the vertical signal line (column read line) 543 is raised.

[0343] Incidentally, assuming that the lower limit of the signal potential level of the vertical signal line (column read line) 543 is determined by a load circuit included in the column signal processing unit 550, by connecting the back gate and source of the amplifier transistor AMP, the amplitude of the signal (pixel signal) that can be processed in the vertical signal line (column read line) 543 can be increased, and the detection accuracy can be improved.

[0344] <10. Third Implementation Plan>

[0345] <10.1 Issues to be resolved by the third implementation plan>

[0346] For example, the charge obtained by photoelectric conversion of the photodiode PD is set to Qp, the FD capacitance of the floating diffusion FD is set to Cfd, and the gain of the source follower circuit is set to Gsf. In this case, the source follower output voltage Vsf is calculated by the formula Vsf = Gsf*Qp / Cfd. Therefore, when a large output voltage is obtained using the same amount of light, the signal-to-noise ratio (S / N) is improved. However, as the FD capacitance (Cfd) increases, the source follower output voltage (Vsf) decreases. Therefore, the source follower output voltage (Vsf) can be increased by increasing the gain (Gsf) of the source follower circuit. However, the influence of the parasitic capacitance of the FD capacitance (Cfd) is large, and the parasitic capacitance needs to be reduced.

[0347] <10.2 Overview of the Third Implementation Plan>

[0348] Therefore, the camera device has a first substrate, a second substrate, wiring and a shielding wiring. The first substrate has a pixel including a photodiode and a floating diffusion portion that holds a charge converted by the photodiode. The second substrate has a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion portion of the pixel, and is stacked on the first substrate. The wiring electrically connects the floating diffusion portion in the first substrate to the amplifying transistor in the pixel circuit of the second substrate, and is formed on the first substrate and the second substrate. In a state where the well layer of the pixel circuit and the well layer of the amplifying transistor of the pixel circuit are electrically isolated from each other, the shielding wiring electrically connects the gate of the amplifying transistor and the source of the amplifying transistor, and the shielding wiring shields the wiring while extending in parallel with the wiring.

[0349] In an imaging device, in a state where a well layer of a pixel circuit and a well layer of an amplifier transistor are electrically isolated from each other, a shielding wiring extends in parallel with the wiring and shields the wiring, and the shielding wiring electrically connects the gate of the amplifier transistor and the source of the amplifier transistor. That is, the source of the amplifier transistor and the well layer of the amplifier transistor are connected to have the same potential, thereby eliminating the substrate bias effect, and the gain of the floating diffusion amplitude and the amplifier transistor source amplitude is set to 1. In addition, the shielding wiring that leads to the source potential of the amplifier transistor is arranged around the wiring, and the wiring connected to the floating diffusion moves with the same amplitude as the floating diffusion. Therefore, since the wiring connection capacitance is reduced, the capacitance of the floating diffusion is reduced, thereby improving the charge-voltage conversion efficiency.

[0350] That is, in the image pickup device, the capacitance of the floating diffusion caused by the parasitic resistance of the wiring is reduced, thereby improving the charge-voltage conversion efficiency. In addition, by shielding the wiring, crosstalk with adjacent wiring can be suppressed.

[0351] <10.3 Specific example of implementation plan 3-1>

[0352] <10.3.1 Structure of Implementation Plan 3-1>

[0353] Fig.50A 1 is an equivalent circuit diagram showing a configuration example of a plurality of pixel circuits 210B of a second substrate 200 of the 3-1 embodiment. The second substrate 200 includes a common p-well layer 250 common to all pixels and an independent p-well layer 251 for an amplifier transistor AMP of each pixel 541, and the common p-well layer 250 and the independent p-well layer 251 are electrically isolated by a full trench (FTI) T7.

[0354] The reset transistor RST and the selection transistor SEL of each pixel circuit 210B are formed in the common p-well layer 250. Since the common p-well layer 250 is connected to the GND potential, the back gates of the reset transistor RST and the selection transistor SEL are fixed to the GND potential.

[0355] On the other hand, the amplifier transistor AMP of the pixel circuit 210B is formed in the independent p-well layer 251. Since the independent p-well layer 251 is connected to the source of the amplifier transistor AMP, the potential of the independent p-well layer 251 changes with the source potential of the amplifier transistor AMP. That is, since the back gate and source potentials of the amplifier transistor AMP have the same potential, the gain of the source follower circuit becomes 1.

[0356] For example, when the back gate of the amplifier transistor AMP is fixed to the GND potential, a substrate bias effect occurs according to the fluctuation of the source potential of the amplifier transistor AMP, and the gain of the source follower circuit becomes a value of about 0.85. Therefore, since the independent p-well layer 251 follows the source potential of the amplifier transistor AMP, the gain of the source follower circuit increases by 17%, which results in a 17% increase in the source follower output voltage (Vsf).

[0357] Meanwhile, the column signal processing units 550 are connected to the vertical signal lines (column reading lines) 543 , respectively, and read pixel signals through the vertical signal lines (column reading rows) 543 .

[0358] Here, the configuration of the column signal processing unit 550 will be described.

[0359] Fig.50B is a schematic block diagram of the column signal processing unit of the first aspect.

[0360] The column signal processing unit 550 includes, for example, a reference signal generating unit 551 constructed as a constant voltage source, an AD converter 552 that performs AD conversion based on a reference signal input from the reference signal generating unit 551, and a load circuit LD constructed as a current source, and outputs the AD conversion output ADCOUT as pixel data according to the voltage of the vertical signal line (column read line) 543.

[0361] According to the above configuration, the read pixel signal can be converted into digital data and output.

[0362] Fig.50C is a schematic block diagram of the column signal processing unit of the second aspect.

[0363] The column signal processing unit 550 of the second aspect is constructed using a single slope ADC.

[0364] The column signal processing unit 550 includes, for example, a RAMP generating circuit 553 that generates and outputs a RAMP waveform, a comparator 554 that compares the voltage of the pixel signal read through the vertical signal line (column read line) 543 with the voltage of the RAMP waveform and outputs a comparison result signal, a counter 555 that counts up when the level of the comparison result signal of the comparator 554 is, for example, an "H" level, and a latch 556 that receives the count value of the counter 555 at predetermined intervals and outputs the AD conversion output ADCOUT as pixel data according to the voltage of the vertical signal line (column read line) 543.

[0365] Also with the above configuration, the read pixel signal can be converted into digital data and output.

[0366] Here, a circuit configuration example of the above-mentioned comparator 554 will be described.

[0367] Fig.50D is an explanatory diagram of a first configuration example of a comparator.

[0368] like Fig.50D As shown, the comparator 554 includes P-type MOS (PMOS) transistors PT11 and PT12, N-type MOS (NMOS) transistors NT11 and NT12, capacitors C11 and C12, and switches SW11 and SW12.

[0369] In the above configuration, the source of the PMOS transistor PT11 and the source of the PMOS transistor PT12 are connected to the high potential side power supply VDD.

[0370] The drain of the PMOS transistor PT11 is connected to the drain of the NMOS transistor NT11 .

[0371] Furthermore, the drain and gate of the PMOS transistor PT11 are connected, and the connection point thereof is connected to the gate of the PMOS transistor 12 .

[0372] The drain of the PMOS transistor PT12 is connected to the drain of the NMOS transistor NT12 , and the connection point thereof is the output terminal OUT1 .

[0373] The source of the NMOS transistor NT11 and the source of the NMOS transistor NT12 are connected to each other, and the connection point thereof is connected to the drain of the NMOS transistor NT13 .

[0374] Furthermore, the drain of the NMOS transistor NT13 is connected to the low potential side power supply GND.

[0375] The gate of the NMOS transistor NT11 is connected to one terminal of the capacitor C11 , and the other terminal of the capacitor C11 is an input terminal to which a RAMP signal is input.

[0376] Furthermore, the gate of the NMOS transistor NT12 is connected to one terminal of the capacitor C12 , and the other terminal of the capacitor C12 is an input terminal to which the pixel signal VSL is input.

[0377] Therefore, in the comparator 554, the PMOS transistor PT11 and the PMOS transistor PT12 constitute a current mirror circuit, and the NMOS transistor NT11 and the NMOS transistor NT12 function as a differential comparison circuit using the NMOS transistor NT13 as a current source.

[0378] Fig.50E is an explanatory diagram of a second configuration example of a comparator.

[0379] like Fig.50E As shown, the comparator 554 includes PMOS transistors PT21 to PT23 , NMOS transistors NT21 and NT22 , capacitors C21 to C23 , and switches SW21 and SW22 .

[0380] In the above configuration, the source of the NMOS transistor NT21 and the source of the NMOS transistor NT22 are connected to the low potential side power supply GND.

[0381] The drain of the NMOS transistor NT21 is connected to the gate of the NMOS transistor NT22 and the drain of the PMOS transistor PT22 .

[0382] The drain of the NMOS transistor NT22 is connected to the drain of the PMOS transistor PT23 and the output terminal OUT1.

[0383] The source of the PMOS transistor PT22 is connected to the source of the PMOS transistor PT23 and the drain of the PMOS transistor PT21. The source of the PMOS transistor PT21 is connected to the high potential side power supply VDD.

[0384] The NMOS transistor NT21 and the NMOS transistor NT22 constitute a current mirror circuit.

[0385] Furthermore, the gate of the PMOS transistor PT22 is connected to one terminal of the capacitor C21 , and the other terminal of the capacitor C21 is an input terminal to which the pixel signal VSL is input.

[0386] The gate of the PMOS transistor PT22 is connected to one terminal of the capacitor C22, and the other terminal of the capacitor C22 is an input terminal to which a RAMP signal is input.

[0387] Capacitor C21 and capacitor C22 serve as input capacitance.

[0388] Therefore, the PMOS transistor PT21 to the PMOS transistor PT23 constitute a differential comparison circuit, and the entire circuit functions as a comparator.

[0389] Fig.50F is an explanatory diagram of a third configuration example of a comparator.

[0390] like Fig.50F As shown, the comparator 554 includes a PMOS transistor PT31, NMOS transistors NT31 and NT32, capacitors C31 and C32, and a switch SW31.

[0391] In the above configuration, the drain of the NMOS transistor NT31 is connected to the high potential side power supply VDD, and the source of the NMOS transistor NT31 is connected to the source of the PMOS transistor PT31.

[0392] The drain of the PMOS transistor PT31 is connected to the drain of the NMOS transistor NT32 and the output terminal OUT1 .

[0393] The source of the NMOS transistor NT32 is connected to the low potential side power supply GND.

[0394] Furthermore, the switch SW31 is connected between the gate terminal and the drain terminal of the PMOS transistor PT31 .

[0395] The gate of the PMOS transistor PT31 is connected to one terminal of the capacitor C31 , and the other terminal of the capacitor C31 is an input terminal to which the pixel signal VSL is input.

[0396] The gate of the PMOS transistor PT31 is connected to one terminal of the capacitor C32 , and the other terminal of the capacitor C32 is an input terminal to which a RAMP signal is input.

[0397] The capacitor C31 and the capacitor C32 serve as input capacitances.

[0398] Therefore, a comparison circuit is formed by the voltage division ratio of the PMOS transistor PT31 and the NMOS transistor NT31 and the NMOS transistor NT32 , and functions as a comparator of the entire circuit.

[0399] Next, the column signal processing unit of the third aspect will be described.

[0400] Figure 50G is a schematic block diagram of the column signal processing unit of the third aspect.

[0401] The column signal processing unit 550 of the third aspect includes, for example, a RAMP generating circuit 557 that generates and outputs a RAMP waveform, a comparator 558 that compares the voltage of the pixel signal read through the vertical signal line (column read line) with the voltage of the RAMP waveform and outputs a comparison result signal, a counter 559 that counts up when the level of the comparison result signal of the comparator 558 is, for example, an "H" level, and a latch 560 that receives the count value of the counter 559 at predetermined intervals and outputs an AD conversion output ADCOUT as pixel data according to the voltage of the vertical signal line (column read line) 543.

[0402] In the column signal processing unit 550 of the third aspect, the current generated by the load circuit LD is connected to the vertical signal line (column read line) 543 through the comparator 558; through the current flowing through the load circuit LD, the bias current is simultaneously applied to the amplifier transistor AMP and the comparator 558 constituting the pixel, thereby reducing the consumption current.

[0403] Figure 50H It is an explanatory diagram of a configuration example of a comparator according to the third aspect.

[0404] like Figure 50H As shown, the comparator 558 includes a PMOS transistor PT41, a capacitor C41, a switch SW41, and a load circuit LD.

[0405] In the above configuration, the source of the PMOS transistor PT41 is an input terminal to which the pixel signal VSL is input, and the drain of the PMOS transistor PT41 is connected to the load circuit LD and the output terminal OUT1.

[0406] Furthermore, the switch SW41 is connected between the gate terminal and the drain terminal of the PMOS transistor PT41 .

[0407] The gate of the PMOS transistor PT41 is connected to one terminal of the capacitor C41 , and the other terminal of the capacitor C41 is an input terminal to which a RAMP signal is input.

[0408] Capacitor C41 serves as an input capacitor.

[0409] Thus, a comparison circuit that outputs an output signal according to the gate-source voltage of the PMOS transistor PT41 is constructed, and the entire circuit functions as a comparator.

[0410] Next, the column signal processing unit of the fourth aspect will be described.

[0411] Fig.50I is a schematic block diagram of the column signal processing unit of the fourth aspect.

[0412] The column signal processing unit 550 of the fourth aspect includes a load circuit LD, a pre-circuit 561 that connects the current generated by the load circuit LD to the vertical signal line (column read line) 543, a reference signal generating unit 562 that is constructed as a constant voltage source, for example, and an AD converter 563 that performs AD conversion based on the reference signal input from the reference signal generating unit 562.

[0413] Here, a configuration example of the preamplifier circuit 561 will be described.

[0414] Fig.50J It is an explanatory diagram of a configuration example of a front-end circuit.

[0415] like Fig.50J As shown, the preamplifier circuit 561 includes a PMOS transistor PT51, capacitors C51 and C52, and a load circuit LD.

[0416] In the above configuration, the source of the PMOS transistor PT51 is an input terminal to which the pixel signal VSL is input, and the drain of the PMOS transistor PT51 is connected to the load circuit LD and the output terminal OUT1.

[0417] Furthermore, a capacitor C52 is connected between the gate terminal and the drain terminal of the PMOS transistor PT51. The capacitor C52 serves as a feedback capacitance.

[0418] Furthermore, a capacitor C51 serves as a reference capacitor, one terminal of the capacitor C51 is connected to the gate of the PMOS transistor PT51 , and the other terminal of the capacitor C51 is connected to the low potential side power supply GND.

[0419] The pre-amplifier circuit 561 is configured as a current reuse column amplifier (CRCA).

[0420] According to the above configuration, the gate-source voltage of the PMOS transistor PT51 fluctuates according to the pixel signal VSL input to the source of the PMOS transistor PT51, and the drain current of the PMOS transistor PT51 is changed. The output voltage Vout corresponding to the drain current is output from the output terminal OUT1 through the drain of the PMOS transistor PT51.

[0421] As described above, the pre-circuit 561 functions as a comparison circuit that effectively outputs an output signal according to the pixel signal VSL, and the entire circuit functions as an amplifier.

[0422] Fig.513-1 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate 100 and a second substrate 200 of the first embodiment. The first substrate 100 includes a photodiode PD, a transfer transistor TR, and a floating diffusion FD. The pixel circuit 210B on the second substrate 200 includes a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, and an FD wiring FDL. The wiring layer 100T including multiple layers (M1 to M3) on the first substrate 100 and the wiring layer 200T including multiple layers (MP to M1) on the second substrate 200 are connected by a copper-copper junction CC.

[0423] The wiring layer 100T and the wiring layer 200T penetrate from the first substrate 100 to the second substrate 200 , and an FD wiring FDL connecting the floating diffusion FD of each pixel 541 on the first substrate 100 to the amplifier transistor AMP in the pixel circuit 210B on the second substrate 200 is arranged.

[0424] The amplifier transistor AMP for each pixel 541 of the independent p-well layer 251 on the second substrate 200 is electrically isolated from the common p-well layer 250 by the full trench T7. The gate of the amplifier transistor AMP is connected to the FD wiring FDL, the drain of the amplifier transistor AMP is connected to the independent p-well layer 251, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. In addition, the source of the amplifier transistor AMP is electrically connected to the shielding wiring SL2 extending in parallel with the FD wiring FDL and connected to each layer in the wiring layer 100T and the wiring layer 200T.

[0425] The shielding wiring SL2 is a wiring for the source potential of the amplifier transistor AMP (= the back gate potential of the amplifier transistor AMP). The shielding wiring SL2 is arranged to cover the FD wiring FDL. The shielding wiring SL2 is arranged so that the coupling capacitance between the floating diffusion FD and the source of the amplifier transistor AMP is large, and the coupling capacitance between the floating diffusion FD and the wiring other than the floating diffusion FD is as small as possible. The shielding wiring SL2 extends from the wiring layer 200T to the wiring layer 100T through the joint CC between the wiring layer 100T of the first substrate 100 and the wiring layer 200T of the second substrate 200, and is arranged to cover the FD wiring FDL.

[0426] Since the independent p-well layer 251 is connected to the source of the amplifier transistor AMP, the potential of the independent p-well layer 251 changes with the source potential of the amplifier transistor AMP. That is, since the back gate and source potentials of the amplifier transistor AMP have the same potential, the gain of the source follower circuit becomes 1. The gate potential amplitude and the source potential amplitude of the amplifier transistor AMP become equal. That is, the potential of the shielding wiring SL2 also changes with the amount of change in the potential of the floating diffusion FD of the FD wiring FDL. Therefore, no charge transfer occurs between the FD wiring FDL and the shielding wiring SL2, and the capacitance value between the FD wiring FDL and the shielding wiring SL2 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL2 is large, it can be ignored as the capacitance of the floating diffusion FD in the actual reading operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the capacitance of the floating diffusion FD becomes a small value. That is, since the parasitic capacitance of the floating diffusion FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0427] Furthermore, since the shield wiring SL2 is arranged between the FD wirings FDL of the adjacent pixels 541, each FD wiring FDL can be shielded by the shield wiring SL2. Therefore, the occurrence of crosstalk between the adjacent FD wirings FDL can be suppressed.

[0428] If the periphery of the FD wiring FDL is shielded by the potential of the node, the FD wiring follows with the same amplitude as the potential of the floating diffusion FD, so that the inter-wiring capacitance appears zero, and thus the FD capacitance can be reduced.

[0429] In a state where the independent p-well layer 251 of the amplifier transistor AMP for each pixel 541 is isolated by the full trench T7, the source of the amplifier transistor AMP and the independent p-well layer 251 are connected to have the same potential. Therefore, the substrate bias effect is eliminated, and the amplitude of the floating diffusion portion FD potential and the gain of the source potential amplitude of the amplifier transistor AMP are set to 1.

[0430] In order to cover the periphery of the FD wiring FDL with the shield wiring SL2 that leads out the source potential of the amplifier transistor AMP, the wiring connected to the floating diffusion FD moves with the same amplitude as the floating diffusion FD. Therefore, since the wiring coupling capacitance is zero, the floating diffusion FD capacitance can be reduced to improve the charge-voltage conversion efficiency.

[0431] Fig.522 is a schematic diagram showing an example of a planar configuration of a pixel circuit 210B. In the pixel circuit 210B, a reset transistor RST and a selection transistor SEL are arranged in the common p-well layer 250, and an amplifier transistor AMP is arranged in the independent p-well layer 251, while the common p-well layer 250 and the independent p-well layer 251 are electrically isolated by the full trench T7. Note that the common p-well layer 250 of the reset transistor RST and the selection transistor SEL is fixed to the GND potential.

[0432] Fig.53 The FD wiring FDL and the shield wiring SL2 are shown in FIG. Fig.52 Schematic diagram of an example of a planar configuration in which the front surface of the pixel circuit 210B shown is overlapped. The FD wiring FDL electrically connects the floating diffusion portion FD in the pixel 541 to the gate of the amplifier transistor AMP and the source of the reset transistor RST. In addition, the shield wiring SL2 electrically connects the source of the amplifier transistor AMP to the drain of the selection transistor SEL, and electrically connects the independent p-well layer 251 to the source of the amplifier transistor AMP. The shield wiring SL2 electrically connected to the source potential of the amplifier transistor AMP is arranged to cover the periphery of the FD wiring FDL, and is laid out to increase the coupling therebetween.

[0433] <10.3.2 Operation and Effect of Implementation Plan 3-1>

[0434] In the image pickup device 1, the common p-well layer 250 and the independent p-well layer 251 of the amplifier transistor AMP are electrically isolated from each other, and the FD wiring FDL is shielded by the shield wiring SL2 that connects the gate of the amplifier transistor AMP to the source of the amplifier transistor AMP. That is, by connecting the source of the amplifier transistor AMP and the independent p-well layer 251 of the amplifier transistor AMP to have the same potential, the substrate bias effect is eliminated, and the gain of the floating diffusion FD amplitude and the source amplitude of the amplifier transistor AMP is set to 1. In addition, by arranging the shield wiring SL2 that leads to the source potential of the amplifier transistor AMP around the FD wiring FDL, the wiring connected to the floating diffusion FD moves with the same amplitude as the floating diffusion FD. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0435] That is, in the image pickup device 1 , the capacitance of the FD capacitor due to the parasitic resistance of the FD wiring FDL is reduced, thereby improving the charge-voltage conversion efficiency. In addition, crosstalk between adjacent floating diffusions FD can be suppressed by the shield wiring SL2 .

[0436] Note that in Embodiment 3-1, an example has been described in which full trench isolation is used as an example of a structure for individually isolating the p-well layer of the amplifier transistor AMP, but the present invention is not limited to this and other methods may be used as long as the p-well layer can be individually isolated.

[0437] In the FD wiring FDL that connects the amplifier transistor AMP in the second substrate 200 to the floating diffusion FD in the first substrate 100, the portion of the FD wiring FDL that passes through the second substrate 200 and the first substrate 100 is shielded by the shielding wiring SL2. Within the FD wiring FDL, the portion of the FD wiring FDL that passes through the wiring layer 100T of the first substrate 100 and the wiring layer 200T of the second substrate 200 is shielded. However, the shielding wiring SL2 can shield the portion of the FD wiring FDL that passes through the wiring layer 200T of the second substrate 200, and the embodiment thereof is described below as the 3-2nd embodiment.

[0438] <10.4 Specific example of implementation plan 3-2>

[0439] <10.4.1 Structure of Implementation Plan 3-2>

[0440] Fig.54 3-2 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate 100 and a second substrate 200 of the 3-2 embodiment. The 3-2 embodiment is an example of a case where the number of arrangements of the joint CC between the wiring layer 100T and the wiring layer 200T is limited, for example, when the pixel size is reduced. The wiring layer 100T and the wiring layer 200T have an FD wiring FDL penetrating from the first substrate 100 side to the second substrate 200. The FD wiring FDL electrically connects the floating diffusion FD of the first substrate 100 to the gate of the amplifier transistor AMP of the pixel circuit 210 of the second substrate 200. The shielding wiring SL2 shields the FD wiring FDL portion of the FD wiring FDL that passes through the wiring layer 200T of the second substrate 200.

[0441] <10.4.2 Functions and Effects of Implementation Plan 3-2>

[0442] In the case where the number of joints CC is limited due to the reduction in size of the pixel 541, the shielding wiring SL2 is limited to the shielding of the FD wiring FDL in the FD wiring layer 200T on the second substrate 200 side. For example, in the case where only one joint CC can be arranged in one pixel, the FD wiring FDL can pass through the wiring layer 100T and the wiring layer 200T to connect the wiring layer 100T to the wiring layer 200T, but the source potential of the amplifier transistor AMP cannot extend to the wiring layer 100T on the first substrate 100 side. In this case, the shielding wiring SL2 is arranged to cover only the FD wiring FDL in the wiring layer 200T of the second substrate 200. Therefore, the effect of reducing the floating diffusion FD capacitance of the wiring layer 100T on the first substrate side cannot be obtained, and the FD capacitance is slightly increased compared with the FD capacitance of the 3-1 embodiment. However, the effect of reducing the FD capacitance of the wiring layer 200T on the second substrate 200 side can be obtained. It is also possible to cope with pixel reduction.

[0443] <10.5 Specific example of implementation plan 3-3>

[0444] <10.5.1 Structure of Implementation Plan 3-3>

[0445] Fig.55 2 is an equivalent circuit diagram showing a configuration example of a plurality of pixel circuits 210C and 210D of the second substrate 200 of the 3-3 embodiment. The pixel circuit 210C electrically isolates the independent p-well layer 251A from the common p-well layer 250 through the full trench T8, in which a group of amplifier transistors AMP of a plurality of pixel circuits adjacent in the column direction are arranged in the independent p-well layer 251A, and a group of reset transistors RST and selection transistors SEL adjacent in the column direction are arranged in the common p-well layer 250. In addition, the pixel circuit 210D is located in a row different from the pixel circuit 210C. Then, the pixel circuit 210D electrically isolates the independent p-well layer 251A from the common p-well layer 250 through the full trench T8, in which a group of amplifier transistors AMP of a plurality of pixel circuits adjacent in the column direction are arranged in the independent p-well layer 251A, and a group of reset transistors RST and selection transistors SEL adjacent in the column direction are arranged in the common p-well layer 250.

[0446] The amplifier transistors AMP to be read simultaneously are the amplifier transistors AMP adjacent in the row direction. Therefore, in the case of sequentially reading the pixels 541 in a row manner, when the amplifier transistors AMP read the pixel signals, the pixel signals of the amplifier transistors AMP adjacent in the column direction are not read simultaneously. Therefore, in a state where the independent p-well layers 251A of the amplifier transistors AMP adjacent in the row direction are isolated, the independent p-well layers 251A of the amplifier transistors AMP adjacent in the column direction are shared. That is, the well layer potential of the amplifier transistor AMP group adjacent in the column direction is shared, and the well layer potential of the amplifier transistor AMP group adjacent in the column direction of the next row is also shared.

[0447] Therefore, when the amplifying transistor AMP of the pixel circuit 210C1 reads the pixel signal, the well layer potential of the amplifying transistor AMP group of the pixel circuit 210C2 and the pixel circuit 210C3 of the column has the same potential as the source potential of the amplifying transistor AMP of the pixel circuit 210C1. In addition, the well layer potential of the amplifying transistor AMP of the pixel circuit 210C2 and the pixel circuit 210C3 also has the same potential as the source potential of the amplifying transistor AMP of the pixel circuit 210C1. However, since the amplifying transistor AMP of the other adjacent pixel circuits 210C2 and 210C3 in the column direction is in a non-reading period, the selection transistor SEL is disconnected and does not operate as an amplifying circuit, so there is no special influence.

[0448] For example, in the case where the pixels 541 are read sequentially in a row manner, it can be said that the amplifier transistor AMP of the pixel circuit 210C1 is read simultaneously with the amplifier transistor AMP of the pixel circuit 210D1 adjacent in the row direction. Therefore, the well layer potential of the amplifier transistor AMP of the pixel circuit 210C1 and the well layer potential of the amplifier transistor AMP of the pixel circuit 210D1 adjacent in the row direction have different potentials according to the pixel signal amount, and therefore, it is necessary to isolate the two well layers. That is, the well layer of the pixel 541 to be read simultaneously must be isolated, but there is no problem even if the well layer of the pixel 541 not to be read simultaneously is shared.

[0449] <10.5.2 Operation and Effect of Implementation Plan 3-3>

[0450] Therefore, even when the p-well layer cannot be isolated independently for each pixel due to a decrease in the number of pixels 541 or the like, the same effect as that of the 3-2nd embodiment can be obtained by isolating the p-well layer only in the row direction.

[0451] <10.6 Specific examples of implementation plans 3-4>

[0452] <10.6.1 Structure of Implementation Plan 3-4>

[0453] For example, the camera device of the 3rd-4th embodiment is a pixel camera device including a charge retention unit for a global shutter. The global shutter mode is generally a mode of performing global exposure in which the exposure of all pixels starts at the same time and the exposure of all pixels ends at the same time. Here, all pixels refer to all pixels in the portion appearing in the image, and do not include pseudo pixels, etc. In addition, if the time difference and distortion of the image are small enough so as not to cause problems, as an alternative to performing global exposure on all pixels at the same time, the global shutter mode also includes a mode of moving the area where global exposure is performed while performing global exposure in units of multiple rows (for example, tens of rows). In addition, as an alternative to all pixels in the portion appearing in the image, the global shutter mode also includes a mode of performing global exposure on pixels in a predetermined area.

[0454] Fig.56 : is an equivalent circuit diagram showing a configuration example of a pixel sharing unit 400 of a global shutter mode camera device of the third-fourth embodiment. The pixel sharing unit 400 of the global shutter mode camera device has a pixel 410 and a pixel circuit 420. The pixel 410 has a photodiode 411, a charge holding unit 412, a transfer transistor TR413, and an overflow transistor 414. In addition, the pixel circuit 420 has a reset transistor RST42, an amplifier transistor AMP42, a selection transistor SEL42, and a floating diffusion FD42.

[0455] The reset transistor RST42 has a drain connected to the power supply RST and a source connected to the floating diffusion FD42. The reset transistor RST42 initializes (i.e., resets) the floating diffusion FD42 according to the drive signal applied to its gate. For example, when the drive signal turns on the reset transistor RST42, the potential of the floating diffusion FD42 is reset to the voltage level of the power supply RST. That is, the floating diffusion FD42 is initialized.

[0456] The floating diffusion FD42 converts the charge transferred from the photodiode PD through the transfer transistor 413 and the charge holding unit 412 into an electrical signal (e.g., a voltage signal) and outputs the electrical signal. A reset transistor RST42 is connected to the floating diffusion FD42, and a vertical signal line VSL is connected to the floating diffusion FD42 through an amplifier transistor AMP42 and a select transistor SEL42.

[0457] The amplifier transistor AMP42 outputs an electrical signal according to the potential of the floating diffusion FD42. The amplifier transistor AMP42, for example, forms a source-source follower circuit together with a constant current source provided in the column signal processing unit. When a pixel is selected, the selection transistor SEL42 is turned on, and the electrical signal from the floating diffusion FD42 via the amplifier transistor AMP42 is output to the column signal processing unit through the vertical signal line VSL.

[0458] In the pixel sharing unit 400 of such a global shutter mode imaging device, pixels 410 are formed on the first substrate 100 , pixel circuits 420 are formed on the second substrate 200 , and the pixels 410 and the pixel circuits 420 are connected by FD wirings FDL.

[0459] The second substrate 200 includes a common p-well layer common to all pixels and an independent p-well layer for each amplifier transistor AMP42, and the common p-well layer and the independent p-well layer are electrically isolated by a full trench (FTI). In the common p-well layer, a reset transistor RST42 and a selection transistor SEL42 of each pixel circuit 420 are formed. Since the common p-well layer is connected to the GND potential, the back gate of the reset transistor RST42 and the back gate of the selection transistor SEL42 are fixed to the GND potential.

[0460] On the other hand, in the independent p-well layer, the amplifier transistor AMP42 of the pixel circuit 420 is formed. Since the independent p-well layer is connected to the source of the amplifier transistor AMP42, the potential of the independent p-well layer changes with the source potential of the amplifier transistor AMP42. That is, since the back gate and source potentials of the amplifier transistor AMP42 have the same potential, the gain of the source follower circuit becomes 1.

[0461] That is, the gate potential amplitude of the amplifier transistor AMP42 is equal to the source potential amplitude. That is, the potential of the shielding wiring SL4 also changes with the change in the FD potential of the FD wiring FDL. Therefore, charge transfer does not occur between the FD wiring FDL and the shielding wiring SL4, and the capacitance value between the FD wiring FDL and the shielding wiring SL4 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL4 is large, it can be ignored as the capacitance of the floating diffusion FD during the actual reading operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the FD capacitance becomes a small value. That is, since the parasitic capacitance of the FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0462] <10.6.2 Operation and Effect of Implementation Plan 3-4>

[0463] The pixel sharing unit 400 of the global shutter mode camera device of the 3rd-4th embodiment is in a state where the shared p-well layer of the amplifier transistor AMP42 is electrically isolated from the independent p-well layer. In addition, in the pixel sharing unit 400, the FD wiring FDL is shielded by the shielding wiring SL4 that connects the gate of the amplifier transistor AMP42 to the source of the amplifier transistor AMP42. That is, by connecting the source of the amplifier transistor AMP42 and the independent p-well layer of the amplifier transistor AMP42 to have the same potential, the substrate bias effect is eliminated, and the gain of the FD amplitude and the source amplitude of the amplifier transistor AMP42 is set to 1. In addition, the periphery of the FD wiring FDL is shielded by the shielding wiring SL4 that leads out the source potential of the amplifier transistor AMP42, so that the wiring connected to the floating diffusion part FD moves with the same amplitude as the floating diffusion part FD. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0464] That is, in the pixel sharing unit 400 in the global shutter mode camera device, the S / N ratio of the pixel signal is improved by improving the charge-voltage conversion efficiency while suppressing the increase of the FD capacitance due to the parasitic resistance of the FD wiring FDL. In addition, the crosstalk between adjacent floating diffusions FD can be suppressed by the shield wiring SL4.

[0465] <10.7 Specific examples of implementation plans 3-5>

[0466] <10.7.1 Structure of Implementation Plans 3-5>

[0467] Fig.57 4 is an equivalent circuit diagram showing a configuration example of a pixel sharing unit 400A of a storage-holding type global shutter mode camera device of the third to fifth embodiments. The pixel sharing unit 400A has pixels PX1 and PX4 and a pixel circuit 420A. The pixel PX1 has a photodiode PD1, first to third transfer transistors TR1A to TR1C, a charge retention unit MEM1, a discharge transistor OFG1, a discharge unit OFD1, and a buffer BUF1. The first transfer transistor TR1A includes a transfer gate TRZ1, the second transfer transistor TR1B includes a transfer gate TRY1 and a transfer gate TRX1, and the third transfer transistor TR1C includes a transfer gate TRG1.

[0468] Similarly, the pixel PX4 has a photodiode PD4, first to third transfer transistors TR4A to TR4C, a charge holding unit MEM4, a discharge transistor OFG4, a discharge unit OFD4, and a buffer BUF4. The first transfer transistor TR4A includes a transfer gate TRZ4, the second transfer transistor TR4B includes a transfer gate TRY4 and a transfer gate TRX4, and the third transfer transistor TR4C includes a transfer gate TRG4.

[0469] Furthermore, the pixel PX1 and the pixel PX4 share a pixel circuit 420A such as the power sources VDD1 and VDD2 , the floating diffusion FD14 , the reset transistor RST14 , the amplifier transistor AMP14 , and the select transistor SEL14 .

[0470] In this example, the first to third transfer transistors TR1A to TR1C and the first to third transfer transistors TR4A to TR4C are N-type MOS transistors. In addition, the reset transistor RST14, the amplifier transistor AMP14 and the selection transistor SEL14 are also N-type MOS transistors. Based on the drive control of the system control unit, the vertical drive unit and the horizontal drive unit supply drive signals to the gates of the first to third transfer transistors TR1A to TR1C and the first to third transfer transistors TR4A to TR4C. In addition, based on the drive control of the system control unit, the vertical drive unit and the horizontal drive unit supply drive signals to the respective gates of the reset transistor RST14, the amplifier transistor AMP14 and the selection transistor SEL14. These drive signals are pulse signals, in which the high level state is an active state (conduction state), and the low level state is an inactive state (cut-off state). Note that, hereinafter, setting the drive signal to the active state is also referred to as a conduction drive signal, and setting the drive signal to the inactive state is also referred to as a cut-off drive signal.

[0471] The photodiode PD1 and the photodiode PD4 are photoelectric conversion elements including PN junction photodiodes, for example, and are configured to receive light from a subject, generate charge by photoelectric conversion according to the amount of received light, and accumulate the charge.

[0472] The charge retention unit MEM1 and the charge retention unit MEM4 are respectively disposed between the photodiode PD1 and the floating diffusion FD14 and between the photodiode PD4 and the floating diffusion FD14. In addition, the charge retention unit MEM1 and the charge retention unit MEM4 are regions that temporarily retain the charges generated and accumulated in the photodiode PD1 and the photodiode PD4 until the charges are transferred to the floating diffusion FD14 to implement a global shutter function.

[0473] The first transfer transistor TR1A and the second transfer transistor TR1B are sequentially arranged between the photodiode PD1 and the charge retention unit MEM1. The third transfer transistor TR1C is arranged between the charge retention unit MEM1 and the floating diffusion FD14. The first transfer transistor TR1A and the second transfer transistor TR1B are configured to transfer the charge accumulated in the photodiode PD1 to the charge retention unit MEM1 according to the driving signal applied to the gate thereof.

[0474] Similarly, the first transfer transistor TR4A and the second transfer transistor TR4B are sequentially arranged between the photodiode PD4 and the charge retention unit MEM4. The third transfer transistor TR4C is arranged between the charge retention unit MEM4 and the floating diffusion FD14. The first transfer transistor TR4A and the second transfer transistor TR4B are configured to transfer the charge accumulated in the photodiode PD4 to the charge retention unit MEM4 according to the drive signal applied to the gate thereof.

[0475] The third transfer transistor TR1C and the third transfer transistor TR4C transfer the charges temporarily held in the charge holding unit MEM1 and the charge holding unit MEM4 to the floating diffusion FD14 according to the driving signal applied to the gate.

[0476] For example, in the pixels PX1 and PX4, it is assumed that the second transfer transistors TR1B and TR4B are turned off and the third transfer transistors TR1C and TR4C are turned on. In this case, the charges respectively held in the charge holding unit MEM1 and the charge holding unit MEM4 are transferred to the floating diffusion FD14 through the third transfer transistors TR1C and TR4C.

[0477] Buffer BUF1 and buffer BUF4 are charge accumulation regions formed between the first transfer transistor TR1A and the second transfer transistor TR1B, respectively. Reset transistor RST14 has a drain connected to power supply VDD1 and a source connected to floating diffusion FD14. Reset transistor RST14 initializes (i.e., resets) floating diffusion FD14 according to a drive signal applied to its gate. For example, when the drive signal turns on reset transistor RST14, the potential of floating diffusion FD14 is reset to the voltage level of power supply VDD1. That is, floating diffusion FD14 is initialized.

[0478] The floating diffusion FD14 converts the charge transferred from the photodiode PD1 and the photodiode PD4 through the first to third transfer transistors TR1A to TR1C and TR4A to TR4C and the charge retention units MEM1 and MEM4 into an electrical signal (e.g., a voltage signal) and outputs the electrical signal. A reset transistor RST14 is connected to the floating diffusion FD14, and a vertical signal line VSL117 is connected to the floating diffusion FD14 through an amplifier transistor AMP14 and a select transistor SEL14.

[0479] The amplifier transistor AMP14 outputs an electrical signal according to the potential of the floating diffusion FD14. The amplifier transistor AMP14, for example, forms a source follower circuit together with a constant current source provided in the column signal processing unit. When the pixel PX is selected, the selection transistor SEL14 is turned on, and the electrical signal from the floating diffusion FD14 via the amplifier transistor AMP14 is output to the column signal processing unit through the vertical signal line VSL117.

[0480] In addition to the floating diffusion FD14 as the charge transfer destination of the photodiode PD1 and the photodiode PD4, the pixels PX1 and PX4 include discharge units OFD1 and OFD4. The discharge transistor OFG1 is arranged between the first transfer transistor TR1A and the second transfer transistor TR1B, and the discharge transistor OFG4 is arranged between the first transfer transistor TR4A and the second transfer transistor TR4B.

[0481] The discharge transistor OFG1 has a drain connected to the discharge unit OFD1 and a source connected to a wiring connecting the first transfer transistor TR1A to the second transfer transistor TR1B. Similarly, the discharge transistor OFG4 has a drain connected to the discharge unit OFD4 and a source connected to a wiring connecting the first transfer transistor TR4A to the second transfer transistor TR4B. The discharge transistor OFG1 and the discharge transistor OFG4 initialize (i.e., reset) the photodiode PD1 and the photodiode PD4 according to the drive signal applied to the respective gates. Resetting the photodiode PD1 and the photodiode PD4 means depleting the photodiode PD1 and the photodiode PD4.

[0482] In addition, the discharge transistors OFG1 and OFG4 form overflow channels, respectively, and discharge the charges overflowing from the photodiodes PD1 and PD4 to the discharge units OFD1 and OFD4, respectively. As described above, in the pixels PX1 and PX4 of the present embodiment, the discharge transistors OFG1 and OFG4 can directly reset the photodiodes PD1 and PD4.

[0483] The pixel PX1, the pixel PX4, and the floating diffusion FD14 are arranged on the first substrate 100, and the pixel circuit 420A such as the reset transistor RST14, the amplifier transistor AMP14, and the selection transistor SEL14 are arranged on the second substrate 200. In addition, the gates of the floating diffusion FD of the first substrate 100 and the amplifier transistor AMP14 of the second substrate 200 are connected by the FD wiring FDL.

[0484] The second substrate 200 includes a common p-well layer shared by all pixels and an independent p-well layer for each amplifier transistor AMP14 of the pixel, and the common p-well layer and the independent p-well layer are electrically isolated by a full trench (FTI). In the common p-well layer, a reset transistor RST14 and a selection transistor SEL14 of each pixel circuit 420 are formed. Since the common p-well layer is connected to the GND potential, the back gates of the reset transistor RST14 and the selection transistor SEL14 are fixed to the GND potential.

[0485] On the other hand, in the independent p-well layer, the amplifier transistor AMP14 of the pixel circuit 420 is formed. Since the independent p-well layer is connected to the source of the amplifier transistor AMP14, the potential of the independent p-well layer changes with the source potential of the amplifier transistor AMP14. That is, since the back gate and source potentials of the amplifier transistor AMP14 have the same potential, the gain of the source follower circuit becomes 1.

[0486] That is, the gate potential amplitude of the amplifier transistor AMP14 is equal to the source potential amplitude. That is, the potential of the shielding wiring SL5 also changes with the change in the FD potential of the FD wiring FDL. Therefore, no charge transfer occurs between the FD wiring FDL and the shielding wiring SL5, and the capacitance value between the FD wiring FDL and the shielding wiring SL5 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL5 is large, it can be ignored as the capacitance of the floating diffusion FD during the actual reading operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the FD capacitance becomes a small value. That is, since the parasitic capacitance of the FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0487] <10.7.2 Operation and Effect of Implementation Plans 3-5>

[0488] The pixel sharing unit 400A of the storage-holding type global shutter mode camera device of the 3rd to 5th embodiments is in a state where the shared p-well layer is electrically isolated from the independent p-well layer of the amplifier transistor AMP. In the pixel sharing unit 400A, the FD wiring FDL is shielded by the shielding wiring SL5 that connects the gate of the amplifier transistor AMP14 to the source of the amplifier transistor AMP14. That is, by connecting the source of the amplifier transistor AMP14 to the independent p-well layer of the amplifier transistor AMP14 to have the same potential, the substrate bias effect is eliminated, and the gain of the FD amplitude and the source amplitude of the amplifier transistor AMP14 is set to 1. The periphery of the FD wiring FDL is shielded by the source potential shielding wiring SL5 that leads out the amplifier transistor AMP14, so that the wiring connected to the floating diffusion FD14 moves with the same amplitude as the floating diffusion FD14. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0489] That is, in the storage hold type global shutter mode camera, the S / N of the pixel signal is improved by improving the charge-voltage conversion efficiency while suppressing the increase of the FD capacitance due to the parasitic resistance of the FD wiring FDL. In addition, the shield wiring SL5 can suppress crosstalk between adjacent floating diffusions FD14.

[0490] In the embodiments and variations of the present invention, examples of methods for forming the above-mentioned layers, films, elements, etc. include physical vapor deposition (PVD), CVD, etc. Examples of PVD include vacuum vapor deposition using resistance heating or high-frequency heating, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, and molecular beam epitaxy (MBE), laser transfer, etc. Examples of CVD include plasma CVD, thermal CVD, MOCVD, and optical CVD. In addition, other methods include electroplating, chemical plating, and spin coating; immersion; casting; microcontact printing; drop casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; stamping; spraying; and various coating methods such as air coater, blade coater, rod coater, knife coater, extrusion coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit hole coater, and calendar coater. Examples of patterning methods of each layer include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet rays, lasers, etc. In addition, examples of planarization techniques include CMP, laser planarization, and reflow. That is, the image pickup device 1 according to the embodiment and the modification example of the present invention can be manufactured easily and inexpensively using an existing semiconductor device manufacturing process.

[0491] In the above description, an example has been described in which the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST of the pixel circuit 210 constituting the second substrate 211 are formed on the same semiconductor substrate, but the second substrate 211 may be formed of a plurality of semiconductor substrates.

[0492] In this case, if the amplifier transistor AMP is arranged at a position away from the floating diffusion, capacitance is formed between the amplifier transistor AMP and the floating diffusion, which may cause a decrease in conversion efficiency.

[0493] Therefore, preferably, among the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST, at least the amplification transistor AMP and the floating diffusion are formed on the same semiconductor substrate, and the remaining transistors are formed on other semiconductor substrates.

[0494] In this case, if the trench width W of the amplifier transistor AMP can be increased, noise can be reduced. Therefore, by adopting the above configuration in which the second substrate is formed of a plurality of semiconductors, the area that can be allocated to the amplifier transistor AMP can be increased, and noise can be reduced to improve performance.

[0495] <11. Application Examples>

[0496] Fig.58 An example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above-described embodiment and its modified examples is shown.

[0497] For example, the camera system 7 is an electronic device such as a camera device (such as a digital camera or a video camera) or a portable terminal device such as a smartphone or a tablet terminal. The camera system 7 includes, for example, the camera device 1 according to the above-mentioned embodiment and its modified example, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the camera system 7, the camera device 1 according to the above-mentioned embodiment and its modified example, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other through a bus 249.

[0498] The image pickup device 1 according to the above-described embodiment and its modified example outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the image pickup device 1 according to the above-described embodiment and its modified example. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 in units of frames. The display unit 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the image pickup device 1 according to the above-described embodiment and its modified example. The storage unit 246 records the image data of the moving image or the still image captured by the image pickup device 1 according to the above-described embodiment and its modified example in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the image pickup system 7 according to the user's operation. The power supply unit 248 appropriately supplies various power sources used as operation power sources of the image pickup device 1 according to the above-described embodiment and its modified example, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 to these supply targets.

[0499] Next, an image capturing process by the image capturing system 7 will be described.

[0500] Fig.59 An example of a flowchart of an imaging operation of the imaging system 7 is shown. The user instructs to start imaging by operating the operating unit 247 (step S101). Then, the operating unit 247 sends an imaging command to the imaging device 1 (step S102). When receiving the imaging command, the imaging device 1 (specifically, the system control circuit) performs imaging by a predetermined imaging method (step S103).

[0501] The image pickup device 1 outputs the image data obtained by the image pickup to the DSP circuit 243. Here, the image data is data for all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the image pickup device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In this way, the image pickup of the image pickup system 7 is performed.

[0502] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 7. Therefore, since the imaging device 1 can be downsized or have high definition, a small or high-definition imaging system 7 can be provided.

[0503] <12. Application Examples>

[0504] [First application example]

[0505] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile object such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0506] Fig.60 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0507] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.60 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the integrated control unit 12050.

[0508] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a drive force for the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force for the vehicle, etc.

[0509] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, flashers, and fog lights. In this case, radio waves emitted from a portable device that replaces the key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, power window device, or lights of the vehicle.

[0510] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing of a person, a vehicle, an obstacle, a sign, text on the road surface, etc., or distance detection processing.

[0511] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or invisible light such as infrared light.

[0512] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that photographs the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0513] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0514] In addition, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, etc. based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control such as automatic driving aimed at allowing the vehicle to travel autonomously without relying on the driver's operation.

[0515] Furthermore, based on the information about the exterior of the vehicle acquired by the exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare, such as switching from high beam to low beam, by controlling the headlights according to the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030.

[0516] The sound and image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of visually or auditorily providing information notification to the passengers of the vehicle or the outside of the vehicle. Fig.60 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0517] Fig.61 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0518] exist Fig.61 In the figure, the vehicle 12100 includes a camera unit 12101 as the camera unit 12031 , a camera unit 12102 , a camera unit 12103 , a camera unit 12104 , and a camera unit 12105 .

[0519] The camera unit 12101, the camera unit 12102, the camera unit 12103, the camera unit 12104 and the camera unit 12105 are, for example, arranged at positions of the vehicle 12100 such as the front nose, the side mirrors, the rear bumper, the rear door and the upper part of the windshield in the vehicle. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly acquire images of the front part of the vehicle 12100. The camera unit 12102 and the camera unit 12103 arranged at the side mirrors mainly acquire images of the parts on both sides of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or the rear door mainly acquires images of the rear part of the vehicle 12100. The front images acquired by the camera unit 12101 and the camera unit 12105 are mainly used to detect the front vehicle, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0520] Fig.61 An example of the photographing range of the camera units 12101 to 12104 is shown. The photographing range 12111 represents the photographing range of the camera unit 12101 provided at the front nose, the photographing range 12112 and the photographing range 12113 represent the photographing ranges of the camera units 12102 and 12103 provided at the side mirrors, respectively, and the photographing range 12114 represents the photographing range of the camera unit 12104 provided at the rear bumper or the rear cover. For example, by superimposing the image data photographed by the camera units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above is obtained.

[0521] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0522] For example, based on the distance information obtained from the camera unit 12101 to the camera unit 12104, the microcomputer 12051 obtains the distance of each three-dimensional object in the camera range 12111 to the camera range 12114 and the time change of the distance (relative speed relative to the vehicle 12100), so that the three-dimensional object traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the same direction as the vehicle 12100, in particular, the closest three-dimensional object on the driving path of the vehicle 12100 can be extracted as the front vehicle. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance maintained with the front vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As described above, it is possible to perform cooperative control such as automatic driving aimed at automatically driving the vehicle without relying on the driver's operation.

[0523] For example, based on the distance information obtained from the camera unit 12101 to the camera unit 12104, the microcomputer 12501 can classify the three-dimensional object data about the three-dimensional object into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, and other three-dimensional objects such as electric poles, extract the three-dimensional object data, and use the three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 classifies the obstacles around the vehicle 12100 into obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk representing the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 can perform assisted driving to avoid collision by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062 or performing forced deceleration or evasive steering by the drive system control unit 12010.

[0524] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in an image captured by the camera units 12101 to 12104. For example, such identification of a pedestrian is performed by the following steps: a step of extracting feature points in an image captured by the camera units 12101 to 12104 as infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in an image captured by the camera units 12101 to 12104 and identifies the pedestrian, the sound image output unit 12052 causes the display unit 12062 to superimpose and display a square contour line for emphasis on the identified pedestrian. In addition, the sound image output unit 12052 may cause the display unit 12062 to display an icon representing a pedestrian at a desired position, etc.

[0525] An example of a mobile body control system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the camera unit 12031 constructed as described above. Specifically, the camera device 1 according to the above-mentioned embodiment and its modified example can be applied to the camera unit 12031. By applying the technology according to the present invention to the camera unit 12031, a high-definition captured image with low noise can be obtained, and thus high-precision control can be performed in the mobile body control system by using the captured image.

[0526] [Second application example]

[0527] Fig.62 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present invention (the present technology) can be applied.

[0528] Fig.62 The figure shows a state in which an operator (doctor) 11131 performs surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0529] The endoscope 11100 includes a lens barrel 11101, a region of which a predetermined length from the distal end is inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 configured as a so-called rigid scope having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0530] An opening portion in which an objective lens is installed is provided at the distal end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel through a light guide extending inside the lens barrel 11101 and irradiated toward an observation target in a body cavity of a patient 11132 through the objective lens. Note that the endoscope 11100 may be a forward-looking endoscope, an oblique-looking endoscope, or a side-looking endoscope.

[0531] An optical system and an imaging element are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is gathered on the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the camera control unit (CCU) 11201 as raw data.

[0532] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and centrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing for displaying an image based on the image signal, such as development processing (demosaic processing), on the image signal.

[0533] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201 under the control of the CCU 11201 .

[0534] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light for photographing a surgical site, etc., to the endoscope 11100 .

[0535] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information and instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs instructions to change the imaging conditions of the endoscope 11100 (type of irradiation light, magnification or focal length, etc.).

[0536] The treatment tool control device 11205 controls the driving of the energy treatment device 11112 for cauterization and incision of tissues, sealing of blood vessels, etc. The pneumoperitoneum device 11206 delivers gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity to ensure the field of view of the endoscope 11100 and to ensure the working space of the operator. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms (such as text, images, or graphics, etc.).

[0537] For example, the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical area may include an LED, a laser light source, or a white light source including a combination thereof. In the case where the white light source includes a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 11203. In addition, in this case, by using lasers from each RGB laser light source to irradiate the observation target in a time-sharing manner, and controlling the drive of the imaging element of the camera 11102 in synchronization with the irradiation timing, it is also possible to capture images corresponding to RGB in a time-sharing manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0538] In addition, the drive of the light source device 11203 can be controlled so that the intensity of the output light changes every predetermined time. By controlling the drive of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire pictures in a time-division manner and synchronize the images, it is possible to produce an image with a high dynamic range without so-called underexposed shadows and overexposed highlights.

[0539] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed in which predetermined tissues (such as blood vessels of the surface layer of the mucosa, etc.) are imaged with high contrast by emitting light of a narrower wavelength band than the irradiation light (i.e., white light) during ordinary observation by utilizing the wavelength dependence of light absorption in human tissue. Alternatively, in special light observation, fluorescence observation for obtaining an image by fluorescence generated by irradiation with excitation light can be performed. In fluorescence observation, for example, body tissue can be irradiated with excitation light to observe fluorescence from body tissue (autofluorescence observation), or a reagent (such as indocyanine green (ICG)) can be locally injected into human tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated on the human tissue to obtain a fluorescent image. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0540] Fig.63 It shows Fig.62 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0541] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 in a manner capable of communication.

[0542] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken from the distal end of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0543] The imaging unit 11402 includes an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type) imaging elements. For example, when the imaging unit 11402 is configured as a multi-board type, image signals corresponding to RGB can be generated by respective imaging elements, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal corresponding to a three-dimensional (3D) display. By performing a 3D display, the surgeon 11131 is able to more accurately understand the depth of living tissue in the surgical site. Note that when the imaging unit 11402 is configured as a multi-board type, a plurality of lens units 11401 may be provided corresponding to the respective imaging elements.

[0544] In addition, the camera unit 11402 does not have to be arranged on the camera head 11102. For example, the camera unit 11402 can be arranged inside the lens barrel 11101, immediately behind the objective lens.

[0545] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0546] The communication unit 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the imaging unit 11402 to the CCU 11201 through the transmission cable 11400 as RAW data.

[0547] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control information includes, for example, information related to imaging conditions, such as information for specifying a frame rate of an image to be captured, information for specifying an exposure value when capturing an image, and / or information for specifying a magnification and a focus of a captured image.

[0548] Note that imaging conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are installed in the endoscope 11100.

[0549] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received through the communication unit 11404 .

[0550] The communication unit 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0551] In addition, the communication unit 11411 sends a control signal to the camera 11102 to control the driving of the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0552] The image processing unit 11412 performs various types of image processing on the image signal of RAW data sent from the camera 11102 .

[0553] The control unit 11413 performs various types of control related to photographing of a surgical site, etc. by the endoscope 11100 and display of a photographed image obtained by photographing the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0554] In addition, the control unit 11413 causes the display device 11202 to display a captured image in which a surgical site, etc., is shown based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, fog when the energy treatment device 11112 is used, etc. by detecting the shape, color, etc. of the edge of the object contained in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can superimpose and display various types of surgical support information on the image of the surgical site by using the result of the recognition. Since the surgical support information is superimposed and displayed and presented to the operator 11131, the burden of the operator 11131 can be reduced, and the operator 11131 can perform the operation with confidence.

[0555] The transmission cable 11400 connecting the camera head 11102 to the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0556] Here, in the example shown in the drawing, communication is performed by wired means using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed wirelessly.

[0557] An example of an endoscopic surgical system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the imaging unit 11402 of the camera head 11102 of the endoscope 11100 in the above-mentioned structure. By applying the technology according to the present invention to the imaging unit 11402, the imaging unit 11402 can be reduced in size or have high definition, so that a small-sized or high-definition endoscope 11100 can be provided.

[0558] Although the present invention has been described with reference to the embodiments, variations and application examples thereof, the present invention is not limited to the embodiments described above, etc., and various variations are possible. Note that the effects described in this specification are merely examples. The effects of the present invention are not limited to the effects described in this specification. The present invention may have effects other than those described in this specification.

[0559] Furthermore, for example, the present invention may have the following configurations.

[0560] (1) A camera device, comprising:

[0561] a first substrate having a pixel including a photodiode and a floating diffusion portion, the floating diffusion portion holding charges converted by the photodiode;

[0562] a second substrate including a pixel circuit and stacked on the first substrate, the pixel circuit reading a pixel signal based on the charge held in the floating diffusion within the pixel;

[0563] a wiring that penetrates the first substrate and the second substrate in a stacking direction and electrically connects the floating diffusion in the first substrate to an amplifying transistor in the pixel circuit of the second substrate; and

[0564] A trench is formed at least in the second substrate, extends parallel to the wiring, and has a depth equal to or greater than a thickness of the semiconductor layer in the second substrate. (2)

[0566] The imaging device according to (1), further comprising: a shield wiring connecting the conductive material embedded in the trench to a source of the amplifying transistor. (3)

[0568] The imaging device according to (1), wherein a gas having a low dielectric constant is sealed in the groove. (4)

[0570] The imaging device according to (1) or (2),

[0571] Characterized in that the first substrate has:

[0572] semiconductor layer, and

[0573] A wiring layer, which is stacked on the semiconductor layer and is made of SiO 2 form. (5)

[0575] The imaging device according to (1) or (2),

[0576] Characterized in that the first substrate has:

[0577] semiconductor layer, and

[0578] The wiring layer is stacked on the semiconductor layer and is made of a dielectric constant lower than that of SiO 2 of insulating material. (6)

[0580] According to the imaging device described in (1),

[0581] Characterized in that the groove

[0582] formed on the semiconductor layer in the second substrate to electrically separate the wiring from other wirings extending parallel thereto. (7)

[0584] According to the imaging device described in (6),

[0585] It is characterized in that, when observed from the stacking surface of the second substrate,

[0586] The groove is formed on the semiconductor layer in the second substrate and surrounds the wiring in a circular shape. (8)

[0588] According to the imaging device described in (6),

[0589] It is characterized in that, when observed from the stacking surface of the second substrate,

[0590] The trench is formed on the semiconductor layer in the second substrate and surrounds the wiring in a rectangular shape. (9)

[0592] A camera device, comprising:

[0593] a first substrate having a pixel including a photodiode and a floating diffusion portion, the floating diffusion portion holding charges converted by the photodiode;

[0594] a second substrate having a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion within the pixel and is stacked on the first substrate;

[0595] a wiring which electrically connects the floating diffusion in the first substrate to the amplifying transistor in the pixel circuit of the second substrate and is formed in the first substrate and the second substrate, and

[0596] A shielding wiring electrically connects the gate of the amplifier transistor and the source of the amplifier transistor in a state where the well layer of the pixel circuit and the well layer of the amplifier transistor in the pixel circuit are electrically isolated from each other, and the shielding wiring shields the wiring while extending in parallel with the wiring. (10)

[0598] According to the imaging device described in (9),

[0599] Characterized in that the shielded wiring

[0600] At least a wiring portion passing through the second substrate of the wiring connecting the amplifying transistor in the second substrate to the floating diffusion in the first substrate is shielded. (11)

[0602] According to the imaging device described in (9),

[0603] Characterized in that the shielded wiring

[0604] A wiring portion of the wiring connecting the amplifying transistor in the second substrate to the floating diffusion in the first substrate that passes through the second substrate and the first substrate is shielded. (12)

[0606] The imaging device according to (9), characterized in that at least a portion of the shielding wiring is located at a shorter distance from the wiring than other wiring. (13)

[0608] The imaging device according to (9), wherein a coupling capacitance between the wiring and the shield wiring is larger than a coupling capacitance between the wiring and other wirings. (14)

[0610] The imaging device according to (9), further comprising:

[0611] a column signal processing unit connected to the plurality of pixel circuits via a plurality of vertical signal lines,

[0612] The column signal processing unit includes an AD converter and a load circuit, and outputs pixel data according to the voltage of the vertical signal line, and the AD converter performs AD conversion based on a reference signal. (15)

[0614] The imaging device according to (9), further comprising:

[0615] a column signal processing unit connected to the plurality of pixel circuits via a plurality of vertical signal lines,

[0616] Wherein, the column signal processing unit comprises:

[0617] RAMP generating circuit, which generates and outputs RAMP waveform,

[0618] a comparator that compares the voltage of the pixel signal read through the vertical signal line with the voltage of the RAMP waveform,

[0619] a counter for counting based on the comparison result signal of the comparator, and

[0620] A latch outputs pixel data according to the count value of the counter. (16)

[0622] According to the imaging device described in (15),

[0623] The comparator is constructed as a single slope ADC. (17)

[0625] According to the imaging device described in (15),

[0626] The comparator includes a transistor having a source terminal and a gate terminal and outputting a comparison result signal according to a gate-source voltage, wherein the source terminal is applied with the pixel signal read through the vertical signal line, and the gate terminal is applied with the RAMP waveform. (18)

[0628] The imaging device according to (9), further comprising:

[0629] a column signal processing unit connected to the plurality of pixel circuits via a plurality of vertical signal lines,

[0630] Wherein, the column signal processing unit comprises:

[0631] Load circuit,

[0632] a front circuit that connects the current generated by the load circuit to the vertical signal line and is configured as a current reuse circuit, and

[0633] an AD converter that performs AD conversion based on a predetermined reference signal, and

[0634] The column signal processing unit outputs pixel data according to the voltage of the vertical signal line.

[0635] Reference numerals list

[0636] 1 Camera device

[0637] 100 First Substrate

[0638] 100T wiring layer

[0639] 200 Second substrate

[0640] 200T wiring layer

[0641] 210A pixel circuit

[0642] 250 shared p-well layer

[0643] 251 Independent P-well layer

[0644] 541 pixels

[0645] 554 Comparator

[0646] 558 Comparator

[0647] 561 preamplifier circuit

[0648] PD Photodiode

[0649] FD floating diffusion

[0650] FDL FD wiring

[0651] T groove

[0652] SL shielded wiring

Claims

1. A light detection device, comprising: A first semiconductor layer including a photoelectric conversion region and a floating diffusion; a second semiconductor layer including an amplifying transistor; a first wiring layer including a first electrode and a second electrode; and a second wiring layer including a third electrode and a fourth electrode, wherein the first electrode contacts the third electrode, wherein the second electrode contacts the fourth electrode, wherein the first electrode is electrically connected to the first element, wherein the second electrode is electrically connected to the second element, and Wherein, the first element and the second element are different.

2. The light detection device according to claim 1, wherein: The first element is the floating diffusion or the photoelectric conversion region.

3. The light detection device according to claim 1, wherein: The second element is a first wiring in the first wiring layer or a second wiring in the second wiring layer.

4. The light detection device according to claim 3, wherein: The first wiring or the second wiring is a shielded wiring.

5. The light detection device according to claim 3, wherein: The first wiring or the second wiring is electrically connected to a predetermined potential, a ground potential, or a fixed potential.

6. The light detection device according to claim 3, wherein: The first wiring or the second wiring electrically isolates the floating diffusion.

7. The light detection device according to claim 1, wherein The first electrode and the second electrode are electrically separated from each other.

8. The light detection device according to claim 1, wherein The first electrode is electrically independent from the second electrode.

9. The light detection device according to claim 1, wherein: The second semiconductor layers are separated by isolation regions.

10. The light detection device according to claim 9, wherein: The isolation region is a full trench.

11. The light detection device according to claim 1, wherein: The third electrode is electrically connected to the amplifying transistor, the reset transistor, or the selecting transistor.

12. The light detection device according to claim 1, wherein The fourth electrode is electrically connected to a first wiring in the first wiring layer or a second wiring in the second wiring layer.

13. The light detection device according to claim 12, wherein: The first wiring or the second wiring is a shielded wiring.

14. The light detection device according to claim 12, wherein: The first wiring or the second wiring is electrically connected to a predetermined potential, a ground potential, or a fixed potential.

15. The light detection device according to claim 12, wherein: The first wiring or the second wiring electrically separates the floating diffusion.

16. The light detection device according to claim 1, wherein The third wiring or the fourth wiring is electrically separated from each other.

17. The light detection device according to claim 1, wherein The third electrode is electrically independent from the fourth electrode.

18. A light detection device, comprising: A first semiconductor layer including a photoelectric conversion region and a floating diffusion; a second semiconductor layer including an amplifying transistor; a first wiring layer including a first electrode and a second electrode; and a second wiring layer including a third electrode and a fourth electrode, wherein the first electrode contacts the third electrode, wherein the second electrode contacts the fourth electrode, wherein the first electrode is electrically connected to the floating diffusion portion, wherein the third electrode is electrically connected to the amplifying transistor, and Wherein, the second semiconductor layers are separated by isolation regions.

19. The light detection device according to claim 18, wherein: The isolation region is a full trench.

20. The light detection device according to claim 18, wherein The first region of the second semiconductor layer includes the amplifying transistor, and the second region of the second semiconductor layer includes a reset transistor, a selection transistor, or a region electrically connected to a ground level.

Images