Preparation method of back contact solar cell

Abstract

The invention relates to a preparation method of a back contact solar cell. The preparation method comprises the following steps: carrying out double-sided polishing on a crystalline silicon substrate; performing phosphorus diffusion on the crystalline silicon substrate to form an n-type heavily doped region; sequentially depositing a silicon oxide thin film, a phosphorus-doped polycrystalline silicon layer and a mask layer on the back surface of the crystalline silicon substrate; forming first opening areas distributed at intervals on the back surface of the crystalline silicon substrate; cleaning and texturing, forming a textured surface on the front surface of the crystalline silicon substrate, and removing the n-type heavily doped region at the first opening region; performing cleaning; an intrinsic amorphous silicon layer and a silicon nitride anti-reflection layer are sequentially deposited on the front surface, and an intrinsic amorphous silicon layer and a borohydride-doped microcrystalline silicon layer are sequentially deposited on the back surface; forming second opening areas distributed at intervals on the back surface; depositing a transparent conductive film on the back surface, and then forming third opening areas distributed at intervals; and preparing a metal electrode on the outer side of the transparent conductive film on the back of the crystalline silicon substrate. The open-circuit voltage and the current density of the back contact solar cell are improved, and the product performance is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cell components, and in particular relates to a method for preparing a back-contact solar cell. Background Art

[0002] With the development of solar cell technology, heterojunction back-contact cells that combine silicon-based heterojunction solar cell technology and back-contact technology have attracted more and more attention from the industry. The front of the heterojunction back-contact cell has no metal electrode blocking, eliminating the problem of front electrode shading loss and can receive more sunlight. The surface of the silicon substrate uses intrinsic amorphous silicon passivation or tunneling oxide layer passivation, which reduces surface recombination and can increase the open circuit voltage. It is a very efficient solar cell technology solution.

[0003] CN117410385B discloses a method for preparing a combined passivation back contact battery by removing part of the mask layer, which comprises the following steps: S1, providing a double-sided polished silicon wafer; S2, sequentially forming a first semiconductor layer and a mask layer on the back of the silicon wafer obtained in S1, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline layer; S3, performing a first etching on the first semiconductor layer in a preset area on the back of the silicon wafer obtained in S2 to form a second semiconductor opening area with interval distribution; S4, forming a velvet surface in the second semiconductor opening area on the back and on the front at the same time through velvet cleaning; S5, then removing part of the mask layer to reduce the thickness D of the mask layer formed in S2, wherein the thickness of the removed mask layer is d satisfies: 50%≤d / D<100%; S6, then a second semiconductor layer is formed on the back side obtained in S5, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer; a front passivation layer and an anti-reflection layer are formed on the front side of the silicon wafer; S7, a second etching is performed on the polished area on the back side of the silicon wafer obtained in S6 by laser to form a first semiconductor opening area; S8, a conductive film layer is formed on the back side of the silicon wafer obtained in S7; S9, a third etching is performed on the conductive film layer on the back side of the silicon wafer obtained in S8 to form an insulating groove located between the first semiconductor opening area and the second semiconductor opening area; S10, metal electrodes are formed at the first semiconductor opening area and the second semiconductor opening area on the back side of the silicon wafer obtained in S9. Although this method has the advantages of a short process flow and a good passivation effect of the second semiconductor compared with the previous method, the open circuit voltage and current density of the battery still need to be further improved. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a back-contact solar cell with higher open circuit voltage and current density.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A first aspect of the present invention provides a method for preparing a back-contact solar cell, comprising the following steps:

[0007] (1) Double-sided polishing of a crystalline silicon substrate;

[0008] (2) performing phosphorus diffusion on the crystalline silicon substrate treated in step (1), and doping phosphorus on the front and back sides of the crystalline silicon substrate to form an n-type heavily doped region;

[0009] (3) depositing a silicon oxide film, a phosphorus-doped polysilicon layer, and a mask layer in sequence on the back side of the crystalline silicon substrate having the n-type heavily doped region;

[0010] (4) etching a first preset area on the back side of the crystalline silicon substrate processed in step (3) to remove the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer at the first preset area to form first opening areas distributed at intervals;

[0011] (5) cleaning and texturing the crystalline silicon substrate after the treatment in step (4), forming a textured surface on the front side of the crystalline silicon substrate, and removing damage on the back side of the crystalline silicon substrate and the n-type heavily doped region in the first opening area;

[0012] (6) cleaning the crystalline silicon substrate after being processed in step (5) to remove the mask layer;

[0013] (7) depositing an intrinsic amorphous silicon layer and a silicon nitride anti-reflection layer on the front side of the crystalline silicon substrate treated in step (6), and depositing an intrinsic amorphous silicon layer and a boron hydride-doped microcrystalline silicon layer on the back side;

[0014] (8) etching a second preset area on the back side of the crystalline silicon substrate processed in step (7) to remove the intrinsic amorphous silicon layer and the boron hydride-doped microcrystalline silicon layer at the second preset area to form a second opening area distributed at intervals;

[0015] (9) depositing a transparent conductive film on the back side of the crystalline silicon substrate treated in step (8), and then removing a portion of the transparent conductive film to form a third opening area distributed at intervals outside the boron hydride-doped microcrystalline silicon layer;

[0016] (10) Preparing a metal electrode on the outer side of the transparent conductive film on the back side of the crystalline silicon substrate treated in step (9).

[0017] According to some specific implementations, in step (1), when performing the double-sided polishing, the corrosion depth of a single side is controlled to be 3 to 5 microns.

[0018] According to some specific embodiments, the phosphorus diffusion in step (2) is performed in a tube furnace.

[0019] According to some specific embodiments, in step (2), the phosphorus diffusion is performed at 830-870°C.

[0020] According to some specific implementations, in step (2), the doping depth of the n-type heavily doped region is controlled to be 0.5 to 1 micrometer.

[0021] According to some specific embodiments, step (2) further includes the step of cleaning and removing the phosphosilicate glass formed on the surface of the crystalline silicon substrate after the phosphorus diffusion is completed.

[0022] According to some specific embodiments, in step (3), the thickness of the silicon oxide film is 1 to 2.5 nanometers, the thickness of the phosphorus-doped polysilicon layer is 120 to 150 nanometers, and the thickness of the mask layer is 50 to 60 nanometers; the mask layer is a silicon nitride mask layer.

[0023] According to some specific embodiments, in step (4), the first opening area is a straight line segment, the number of the first opening areas is 40 to 70, and the width of each of the first opening areas is 0.5 to 1.5 mm.

[0024] According to some specific embodiments, in step (7), the thickness of the intrinsic amorphous silicon layer is 4 to 6 nanometers, the thickness of the silicon nitride anti-reflection layer is 60 to 80 nanometers, and the thickness of the boron hydride-doped microcrystalline silicon layer is 15 to 25 nm.

[0025] According to some specific embodiments, in step (8), the second opening region is located on the outer surface of the phosphorus-doped polysilicon layer, and the width of the second opening region is smaller than the width of the phosphorus-doped polysilicon layer.

[0026] According to some specific embodiments, in step (9), the material of the transparent conductive film is indium oxide.

[0027] According to some specific embodiments, in step (9), the thickness of the transparent conductive film is 100-110 nm.

[0028] According to some specific embodiments, in step (3), the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer are deposited by PECVD or LPCVD and then annealed, and the annealing temperature is controlled to be 800-900° C. and the annealing time is 20-50 minutes.

[0029] According to some specific embodiments, in step (4) and step (8), the etching is performed using laser.

[0030] According to some specific embodiments, in step (5), an alkaline solution is used to perform the cleaning and texturing to form a pyramid texture surface on the front side of the crystalline silicon substrate.

[0031] According to some specific embodiments, in step (6), HF solution is used for cleaning.

[0032] According to some specific embodiments, in step (7), the deposition is performed using a CVD process.

[0033] According to some specific implementations, in step (9), the deposition is performed by PVD, and a portion of the transparent conductive film is removed by laser etching.

[0034] According to some specific embodiments, in step (10), the metal electrode is prepared by screen printing or electroplating.

[0035] According to some specific embodiments, there are multiple metal electrodes, one metal electrode is arranged on the transparent conductive film at the corresponding position of each first opening area, one metal electrode is arranged on the transparent conductive film at the corresponding position of each second opening area, and one third opening area is arranged between two adjacent metal electrodes.

[0036] The second aspect of the present invention provides a back-contact solar cell manufactured by the above-mentioned manufacturing method.

[0037] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0038] The present invention improves the preparation method so that only the n-type heavily doped region is retained on the front of the silicon oxide film, and through the improvement of other structures of the back contact solar cell, the metal impurities of the silicon wafer are reduced, the life of the silicon wafer is increased, and the resistivity of the back of the silicon wafer is reduced, the thin layer conductivity is improved, and the open circuit voltage and current density of the back contact solar cell are increased, thereby improving the product performance. In addition, the preparation method of the present invention is suitable for industrial large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 is a schematic cross-sectional view of the silicon wafer prepared in step (3);

[0041] Figure 2 is a schematic cross-sectional view of the silicon wafer prepared in step (4);

[0042] Figure 3 is a schematic cross-sectional view of the silicon wafer prepared in step (6);

[0043] Figure 4is a schematic cross-sectional view of the silicon wafer prepared in step (7);

[0044] Figure 5 is a schematic cross-sectional view of the silicon wafer prepared in step (8);

[0045] Figure 6 is a schematic cross-sectional view of the silicon wafer prepared in step (9);

[0046] Figure 7 Schematic diagram of the cross-section of the back-contact solar cell prepared in step (10). DETAILED DESCRIPTION

[0047] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the embodiments of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0048] All features disclosed in the present invention, or steps in all methods or processes disclosed, except mutually exclusive features or steps, may be combined in any manner.

[0049] The technical solution of the present invention is further described below in conjunction with specific embodiments, but the present invention should not be limited to these embodiments. Unless otherwise described, all can be replaced by other alternative features that are equivalent or have similar purposes. Unless otherwise described, each feature is just an example of a series of equivalent or similar features. The terms used in the present invention, unless otherwise specified, generally have the meanings commonly understood by those of ordinary skill in the art. The implementation conditions used in the embodiments can be further adjusted according to the different requirements of specific use, and the implementation conditions not specified are conventional conditions in the industry. The technical features involved in each embodiment of the present invention can be combined with each other as long as they do not conflict with each other.

[0050] In the present invention, the methods without special instructions are conventional methods in the art. The raw materials in the present invention can be purchased from the market or prepared by conventional methods in the prior art. In the present invention, unless otherwise specified, the contents are all mass contents, and "%" is mass percentage.

[0051] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the present invention, the front side refers to the side of the solar cell facing the sun, and the back side refers to the side of the solar cell facing away from the sun, that is, the side opposite to the front side; Figure 7 The above directional words are only used to facilitate the description of the embodiments of the present invention and simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0053] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they can be included or not (or can be included or not).

[0054] The present invention provides a method for preparing a back-contact solar cell, comprising the following steps:

[0055] (1) Double-sided polishing of a crystalline silicon substrate;

[0056] (2) performing phosphorus diffusion on the crystalline silicon substrate treated in step (1), doping phosphorus on the front and back sides of the crystalline silicon substrate to form an n-type heavily doped region, and depositing phosphosilicate glass on the surface; and cleaning with an HF solution to remove the phosphosilicate glass;

[0057] (3) depositing a silicon oxide film, a phosphorus-doped polysilicon layer, and a mask layer in sequence on the back side of the crystalline silicon substrate having the n-type heavily doped region;

[0058] (4) etching a first preset area on the back side of the crystalline silicon substrate processed in step (3) to remove the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer at the first preset area to form first opening areas distributed at intervals;

[0059] (5) cleaning and texturing the crystalline silicon substrate after the treatment in step (4), forming a textured surface on the front side of the crystalline silicon substrate, and removing damage on the back side of the crystalline silicon substrate and the n-type heavily doped region in the first opening area;

[0060] (6) cleaning the crystalline silicon substrate after being processed in step (5) to remove the mask layer;

[0061] (7) depositing an intrinsic amorphous silicon layer and a silicon nitride anti-reflection layer on the front side of the crystalline silicon substrate treated in step (6), and depositing an intrinsic amorphous silicon layer and a boron hydride-doped microcrystalline silicon layer on the back side;

[0062] (8) etching a second preset area on the back side of the crystalline silicon substrate processed in step (7) to remove the intrinsic amorphous silicon layer and the boron hydride-doped microcrystalline silicon layer at the second preset area to form a second opening area distributed at intervals;

[0063] (9) depositing a transparent conductive film on the back side of the crystalline silicon substrate treated in step (8), and then removing a portion of the transparent conductive film to form a third opening area distributed at intervals outside the boron hydride-doped microcrystalline silicon layer;

[0064] (10) Preparing a metal electrode on the outer side of the transparent conductive film on the back side of the crystalline silicon substrate treated in step (9).

[0065] In some specific implementations, in step (1), when performing the double-sided polishing, the etching depth of a single side is controlled to be 3 to 5 microns, wherein a single side refers to the front side or the back side of the crystalline silicon substrate.

[0066] In some specific embodiments, the crystalline silicon substrate can be any single crystal silicon wafer, such as N-type single crystal silicon. The size of the crystalline silicon substrate can also be any size, such as 210 mm×105 mm or 182 mm×91 mm in length and width, and 80 microns to 130 microns in thickness. Those skilled in the art can use sodium hydroxide alkaline solution to clean according to the actual needs in accordance with the conventional method.

[0067] In some specific embodiments, the phosphorus diffusion in step (2) is performed in a tube furnace.

[0068] In some specific embodiments, in step (2), the phosphorus diffusion is performed at 830-870°C.

[0069] In some specific embodiments, in step (2), the doping depth of the n-type heavily doped region is controlled to be 0.5 to 1 micron. Further controlling the doping depth of the n-type heavily doped region is beneficial to further improve the open circuit voltage and current density of the battery.

[0070] The n-type heavily doped region of the present invention can be prepared by conventional methods in the art. For example, when phosphorus diffusion is performed, the ion concentration is 10e17cm -3 Above, for example 10e17cm -3 ~10e18cm -3 , more specifically 10e17cm -3 The components of the phosphosilicate glass in the present invention include phosphorus pentoxide, silicon oxide and the like.

[0071] In some specific embodiments, in step (3), the thickness of the silicon oxide film is 1 to 2.5 nanometers, the thickness of the phosphorus-doped polysilicon layer is 120 to 150 nanometers, and the thickness of the mask layer is 50 to 60 nanometers.

[0072] In some specific embodiments, the mask layer is a silicon nitride mask layer.

[0073] In some specific embodiments, in step (3), the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer are deposited by PECVD or LPCVD and then annealed, and the annealing temperature is controlled to be 800-900° C. and the annealing time is 20-50 minutes.

[0074] In some specific embodiments, in step (4), the first opening area is a straight line segment, the number of the first opening areas is 40 to 70, and the width of each of the first opening areas is 0.5 to 1.5 mm.

[0075] In some specific embodiments, the etching in step (4) is performed using a laser.

[0076] In some specific embodiments, in step (5), an alkaline solution is used to perform the cleaning and texturing to form a pyramid texture surface on the front side of the crystalline silicon substrate.

[0077] In some specific embodiments, in step (6), HF solution is used for cleaning.

[0078] In some specific embodiments, in step (7), the thickness of the intrinsic amorphous silicon layer located on the front side of the crystalline silicon substrate is 4 to 6 nanometers, the thickness of the intrinsic amorphous silicon layer located on the back side of the crystalline silicon substrate is 4 to 6 nanometers, the thickness of the silicon nitride anti-reflection layer is 60 to 80 nanometers, and the thickness of the boron hydride-doped microcrystalline silicon layer is 15 to 25 nm.

[0079] In some specific embodiments, in step (7), the deposition is performed using a CVD process.

[0080] In some specific embodiments, in step (8), the second opening region is located on the outer surface of the phosphorus-doped polysilicon layer, and the width of the second opening region is smaller than the width of the phosphorus-doped polysilicon layer.

[0081] In some specific embodiments, in step (8), the etching is performed using a laser.

[0082] In some specific embodiments, in step (9), the material of the transparent conductive film is indium oxide.

[0083] In some specific embodiments, in step (9), the thickness of the transparent conductive film is 100-110 nm.

[0084] In some specific embodiments, in step (9), the deposition is performed by PVD, and a portion of the transparent conductive film is removed by laser etching.

[0085] In some specific embodiments, in step (10), the metal electrode is prepared by screen printing or electroplating.

[0086] In some specific embodiments, there are multiple metal electrodes, one metal electrode is disposed on the transparent conductive film at a position corresponding to each first opening region, one metal electrode is disposed on the transparent conductive film at a position corresponding to each second opening region, and one third opening region is disposed between two adjacent metal electrodes. It is understandable that the polarity of the metal electrode at the first opening region is different from that of the metal electrode at the second opening region.

[0087] The specific conditions of the processes such as PECVD, LPCVD, laser etching, CVD and PVD in the present invention can be carried out with reference to the prior art, as long as the corresponding purposes of the present invention can be achieved.

[0088] The thickness of each layer in the present invention is measured by average thickness, and the layers in the drawings are only exemplary and do not represent the actual structure of the product.

[0089] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0090] Example 1

[0091] A method for preparing a back-contact solar cell comprises the following steps:

[0092] (1) using a sodium hydroxide alkaline solution to perform double-sided polishing on an N-type single crystal silicon substrate 11 having a length and width of 210 mm×105 mm and a thickness of 80 μm to 130 μm, and the etching depth of one side is 4 μm;

[0093] (2) performing phosphorus diffusion on the crystalline silicon substrate 11 treated in step (1) in a tube furnace, controlling the phosphorus diffusion temperature to be 850° C., doping phosphorus on the front and back sides of the crystalline silicon substrate to form an n-type heavily doped region, with a doping depth of 0.7 μm; and depositing phosphosilicate glass on the surface; using HF solution to clean and remove the phosphosilicate glass;

[0094] (3) On the back side of the crystalline silicon substrate 11 with the n-type heavily doped region, deposition is performed by PECVD or LPCVD, followed by annealing, and a silicon oxide film 14, a phosphorus-doped polysilicon layer 15, and a silicon nitride mask layer 21 are sequentially deposited to form a Figure 1 In the structure shown, the thickness of the silicon oxide film 14 is 1.5 nanometers, the thickness of the phosphorus-doped polysilicon layer 15 is 135 nanometers, and the thickness of the silicon nitride mask layer 21 is 55 nanometers; the annealing temperature is controlled to be 850° C., and the annealing time is 35 minutes;

[0095] (4) laser etching is performed on a first preset area on the back side of the crystalline silicon substrate 11 processed in step (3) to remove the silicon oxide film 14, the phosphorus-doped polysilicon layer 15 and the mask layer 21 at the first preset area to form first opening areas 22 distributed at intervals, and to form a first opening area 22 as shown in FIG. Figure 2 The structure shown; the first opening area 22 is a straight line segment, the number of the first opening areas 22 is 60, and the width of each of the first opening areas 22 is 1 mm.

[0096] (5) cleaning and texturing the crystalline silicon substrate 11 after the treatment in step (4) with an alkaline solution, forming a pyramid texture surface on the front side of the crystalline silicon substrate 11, and removing damage on the back side of the crystalline silicon substrate and the n-type heavily doped region at the first opening area 22;

[0097] (6) The crystalline silicon substrate 11 treated in step (5) is cleaned with an HF solution to remove the mask layer 21, forming a Figure 3 The structure shown;

[0098] (7) Using a CVD process, an intrinsic amorphous silicon layer 12 and a silicon nitride anti-reflection layer 13 are sequentially deposited on the front side of the crystalline silicon substrate 11 after the treatment in step (6), and an intrinsic amorphous silicon layer 16 and a boron-hydrogen-doped microcrystalline silicon layer 17 are sequentially deposited on the back side to form a Figure 4 The structure shown; the thickness of the intrinsic amorphous silicon layer 12 located on the front side of the crystalline silicon substrate 11 is 5 nanometers, the thickness of the intrinsic amorphous silicon layer 16 located on the back side of the crystalline silicon substrate 11 is 5 nanometers, the thickness of the silicon nitride anti-reflection layer 13 is 70 nanometers, and the thickness of the boron hydride-doped microcrystalline silicon layer 17 is 20 nm;

[0099] (8) laser etching is performed on the second preset area on the back side of the crystalline silicon substrate 11 after the treatment in step (7), and the intrinsic amorphous silicon layer 16 and the boron hydride-doped microcrystalline silicon layer 17 at the second preset area are removed to form a second opening area 23 distributed at intervals, and the second opening area 23 is formed as shown in FIG. Figure 5 The structure shown; the second opening region 23 is located on the outer surface of the phosphorus-doped polysilicon layer 15, and the width of the second opening region 23 is smaller than the width of the phosphorus-doped polysilicon layer 15;

[0100] (9) using PVD to deposit an indium oxide transparent conductive film 18 on the back side of the crystalline silicon substrate 11 processed in step (8), and then using laser etching to remove a portion of the transparent conductive film 18 to form a third opening region 24 distributed at intervals outside the boron hydride-doped microcrystalline silicon layer 17, forming a Figure 6 The structure shown; the thickness of the transparent conductive film 18 is 105nm;

[0101] (10) A metal electrode 19 is prepared on the outer side of the transparent conductive film 18 on the back side of the crystalline silicon substrate 11 after the treatment in step (9) by screen printing or electroplating to form a Figure 7 The structure shown.

[0102] Example 2

[0103] The method is basically the same as Example 1, except that the temperature of phosphorus diffusion in step (2) is 830° C. and the doping depth of the n-type heavily doped region is 0.5 μm.

[0104] Example 3

[0105] The method is basically the same as Example 1, except that the temperature of phosphorus diffusion in step (2) is 870° C. and the doping depth of the n-type heavily doped region is 1 μm.

[0106] Comparative Example 1

[0107] The method is basically the same as Example 1, except that step (2) is omitted, that is, there is no n-type heavily doped region between the crystalline silicon substrate and the silicon oxide film of the solar cell.

[0108] The back contact solar cell prepared by the present invention can effectively improve the open circuit voltage, current density and photoelectric conversion efficiency of the battery. Among them, the open circuit voltage of Example 1 is 0.744V, and the current density is 42.5mA / cm 2 The cell photoelectric conversion efficiency is 26.5%. Compared with Comparative Example 1, the open circuit voltage of Example 1 is increased by 1 mV, the fill factor is increased by 0.1%, and the efficiency is increased by 0.06%.

[0109] The present invention improves the preparation method so that only the n-type heavily doped region is retained on the front of the silicon oxide film, and through the improvement of other structures of the back contact solar cell, the metal impurities of the silicon wafer are reduced, the life of the silicon wafer is increased, and the resistivity of the back of the silicon wafer is reduced, the thin layer conductivity is improved, and the open circuit voltage and current density of the back contact solar cell are increased, thereby improving the product performance. In addition, the preparation method of the present invention is suitable for industrial large-scale production.

[0110] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a back contact solar cell, characterized in that: The steps include: (1) Double-sided polishing of a crystalline silicon substrate; (2) performing phosphorus diffusion on the crystalline silicon substrate treated in step (1), and doping phosphorus on the front and back sides of the crystalline silicon substrate to form an n-type heavily doped region; (3) depositing a silicon oxide film, a phosphorus-doped polysilicon layer, and a mask layer in sequence on the back side of the crystalline silicon substrate having the n-type heavily doped region; (4) etching a first preset area on the back side of the crystalline silicon substrate processed in step (3) to remove the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer at the first preset area to form first opening areas distributed at intervals; (5) cleaning and texturing the crystalline silicon substrate after the treatment in step (4), forming a textured surface on the front side of the crystalline silicon substrate, and removing damage on the back side of the crystalline silicon substrate and the n-type heavily doped region in the first opening area; (6) cleaning the crystalline silicon substrate after being processed in step (5) to remove the mask layer; (7) depositing an intrinsic amorphous silicon layer and a silicon nitride anti-reflection layer on the front side of the crystalline silicon substrate treated in step (6), and depositing an intrinsic amorphous silicon layer and a boron hydride-doped microcrystalline silicon layer on the back side; (8) etching a second preset area on the back side of the crystalline silicon substrate processed in step (7) to remove the intrinsic amorphous silicon layer and the boron hydride-doped microcrystalline silicon layer at the second preset area to form a second opening area distributed at intervals; (9) depositing a transparent conductive film on the back side of the crystalline silicon substrate treated in step (8), and then removing a portion of the transparent conductive film to form a third opening area distributed at intervals outside the boron hydride-doped microcrystalline silicon layer; (10) Preparing a metal electrode on the outer side of the transparent conductive film on the back side of the crystalline silicon substrate treated in step (9).

2. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (1), when performing the double-sided polishing, the corrosion depth of one side is controlled to be 3 to 5 microns.

3. The method for preparing a back contact solar cell according to claim 1, characterized in that: The phosphorus diffusion in step (2) is carried out in a tube furnace.

4. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (2), the phosphorus diffusion is performed at 830-870°C.

5. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (2), the doping depth of the n-type heavily doped region is controlled to be 0.5 to 1 micron.

6. The method for preparing a back contact solar cell according to claim 1, characterized in that: Step (2) also includes the step of cleaning and removing the phosphosilicate glass formed on the surface of the crystalline silicon substrate after the phosphorus diffusion is completed.

7. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (3), the thickness of the silicon oxide film is 1 to 2.5 nanometers, the thickness of the phosphorus-doped polysilicon layer is 120 to 150 nanometers, and the thickness of the mask layer is 50 to 60 nanometers; the mask layer is a silicon nitride mask layer; or, In step (4), the first opening area is a straight line segment, the number of the first opening areas is 40 to 70, and the width of each first opening area is 0.5 to 1.5 mm; or, In step (7), the thickness of the intrinsic amorphous silicon layer is 4 to 6 nanometers, the thickness of the silicon nitride anti-reflection layer is 60 to 80 nanometers, and the thickness of the boron hydride-doped microcrystalline silicon layer is 15 to 25 nm; or, In step (8), the second opening region is located on the outer surface of the phosphorus-doped polysilicon layer, and the width of the second opening region is smaller than the width of the phosphorus-doped polysilicon layer; or, In step (9), the material of the transparent conductive film is indium oxide; or, In step (9), the thickness of the transparent conductive film is 100 to 110 nm.

8. The method for preparing a back contact solar cell according to claim 1, characterized in that: In step (3), the silicon oxide film, the phosphorus-doped polysilicon layer and the mask layer are deposited by PECVD or LPCVD and then annealed, and the annealing temperature is controlled to be 800-900° C. and the annealing time is 20-50 minutes; or, In step (4) and step (8), the etching is performed by using a laser; or, In step (5), an alkaline solution is used to perform the cleaning and texturing to form a pyramid texture surface on the front side of the crystalline silicon substrate; or, In step (6), HF solution is used for cleaning; or, In step (7), the deposition is performed using a CVD process; or, In step (9), the deposition is performed by PVD, and a portion of the transparent conductive film is removed by laser etching; or, In step (10), the metal electrode is prepared by screen printing or electroplating.

9. The method for preparing a back contact solar cell according to claim 1, characterized in that: There are multiple metal electrodes, one metal electrode is set on the transparent conductive film at the corresponding position of each first opening area, one metal electrode is set on the transparent conductive film at the corresponding position of each second opening area, and one third opening area is set between two adjacent metal electrodes.

10. A back-contact solar cell prepared by the preparation method according to any one of claims 1 to 9.

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