Monolithic three-dimensional integrated transistor and manufacturing method thereof

Abstract

The invention discloses a monolithic three-dimensional integrated transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to integrate a top-layer device compatible with a back end of line (BEOL) under a low thermal budget and realize logic interconnection between layers of the monolithic three-dimensional integrated transistor. The monolithic three-dimensional integrated transistor comprises a substrate, a first transistor and a second transistor, the first transistor is formed on the substrate; the first transistor is a thin film transistor, and an active region of the first transistor is made of indium gallium zinc oxide; and a second transistor formed on the first transistor. The second transistor is an organic thin film transistor; and the second transistor and the first transistor form a three-dimensional laminated complementary transistor. The manufacturing method of the monolithic three-dimensional integrated transistor comprises the following steps: providing a substrate; forming a first transistor on the substrate; the first transistor is a thin film transistor; forming a second transistor on the first transistor; and the second transistor and the first transistor form a three-dimensional laminated complementary transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a monolithic three-dimensional integrated transistor and a manufacturing method thereof. Background Art

[0002] Since the 1960s, the number of devices in a microelectronic chip has doubled every two years, which is known as Moore's Law. Transistors have shrunk so that more transistors can fit on a piece of silicon. However, the continuous scaling of CMOS technology has led to a state below 5 nanometers, where Moore's Law is limited by the inherent physical properties of silicon, where severe second-order effects such as short channel effects and drain-induced barrier lowering (DIBL) are inevitable. Further reduction of transistor size following Moore's Law has encountered a bottleneck. In this case, in addition to the traditional method of reducing the channel size of transistors, three-dimensional integration, which means stacking components in the vertical direction, is a potential solution to further extend Moore's Law. In general, three-dimensional integration can be achieved at the package, wafer, and device levels of monolithic three-dimensional integration (M3D). Monolithic three-dimensional integration is the most practical way to achieve the highest device performance with the lowest cost. Instead of combining two fabricated chips together through bumps or through-silicon vias (TSVs), monolithic three-dimensional integration stacks two or more layers of transistors on top of each other in sequence to improve alignment accuracy, thereby reducing chip area and improving chip functionality.

[0003] However, current monolithic 3D integration still has many problems. On the one hand, the top-level devices compatible with the back-end of the line (BEOL) must be integrated under a low thermal budget; on the other hand, monolithic 3D integrated transistors are simply stacked and cannot achieve logical interconnection between layers. Summary of the invention

[0004] In a first aspect, the present invention aims to provide a monolithic three-dimensional integrated transistor and a method for manufacturing the same, which is used to integrate a back-end-of-line (BEOL) compatible top-level device under a low thermal budget and to achieve logical interconnection between layers of the monolithic three-dimensional integrated transistor.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a monolithic three-dimensional integrated transistor, which comprises: a substrate, a first transistor and a second transistor. The first transistor is formed on the substrate. The first transistor is a thin film transistor, and the active region material of the first transistor is indium gallium zinc oxide. And a second transistor is formed on the first transistor. The second transistor is an organic thin film transistor. The second transistor and the first transistor constitute a three-dimensional stacked complementary transistor.

[0006] In the case of adopting the above technical solution, in the monolithic three-dimensional integrated transistor provided by the present invention, the first transistor is formed on the substrate, and the second transistor is formed on the first transistor. The second transistor and the first transistor constitute a three-dimensional stacked complementary transistor. And the first transistor is a thin film transistor, and the active region material of the first transistor is indium gallium zinc oxide. The second transistor is an organic thin film transistor, and the organic thin film transistor is compatible with the back-end process. The manufacturing process temperature of the organic thin film transistor is relatively low. When preparing the second transistor on the first transistor, compared with the second transistor in the prior art that needs to be made by a high-temperature process, the monolithic three-dimensional integrated transistor provided by the present invention has a lower thermal budget for the first transistor, and is not prone to problems such as degradation of the back-end process and crystallization and deformation of the channel material of the first transistor. In addition, the first transistor is an indium gallium zinc oxide thin film transistor, which has a higher field effect mobility, a higher current switching ratio and a lower off-state leakage current than traditional silicon-based transistors, and has better performance. In addition, the second transistor and the first transistor constitute a three-dimensional stacked complementary transistor, forming a functional device with circuit logic, realizing logical interconnection between layers, and not a simple stack.

[0007] As a possible implementation, a source-drain electrode included in the first transistor is electrically connected to a source-drain electrode included in the second transistor. A gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor. The first transistor and the second transistor share a gate electrode.

[0008] When the above technical solution is adopted, the second transistor and the first transistor constitute a three-dimensional stacked complementary transistor, and the second transistor and the first transistor are connected in series to form an inverter, which has a logic function and realizes the logical interconnection between layers. In addition, the first transistor and the second transistor share a gate electrode, which reduces the volume occupied by the gate electrode and the through holes used to electrically connect the gate electrodes of the first transistor and the second transistor compared to the solution in which the first transistor and the second transistor do not share a gate electrode, which is conducive to improving the transistor density.

[0009] As a possible implementation, the monolithic three-dimensional integrated transistor provided by the present invention further includes: an electrode plug. The first transistor includes: a first electrode, a second electrode, a first active region, a first gate dielectric layer, and a gate electrode. The second transistor includes: a gate electrode, a second gate dielectric layer, a third electrode, a fourth electrode, a second active region, and a patterned layer.

[0010] As a possible implementation, the first electrode and the second electrode are formed on the substrate at intervals along a direction parallel to the substrate. The first active region is at least formed on the substrate, and the active region is partially formed between the first electrode and the second electrode. The first gate dielectric layer is formed on the first electrode, the second electrode and the active region. The gate electrode is formed on the first gate dielectric layer, and the orthographic projection of the gate electrode on the substrate overlaps with the orthographic projection of the first active region on the substrate. The electrode plug penetrates the first gate dielectric layer, and the electrode plug is connected to the second electrode.

[0011] As a possible implementation scheme, the second gate dielectric layer is formed on the gate electrode and the first gate dielectric layer. The electrode plug is connected to the fourth electrode, and the electrode plug passes through the second gate dielectric layer. The third electrode and the fourth electrode are formed on the second gate dielectric layer. The orthographic projection of the third electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate. The second active area is at least formed on the second gate dielectric layer, and the orthographic projection of the second active area on the substrate overlaps with the orthographic projection of the gate electrode on the substrate. The patterned layer is formed on the second active area. The material of the patterned layer includes Cytop.

[0012] In the case of adopting the above technical solution, the electrode plug is connected to the second electrode, which is in turn connected to the fourth electrode, and the electrode plug connects the first transistor and the second transistor in series, while the first transistor and the second transistor share a gate electrode. When the monolithic three-dimensional integrated transistor provided by the present invention is applied, the gate electrode is used as the input terminal, the electrode plug and the second electrode and the fourth electrode connected to the electrode plug are used as the output terminals, and the first electrode and the third electrode are respectively connected to the ground or the power supply, so that the monolithic three-dimensional integrated transistor provided by the present invention can form an inverter structure to realize effective logic functions, rather than a simple stack.

[0013] In a second aspect, the present invention further provides a method for manufacturing a monolithic three-dimensional integrated transistor, the method comprising: providing a substrate. Forming a first transistor on the substrate; the first transistor is a thin film transistor, and the active region material of the first transistor is indium gallium zinc oxide. Forming a second transistor on the first transistor. The second transistor is an organic thin film transistor; the second transistor and the first transistor constitute a three-dimensional stacked complementary transistor.

[0014] Compared with the prior art, the beneficial effects of the method for manufacturing a monolithic three-dimensional integrated transistor provided by the present invention are the same as the beneficial effects of the monolithic three-dimensional integrated transistor of the above technical solution, which will not be elaborated here.

[0015] As a possible implementation, forming a first transistor on a substrate includes: forming a first electrode and a second electrode on a substrate; forming a first active region on a substrate, and forming a first gate dielectric layer on the first active region, the first electrode, and the second electrode; the first active region is partially located between the first electrode and the second electrode. Forming a gate electrode on the first gate dielectric layer. The orthographic projection of the gate electrode on the substrate overlaps with the orthographic projection of the first active region on the substrate; the second transistor and the first transistor share a gate electrode. Forming a second transistor on the first transistor includes: forming a second gate dielectric layer on the gate electrode and the first gate dielectric layer; forming a through hole penetrating the first gate dielectric layer and the second gate dielectric layer, the orthographic projection of the through hole on the substrate does not exceed the orthographic projection of the second electrode on the substrate; forming a third electrode and a fourth electrode on the second gate dielectric layer; the orthographic projection of the third electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate; forming a second active region on the second gate dielectric layer, and forming a patterned layer on the second active region; the orthographic projection of the second active region on the substrate overlaps with the orthographic projection of the gate electrode on the substrate.

[0016] When the above technical solution is adopted, the first transistor and the second transistor are formed layer by layer, including the first active area, the first electrode, the second electrode, the first active area, the first gate dielectric layer, the gate electrode, the second gate dielectric layer, the third electrode, the fourth electrode, the second active area, the patterned layer and the through hole penetrating the first gate dielectric layer and the second gate dielectric layer. The manufacturing method of the monolithic three-dimensional integrated transistor provided by the present invention is highly compatible with the existing process.

[0017] As a possible implementation scheme, the method for manufacturing a monolithic three-dimensional integrated transistor provided by the present invention further includes: forming an electrode plug in the through hole; and electrically connecting the fourth electrode and the second electrode via the electrode plug.

[0018] When the above technical solution is adopted, the second electrode serves as a source-drain electrode of the first transistor, the fourth electrode serves as a source-drain electrode of the second transistor, the fourth electrode and the second electrode are electrically connected through an electrode plug, and the first transistor and the second transistor share a gate electrode, and the first transistor and the second transistor are connected in series. Compared with the prior art, the beneficial effect of connecting the first transistor and the second transistor in series in the manufacturing method of the monolithic three-dimensional integrated transistor provided by the present invention is the same as the beneficial effect of connecting the first transistor and the second transistor in series in the monolithic three-dimensional integrated transistor of the above technical solution, which will not be repeated here.

[0019] As a possible implementation scheme, a second active area is formed on the second gate dielectric layer, and forming a patterned layer on the second active area includes: forming the second active area on the second gate dielectric layer by solution processing and / or epitaxial methods; forming a patterned layer on the second gate dielectric layer by solution processing and / or epitaxial methods; and patterning the second active area and the patterned layer.

[0020] In the case of adopting the above technical solution, the second active area and the patterned layer are formed by a low-temperature solution processing method and / or an epitaxial process, which has a low thermal budget and has little effect on the structure of the first transistor, and can ensure the function and performance of the monolithic three-dimensional integrated transistor manufactured by the manufacturing method of the monolithic three-dimensional integrated transistor provided by the present invention. And after forming the patterned layer on the second active area, the second active area and the patterned layer are patterned together, which can reduce the process steps of patterning the second active area and the patterned layer separately, and the patterned layer can also protect the second active area, preventing the subsequent manufacturing process from affecting the structure and properties of the second active area.

[0021] As a possible implementation scheme, a first active region is formed on a substrate, and a first gate dielectric layer is formed on the first active region, a first electrode, and a second electrode, including: growing the first active region on the substrate; the first gate dielectric layer includes a first gate dielectric sublayer and a second gate dielectric sublayer; depositing the first gate dielectric sublayer on the first active region, the first electrode, and the second electrode; and patterning the first active region and the first gate dielectric sublayer.

[0022] When the above technical solution is adopted, the first active area and the first gate dielectric sublayer are patterned at the same time, which can reduce the process steps of patterning the first active area and the first gate dielectric layer separately, thereby improving the yield and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 A schematic diagram of a monolithic three-dimensional integrated transistor provided by an embodiment of the present invention;

[0025] Figure 2 is a flow chart of an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a substrate is provided in an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of depositing a first metal layer in an embodiment of the present invention;

[0028] Figure 5is a schematic diagram of forming a first electrode and a second electrode in an embodiment of the present invention;

[0029] Figure 6 is a schematic diagram of forming a first active region in an embodiment of the present invention;

[0030] Figure 7 is a schematic diagram of growing a first dielectric sub-layer in an embodiment of the present invention;

[0031] Figure 8 is a schematic diagram of patterning the first gate dielectric sublayer and the first active region in an embodiment of the present invention;

[0032] Fig. 9 is a schematic diagram of forming a second dielectric sub-layer in an embodiment of the present invention;

[0033] Fig.10 is a schematic diagram of forming a gate electrode in an embodiment of the present invention;

[0034] Fig.11 is a schematic diagram of forming a second gate dielectric layer in an embodiment of the present invention;

[0035] Fig.12 is a schematic diagram of forming a through hole in an embodiment of the present invention;

[0036] Fig.13 is a schematic diagram of forming a third electrode and a fourth electrode in an embodiment of the present invention;

[0037] Fig.14 is a schematic diagram of forming a second active region in an embodiment of the present invention;

[0038] Fig.15 is a schematic diagram of forming a patterned layer in an embodiment of the present invention;

[0039] Fig.16 is a schematic diagram of simultaneously patterning the patterned layer and the second active area in an embodiment of the present invention;

[0040] Fig.17 A transfer curve of a first transistor manufactured by the method for manufacturing a monolithic three-dimensional integrated transistor provided by an embodiment of the present invention;

[0041] Fig.18 A transfer curve of a second transistor manufactured by the method for manufacturing a monolithic three-dimensional integrated transistor provided by an embodiment of the present invention;

[0042] Fig.19 A curve showing the relationship between the output voltage, gain and input voltage of an inverter composed of a monolithic three-dimensional integrated transistor provided in an embodiment of the present invention.

[0043] Reference numerals:

[0044] 100-substrate, 200-first electrode layer,

[0045] 201 - first electrode, 202 - second electrode,

[0046] 210 - first active region, 220 - first gate dielectric layer,

[0047] 221 - a first gate dielectric sublayer, 222 - a second gate dielectric sublayer,

[0048] 240 - first transistor, 301 - gate electrode,

[0049] 311-through hole, 312-electrode plug,

[0050] 401 - third electrode, 402 - fourth electrode,

[0051] 410 - second gate dielectric layer, 421 - second active region,

[0052] 422-patterning layer, 430-encapsulation layer,

[0053] 440 - second transistor. DETAILED DESCRIPTION

[0054] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0055] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0057] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0058] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0059] The rapid development of the microelectronics industry has put forward higher requirements on the speed of increasing the density of transistors in integrated circuits, that is, a smaller transistor size is required, but the reduction of the transistor size of two-dimensional integrated circuits is subject to more process restrictions. Monolithic three-dimensional integration (M3D) can improve chip integration, optimize system energy efficiency and achieve functional diversity by stacking multiple layers of computing, storage or sensing circuits in three dimensions without increasing the difficulty of device processing.

[0060] However, the industrial development of monolithic three-dimensional integrated devices still faces many challenges. Limited thermal budget is one of the important problems faced by monolithic three-dimensional integrated devices. In the prior art, monolithic three-dimensional integrated devices manufacture multiple stacked layers on the same wafer in sequence by depositing / recrystallizing the upper semiconductor. However, the channel obtained by the upper layer deposition requires high-temperature annealing of more than 500°C, which will cause the degradation of the back-end process of the lower device, the degradation of the silicide and the diffusion of the dopant, resulting in reduced yield and performance of the monolithic three-dimensional integrated device.

[0061] To solve the above problems, first of all, please refer to Figure 1 , integrating the top-layer devices compatible with the back-end of the line (BEOL) under a low thermal budget, and realizing logical interconnection between the layers of the monolithic three-dimensional integrated transistor. The monolithic three-dimensional integrated transistor includes: a substrate 100, a first transistor 240, and a second transistor 440. The first transistor 240 is formed on the substrate 100. The first transistor 240 is a thin film transistor, and the active region material of the first transistor 240 is indium gallium zinc oxide. And the second transistor 440 is formed on the first transistor 240. The second transistor 440 is an organic thin film transistor. The second transistor 440 and the first transistor 240 constitute a three-dimensional stacked complementary transistor.

[0062] When using the above technical solution, please refer to Figure 1 In the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention, the first transistor 240 is formed on the substrate 100, and the second transistor 440 is formed on the first transistor 240. The second transistor 440 and the first transistor 240 constitute a three-dimensional stacked complementary transistor. In addition, the first transistor 240 is a thin film transistor, the active region material of the first transistor 240 is indium gallium zinc oxide, and the second transistor 440 is an organic thin film transistor. The organic thin film transistor is compatible with the back-end process, and the manufacturing process temperature of the organic thin film transistor is relatively low, and the process temperature is lower than 200°C. When the second transistor 440 is prepared on the first transistor 240, compared with the high-temperature process required for the second transistor 440 in the prior art, the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention generates a lower thermal budget for the first transistor 240, and is not prone to problems such as degradation of the back-end process and crystallization and deformation of the channel material of the first transistor 240. In addition, the first transistor 240 is an indium gallium zinc oxide thin film transistor, which has a higher field effect mobility, a higher current switching ratio and a lower off-state leakage current than traditional silicon-based transistors, and has better performance. In addition, the second transistor 440 and the first transistor 240 constitute a three-dimensional stacked complementary transistor, forming a functional device with circuit logic and realizing logical interconnection between layers, rather than simple stacking.

[0063] As a possible implementation, please refer to Figure 1 A source-drain electrode of the first transistor 240 is electrically connected to a source-drain electrode of the second transistor 440. A gate electrode 301 of the first transistor 240 is electrically connected to a gate electrode 301 of the second transistor 440. The first transistor 240 and the second transistor 440 share the gate electrode 301.

[0064] In the case of adopting the above technical solution, the second transistor 440 and the first transistor 240 constitute a three-dimensional stacked complementary transistor, and the second transistor 440 and the first transistor 240 are connected in series to form an inverter, which has a logic function and realizes the logical interconnection between layers. In addition, the first transistor 240 and the second transistor 440 share the gate electrode 301, which reduces the volume occupied by the gate electrode 301 and the through hole 311 used to electrically connect the gate electrodes 301 of the first transistor 240 and the second transistor 440, compared with the solution in which the first transistor 240 and the second transistor 440 do not share the gate electrode 301, which is conducive to improving the transistor density.

[0065] As a possible implementation, please refer to Figure 1The monolithic three-dimensional integrated transistor provided in the embodiment of the present invention further includes: an electrode plug 312. The first transistor 240 includes: a first electrode 201, a second electrode 202, a first active region 210, a first gate dielectric layer 220, and a gate electrode 301. The second transistor 440 includes: a gate electrode 301, a second gate dielectric layer 410, a third electrode 401, a fourth electrode 402, a second active region 421, and a patterned layer 422.

[0066] The first electrode 201 and the second electrode 202 are formed on the substrate 100 at intervals along a direction parallel to the substrate 100. The first active region 210 is at least formed on the substrate 100, and the active region is partially formed between the first electrode 201 and the second electrode 202. The first gate dielectric layer 220 is formed on the first electrode 201, the second electrode 202 and the active region. The gate electrode 301 is formed on the first gate dielectric layer 220, and the orthographic projection of the gate electrode 301 on the substrate 100 overlaps with the orthographic projection of the first active region 210 on the substrate 100. The electrode plug 312 penetrates the first gate dielectric layer 220, and the electrode plug 312 is connected to the second electrode 202. The second gate dielectric layer 410 is formed on the gate electrode 301 and the first gate dielectric layer 220. The electrode plug 312 is connected to the fourth electrode 402, and the electrode plug 312 penetrates the second gate dielectric layer 410. The third electrode 401 and the fourth electrode 402 are formed on the second gate dielectric layer 410. The orthographic projection of the third electrode 401 on the substrate 100 overlaps with the orthographic projection of the first electrode 201 on the substrate 100, and the orthographic projection of the fourth electrode 402 on the substrate 100 overlaps with the orthographic projection of the second electrode 202 on the substrate 100. The second active area 421 is at least formed on the second gate dielectric layer 410, and the orthographic projection of the second active area 421 on the substrate 100 overlaps with the orthographic projection of the gate electrode 301 on the substrate 100. The patterned layer 422 is formed on the second active area 421. The material of the patterned layer 422 includes Cytop.

[0067] When using the above technical solution, please refer to Figure 1 , the electrode plug 312 is connected to the second electrode 202, and the electrode plug 312 is connected to the fourth electrode 402. The electrode plug 312 connects the first transistor 240 and the second transistor 440 in series, and the first transistor 240 and the second transistor 440 share the gate electrode 301. When the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention is applied, the gate electrode 301 is used as the input terminal, the electrode plug 312 and the second electrode 202 and the fourth electrode 402 connected to the electrode plug 312 are used as the output terminals, and the first electrode 201 and the third electrode 401 are respectively grounded or connected to a power supply, so that the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention can form an inverter structure and realize an effective logic function.

[0068] Regarding the substrate 100 included in the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention, its material can be an insulating material with high strength including silicon oxide, glass, etc. to reduce the leakage of the first transistor 240 to the substrate 100, thereby improving the performance of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention, and can also use organic insulating materials such as PI to achieve better shock resistance or realize flexible transistors; its material can also use semiconductor substrates including silicon and silicon on insulator to improve the compatibility of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention with existing manufacturing processes.

[0069] As for the thickness of the substrate 100, the embodiment of the present invention does not specifically limit it, as long as it can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention when the substrate 100 adopts a specific material. Optionally, the thickness of the substrate 100 is greater than or equal to 0.1 mm and less than or equal to 5 mm. Specifically, the thickness of the substrate 100 can be 0.1 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm.

[0070] As for the first electrode 201 and the second electrode 202 formed on the substrate 100 in a direction parallel to the substrate 100 and spaced apart from each other, they serve as the source electrode or the drain electrode of the first transistor 240 .

[0071] As for the materials of the first electrode 201 and the second electrode 202, the embodiment of the present invention does not specifically limit them, as long as they can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention. Exemplarily, the materials of the first electrode 201 and the second electrode 202 include one or a combination of titanium nitride, gold, titanium, molybdenum, and nickel.

[0072] It should be noted that the material of the first electrode 201 and the material of the second electrode 202 can be the same material, so that the first electrode 201 and the second electrode 202 can be manufactured at the same time when manufacturing the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention; the material of the first electrode 201 and the material of the second electrode 202 can also be different materials to achieve better performance.

[0073] As for the thickness of the first electrode 201 and the second electrode 202 , the embodiment of the present invention does not impose any specific limitation thereon, as long as they can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0074] It should be noted that the thickness of the first electrode 201 and the thickness of the second electrode 202 can be the same, so that the first electrode 201 and the second electrode 202 can be manufactured at the same time when manufacturing the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention; the thickness of the first electrode 201 and the thickness of the second electrode 202 can also be different to achieve more design possibilities.

[0075] As for the position of the first active area 210, it can be formed only on the substrate 100 between the first electrode 201 and the second electrode 202, or it can be appropriately extended to the first electrode 201 and the second electrode 202 to obtain a larger contact area between the active area and the first electrode 201 and the second electrode 202, which is beneficial to reduce the contact resistance between the active area and the first electrode 201 and the second electrode 202 respectively, improve the speed of the first transistor 240, improve the leakage current, and thus improve the performance of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention.

[0076] Please refer to Figure 1 When the first active region 210 properly extends onto the first electrode 201 and the second electrode 202, the portion of the first active region 210 located on the first electrode 201 and the second electrode 202 is defined as the first active sub-region, and the portion of the first active region 210 extending onto the first electrode 201 and the second electrode 202 is defined as the second active sub-region. The region of the first active sub-region not in contact with the first electrode 201 and the second electrode 202 serves as the channel region of the first transistor 240, and the region of the first active sub-region in contact with the first electrode 201 and the region of the second active sub-region located on the first electrode 201, as well as the region of the first active sub-region in contact with the second electrode 202 and the region of the second active sub-region located on the second electrode 202 serve as the source region and the drain region of the first transistor 240, respectively.

[0077] As for the material of the first active region 210 , it is indium gallium zinc oxide (IGZO).

[0078] In the case of adopting the above technical solution, the material of the first active area 210 is indium gallium zinc oxide, which can make the first transistor 240 have a higher field effect mobility, a higher current switching ratio and a lower off-state leakage current compared to traditional silicon-based transistors, and have better performance and lower off-state leakage current. In addition, the material of the first active area 210 is indium gallium zinc oxide, which can make the first active area 210 manufactured at a lower temperature and have better process compatibility with the substrate 100 made of organic insulating materials such as PI. In addition, the material of the first active area 210 is indium gallium zinc oxide, which makes the first transistor 240 an N-type transistor, so that the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention can realize circuit logic.

[0079] As for the length of the first active region 210 , the embodiment of the present invention does not impose any specific limitation thereon, as long as the performance of the first transistor 240 is not affected.

[0080] Exemplarily, the length of the first active sub-region is greater than or equal to 2 μm and less than or equal to 200 μm. Specifically, the length of the first active sub-region may be 2 μm, 40 μm, 80 μm, 120 μm, 160 μm or 200 μm.

[0081] When the above technical solution is adopted, when the length of the portion of the first active region 210 located between the first electrode 201 and the second electrode 202 is within this range, it is possible to avoid the occurrence of a short channel effect due to the length of the first active sub-region being too short, which causes the performance of the first transistor 240 to be reduced, and it is also possible to avoid the increase in resistance of the first active sub-region due to the length of the first active sub-region being too long, which causes the performance of the first transistor 240 to be reduced, thereby ensuring the performance of the monolithic three-dimensional integrated device provided by the embodiment of the present invention.

[0082] As for the thickness of the first active region 210, it needs to meet various performance requirements for the first transistor 240 including the on-off current ratio and the effective mobility. Exemplarily, the thickness of the first active region 210 is greater than or equal to 5nm and less than or equal to 7nm. Specifically, the thickness of the first active region 210 can be 5nm, 5.5nm, 6nm, 6.5nm or 7nm.

[0083] When the above technical solution is adopted, it can be avoided that the first active area 210 is too thin, resulting in the inability to form a uniform and continuous film layer when manufacturing the monolithic three-dimensional integrated device provided by the embodiment of the present invention, thereby ensuring the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention; it can also be avoided that the first active area 210 is too thick, resulting in the weakening of the induced charge of the field effect of the gate electrode 301, and avoiding the problem that the thicker the first active area 210 is, the more defects and oxygen vacancies there are in the film, thereby resulting in a smaller mobility of the first active area 210, thereby ensuring the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0084] The first gate dielectric layer 220 includes a first gate dielectric sublayer 221 and a second gate dielectric sublayer 222. The first gate dielectric sublayer 221 is formed on the first active region 210, and the second gate dielectric sublayer 222 is formed on the first electrode 201, the first gate dielectric sublayer 221 and the second electrode 202.

[0085] The embodiment of the present invention does not impose any specific limitation on the materials of the first gate dielectric sublayer 221 and the second gate dielectric sublayer 222 , which may be silicon oxide, silicon nitride, hafnium dioxide, or zirconium dioxide, as long as the performance requirements for the first gate dielectric layer 220 are met.

[0086] Exemplarily, the material of the first gate dielectric sub-layer 221 and the second gate dielectric sub-layer 222 is hafnium dioxide.

[0087] When the above technical solution is adopted, because the dielectric constant of hafnium dioxide is high, the leakage of the gate electrode 301 to the first active area 210 can be reduced, which is beneficial to improving the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention; at the same time, the material of the first gate dielectric sublayer 221 and the second gate dielectric sublayer 222 is hafnium dioxide, which can speed up the turn-on and turn-off speeds of the first transistor 240, reduce the power consumption of the first transistor 240, enhance the control ability of the gate electrode 301 over the first active area 210, reduce the threshold voltage of the first transistor 240, weaken the short channel effect of the first transistor 240, and help improve the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0088] It should be noted that the material of the first gate dielectric sublayer 221 and the material of the second gate dielectric sublayer 222 can be the same, so as to reduce the interface state density between the first gate dielectric sublayer 221 and the second gate dielectric sublayer 222, thereby reducing the gate capacitance and improving the speed of the first transistor 240; the material of the first gate dielectric sublayer 221 and the material of the second gate dielectric sublayer 222 can also be different, so as to increase the design dimension when applying the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0089] As for the thickness of the first gate dielectric sublayer 221, it needs to meet the performance requirements of the gate capacitance of the first transistor 240. Exemplarily, the thickness of the first gate dielectric sublayer 221 is greater than or equal to 2nm and less than or equal to 5nm. Specifically, the thickness of the first gate dielectric sublayer 221 can be 2nm, 3nm, 4nm or 5nm.

[0090] When the above technical solution is adopted, the thickness of the first gate dielectric sublayer 221 is within this range, which can avoid serious leakage of the gate electrode 301 to the first active area 210 due to too small thickness, thereby ensuring the performance of the first transistor 240; it can also avoid excessive gate capacitance due to excessive thickness, thereby affecting the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0091] As for the thickness of the second gate dielectric sublayer 222, it needs to meet the performance requirements of the gate capacitance of the first transistor 240. Optionally, the thickness of the second gate dielectric sublayer 222 is less than or equal to 15 nm.

[0092] When the above technical solution is adopted, the thickness of the second gate dielectric sublayer 222 is within this range, which can avoid serious leakage of the gate electrode 301 to the first active area 210 due to too small thickness, thereby ensuring the performance of the first transistor 240; it can also avoid excessive gate capacitance due to excessive thickness, thereby affecting the performance of the first transistor 240, thereby ensuring the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0093] For the gate electrode 301 , the material and thickness of the gate electrode 301 may be determined according to the resistivity requirement of the gate electrode 301 , and are not specifically limited here.

[0094] Exemplarily, the material of the gate electrode 301 is one or a combination of titanium nitride, gold, titanium, molybdenum, silver, and nickel.

[0095] Exemplarily, the thickness of the gate electrode 301 may be greater than or equal to 30 nm and less than or equal to 80 nm. Specifically, the thickness of the gate electrode 301 may be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm or 80 nm.

[0096] As for the second gate dielectric layer 410, in addition to being the gate dielectric layer of the second transistor 440, it can also be used as the encapsulation layer 430 of the first transistor 240 to isolate the first transistor 240 from the outside, effectively protect the first active area 210, and thus increase the working life of the first transistor 240. Therefore, the material and thickness of the second gate dielectric layer 410 must meet the above requirements.

[0097] Exemplarily, the material of the second gate dielectric layer 410 includes aluminum oxide and aluminum nitride.

[0098] Exemplarily, the thickness of the second gate dielectric layer 410 may be greater than or equal to 30 nm and less than or equal to 5 μm. Specifically, the thickness of the second gate dielectric layer 410 may be 30 nm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0099] The third electrode 401 and the fourth electrode 402 are formed on the second gate dielectric layer 410, and the orthographic projection of the third electrode 401 on the substrate 100 overlaps with the orthographic projection of the first electrode 201 on the substrate 100, and the orthographic projection of the fourth electrode 402 on the substrate 100 overlaps with the orthographic projection of the second electrode 202 on the substrate 100, that is, the orthographic projection of the area of ​​the second gate dielectric layer 410 not covered by the third electrode 401 and the fourth electrode 402 on the substrate 100 overlaps with the orthographic projection of the gate electrode 301 on the substrate 100, and serves as the channel region, source region and drain region of the second transistor 440 to be formed.

[0100] The embodiment of the present invention does not specifically limit the materials of the third electrode 401 and the fourth electrode 402, as long as they can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention. Exemplarily, the materials of the third electrode 401 and the fourth electrode 402 include one or a combination of titanium nitride, gold, titanium, molybdenum, and nickel.

[0101] It should be noted that the material of the third electrode 401 and the material of the fourth electrode 402 can be the same material, so that the third electrode 401 and the fourth electrode 402 can be manufactured at the same time when manufacturing the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention; the material of the third electrode 401 and the material of the fourth electrode 402 can also be different materials, which can increase the design dimension of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention.

[0102] As for the thickness of the third electrode 401 and the fourth electrode 402, the embodiment of the present invention does not specifically limit it, as long as it can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention. Exemplarily, the thickness of the first electrode 201 and the second electrode 202 is greater than or equal to 30nm and less than or equal to 80nm. Specifically, the thickness of the first electrode 201 and the second electrode 202 can be 30nm, 40nm, 50nm, 60nm, 70nm or 80nm.

[0103] As for the distance between the third electrode 401 and the fourth electrode 402, it is the channel length included in the second active region 421, which has a significant impact on the performance of the second transistor 440. If the distance between the third electrode 401 and the fourth electrode 402 is too large, the channel resistance will increase significantly, thereby reducing the performance of the second transistor 440; if the distance between the third electrode 401 and the fourth electrode 402 is too small, a short channel effect will occur, which will also reduce the performance of the second transistor 440.

[0104] Exemplarily, the distance between the third electrode 401 and the fourth electrode 402 is greater than or equal to 5 μm and less than or equal to 500 μm.

[0105] Specifically, the thickness of the first electrode 201 and the second electrode 202 can be 5 μm, 100 μm, 200 μm, 300 μm, 400 μm or 500 μm. When the distance between the third electrode 401 and the fourth electrode 402 is within this range, the channel resistance can be controlled and the short channel effect can be avoided, thereby ensuring the performance of the second transistor 440.

[0106] As for the second active area 421, its orthographic projection on the substrate 100 overlaps with the orthographic projection of the gate electrode 301 on the substrate 100, so that the gate electrode 301 can produce a field effect on the second active area 421. In addition, the second active area 421 can be only arranged on the second gate dielectric layer 410, and can also be further extended to the third electrode 401 and the fourth electrode 402, so that the second active area 421 has a larger contact area with the third electrode 401 and the fourth electrode 402, thereby improving the speed of the second transistor 440 and improving the leakage current, thereby improving the performance of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0107] As for the material of the second active area 421, it is an organic material, so that when manufacturing the monolithic three-dimensional integrated transistor provided in an embodiment of the present invention, a lower temperature process is used to manufacture the second active area 421, thereby reducing the thermal budget generated on the first transistor 240 and significantly reducing the structural impact on the first transistor 240, thereby ensuring the performance of the first transistor 240.

[0108] Regarding the type of organic material selected for the second active region 421, optionally, the material of the second active region 421 includes conjugated small molecules such as pentacene, 2,7-dioctyl[1]benzothiophene[3,2-b][1]benzothiophene (C8-BTBT, CAS No. 583050-70-8), and conjugated polymers such as PffBT4T-2DT (chemical formula (C70H104N2S5F2)n, CAS No. (C70H104N2S5F2)n), poly-3-hexylthiophene (P3HT, CAS No. 104934-50-1), and other optional organic semiconductor materials.

[0109] When the above technical solution is adopted, the conductivity type of the second active region 421 is P-type, so that the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention can realize circuit logic.

[0110] As for the electrode plug 312, the embodiment of the present invention does not limit its position, as long as the electrode plug 312 can penetrate the first gate dielectric layer 220 and the second gate dielectric layer 410, and electrically connect the second electrode 202 and the fourth electrode 402. Optionally, the orthographic projection of the electrode plug 312 on the substrate 100 overlaps with the orthographic projection of the second electrode 202 on the substrate 100, that is, the orthographic projection of the electrode plug 312 on the substrate 100 overlaps with the orthographic projection of the fourth electrode 402 on the substrate 100, that is, along the thickness direction of the substrate 100, the electrode plug 312 is formed between the second electrode 202 and the fourth electrode 402.

[0111] As for the material of the electrode plug 312, the embodiment of the present invention does not specifically limit it, as long as it can meet the performance requirements of the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention. Exemplarily, the material of the third electrode 401 and the fourth electrode 402 includes one or a combination of titanium nitride, gold, titanium, molybdenum, and nickel.

[0112] In addition, the material of the electrode plug 312 can be the same as that of the fourth electrode 402, so as to facilitate the simultaneous formation of the electrode plug 312 and the fourth electrode 402, thereby reducing the process steps and improving the yield; the material of the electrode plug 312 can also be different from that of the fourth electrode 402, so as to increase the design dimension of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention.

[0113] As for the patterned layer 422 formed on the second active area 421, it at least completely covers the surface of the second active area 421 away from the third electrode 401, the second gate dielectric layer 410 and the fourth electrode 402, so as to serve as a protective layer for the second active area 421 when manufacturing the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention. In addition, the material of the patterned layer 422 is Cytop (perfluoro (1-butenyl vinyl ether) polymer), and the process temperature of Cytop is relatively low, and the thermal budget generated by preparing the patterned layer is relatively low, which greatly reduces the structural impact on the first transistor 240, thereby ensuring the performance of the first transistor 240.

[0114] In addition, the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention further includes an encapsulation layer 430, and the encapsulation layer 430 is formed on the third electrode 401, the patterned layer 422, and the fourth electrode 402. The encapsulation layer 430 is used to isolate the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention from the outside world, to prevent the outside world from affecting the monolithic three-dimensional integrated transistor, to improve the working stability, and thus to extend the working life of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention.

[0115] The material of the encapsulation layer 430 includes epoxy resin or Parylene (poly-para-xylene).

[0116] When the above technical solution is adopted, since epoxy resin or parylene has good resistance to abnormal environments and sealing properties, the encapsulation layer 430 can effectively protect the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention; and epoxy resin or parylene can be made at a lower temperature, and the thermal budget generated when manufacturing the encapsulation layer 430 is lower, which greatly reduces the structural impact on the first transistor 240, thereby ensuring the performance of the first transistor 240.

[0117] Optionally, the material of the encapsulation layer 430 is parylene, because parylene is easier to make into a film with uniform thickness, dense, pinhole-free, stress-free and meniscus-free, so that the encapsulation layer 430 can more effectively protect the monolithic three-dimensional integrated transistor provided by the embodiment of the present invention.

[0118] Compared with the prior art, the second active layer, patterned layer 422 and packaging layer 430 included in the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention can all be manufactured at a lower temperature. The thermal budget generated when manufacturing the packaging layer 430 is lower, which greatly reduces the structural impact on the first transistor 240, thereby ensuring the performance of the first transistor 240.

[0119] In addition, the first transistor 240 and the second transistor 440 are connected in series through a common gate electrode 301 and an electrode plug 312 connecting the second electrode 202 and the fourth electrode 402. The first transistor 240 is an N-type transistor, and the second transistor 440 is a P-type transistor. The gate electrode 301 is used as the input end, the second electrode 202 or the fourth electrode 402 is used as the output end, and the first electrode 201 and the third electrode 401 are grounded and connected to a power supply respectively, so as to form an inverter, so that the first transistor included in the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention has an effective logic function, and is not a simple stack.

[0120] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a monolithic three-dimensional integrated transistor, the method for manufacturing a monolithic three-dimensional integrated transistor comprising: providing a substrate 100. Forming a first transistor 240 on the substrate 100; the first transistor 240 is a thin film transistor, and the active region material of the first transistor 240 is indium gallium zinc oxide. Forming a second transistor 440 on the first transistor 240. The second transistor 440 is an organic thin film transistor; the second transistor 440 and the first transistor 240 constitute a three-dimensional stacked complementary transistor.

[0121] Compared with the prior art, the beneficial effects of the method for manufacturing a monolithic three-dimensional integrated transistor provided by the embodiment of the present invention are the same as the beneficial effects of the monolithic three-dimensional integrated transistor of the above technical solution, which will not be elaborated here.

[0122] As a possible implementation, please refer to Figure 2, forming the first transistor 240 on the substrate 100 includes: forming a first electrode 201 and a second electrode 202 on the substrate 100; forming a first active region 210 on the substrate 100, and forming a first gate dielectric layer 220 on the first active region 210, the first electrode 201 and the second electrode 202; the first active region 210 is partially located between the first electrode 201 and the second electrode 202. Forming a gate electrode 301 on the first gate dielectric layer 220. The orthographic projection of the gate electrode 301 on the substrate 100 overlaps with the orthographic projection of the first active region 210 on the substrate 100; the second transistor 440 and the first transistor 240 share the gate electrode 301. Forming the second transistor 440 on the first transistor 240 includes: forming a second gate dielectric layer 410 on the gate electrode 301 and the first gate dielectric layer 220; forming a through hole 311 penetrating the first gate dielectric layer 220 and the second gate dielectric layer 410, wherein the orthographic projection of the through hole 311 on the substrate 100 does not exceed the orthographic projection of the second electrode 202 on the substrate 100; forming a third electrode 401 and a fourth electrode 402 on the second gate dielectric layer 410; the orthographic projection of the third electrode 401 on the substrate 100 overlaps with the orthographic projection of the first electrode 201 on the substrate 100, and the orthographic projection of the fourth electrode 402 on the substrate 100 overlaps with the orthographic projection of the second electrode 202 on the substrate 100; forming a second active area 421 on the second gate dielectric layer 410, and forming a patterned layer 422 on the second active area 421; the orthographic projection of the second active area 421 on the substrate 100 overlaps with the orthographic projection of the gate electrode 301 on the substrate 100.

[0123] When the above technical solution is adopted, the first transistor 240 and the second transistor 440 are formed layer by layer, including the first active area 210, the first electrode 201, the second electrode 202, the first active area 210, the first gate dielectric layer 220, the gate electrode 301, the second gate dielectric layer 410, the third electrode 401, the fourth electrode 402, the second active area 421, the patterned layer 422 and the through hole 311 passing through the first gate dielectric layer 220 and the second gate dielectric layer 410. The manufacturing method of the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention is highly compatible with the existing process.

[0124] The following will be based on Figures 1 to 17 The schematic diagram of the operation shown in the figure describes the process of manufacturing a monolithic three-dimensional integrated transistor. The parameters such as materials and geometric dimensions of each structure manufactured by the method for manufacturing a monolithic three-dimensional integrated transistor provided in the embodiment of the present invention can refer to the relevant description of the first aspect. Exemplarily, the method for manufacturing a monolithic three-dimensional integrated transistor includes the following steps:

[0125] First, please refer to Figure 3 , providing a substrate 100. Regarding the material, thickness and beneficial effects of the substrate 100, please refer to the related description of the first aspect, which will not be repeated here.

[0126] Next, please refer to Figure 5 , forming a first electrode 201 and a second electrode 202 on the substrate 100. The embodiment of the present invention does not specifically limit the process of forming the first electrode 201 and the second electrode 202, as long as the performance of the formed first electrode 201 and the second electrode 202 can meet the requirements of the first aspect for the first electrode 201 and the second electrode 202.

[0127] For example, please refer to Figure 4 The first metal layer is deposited on the substrate 100 by physical vapor deposition including resistance evaporation process and electron beam evaporation process. Optionally, the first metal layer is deposited on the substrate 100 by electron beam evaporation process, because the evaporation rate of the electron beam evaporation process is faster and the electron beam is accurately positioned, which can avoid evaporation and contamination of the material of the crucible containing the raw material of the first metal layer.

[0128] For example, please refer to Figure 5 The first metal layer is patterned by photolithography and lift-off process to form the first electrode 201 and the second electrode 202. Optionally, the photoresist used in the photolithography is negative photoresist 1500 and positive photoresist 5141, and the photolithography exposure method is contact / proximity photolithography.

[0129] For the materials of the first electrode 201 and the second electrode 202, please refer to the related description of the first aspect, which will not be described again.

[0130] Next, please refer to Fig. 9 , a first active area 210 is formed on the substrate 100, and a first gate dielectric layer 220 is formed on the first active area 210, the first electrode 201 and the second electrode 202. The first active area 210 is partially located between the first electrode 201 and the second electrode 202. The embodiment of the present invention does not specifically limit the method for forming the first active area 210 and the first gate dielectric layer 220, as long as the formed first active area 210 and the first gate dielectric layer 220 can meet the requirements of the first aspect for the first active area 210 and the first gate dielectric layer 220. In addition, the first active area 210 and the first gate dielectric layer 220 can be patterned separately or together.

[0131] Exemplarily, when the first active region 210 and the first gate dielectric layer 220 are patterned together, forming the first active region 210 on the substrate 100, and forming the first gate dielectric layer 220 on the first active region 210, the first electrode 201 and the second electrode 202 includes:

[0132] Please refer to Figure 6, a first active region 210 is formed on the first electrode 201, the substrate 100 and the second electrode 202, and the material of the first active region 210 is indium gallium zinc oxide. The embodiment of the present invention does not specifically limit the method for forming the first active region 210, as long as the formed first active region 210 meets the relevant requirements of the first aspect. Optionally, the first active region 210 is formed on the first electrode 201, the substrate 100 and the second electrode 202 by plasma enhanced atomic layer deposition, and the process temperature of the plasma enhanced atomic layer deposition is greater than or equal to 100°C and less than or equal to 300°C.

[0133] It should be noted that the first active region 210 may also be formed only on the substrate 100 , which may be determined according to the relevant description of the first aspect.

[0134] Afterwards, please refer to Figure 7 , a first dielectric sublayer included in the first gate dielectric layer 220 is grown on the first active region 210. The process for growing the first gate dielectric sublayer 221 adopts the same process as that for forming the first active region 210. For example, when the process for forming the first active region 210 adopts plasma enhanced atomic layer deposition, the first gate dielectric sublayer 221 is also formed by plasma enhanced atomic layer deposition, and the same process parameters are adopted.

[0135] Afterwards, please refer to Figure 8 , patterning the first gate dielectric sublayer 221 and the first active region 210. The embodiment of the present invention does not specifically limit the method of patterning the first gate dielectric sublayer 221 and the first active region 210, as long as the formed first active region 210 meets the relevant requirements of the first aspect. Optionally, the first gate dielectric sublayer 221 and the first active region 210 are patterned by photolithography and dry etching processes.

[0136] Afterwards, please refer to Fig. 9 , a second gate dielectric sublayer 222 included in the first gate dielectric layer 220 is formed on the first electrode 201, the first gate dielectric sublayer 221 and the second electrode 202. The embodiment of the present invention does not specifically limit the formation of the second gate dielectric sublayer 222, as long as the formed second gate dielectric sublayer 222 meets the relevant requirements of the first aspect.

[0137] For the materials and thicknesses of the first active region 210 and the first gate dielectric sublayer 221 and the second gate dielectric sublayer 222 included in the first gate dielectric layer 220 , please refer to the related description of the first aspect and will not be repeated here.

[0138] When the above scheme is adopted, the first gate dielectric sublayer 221 and the first active area 210 are formed and patterned together, and then the second gate dielectric sublayer 222 is formed. By separately forming the first gate dielectric sublayer 221 and the second gate dielectric sublayer 222 included in the first gate dielectric layer 220, it is possible to form a good interface between the first gate dielectric sublayer 221 and the first active area 210 without affecting the protective effect of the first gate dielectric layer 220 on the first active area 210, thereby extending the life of the first transistor 240.

[0139] Next, please refer to Fig.10 , a gate electrode 301 is formed on the first gate dielectric layer 220; the orthographic projection of the gate electrode 301 on the substrate 100 overlaps with the orthographic projection of the first active region 210 on the substrate 100; the second transistor 440 and the first transistor 240 share the gate electrode 301. The embodiment of the present invention does not specifically limit the process of forming the second gate dielectric sublayer 222, as long as the formed second gate dielectric sublayer 222 can meet the relevant requirements of the first aspect.

[0140] Exemplarily, the gate electrode 301 is grown on the active layer by electron beam evaporation, and the gate electrode 301 is patterned by photolithography and lift-off processes.

[0141] Next, please refer to Fig.11 , a second gate dielectric layer 410 is formed on the gate electrode 301 and the first gate dielectric layer 220. The embodiment of the present invention does not specifically limit the process of forming the second gate dielectric layer 410, as long as the formed second gate dielectric layer 410 can meet the relevant requirements of the first aspect.

[0142] Illustratively, the second gate dielectric layer 410 is formed on the gate electrode 301 and the first gate dielectric layer 220 by using an atomic layer deposition process.

[0143] For the material and thickness of the second gate dielectric layer 410 , please refer to the related description of the first aspect and will not be repeated here.

[0144] Next, please refer to Fig.12 , forming a through hole 311 penetrating the first gate dielectric layer 220 and the second gate dielectric layer 410, wherein the orthographic projection of the through hole 311 on the substrate 100 does not exceed the orthographic projection of the second electrode 202 on the substrate 100. The formed through hole 311 is used to form an electrode plug 312 electrically connecting the second electrode 202 and the fourth electrode 402 in a subsequent step. The embodiment of the present invention does not make a specific limitation on the process of forming the through hole 311, as long as the formed through hole 311 can be formed to meet the requirements of the electrode plug 312.

[0145] Exemplarily, the first gate dielectric layer 220 and the second gate dielectric layer 410 are subjected to photolithography and wet etching to form the through hole 311. Optionally, the wet etching agent is a phosphoric acid solution.

[0146] Next, please refer to Fig.13 , a third electrode 401 and a fourth electrode 402 are formed on the second gate dielectric layer 410, and an electrode plug 312 is formed in the through hole 311, the orthographic projection of the third electrode 401 on the substrate 100 overlaps with the orthographic projection of the first electrode 201 on the substrate 100, and the orthographic projection of the fourth electrode 402 on the substrate 100 overlaps with the orthographic projection of the second electrode 202 on the substrate 100. The embodiment of the present invention does not specifically limit the process of forming the third electrode 401 and the fourth electrode 402, as long as the performance of the formed third electrode 401 and the fourth electrode 402 can meet the requirements of the first aspect for the third electrode 401 and the fourth electrode 402.

[0147] Next, please refer to Fig.16 , a second active area 421 is formed on the second gate dielectric layer 410, and a patterned layer 422 is formed on the second active area 421; the orthographic projection of the second active area 421 on the substrate 100 overlaps with the orthographic projection of the gate electrode 301 on the substrate 100. The embodiment of the present invention does not specifically limit the method for forming the second active area 421 and the patterned layer 422, as long as the formed second active area 421 and the patterned layer 422 can meet the requirements of the first aspect for the second active area 421 and the patterned layer 422. For example, the method for forming the second active area 421 and the patterned layer 422 can adopt a solution processing method and / or an epitaxial process. In addition, the second active area 421 and the patterned layer 422 can be patterned separately or together.

[0148] When the above scheme is adopted, the patterned layer 422 and the second active area 421 are formed by low-temperature processes, which has a low thermal budget for the first transistor 240 and is not likely to cause problems such as post-process degradation and crystallization and deformation of the channel material in the first transistor 240, thereby ensuring the function and performance of the monolithic three-dimensional integrated device manufactured by the embodiment of the present invention.

[0149] Exemplarily, when the second active area 421 and the patterned layer 422 are patterned together, forming the second active area 421 on the substrate 100 and forming the patterned layer 422 on the first active area 210, the first electrode 201 and the second electrode 202 includes:

[0150] Please refer to Fig.14, a second active region 421 is formed on the third electrode 401, the second gate dielectric layer 410, and the fourth electrode 402. The material and thickness of the second active region 421 refer to the related description of the first aspect, which will not be repeated here. The embodiment of the present invention does not limit the method for forming the second active region 421, as long as the formed second active region 421 can meet the requirements of the first aspect for the second active region 421.

[0151] Exemplarily, a solution is used as a raw material to form the second active region 421. The types of solutions include solutions of conjugated small molecules such as pentacene, 2,7-dioctyl[1]benzothiophene[3,2-b][1]benzothiophene (C8-BTBT, CAS No. 583050-70-8), and solutions of conjugated polymers such as PffBT4T-2DT (chemical formula (C70H104N2S5F2)n, CAS No. (C70H104N2S5F2)n), poly-3 hexylthiophene (P3HT, CAS No. 104934-50-1), and other optional organic semiconductor material solutions. The concentration of the solution is greater than or equal to 0.1 mg / mL and less than or equal to 10 mg / mL. In addition, the solution is formed on the third electrode 401, the second gate dielectric layer 410, and the fourth electrode 402 using a thermal evaporation process, a spin coating process, and a pulling process. The second active region 421. Specifically, when the thermal evaporation process is selected, the evaporation rate of the thermal evaporation process is greater than or equal to Less than or equal to When spin coating is selected, the spin coating speed of the spin coating process is greater than or equal to 500rpm and less than or equal to 6000rpm; when the pulling process is selected, the pulling speed of the pulling process is greater than or equal to 50μm / s and less than or equal to 1000μm / s.

[0152] Optionally, the second active region 421 is formed by a pulling process. Because the pulling process can grow the second active region 421 with a thickness of a monolayer to a thin film. The energy band, dielectric constant, mobility and other parameters of the second active region 421 with different thicknesses do not change significantly, which is conducive to achieving better contact characteristics between the third electrode 401, the fourth electrode 402 and the second active region 421 by reducing the thickness of the second active region 421, weakening the short channel effect of the second transistor 440, and improving the performance of the second transistor 440.

[0153] Afterwards, please refer to Fig.15 , a patterned layer 422 is formed on the second active region 421. The material of the patterned layer 422 is Cytop. The embodiment of the present invention does not limit the method for forming the patterned layer 422, as long as the formed patterned layer 422 can meet the requirements of the first aspect for the patterned layer 422.

[0154] Exemplarily, a solution is used as a raw material to form the patterned layer 422. The solution is a mixed solution of a Cytop stock solution and a Cytop solvent, and the proportion of the Cytop stock solution in the mixed solution is greater than or equal to 1 / 3 and less than or equal to 1.

[0155] Exemplarily, a patterned layer 422 is formed on the organic semiconductor active layer by spin coating and annealing, the spin coating speed of the spin coating process is greater than or equal to 1200 rpm and less than or equal to 4000 rpm, the annealing temperature is greater than or equal to 50° C. and less than or equal to 120° C., and the annealing time is greater than or equal to 30 minutes and less than or equal to 90 minutes.

[0156] Afterwards, please refer to Fig.16 , the patterned layer 422 and the second active region 421 are patterned simultaneously. The embodiment of the present invention does not limit the patterning method, as long as the patterned layer 422 and the second active region 421 can meet the requirements of the patterned layer 422 in the first aspect.

[0157] Exemplarily, the patterned layer 422 and the second active region 421 are patterned simultaneously by photolithography and oxygen plasma etching processes.

[0158] Next, an encapsulation layer 430 is formed on the third electrode 401, the patterned layer 422 and the fourth electrode 402 to obtain Figure 1 The monolithic three-dimensional integrated transistor shown in the figure. The embodiment of the present invention does not specifically limit the method for forming the encapsulation layer 430, as long as the encapsulation layer 430 formed can meet the requirements of the first aspect for the encapsulation layer 430.

[0159] Exemplarily, the encapsulation layer 430 is formed by a thermal evaporation process.

[0160] Next, interconnect holes are formed on the encapsulation layer 430 to partially expose the first electrode 201, the second electrode 202, the gate electrode 301, the third electrode 401 and the fourth electrode 402 to connect other components to them, so that the monolithic three-dimensional integrated transistor provided in the embodiment of the present invention forms an effective logic element.

[0161] When using the above technical solution, please refer to Fig.17 The first transistor 240 of the monolithic three-dimensional integrated transistor manufactured in the embodiment of the present invention has good performance, and there is no significant performance degradation caused by the manufacturing process of the second transistor 440. Please refer to Fig.18 The second transistor 440 included in the monolithic three-dimensional integrated transistor manufactured by the embodiment of the present invention has good performance.

[0162] Please refer to the relevant description of the first aspect, the gate electrode 301 is used as the input end, the second electrode 202 or the fourth electrode 402 is used as the output end, and the first electrode 201 and the third electrode 401 are grounded and connected to the power supply respectively, so as to form an inverter, and realize the effective logical interconnection of the first transistor 240 and the second transistor 440. Please refer to Fig.19 , the inverter composed of monolithic three-dimensional integrated transistors has significant logical functions.

[0163] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0164] The above is only a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiment of the present invention, which should be included in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiment of the present invention should be based on the protection scope of the claims.

Claims

1. A monolithic three-dimensional integrated transistor, characterized in that: include: substrate; a first transistor formed on the substrate; The first transistor is a thin film transistor, and the active region material of the first transistor is indium gallium zinc oxide; and a second transistor formed on the first transistor; the second transistor is an organic thin film transistor; the second transistor and the first transistor constitute a three-dimensional stacked complementary transistor.

2. The monolithic three-dimensional integrated transistor according to claim 1, characterized in that: A source-drain electrode included in the first transistor is electrically connected to a source-drain electrode included in the second transistor; a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor; and the first transistor and the second transistor share a gate electrode.

3. The monolithic three-dimensional integrated transistor according to claim 2, characterized in that: The monolithic three-dimensional integrated transistor further comprises: Electrode embolization; The first transistor comprises: a first electrode, a second electrode, a first active region, a first gate dielectric layer and a gate electrode; The second transistor includes: a gate electrode, a second gate dielectric layer, a third electrode, a fourth electrode, a second active region and a patterned layer.

4. The monolithic three-dimensional integrated transistor according to claim 3, characterized in that: The first electrode and the second electrode are formed on the substrate at intervals along a direction parallel to the substrate; The first active region is at least formed on the substrate, and the active region is partially formed between the first electrode and the second electrode; The first gate dielectric layer is formed on the first electrode, the second electrode and the active area; The gate electrode is formed on the first gate dielectric layer, and an orthographic projection of the gate electrode on the substrate overlaps with an orthographic projection of the first active region on the substrate; The electrode plug penetrates the first gate dielectric layer, and the electrode plug is connected to the second electrode.

5. The monolithic three-dimensional integrated transistor according to claim 3, characterized in that: The second gate dielectric layer is formed on the gate electrode and the first gate dielectric layer; The electrode plug is connected to the fourth electrode, and the electrode plug penetrates the second gate dielectric layer; The third electrode and the fourth electrode are formed on the second gate dielectric layer; The orthographic projection of the third electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate; The second active region is at least formed on the second gate dielectric layer, and an orthographic projection of the second active region on the substrate overlaps with an orthographic projection of the gate electrode on the substrate; The patterned layer is formed on the second active region; the material of the patterned layer includes Cytop.

6. A method for manufacturing a monolithic three-dimensional integrated transistor, characterized in that: include: providing a substrate; forming a first transistor on the substrate; The first transistor is a thin film transistor, and the active region material of the first transistor is indium gallium zinc oxide; A second transistor is formed on the first transistor; the second transistor is an organic thin film transistor; the second transistor and the first transistor constitute a three-dimensional stacked complementary transistor.

7. The method for manufacturing a monolithic three-dimensional integrated transistor according to claim 6, characterized in that: The forming the first transistor on the substrate comprises: forming a first electrode and a second electrode on the substrate; forming a first active region on the substrate, and forming a first gate dielectric layer on the first active region, the first electrode and the second electrode; the first active region is partially located between the first electrode and the second electrode; forming a gate electrode on the first gate dielectric layer; an orthographic projection of the gate electrode on the substrate overlaps with an orthographic projection of the first active region on the substrate; the second transistor and the first transistor share the gate electrode; The forming a second transistor on the first transistor comprises: forming a second gate dielectric layer on the gate electrode and the first gate dielectric layer; forming a through hole penetrating the first gate dielectric layer and the second gate dielectric layer, wherein an orthographic projection of the through hole on the substrate does not exceed an orthographic projection of the second electrode on the substrate; Forming a third electrode and a fourth electrode on the second gate dielectric layer, wherein the orthographic projection of the third electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate; A second active region is formed on the second gate dielectric layer, and a patterned layer is formed on the second active region; an orthographic projection of the second active region on the substrate overlaps with an orthographic projection of the gate electrode on the substrate.

8. The method for manufacturing a monolithic three-dimensional integrated transistor according to claim 7, characterized in that: The method for manufacturing the monolithic three-dimensional integrated transistor further includes: An electrode plug is formed in the through hole; the fourth electrode and the second electrode are electrically connected via the electrode plug.

9. The method for manufacturing a monolithic three-dimensional integrated transistor according to claim 7, characterized in that: The forming of the second active area on the second gate dielectric layer and the forming of the patterned layer on the second active area comprises: forming the second active region on the second gate dielectric layer by solution processing and / or epitaxy; forming the patterned layer on the second gate dielectric layer by solution processing and / or epitaxy; The second active region and the patterned layer are patterned.

10. The method for manufacturing a monolithic three-dimensional integrated transistor according to claim 7, characterized in that: The forming of a first active area on the substrate, and forming a first gate dielectric layer on the first active area, the first electrode and the second electrode comprises: growing the first active region on the substrate; The first gate dielectric layer includes a first gate dielectric sublayer and a second gate dielectric sublayer; the first gate dielectric sublayer is deposited on the first active region, the first electrode and the second electrode; The first active region and the first gate dielectric sublayer are patterned.

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