Semiconductor apparatus and method of manufacturing semiconductor device
By annealing the semiconductor structure before manufacturing the oxide semiconductor layer and transferring the wafer in a vacuum environment, the problem of the oxide interface layer affecting the performance of semiconductor devices in the prior art is solved, and the device performance and reliability are improved Effect.
Patent Information
- Application Number
- CN202311007295.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-10
- Publication Date
- 2025-02-18
AI Technical Summary
In the prior art, when using atomic layer deposition technology to manufacture semiconductor devices containing oxide semiconductors as channel materials, an oxide interface layer is easily generated, which affects the performance and reliability of the semiconductor devices.
Before manufacturing the oxide semiconductor layer, the first structure of the semiconductor structure is annealed, and the first structure is annealed in a vacuum environment using a vacuum treatment chamber to reduce the hydrogen ions and hydroxide ions attached to the inside and the surface. content. At the same time, the wafer is transported in a vacuum environment through the vacuum transfer chamber to avoid contact with water vapor and oxygen in the outside air.
Through annealing treatment and vacuum transmission, the content of hydrogen ions and hydroxide ions in the semiconductor device is reduced, the stability of the oxide semiconductor layer is improved, and the performance and reliability of the semiconductor device are improved.
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Figure CN119465087A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device. Background Art
[0002] Atomic layer deposition (ALD) technology has the ability to control ultra-thin films, excellent film uniformity and step coverage due to its self-limiting growth characteristics. It can provide the best solution to the filling problems associated with the continuous miniaturization of semiconductor devices.
[0003] However, when using atomic layer deposition technology to manufacture semiconductor devices containing oxide semiconductors as channel materials, an oxide interface layer is easily generated, which affects the performance and reliability of the semiconductor devices. Summary of the invention
[0004] In view of the shortcomings of the existing methods, the present application proposes a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the technical problem that when using atomic layer deposition technology to manufacture semiconductor devices containing oxide semiconductors as channel materials in the prior art, an oxide interface layer is easily generated, which affects the performance and reliability of the semiconductor devices.
[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: at least one vacuum processing chamber and at least one vacuum transfer chamber, each of the vacuum processing chambers being connected to the vacuum transfer chamber;
[0006] The vacuum transfer chamber is used to transfer wafers;
[0007] At least one of the vacuum processing chambers includes a first vacuum processing chamber, which is used to anneal a first structure of the semiconductor structure on the wafer under a vacuum environment; the semiconductor structure also includes an oxide semiconductor layer arranged on one side of the first structure.
[0008] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device based on the semiconductor device of the first aspect, comprising:
[0009] transporting a wafer having a first structure to a first vacuum processing chamber through a vacuum transfer chamber;
[0010] Performing an annealing process on the first structure of the wafer in a vacuum environment using a first vacuum processing chamber;
[0011] An oxide semiconductor layer is manufactured on one side of the first structure to obtain a semiconductor structure.
[0012] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0013] Before manufacturing the oxide semiconductor layer, the first structure of the semiconductor structure is annealed, that is, the first structure is annealed in a vacuum environment using a first vacuum processing chamber, which can reduce the content of hydrogen ions and hydroxide ions attached to the interior and surface of the first structure, thereby facilitating the improvement of the stability of the subsequently manufactured oxide semiconductor layer, and further facilitating the improvement of the performance and reliability of the semiconductor device.
[0014] Moreover, the vacuum transfer chamber transfers wafers in a vacuum environment, which can avoid contact with water vapor and oxygen in the outside air, thereby helping to reduce the content of hydrogen ions and hydroxide ions in semiconductor devices, and further helping to improve the performance and reliability of semiconductor devices.
[0015] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0017] Figure 1 A schematic structural diagram of a first semiconductor device provided in an embodiment of the present application;
[0018] Figure 2 A schematic diagram of the structure of a second semiconductor device provided in an embodiment of the present application;
[0019] Figure 3 A schematic structural diagram of a third semiconductor device provided in an embodiment of the present application;
[0020] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;
[0021] Figures 5 to 11 A schematic cross-sectional view of each step of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
[0022] Description of reference numerals:
[0023] 1- vacuum processing chamber; 11- first vacuum processing chamber; 12- second vacuum processing chamber; 13- third vacuum processing chamber; 14- fourth vacuum processing chamber; 15- fifth vacuum processing chamber; 16- sixth vacuum processing chamber; 17- seventh vacuum processing chamber; 18- eighth vacuum processing chamber;
[0024] 2- vacuum transfer chamber; 21- first vacuum transfer chamber; 22- second vacuum transfer chamber; 23- third vacuum transfer chamber;
[0025] 3- Vacuum loading chamber;
[0026] 4-first structure; 41-first source / drain layer; 42-first insulating layer; 43-second source / drain layer; 44-first through hole; 45-second insulating layer; 46-third insulating layer;
[0027] 5-semiconductor structure; 51-first oxide semiconductor layer; 52-second oxide semiconductor layer;
[0028] 61-first gate insulating layer; 62-second gate insulating layer; 63-gate electrode layer;
[0029] 71 - initial first source / drain layer; 72 - initial first insulating layer; 73 - initial second source / drain layer; 74 - initial third insulating layer. DETAILED DESCRIPTION
[0030] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0031] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0033] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0034] The present application embodiment provides a semiconductor device. The structure diagram of the semiconductor device is as follows: Figures 1 to 3 As shown, it includes: at least one vacuum processing chamber 1 and at least one vacuum transfer chamber 2 , and each vacuum processing chamber 1 is connected to the vacuum transfer chamber 2 .
[0035] The vacuum transfer chamber 2 is used to transfer wafers.
[0036] At least one vacuum processing chamber 1 includes a first vacuum processing chamber 11, which is used to anneal the first structure 4 of the semiconductor structure 5 on the wafer under a vacuum environment; the semiconductor structure 5 also includes an oxide semiconductor layer arranged on one side of the first structure 4.
[0037] In this embodiment, before manufacturing the oxide semiconductor layer, the first structure 4 is annealed, that is, the first structure 4 is annealed in a vacuum environment using the first vacuum processing chamber 11, which can reduce the content of hydrogen ions and hydroxide ions attached to the interior and surface of the first structure 4, thereby facilitating the improvement of the stability of the subsequently manufactured oxide semiconductor layer, and further facilitating the improvement of the performance and reliability of the semiconductor device.
[0038] Moreover, the vacuum transfer chamber 2 transfers wafers in a vacuum environment, which can avoid contact with water vapor and oxygen in the outside air, thereby helping to reduce the content of hydrogen ions and hydroxide ions in semiconductor devices, and further helping to improve the performance and reliability of semiconductor devices.
[0039] Optionally, the first structure 4 includes a first source / drain layer 41, a first insulating layer 42 and a second source / drain layer 43 which are stacked, and a first through hole 44 which penetrates the second source / drain layer 43, the first insulating layer 42 and at least part of the first source / drain layer 41.
[0040] The number of the vacuum processing chambers 1 is at least two, and the second vacuum processing chamber 12 is also included. The second vacuum processing chamber 12 is connected to the vacuum transfer chamber 2 through a corresponding gate valve and is used to perform anti-oxidation treatment on the first structure 4 on the wafer.
[0041] In the related art, an oxygen source needs to be introduced in the process of manufacturing the oxide semiconductor layer. However, the introduced oxygen source easily oxidizes the source metal and the drain metal, so an oxide interface layer is easily formed at the contact surface between the source metal and the oxide semiconductor layer, and an oxide interface layer is easily formed at the contact surface between the drain metal and the oxide semiconductor layer, thereby increasing the contact resistance between the source metal and the oxide semiconductor layer, and between the drain metal and the oxide semiconductor layer.
[0042] In this embodiment, before manufacturing the oxide semiconductor layer, the first source / drain layer 41 and the second source / drain layer 43 are subjected to an anti-oxidation treatment to improve the anti-oxidation ability of the first source / drain layer 41 and the second source / drain layer 43, thereby reducing the possibility of forming an oxide interface layer, which is beneficial to improving the performance of the semiconductor device.
[0043] Optionally, the number of the vacuum processing chambers is at least four, further comprising a third vacuum processing chamber 13 and a fourth vacuum processing chamber 14; the third vacuum processing chamber 13 and the fourth vacuum processing chamber 14 are connected to the vacuum transfer chamber 2 through respective corresponding gate valves.
[0044] The third vacuum processing chamber 13 is used to conformally manufacture the first oxide semiconductor layer 51 in the first through hole 44 of the first structure 4 on the wafer under the first oxidant; the fourth vacuum processing chamber 14 is used to manufacture the second oxide semiconductor layer 52 on the surface of the first oxide semiconductor layer 51 under the second oxidant to form a semiconductor structure 5, wherein the oxide semiconductor layer includes the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52, and the oxidizing ability of the first oxidant is less than that of the second oxidant.
[0045] In this embodiment, the oxide semiconductor layer is manufactured in two steps. First, the first oxide semiconductor layer 51 is manufactured using a first oxidant with a weaker oxidizing ability as an oxygen source, and then the second oxide semiconductor layer 52 is manufactured using a second oxidant with a stronger oxidizing ability as an oxygen source. By first using the first oxidant with a weaker oxidizing ability as an oxygen source, the first source / drain layer 41 and the second source / drain layer 43 can be prevented from being oxidized as much as possible on the basis of improving the anti-oxidation ability of the first source / drain layer 41 and the second source / drain layer 43, thereby improving the performance and reliability of the semiconductor device; and then using the second oxidant with a stronger oxidizing ability as an oxygen source, the film quality of the second oxide semiconductor layer 52 can be improved.
[0046] Alternatively, the first oxidant may include at least one of IPA (isopropyl alcohol) and water, and the second oxidant may include at least one of ozone and oxygen plasma.
[0047] Optionally, the material of the first oxide semiconductor layer 51 and the material of the second oxide semiconductor layer 52 both include metal oxide.
[0048] In some embodiments, the material of the metal oxide may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, As long as the leakage current of the semiconductor structure 5 can meet the requirements, the specific materials can be adjusted according to the actual situation.
[0049] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the semiconductor device.
[0050] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.
[0051] Optionally, the number of vacuum processing chambers 1 is at least five, and also includes a fifth vacuum processing chamber 15, which is connected to the vacuum transfer chamber 2 through a corresponding gate valve and is used to perform ultraviolet irradiation treatment and / or annealing treatment on the semiconductor structure 5 on the wafer.
[0052] In this embodiment, the semiconductor structure 5 having the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 is subjected to ultraviolet irradiation treatment, so that the structure of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 can be reconstructed and intrinsic defects can be removed; the semiconductor structure 5 having the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 is subjected to post-annealing treatment, so that the content of hydrogen ions or defects such as oxygen vacancies can be reduced. Therefore, the ultraviolet irradiation treatment and / or annealing treatment of the semiconductor structure 5 on the wafer can improve the quality of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52.
[0053] Optionally, the number of the vacuum processing chambers 1 is at least seven, further comprising a sixth vacuum processing chamber 16 and a seventh vacuum processing chamber 17 ; the sixth vacuum processing chamber 16 and the seventh vacuum processing chamber 17 are connected to the vacuum transfer chamber 2 via respective corresponding gate valves.
[0054] The sixth vacuum processing chamber 16 is used to manufacture the first gate insulating layer 61 on the surface of the second oxide semiconductor layer 52 of the semiconductor structure 5 at a first temperature, and the seventh vacuum processing chamber 17 is used to manufacture the second gate insulating layer 62 on the surface of the first gate insulating layer 61 at a second temperature, wherein the first temperature is lower than the second temperature.
[0055] In this embodiment, the manufacturing of the gate insulating layer is divided into two steps. First, the first gate insulating layer 61 is manufactured at a first temperature at a relatively low temperature, which can prevent the elements in the oxide semiconductor layer from diffusing at a high temperature, and is conducive to ensuring the performance of the oxide semiconductor layer; and then the second gate insulating layer 62 is manufactured at a second temperature at a relatively high temperature. Specifically, the first temperature is not less than 100 degrees Celsius and not higher than 200 degrees Celsius, and the second temperature is not less than 200 degrees Celsius and not higher than 300 degrees Celsius.
[0056] Optionally, the number of vacuum processing chambers 1 is at least eight, and also includes an eighth vacuum processing chamber 18. The eighth vacuum processing chamber 18 is connected to the vacuum transfer chamber 2 through a corresponding gate valve, and is used to manufacture a gate electrode layer 63 on the surface of the second gate insulation layer 62 on the wafer, and the gate electrode layer 63 fills the first through hole 44.
[0057] In this embodiment, the material of the gate electrode layer 63 can be at least one of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminide (TiAl) and tantalum nitride (TaN).
[0058] Optionally, the semiconductor device further includes at least one vacuum loading chamber 3 , and the vacuum loading chamber 3 and the vacuum processing chamber 1 are both arranged on the periphery of the vacuum transfer chamber 2 .
[0059] In this embodiment, the vacuum loading chamber 3 and the vacuum processing chamber 1 are both arranged on the periphery of the vacuum transfer chamber 2. By transferring the wafer in the vacuum environment of the vacuum transfer chamber 2, the wafer can be prevented from contacting with water vapor and oxygen in the air, which is beneficial to reducing the content of hydrogen ions and hydroxide ions in the wafer, and further beneficial to improving the performance and reliability of semiconductor devices.
[0060] For example, Figure 1 A vacuum loading chamber 3 , a vacuum transfer chamber 2 and a vacuum processing chamber 1 are arranged therein, and the vacuum loading chamber 3 and the vacuum processing chamber 1 are both arranged on the periphery of the vacuum transfer chamber 2 .
[0061] Figure 2 A vacuum loading chamber 3 , a vacuum transfer chamber 2 and eight vacuum processing chambers 1 are arranged therein, and the vacuum loading chamber 3 and the eight vacuum processing chambers 1 are all arranged on the periphery of the vacuum transfer chamber 2 .
[0062] In the present application, a vacuum loading chamber 3 is used to transport wafers into or take out wafers from the outside.
[0063] Optionally, refer to Figure 3 There are three vacuum transmission chambers 2, including a first vacuum transmission chamber 21, a second vacuum transmission chamber 22 and a third vacuum transmission chamber 23. The first vacuum transmission chamber 21 is connected to the third vacuum transmission chamber 23 through the second vacuum transmission chamber 22.
[0064] The semiconductor device also includes two vacuum loading chambers 3, one vacuum loading chamber 3 and part of the vacuum processing chambers in at least two vacuum processing chambers 1 are arranged on the periphery of the first vacuum transfer chamber 21, and another vacuum loading chamber 3 and another part of the vacuum processing chambers in at least two vacuum processing chambers 1 are arranged on the periphery of the third vacuum transfer chamber 23.
[0065] In this embodiment, reference Figure 3 The first vacuum transfer chamber 21 is connected to the third vacuum transfer chamber 23 through the second vacuum transfer chamber 22, thereby ensuring that the entire process of transferring the wafer is carried out in a vacuum environment, which can prevent the wafer from contacting with water vapor and oxygen in the air, and is beneficial to reducing the content of hydrogen ions and hydroxide ions in the wafer, thereby helping to improve the performance and reliability of semiconductor devices.
[0066] Figure 3 As shown in the figure, there are two vacuum loading chambers 3, one of which is for transporting wafers from the outside, and the other is for transporting wafers out. This can avoid interference caused by transporting wafers in and out, which is beneficial to protecting the wafers.
[0067] It should be noted that Figures 1 to 3 It is just an example, and the specific numbers of the vacuum processing chamber 1 , the vacuum transfer chamber 2 and the vacuum loading chamber 3 can be set according to actual conditions.
[0068] Optionally, the semiconductor device further comprises at least one vacuum pump for adjusting the vacuum processing chamber 1 , the vacuum transfer chamber 2 and the vacuum loading chamber 3 to a vacuum state.
[0069] It should be noted that the requirements for vacuum degree of each chamber in the vacuum processing chamber 1 are different, among which the first vacuum processing chamber 11, the second vacuum processing chamber 12, and the fifth vacuum processing chamber 15 have higher requirements for vacuum degree, specifically, the vacuum degree is not less than 1e-10Pa (Pascal) and not greater than 1e-5Pa (Pascal). The third vacuum processing chamber 13, the fourth vacuum processing chamber 14, the sixth vacuum processing chamber 16, the seventh vacuum processing chamber 17, and the eighth vacuum processing chamber 18 have lower requirements for vacuum degree, specifically, the vacuum degree is not less than 1e-1Pa and not greater than 1e3Pa.
[0070] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a semiconductor device based on the semiconductor device provided in the above embodiment. The flow chart of the method is as follows: Figure 4 As shown, the method comprises steps S1 and S2:
[0071] S1 : transporting the wafer having the first structure 4 to the first vacuum processing chamber 11 through the vacuum transfer chamber 2 .
[0072] It is understandable that in the semiconductor device, a mechanical conveying device is provided in the vacuum transfer chamber 2 , and the wafer having the first structure 4 is conveyed to the first vacuum processing chamber 11 through the vacuum transfer chamber 2 by the mechanical conveying device.
[0073] S2: using the first vacuum processing chamber 11 to perform annealing treatment on the first structure 4 of the wafer in a vacuum environment.
[0074] S3: manufacturing an oxide semiconductor layer on one side of the first structure 4 to obtain a semiconductor structure.
[0075] In the related art, the semiconductor layer containing oxide semiconductor materials easily absorbs water vapor and oxygen in the air. Under radiation conditions, water vapor and oxygen are easily decomposed into hydrogen ions, oxygen ions and hydroxide ions, thereby reducing the performance and reliability of semiconductor devices.
[0076] In this embodiment, before manufacturing the oxide semiconductor layer, the first structure 4 is first annealed, that is, the first structure 4 is annealed in a vacuum environment using the first vacuum processing chamber 11, which can reduce the content of hydrogen ions and hydroxide ions attached to the interior and surface of the first structure 4, thereby facilitating the improvement of the stability of the oxide semiconductor layer manufactured subsequently, and further facilitating the improvement of the performance and reliability of the semiconductor device. Specifically, the annealing temperature is not less than 300 degrees Celsius and not more than 1000 degrees Celsius; the annealing time is not less than 5 minutes and not more than 10 hours, which can be set according to actual needs.
[0077] Moreover, transporting the wafer in a vacuum environment can avoid contact with water vapor and oxygen in the air, thereby helping to reduce the content of hydrogen ions and hydroxide ions in semiconductor devices.
[0078] Optionally, after step S2 and before step S3, the manufacturing method further includes:
[0079] The wafer having the first structure 4 is transferred from the first vacuum processing chamber 11 to the second vacuum processing chamber 12 through the vacuum transfer chamber 2; the first structure 4 of the wafer is subjected to an anti-oxidation treatment by the second vacuum processing chamber 12; the first structure 4 includes a first source / drain layer 41, a first insulating layer 42, and a second source / drain layer 43 which are stacked, and a first through hole 44 which penetrates the second source / drain layer 43, the first insulating layer 42, and at least a portion of the first source / drain layer 41.
[0080] In the related art, an oxygen source needs to be introduced in the process of manufacturing the oxide semiconductor layer. However, the introduced oxygen source easily oxidizes the source metal and the drain metal, so an oxide interface layer is easily formed at the contact surface between the source metal and the oxide semiconductor layer, and an oxide interface layer is easily formed at the contact surface between the drain metal and the oxide semiconductor layer, thereby increasing the contact resistance between the source metal and the oxide semiconductor layer, and between the drain metal and the oxide semiconductor layer.
[0081] In this embodiment, before manufacturing the oxide semiconductor layer, the first source / drain layer 41 and the second source / drain layer 43 are subjected to an anti-oxidation treatment to improve the anti-oxidation ability of the first source / drain layer 41 and the second source / drain layer 43, thereby reducing the possibility of forming an oxide interface layer, which is beneficial to improving the performance of the semiconductor device.
[0082] It should be noted that the first source / drain layer 41 can be a source, and the second source / drain layer 43 can be a drain; or, the first source / drain layer 41 can be a drain, and the second source / drain layer 43 can be a source. It can be specifically set according to actual conditions and is not limited here.
[0083] Optionally, the wafer having the first structure 4 in step S1 further includes a second insulating layer 45 disposed on a side of the first source / drain layer 41 away from the first insulating layer 42 and a third insulating layer 46 disposed on a side of the second source / drain layer 43 away from the first insulating layer 42. The method for manufacturing the first structure 4 includes:
[0084] A second insulating layer 45 , an initial first source / drain electrode layer 71 , an initial first insulating layer 72 , an initial second source / drain electrode layer 73 , and an initial third insulating layer 74 are stacked and manufactured on one side of the substrate.
[0085] The entire substrate is patterned to obtain a first through hole 44, so that the first through hole 44 passes through the initial third insulating layer 74, the initial second source / drain layer 73, the initial first insulating layer 72 and a portion of the initial first source / drain layer 71, to obtain a third insulating layer 46 formed by the initial third insulating layer 74, a second source / drain layer 43 formed by the initial second source / drain layer 73, a first insulating layer 42 formed by the initial first insulating layer 72 and a first source / drain layer 41 formed by the initial first source / drain layer 71.
[0086] In this embodiment, the wafer having the first structure 4 can be obtained in another semiconductor device, or manufactured in the semiconductor device of the present application.
[0087] Figure 5 It is a schematic cross-sectional view obtained after manufacturing a second insulating layer 45, an initial first source / drain layer 71, an initial first insulating layer 72, an initial second source / drain layer 73 and an initial third insulating layer 74 which are stacked on one side of a substrate. Figure 6 The entire substrate is patterned to obtain the first through hole 44 , so that the first through hole 44 passes through the initial third insulating layer 74 , the initial second source / drain layer 73 , the initial first insulating layer 72 and part of the initial first source / drain layer 71 .
[0088] Specifically, the first insulating layer 42, the second insulating layer 45 and the third insulating layer 46 can all be grown by PVD (Physical Vapor Deposition), CVD (chemical vapor deposition) or ALD (Atomic Layer Deposition). The material of the first insulating layer 42, the material of the second insulating layer 45 and the material of the third insulating layer 46 can all be insulating materials with a relatively small dielectric constant (such as silicon dioxide), which can be beneficial for reducing parasitic capacitance. The first source / drain layer 41 and the second source / drain layer 43 can also be grown by PVD, CVD or ALD, and the material of the first source / drain layer 41 and the material of the second source / drain layer 43 can be the same or different. The material of the first source / drain layer 41 and the material of the second source / drain layer 43 can be independently selected from at least one of materials with relatively low resistivity such as titanium nitride, tungsten or molybdenum, which can reduce parasitic resistance.
[0089] Optionally, in step S3, an oxide semiconductor layer is manufactured on one side of the first structure 4 to obtain a semiconductor structure, including:
[0090] The wafer with the first structure 4 is transferred from the second vacuum processing chamber 12 to the third vacuum processing chamber 13 through the vacuum transfer chamber 2 ; the first oxide semiconductor layer 51 is conformally manufactured in the first through hole 44 in the third vacuum processing chamber 13 under the first oxidant.
[0091] The wafer having the first oxide semiconductor layer 51 is transferred from the third vacuum processing chamber 13 to the fourth vacuum processing chamber 14 through the vacuum transfer chamber 2; the second oxide semiconductor layer 52 is manufactured on the surface of the first oxide semiconductor layer 51 in the fourth vacuum processing chamber 14 under the second oxidant to obtain a semiconductor structure 5.
[0092] In this embodiment, on the basis of improving the anti-oxidation ability of the first source / drain layer 41 and the second source / drain layer 43, the oxide semiconductor layer is manufactured in two steps in this application. First, the first oxide semiconductor layer 51 is manufactured using the first oxidant with a weaker oxidizing ability as an oxygen source, and then the second oxide semiconductor layer 52 is manufactured using the second oxidant with a stronger oxidizing ability as an oxygen source. By first using the first oxidant with a weaker oxidizing ability as an oxygen source, the first source / drain layer 41 and the second source / drain layer 43 can be prevented from being oxidized as much as possible on the basis of improving the anti-oxidation ability of the first source / drain layer 41 and the second source / drain layer 43, thereby improving the performance and reliability of the semiconductor device; and then using the second oxidant with a stronger oxidizing ability as an oxygen source, the film quality of the second oxide semiconductor layer 52 can be improved. Specifically, the thickness of the first oxide semiconductor layer 51 is not less than 1 nanometer and not more than 3 nanometers, and the thickness of the first oxide semiconductor layer 51 is 2 nanometers; the thickness of the second oxide semiconductor layer 52 is not less than 1 nanometer and not more than 50 nanometers.
[0093] Moreover, by using the vacuum transfer chamber 2 to transfer the wafer from the first vacuum processing chamber 11 to the second vacuum processing chamber 12 of at least two vacuum processing chambers 1, that is, by transferring the wafer in a vacuum environment, it is possible to avoid contact with water and oxygen in the air, thereby reducing the content of hydrogen ions and hydroxide ions in the wafer, which is beneficial to improving the performance and reliability of semiconductor devices.
[0094] Figure 7 It is a cross-sectional schematic diagram after the first oxide semiconductor layer 51 is conformally manufactured in the first through hole 44 under the first oxidant by using the third vacuum processing chamber 13; Figure 8 It is a cross-sectional schematic diagram of manufacturing the second oxide semiconductor layer 52 on the surface of the first oxide semiconductor layer 51 in the presence of a second oxidant by using the fourth vacuum processing chamber 14 after forming the semiconductor structure 5 .
[0095] Optionally, the anti-oxidation treatment comprises plasma treatment, wherein the ions in the plasma comprise at least one of nitrogen ions and fluorine ions; or, annealing treatment in an atmosphere of nitrogen or nitrogen fluoride.
[0096] In this embodiment, nitrogen ions and fluorine ions are both low-power ions, and other low-power plasma treatments may also be used.
[0097] Optionally, after the second oxide semiconductor layer 52 is manufactured on the surface of the first oxide semiconductor layer 51 in the presence of a second oxidant using the fourth vacuum processing chamber 14 to obtain the semiconductor structure 5, the method further includes:
[0098] The wafer with the semiconductor structure 5 is transferred from the fourth vacuum processing chamber 14 to the fifth vacuum processing chamber 15 through the vacuum transfer chamber 2 ; the semiconductor structure 5 of the wafer is subjected to ultraviolet irradiation treatment and / or annealing treatment by the fifth vacuum processing chamber 15 .
[0099] In this embodiment, the semiconductor structure 5 having the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 is subjected to ultraviolet irradiation treatment or annealing treatment, so that the quality of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 can be improved.
[0100] Optionally, after the semiconductor structure 5 of the wafer is subjected to ultraviolet irradiation treatment and / or annealing treatment by the fifth vacuum processing chamber 15, the method further includes:
[0101] The wafer with the semiconductor structure 5 is transferred from the fifth vacuum processing chamber 15 to the sixth vacuum processing chamber 16 through the vacuum transfer chamber 2; the first gate insulating layer 61 is manufactured on the surface of the second oxide semiconductor layer 52 of the semiconductor structure 5 at the first temperature by the sixth vacuum processing chamber 16.
[0102] The wafer having the first gate insulating layer 61 is transferred from the sixth vacuum processing chamber 16 to the seventh vacuum processing chamber 17 through the vacuum transfer chamber 2; the second gate insulating layer 62 is manufactured on the surface of the first gate insulating layer 61 at a second temperature in the seventh vacuum processing chamber 17, wherein the first temperature is lower than the second temperature.
[0103] The wafer with the second gate insulating layer 62 is transferred from the seventh vacuum processing chamber 17 to the eighth vacuum processing chamber 18 through the vacuum transfer chamber 2; the gate electrode layer 63 is manufactured on the surface of the second gate insulating layer 62 by the eighth vacuum processing chamber 18, so that the gate electrode layer 63 fills the first through hole 44.
[0104] In this embodiment, Fig. 9 It is a schematic cross-sectional view obtained after the first gate insulating layer 61 is manufactured on the surface of the second oxide semiconductor layer 52 of the semiconductor structure 5 at the first temperature by using the sixth vacuum processing chamber 16 . Fig.10It is a schematic cross-sectional view obtained after the second gate insulating layer 62 is manufactured on the surface of the first gate insulating layer 61 at the second temperature using the seventh vacuum processing chamber 17 . Fig.11 The schematic cross-sectional view is obtained after the gate electrode layer 63 is manufactured on the surface of the second gate insulating layer 62 by using the eighth vacuum processing chamber 18 so that the gate electrode layer 63 fills the first through hole 44 .
[0105] refer to Figures 9 and 10 In the present application, the manufacturing of the gate insulating layer is divided into two steps. First, the first gate insulating layer 61 is manufactured at a lower first temperature, which can prevent the elements in the oxide semiconductor layer from diffusing at high temperature, which is conducive to ensuring the performance of the oxide semiconductor layer; and then the second gate insulating layer 62 is manufactured at a higher second temperature. Specifically, the first temperature is not less than 100 degrees Celsius and not higher than 200 degrees Celsius, and the second temperature is not less than 200 degrees Celsius and not higher than 300 degrees Celsius.
[0106] Optionally, the material of the first gate insulating layer 61 and the material of the second gate insulating layer 62 can be independently selected from at least one of high dielectric constant materials such as hafnium dioxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), and lanthanum-doped hafnium dioxide (HfLaO).
[0107] Optionally, the material of the gate electrode layer 63 may be at least one of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminide (TiAl), and tantalum nitride (TaN).
[0108] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0109] 1. In the embodiment of the present application, before manufacturing the oxide semiconductor layer, the first structure is annealed, that is, the first structure is annealed in a vacuum environment using a first vacuum processing chamber, which can reduce the content of hydrogen ions and hydroxide ions attached to the interior and surface of the first structure, thereby facilitating the improvement of the stability of the subsequently manufactured oxide semiconductor layer, and further facilitating the improvement of the performance and reliability of the semiconductor device.
[0110] 2. In the embodiment of the present application, the vacuum transfer chamber transfers the wafer under a vacuum state, which can avoid contact with water vapor and oxygen in the outside air, thereby helping to reduce the content of hydrogen ions and hydroxide ions in the semiconductor device, and further helping to improve the performance and reliability of the semiconductor device.
[0111] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0112] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0113] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0114] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0115] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0116] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.
[0117] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that: include: at least one vacuum processing chamber and at least one vacuum transfer chamber, each of the vacuum processing chambers being connected to the vacuum transfer chamber; The vacuum transfer chamber is used to transfer wafers; At least one of the vacuum processing chambers includes a first vacuum processing chamber, which is used to anneal a first structure of the semiconductor structure on the wafer under a vacuum environment; the semiconductor structure also includes an oxide semiconductor layer arranged on one side of the first structure.
2. The semiconductor device according to claim 1, wherein: The first structure includes a first source / drain layer, a first insulating layer, and a second source / drain layer that are stacked, and a first through hole that penetrates the second source / drain layer, the first insulating layer, and at least a portion of the first source / drain layer; The number of the vacuum processing chambers is at least two, and the second vacuum processing chamber is further included. The second vacuum processing chamber is connected to the vacuum transfer chamber through a corresponding gate valve and is used to perform anti-oxidation treatment on the first structure on the wafer.
3. The semiconductor device according to claim 2, wherein: The number of the vacuum processing chambers is at least four, and further includes a third vacuum processing chamber and a fourth vacuum processing chamber; the third vacuum processing chamber and the fourth vacuum processing chamber are connected to the vacuum transfer chamber through respective corresponding gate valves; The third vacuum processing chamber is used to conformally manufacture a first oxide semiconductor layer in the first through hole of the first structure on the wafer under a first oxidant, and the fourth vacuum processing chamber is used to manufacture a second oxide semiconductor layer on the surface of the first oxide semiconductor layer under a second oxidant, wherein the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the oxidizing ability of the first oxidant is less than that of the second oxidant.
4. The semiconductor device according to claim 3, characterized in that The number of the vacuum processing chambers is at least five, and also includes a fifth vacuum processing chamber, which is connected to the vacuum transfer chamber through a corresponding gate valve and is used to perform ultraviolet irradiation treatment and / or annealing treatment on the semiconductor structure on the wafer.
5. The semiconductor device according to claim 4, characterized in that The number of the vacuum processing chambers is at least seven, and further includes a sixth vacuum processing chamber and a seventh vacuum processing chamber; the sixth vacuum processing chamber and the seventh vacuum processing chamber are connected to the vacuum transfer chamber through respective corresponding gate valves; The sixth vacuum processing chamber is used to manufacture a first gate insulating layer on the surface of the second oxide semiconductor layer of the semiconductor structure at a first temperature, and the seventh vacuum processing chamber is used to manufacture a second gate insulating layer on the surface of the first gate insulating layer at a second temperature, wherein the first temperature is lower than the second temperature.
6. The semiconductor device according to claim 5, characterized in that The number of the vacuum processing chambers is at least eight, and also includes an eighth vacuum processing chamber, which is connected to the vacuum transfer chamber through a corresponding gate valve and is used to manufacture a gate electrode layer on the surface of the second gate insulation layer on the wafer, and the gate electrode layer fills the first through hole.
7. The semiconductor device according to claim 1, wherein: The vacuum transfer chamber further comprises at least one vacuum loading chamber. The vacuum loading chamber and the vacuum processing chamber are both arranged on the periphery of the vacuum transfer chamber.
8. The semiconductor device according to claim 2, wherein: The number of the vacuum transmission chambers is three, including a first vacuum transmission chamber, a second vacuum transmission chamber and a third vacuum transmission chamber, and the first vacuum transmission chamber is connected to the third vacuum transmission chamber through the second vacuum transmission chamber; The semiconductor device further includes two vacuum loading chambers, one of the vacuum loading chambers and a portion of the vacuum processing chambers among at least two of the vacuum processing chambers are arranged on the periphery of the first vacuum transfer chamber, and another of the vacuum loading chambers and another portion of the vacuum processing chambers among at least two of the vacuum processing chambers are arranged on the periphery of the third vacuum transfer chamber.
9. A method for manufacturing a semiconductor device based on the semiconductor device according to any one of claims 1 to 8, characterized in that: include: transporting a wafer having a first structure to a first vacuum processing chamber through a vacuum transfer chamber; Utilizing the first vacuum processing chamber to perform annealing on the first structure of the wafer in a vacuum environment; An oxide semiconductor layer is manufactured on one side of the first structure to obtain a semiconductor structure.
10. The manufacturing method according to claim 9, characterized in that: After annealing the first structure of the wafer in a vacuum environment using a first vacuum processing chamber and before manufacturing an oxide semiconductor layer on one side of the first structure, the method further includes: The wafer having the first structure is transferred from the first vacuum processing chamber to the second vacuum processing chamber through the vacuum transfer chamber; the first structure on the wafer is subjected to an anti-oxidation treatment using the second vacuum processing chamber; the first structure comprises a first source / drain layer, a first insulating layer and a second source / drain layer which are stacked, and a first through hole which penetrates the second source / drain layer, the first insulating layer and at least a portion of the first source / drain layer.
11. The manufacturing method according to claim 10, characterized in that: Manufacturing an oxide semiconductor layer on one side of the first structure to obtain a semiconductor structure, comprising: The wafer having the first structure is transferred from the second vacuum processing chamber to the third vacuum processing chamber through the vacuum transfer chamber; the first oxide semiconductor layer is conformally manufactured in the first through hole in the third vacuum processing chamber under the first oxidant; The wafer having the first oxide semiconductor layer is transferred from the third vacuum processing chamber to the fourth vacuum processing chamber through the vacuum transfer chamber; the second oxide semiconductor layer is manufactured on the surface of the first oxide semiconductor layer in the presence of a second oxidant in the fourth vacuum processing chamber to obtain a semiconductor structure.
12. The manufacturing method according to claim 10, characterized in that: The anti-oxidation treatment comprises: Plasma treatment, wherein the ions in the plasma include at least one of nitrogen ions and fluorine ions; Alternatively, the annealing process is performed in a nitrogen or nitrogen fluoride atmosphere.
13. The manufacturing method according to claim 11, characterized in that: After manufacturing a second oxide semiconductor layer on the surface of the first oxide semiconductor layer in the presence of a second oxidant using the fourth vacuum processing chamber to obtain a semiconductor structure, the method further includes: The wafer having the semiconductor structure is transferred from the fourth vacuum processing chamber to the fifth vacuum processing chamber through the vacuum transfer chamber; and the semiconductor structure of the wafer is subjected to ultraviolet irradiation treatment and / or annealing treatment by using the fifth vacuum processing chamber.
14. The manufacturing method according to claim 13, characterized in that: After the semiconductor structure of the wafer is subjected to ultraviolet irradiation treatment and / or annealing treatment by the fifth vacuum processing chamber, the method further comprises: Transferring the wafer having the semiconductor structure from the fifth vacuum processing chamber to the sixth vacuum processing chamber through the vacuum transfer chamber; manufacturing a first gate insulating layer on the surface of the second oxide semiconductor layer of the semiconductor structure at a first temperature by using the sixth vacuum processing chamber; Transferring the wafer having the first gate insulating layer from the sixth vacuum processing chamber to the seventh vacuum processing chamber through the vacuum transfer chamber; manufacturing a second gate insulating layer on the surface of the first gate insulating layer at a second temperature by using the seventh vacuum processing chamber, wherein the first temperature is lower than the second temperature; The wafer having the second gate insulating layer is transferred from the seventh vacuum processing chamber to the eighth vacuum processing chamber through the vacuum transfer chamber; and a gate electrode layer is manufactured on the surface of the second gate insulating layer by using the eighth vacuum processing chamber so that the gate electrode layer fills the first through hole.