Circuit board open circuit analysis method

Abstract

The invention relates to the technical field of circuit board detection, and discloses a circuit board open circuit analysis method, which comprises the following steps: performing on-off detection on a target circuit board through a universal meter to judge whether the target circuit board is open or not, and judging whether the target circuit board has appearance defects or not through a metallographic microscope when the target circuit board is open or not. When the target circuit board does not have appearance defects, detecting the outer layer network of the target circuit board through a metallographic microscope to judge whether the outer layer network has defects or not, and under the condition that the outer layer network does not have line defects, detecting the inner layer network of the target circuit board through the metallographic microscope to judge whether the outer layer network has defects or not; and judging whether the inner-layer network has defects or not. According to the invention, appearance detection, outer-layer network detection and inner-layer network detection are sequentially carried out on the circuit board through the existing electronic equipment, and open circuit analysis can be comprehensively carried out on the circuit board, so that the defect position can be quickly determined from the circuit board, and the purpose of improving the open circuit analysis efficiency of the circuit board can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board detection, and in particular to a circuit board open circuit analysis method. Background Art

[0002] With the rapid development of science and technology, the structure of circuit boards is becoming more and more complex. For example, the number of circuit boards is increasing and the size is getting larger. When an open circuit occurs on the circuit board, the open circuit analysis of the circuit board becomes more and more difficult.

[0003] At present, a non-destructive method is usually used to perform open circuit analysis on a circuit board, such as using a 3D X-ray diffractometer to perform open circuit analysis on the circuit board. However, this method is time-consuming. For example, a 3D X-ray diffractometer test takes about 24 hours. Therefore, the existing circuit board open circuit analysis method has the problem of low efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a circuit board open circuit analysis method to solve the problem of low efficiency of circuit board open circuit analysis in response to the above technical problems.

[0005] A circuit board open circuit analysis method, the method comprising: Performing a continuity test on the target circuit board by using a multimeter to determine whether an open circuit occurs on the target circuit board; If the target circuit board has an open circuit, determine whether the target circuit board has an appearance defect by using a metallographic microscope; If the target circuit board has no appearance defects, inspecting the outer network of the target circuit board through a metallographic microscope to determine whether the outer network has defects; In the case that no line defects occur in the outer layer network, the inner layer network of the target circuit board is inspected by a metallographic microscope to determine whether the inner layer network has defects.

[0006] Optionally, the method includes detecting the outer network of the target circuit board by a metallographic microscope to determine whether the outer network has defects, including: Performing ink fading treatment on the target circuit board so that the target circuit board leaks out the outer network; The outer network is inspected by a metallographic microscope to determine whether there are defects in the outer network.

[0007] In the above method, optionally, the ink fading process comprises: The target circuit is immersed in a sodium hydroxide solution with a concentration of 25% and a temperature of 90° C. for a preset time.

[0008] Optionally, the method includes performing an inner layer network inspection on the target circuit board through a metallographic microscope to determine whether the inner layer network has defects, including: If the inner network of the target circuit board is an inner circuit, the target circuit board is subjected to a flat grinding process so that the inner circuit of the target circuit board is exposed; Inspecting the inner layer circuit by metallographic microscope to determine whether the inner layer circuit has defects; If the inner layer network of the target circuit board is a through hole, slicing the target circuit board to reveal the through hole on the slice; The through hole is inspected by a metallographic microscope to determine whether the through hole has defects.

[0009] The above method, optionally, when the inner layer circuit has no defects and the through hole has no defects, the method further comprises: The slices are baked to obtain sample slices; The sample is inspected by a metallographic microscope to determine whether the through hole has defects.

[0010] Optionally, in the above method, when it is determined that the through hole has a defect, the method further comprises: Performing gold spraying on the slice to obtain a gold sprayed slice; The gold-sprayed slice is inspected by a scanning electron microscope, and the composition of the gold-sprayed slice is analyzed by an energy spectrum analyzer to determine whether the through hole has defects.

[0011] In the above method, optionally, the baking temperature of the baking treatment is 125° C. and the baking time is 3 minutes.

[0012] In the above method, optionally, the defects of the inner layer circuit include: circuit cracking, circuit gap, circuit width, circuit thinness and circuit flying wire.

[0013] In the above method, optionally, the defects of the through hole include: missed drilling, foreign matter in the hole, cracks in the hole, and voids in the hole extending to the hole wall.

[0014] In the above method, optionally, the appearance defects include: surface stains, surface debris, surface pits, surface tin slag residue and surface scratches exposing the base material.

[0015] In a circuit board open circuit analysis method disclosed in the present invention, firstly, a multimeter is used to perform on-off detection on a target circuit board to determine whether an open circuit occurs on the target circuit board. When it is determined that an open circuit occurs on the target circuit board, a metallographic microscope is used to determine whether the target circuit board has appearance defects. When the target circuit board does not have appearance defects, the outer network of the target circuit board is detected by a metallographic microscope to determine whether the outer network has defects. When no line defects occur in the outer network, the inner network of the target circuit board is detected by a metallographic microscope to determine whether the inner network has defects. It can be seen that the present invention can perform appearance detection, outer network detection, and inner network detection on the circuit board in sequence through existing electronic equipment, and can comprehensively perform open circuit analysis on the circuit board, thereby quickly determining the defect location from the circuit board, and can achieve the purpose of improving the efficiency of circuit board open circuit analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0017] Figure 1 It is a flow chart for realizing a circuit board open circuit analysis method disclosed in one embodiment of the present invention; Figure 2 It is a partial flow chart of a circuit board open circuit analysis method disclosed in one embodiment of the present invention; Figure 3 It is a partial flow chart of a circuit board open circuit analysis method disclosed in one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0019] It should be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and to illustrate the best mode of the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize the applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0020] It should also be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0021] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0022] It should also be understood that the terms "upper", "lower", "left", "right", "front", "back", "bottom", "middle", "middle", "top", etc. may be used herein to describe various elements, and the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore these elements should not be restricted by these terms.

[0023] These terms are only used to distinguish one element from another element. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element according to the relative orientation of these elements without departing from the scope of the present disclosure.

[0024] It is further understood that the terms “comprises,” “includes,” “including,” and / or “comprising,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0026] The present invention discloses a circuit board open circuit analysis method. First, a multimeter is used to perform on-off detection on a target circuit board to determine whether an open circuit occurs on the target circuit board. When it is determined that an open circuit occurs on the target circuit board, a metallographic microscope is used to determine whether the target circuit board has an appearance defect. When the target circuit board does not have an appearance defect, the outer network of the target circuit board is detected by a metallographic microscope to determine whether the outer network has a defect. When no line defect occurs on the outer network, the inner network of the target circuit board is detected by a metallographic microscope to determine whether the inner network has a defect. It can be seen that the present invention can perform an open circuit analysis on the circuit board comprehensively by sequentially performing an appearance detection, an outer network detection, and an inner network detection on the circuit board through existing electronic equipment, thereby quickly determining the defect location from the circuit board, and achieving the purpose of improving the efficiency of circuit board open circuit analysis.

[0027] like Figure 1 FIG. 1 is a flowchart of a method for analyzing an open circuit of a circuit board disclosed in an embodiment of the present invention. The method specifically includes the following steps: S101: Perform a continuity test on the target circuit board using a multimeter to determine whether an open circuit occurs on the target circuit board.

[0028] Specifically, in this embodiment, a wire can be welded to the circuit network on the front or back of the circuit board to lead out a detection end, and then the detection end is connected through a probe of a multimeter. When the multimeter displays infinite resistance, it is determined that the target circuit board has an open circuit.

[0029] S102: If an open circuit occurs on the target circuit board, determine whether the target circuit board has appearance defects through a metallographic microscope.

[0030] Among them, appearance defects include but are not limited to one or more defects such as surface stains, surface debris, surface pits, surface tin slag residue, and surface scratches exposing the base material.

[0031] Specifically, in this embodiment, the target circuit board can be placed in the observation area of ​​the metallographic microscope, and then the outer surface of the target circuit board can be observed through the metallographic microscope to see if there are any defects. When it is determined that the outer surface of the target circuit board has any of the defects of surface stains, surface debris, surface pits, surface tin slag residue, and surface scratches exposing the base material, it is determined that the target circuit board has appearance defects; if the outer surface of the target circuit board does not have defects, the outer layer network of the target circuit board is inspected through the metallographic microscope to determine whether there are defects in the outer layer network.

[0032] It should be noted that using a metallographic microscope to determine whether the target circuit board has appearance defects is only one implementation method in this embodiment. Other types of microscopes can also be used in this embodiment, and the resulting technical solutions are all within the protection scope of the present invention.

[0033] S103: If the target circuit board has no appearance defects, the outer network of the target circuit board is inspected by a metallographic microscope to determine whether the outer network has defects.

[0034] The outer network is generally a line network, and therefore, the defects of the outer network include but are not limited to one or more defects in line cracks, line gaps, line widths, line thinness, and line flying wires.

[0035] Specifically, step S103 in this embodiment can be implemented by the following steps: Figure 2 As shown: S201: performing ink fading treatment on the target circuit board so that the target circuit board leaks out the outer network.

[0036] The ink fading treatment includes: soaking the target circuit in a sodium hydroxide solution with a concentration of 25% and a temperature of 90° C. for a preset time. The preset time includes but is not limited to 90 minutes, 100 minutes, or 120 minutes, etc., which is not limited in this embodiment.

[0037] S202: Inspect the outer network through a metallographic microscope to determine whether there are defects in the outer network.

[0038] Specifically, in this embodiment, the leaked outer network of the target circuit can be placed upward in the observation area of ​​the metallographic microscope, and then the metallographic microscope is used to observe whether the line of the outer network has defects. When it is determined that the line of the outer network has one or more defects such as line cracking, line gap, line width, line thinness, and line flying wire, it is determined that the outer network has appearance defects; if the outer network does not have defects, the inner network of the target circuit board is inspected with a metallographic microscope to determine whether the inner network has defects.

[0039] S104: When no line defects occur in the outer layer network, the inner layer network of the target circuit board is inspected by a metallographic microscope to determine whether there are defects in the inner layer network.

[0040] The inner network of the circuit board includes through holes, blind holes and inner circuits. The defects of through holes include but are not limited to one or more of missed holes, foreign matter in the holes, cracks in the holes and holes extending into the hole walls; the defects of inner circuits include but are not limited to one or more of circuit cracks, circuit gaps, circuit width, circuit thinness and circuit flying wires.

[0041] On the one hand, when the inner layer network of the circuit board is an inner layer line, the target circuit board can be flat-ground in this embodiment to make the inner layer line of the target circuit board leak out, and then the inner layer line is inspected through a metallographic microscope to determine whether there are defects in the inner layer line, that is, to observe through a metallographic microscope whether the inner layer line has one or more defects such as line cracking, line gap, line width, line thinness and line flying line.

[0042] Secondly, when the inner layer network of the circuit board is a through hole or a blind hole, in this embodiment, the target circuit board can be sampled to obtain a sample, and then the sample is made into slices, and then the through hole is inspected through a metallographic microscope to determine whether there are defects in the through hole, that is, the slice is observed through a metallographic microscope to determine whether there are one or more defects such as missed holes, foreign matter in the hole, cracks in the hole, and voids in the hole extending to the hole wall.

[0043] In summary, in a circuit board open circuit analysis method disclosed by the present invention, firstly, a multimeter is used to perform on-off detection on the target circuit board to determine whether an open circuit occurs in the target circuit board. When it is determined that the target circuit board occurs an open circuit, a metallographic microscope is used to determine whether the target circuit board has an appearance defect. When the target circuit board does not have an appearance defect, the outer network of the target circuit board is detected by a metallographic microscope to determine whether the outer network has a defect. When there is no line defect in the outer network, the inner network of the target circuit board is detected by a metallographic microscope to determine whether the inner network has a defect. It can be seen that the present invention can perform an open circuit analysis on the circuit board comprehensively by sequentially performing appearance detection, outer network detection, and inner network detection on the circuit board through existing electronic equipment, thereby quickly determining the defect location from the circuit board, and achieving the purpose of improving the efficiency of circuit board open circuit analysis.

[0044] In one embodiment, when there are no defects in the inner layer circuit and the through hole, the method further includes the following steps: Figure 3 As shown: S301: baking the slices to obtain sample slices.

[0045] S302: inspecting the sample through a metallographic microscope to determine whether there are defects in the through hole.

[0046] It should be understood that the process of making slices usually includes steps such as sampling, glue filling, membrane, polishing and micro-etching. Therefore, after observing the produced slices through a metallographic microscope, if no defects of through holes or blind holes are observed on the slices, in this embodiment, the slices can also be baked to melt the colloid on the surface of the slices, and then the sample in the colloid is taken out by tweezers, and then the sample is inspected by a metallographic microscope to determine whether there are defects in the through holes.

[0047] Specifically, in this embodiment, the slices can be placed in a closed oven, and then baked at a baking temperature of 125°C and a baking time of 3 minutes. It should be noted that the above baking temperature and baking time are only one implementation method in this embodiment, and the technical solutions formed by simply changing the baking temperature and baking time are within the protection scope of the present invention.

[0048] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A circuit board open circuit analysis method, characterized in that: The method comprises: Performing a continuity test on the target circuit board by using a multimeter to determine whether an open circuit occurs on the target circuit board; If the target circuit board has an open circuit, determine whether the target circuit board has an appearance defect by using a metallographic microscope; If the target circuit board has no appearance defects, inspecting the outer network of the target circuit board through a metallographic microscope to determine whether the outer network has defects; In the case that no line defects occur in the outer layer network, the inner layer network of the target circuit board is inspected by a metallographic microscope to determine whether the inner layer network has defects.

2. The circuit board open circuit analysis method according to claim 1, characterized in that: The detecting the outer network of the target circuit board by a metallographic microscope to determine whether the outer network has defects includes: Performing ink fading treatment on the target circuit board so that the target circuit board leaks out the outer network; The outer network is inspected by a metallographic microscope to determine whether there are defects in the outer network.

3. The circuit board open circuit analysis method according to claim 2, characterized in that: The ink fading process comprises: The target circuit is immersed in a sodium hydroxide solution with a concentration of 25% and a temperature of 90° C. for a preset time.

4. The circuit board open circuit analysis method according to claim 1, characterized in that: The inner layer network detection of the target circuit board is performed by a metallographic microscope to determine whether the inner layer network has defects, including: If the inner network of the target circuit board is an inner circuit, the target circuit board is subjected to a flat grinding process so that the inner circuit of the target circuit board is exposed; Inspecting the inner layer circuit by metallographic microscope to determine whether the inner layer circuit has defects; If the inner layer network of the target circuit board is a through hole, slicing the target circuit board to reveal the through hole on the slice; The through hole is inspected by a metallographic microscope to determine whether the through hole has defects.

5. The circuit board open circuit analysis method according to claim 4, characterized in that: In the case where the inner layer circuit has no defects and the through hole has no defects, the method further includes: The slices are baked to obtain sample slices; The sample is inspected by a metallographic microscope to determine whether the through hole has defects.

6. The circuit board open circuit analysis method according to claim 5, characterized in that: In the case where it is determined that the through hole has a defect, the method further includes: Performing gold spraying on the slice to obtain a gold sprayed slice; The gold-sprayed slice is inspected by a scanning electron microscope, and the composition of the gold-sprayed slice is analyzed by an energy spectrum analyzer to determine whether the through hole has defects.

7. The circuit board open circuit analysis method according to claim 5, characterized in that: The baking temperature of the baking process is 125° C. and the baking time is 3 minutes.

8. The circuit board open circuit analysis method according to claim 4, characterized in that: The defects of the inner layer circuit include: circuit cracking, circuit gap, circuit width, circuit thinness and circuit flying wire.

9. The circuit board open circuit analysis method according to claim 4, characterized in that: The defects of the through hole include: missed drilling, foreign matter in the hole, cracks in the hole, and cavities in the hole extending to the hole wall.

10. The circuit board open circuit analysis method according to claim 1, characterized in that: The appearance defects include: surface stains, surface debris, surface pits, surface tin slag residue and surface scratches exposing the base material.

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