Chip contact reliability detection device and method

Abstract

The invention discloses a chip contact reliability detection device and method in the technical field of electronic device reliability testing. The device comprises a burn-in board which is provided with a plurality of sockets, and the sockets are used for installing chips to be tested; the reliability equipment comprises a digital signal generation board, a power board, a back board and an adapter board, and the digital signal generation board and the power board are connected with the burn-in board through the back board and the adapter board; the detection assembly comprises a current measurement circuit, a voltage measurement circuit, an input circuit and an output circuit; and the PC is in communication connection with the power panel, the digital signal generation board and the detection assembly and is used for controlling the power panel, the digital signal generation board and the detection assembly to work and acquiring detection information. According to the detection method, which one of a plurality of chips connected in parallel on the burn-in board has a power supply short circuit and an open circuit can be positioned; and besides the power supply, whether other digital pins of the chip are in reliable contact can be detected.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic device reliability testing, and in particular to a chip contact reliability detection device and method. Background Art

[0002] The present invention belongs to the field of electronic device reliability testing, and more specifically, is a method and device for detecting the reliable connection between a chip and a fixture during reliability testing of electronic components such as CPU, GPU, MCU and other integrated circuits.

[0003] Usually, when conducting reliability tests on chips, the chips are first placed in sockets, and multiple sockets are connected to BIBs (aging boards) through installation or welding, and the BIBs are then connected to reliability testing equipment through connectors. Finally, the reliability testing equipment provides environmental stimuli such as temperature, humidity, and pressure, as well as power and digital signals to the chip, thereby achieving the purpose of verifying the chip reliability.

[0004] As chip manufacturing processes become more sophisticated, chip integration becomes higher, and functions become more complex, the number of chip pins has reached thousands. Due to the processing problems of the socket and the probe inside the socket, there may be poor contact between the probe and the chip. In addition, the socket probe is a spring structure. As the BIB is used for a longer time, the performance of the probe spring deteriorates in a high temperature environment, and the poor contact between the probe and the chip will be aggravated. When there is poor contact between the probe and the chip, it will cause: 1) The probe burns or the chip burns 2) The chip test results fail due to contact, causing test miskilling and chip waste 3) Reliability testing usually takes a long time, reaching dozens or even thousands of hours. If the poor contact cannot be identified at the beginning of the test, it will cause a waste of test time and increase the test cost. However, the current chip contact test only performs an overall voltage and current test on the power pins of the chip of the entire BIB. When individual chips have poor contact, it will be covered up as a whole, resulting in the inability to identify the problems of individual chips, which will still cause the above-mentioned harmful consequences. Summary of the invention

[0005] The present application solves the problem in the prior art that chip contact testing cannot determine whether individual chips have poor contact by providing a chip contact reliability detection device and method, thereby achieving accurate detection of a single chip.

[0006] The embodiment of the present application provides a chip contact reliability detection device, comprising:

[0007] A burn-in board, the burn-in board is provided with a plurality of sockets, the sockets are used for installing the chips to be tested, and the burn-in board is also used for providing peripheral circuits necessary for the chip to work;

[0008] A reliability device, comprising a digital signal generating board, a power board, a backplane and an adapter board, wherein the power board is used to provide output power to the chip under test, and the digital signal generating board is used to output digital signals to the chip under test and read back the digital signal level output by the chip under test; the digital signal generating board and the power board are connected to the aging board through the backplane and the adapter board;

[0009] A detection component, including a current measurement circuit, a voltage measurement circuit, an input circuit, and an output circuit, wherein the current measurement circuit, the voltage measurement circuit, the input circuit, and the output circuit are respectively connected to the pins of the chip to be tested through corresponding probes;

[0010] The PC is connected to the power board, the digital signal generating board and the detection component for controlling the power board, the digital signal generating board and the detection component to work and obtain detection information.

[0011] Based on the above embodiments, the present application can be further improved as follows:

[0012] In one of the embodiments of the present application, the power board is provided with a current and voltage detection device for checking the output power and output current of the power board.

[0013] In one of the embodiments of the present application, the power board is also provided with a protection device to perform a shutdown or clamping action when a short circuit or open circuit occurs.

[0014] The embodiment of the present application also provides a chip contact reliability detection method, based on the above reliability detection device, comprising the following steps:

[0015] S1: Installing a number of the chips to be tested into the sockets corresponding to the aging board, and docking the aging board with the reliability equipment;

[0016] S2: The PC sets the upper and lower limits of the output voltage and current of the power board, the upper and lower limits of the working voltage and current of the aging board, sets the open circuit voltage and current detection threshold, and sets the short circuit voltage and current detection threshold;

[0017] S3: The power board supplies power to the aging board, detects the output voltage and current of the power board and the working voltage and current of the aging board, and determines whether the power supply is short-circuited or open-circuited by the output voltage and current. If it is determined that the power supply is short-circuited or open-circuited, the power board starts power protection. If the working voltage and current of the aging board exceed the preset upper and lower limits of the working voltage and current, the power board starts power protection. After starting the power protection, the power board feeds back a signal to the PC, and the PC records the error and terminates the detection.

[0018] S4: If the above tests are normal, the following tests are performed on each of the chips to be tested on the aging board in turn:

[0019] S4.1: A group of power pins in the chip under test is used as a test group, and the other power pins are used as a normal group. The voltage of the power pins in the test group is detected and compared with the voltage of the power pins in the normal group to determine whether the voltage of the power pins in the test group is normal. If it is not normal, the power board starts power protection and feeds back a signal to the PC, and the PC records the error and terminates the detection;

[0020] S4.2: The digital signal generating board is connected to the input pin of the chip under test through the input circuit, and is connected to the output pin of the chip under test through the output circuit. The digital signal generating board outputs a test signal to the input pin of the chip under test, and detects the actual level of the input pin to determine whether the actual level is consistent with the expected level. If not, it is determined that the chip under test has an open circuit or a short circuit, and a signal is fed back to the PC. The PC records the error and terminates the detection.

[0021] S4.3: The digital signal generating board detects the output signal of the output pin of the chip under test, determines whether the output signal is consistent with the expectation, and if not, determines that the chip under test has an open circuit or a short circuit, and feeds back a signal to the PC, which records the error and terminates the detection;

[0022] S4.4: If the above tests are all normal, the chip to be tested is determined to be normal and the test ends.

[0023] In one embodiment of the present application, when the detection of the current chip to be tested in steps S4.1-S4.3 is terminated due to a short circuit or an open circuit, the next chip to be tested is tested sequentially until all chips are tested.

[0024] In one embodiment of the present application, the power protection is a clamping or shutting down action.

[0025] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0026] 1. Compared with the existing solutions, this detection method can locate which chip among several chips connected in parallel on the aging board has a power short circuit or open circuit.

[0027] 2. Compared with the existing solutions, this detection method can detect whether other digital pins of the chip are in reliable contact except the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0029] Figure 1 It is a structural block diagram of a chip contact reliability detection device in an embodiment;

[0030] Figure 2 A flowchart of a chip contact reliability detection method in an embodiment;

[0031] Figure 3 This is a block diagram of short-circuit and open-circuit detection of a single chip power supply in an embodiment;

[0032] Figure 4 This is a block diagram of open-circuit and short-circuit detection of digital signals of a single chip in an embodiment. DETAILED DESCRIPTION

[0033] The present invention is further explained below in conjunction with specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0034] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention and the features of different embodiments or examples without contradiction.

[0037] Embodiment 1:

[0038] like Figure 1 As shown, a chip contact reliability detection device includes: an aging board, a reliability device and a PC.

[0039] Aging board, the aging board is provided with multiple sockets, the sockets are used for installing the chip to be tested, and the aging board is also used to provide the peripheral circuit necessary for the chip to work; the ball at the bottom of the chip contacts the probe of the socket, the ball of the chip contacts one end of the socket probe, and the other end of the socket probe is connected to the aging board, and each pin of the chip corresponds to a probe.

[0040] Reliability equipment, including digital signal generation board, power board, backplane and adapter board:

[0041] The power board is used to provide output power to the chip under test. The power board can set current and voltage protection thresholds, detect current and voltage, determine short circuit and open circuit, and record and feedback short circuit and open circuit error signals; the power board is also provided with a current and voltage detection device to check the output power and output current of the power board. The power board is also provided with a protection device to execute a shutdown or clamping strategy when a short circuit or open circuit occurs;

[0042] The digital signal generating board is used to output digital signals to the chip under test according to the chip test vector, detect the output digital signal level, and read back the digital signal level output by the chip under test, determine whether the chip digital pin is open or short-circuited, and record and feedback the open or short-circuit error signal;

[0043] The backplane and adapter board are used to connect the digital signal generating board, the power board and the aging board.

[0044] The detection component includes a current measurement circuit and a voltage measurement circuit arranged on the aging board, and an input circuit and an output circuit arranged on the digital signal generating board; the current measurement circuit, the voltage measurement circuit, the input circuit and the output circuit are respectively connected to the corresponding pins of the chip to be tested through the corresponding probes of the socket.

[0045] The PC is connected to the power board, digital signal generating board and detection component for communication. The PC is used to install the test system software to execute the following test method. The PC communicates with the power board and digital signal generating board to obtain the working status and connection status of the chip, control the working of the power board, digital signal generating board and detection component and obtain detection information.

[0046] Embodiment 2:

[0047] like Figure 2 As shown, a chip contact reliability detection method, based on the above reliability detection device, includes the following steps:

[0048] S1: Install several chips to be tested into the corresponding sockets of the aging board, connect the aging board to the reliability equipment; connect several chips in parallel to one power supply.

[0049] S2: PC sets the upper and lower limits of the output voltage and current of the power board, sets the upper and lower limits of the working voltage and current of the aging board, sets the open circuit voltage and current detection threshold, and sets the short circuit voltage and current detection threshold;

[0050] S3: The power board supplies power to the aging board, detects the output voltage and current of the power board and the working voltage and current of the aging board, and determines whether the power supply is short-circuited or open-circuited by the output voltage and current. If it is determined that the power supply is short-circuited or open-circuited, the power board starts the power protection (clamping or shutting down). If the working voltage and current of the aging board exceed the preset upper and lower limits of the working voltage and current, the power board starts the power protection (clamping or shutting down). After the power board starts the power protection, it feeds back a signal to the PC, and the PC records the error and terminates the detection;

[0051] S4: If the above tests are normal, perform the following tests on each chip to be tested on the aging board in turn:

[0052] S4.1: Take a group of power pins in the chip under test as the test group, and the other power pins as the normal group. Detect the voltage of the power pins of the test group and compare it with the voltage of the power pins of the normal group to determine whether the voltage of the power pins of the test group is normal. If it is not normal, the power board starts power protection (clamping or shutting down) and feeds back a signal to the PC. The PC records the error and terminates the test;

[0053] S4.2: The digital signal generating board is connected to the input pin of the chip under test through the input circuit, and is connected to the output pin of the chip under test through the output circuit. The digital signal generating board outputs the test signal to the input pin of the chip under test, and detects the actual level of the input pin to determine whether the actual level is consistent with the expected level. If not, it is determined that the chip under test has an open circuit or a short circuit, and a signal is fed back to the PC. The PC records the error and terminates the detection;

[0054] S4.3: The digital signal generating board detects the output signal of the output pin of the chip under test, and determines whether the output signal is consistent with the expectation. If not, it determines that the chip under test has an open circuit or a short circuit, and feeds back the signal to the PC, which records the error and terminates the test;

[0055] S4.4: If the above tests are all normal, the chip to be tested is determined to be normal, and the next chip to be tested is switched. If all chips are tested, the test is terminated.

[0056] When the current chip to be tested is terminated due to a short circuit or an open circuit in steps S4.1-S4.3, the next chip to be tested is tested sequentially until all chips are tested.

[0057] Regarding step S4.1:

[0058] by Figure 3 Take a chip as an example. The pins 1-8 of the chip are all provided by the same power supply (considering the insufficient overcurrent capacity of a single pin, a power supply of a general chip requires several pins to meet the overcurrent capacity). The chip pins 1-8 are directly connected together inside the chip. Considering that the pins 1-8 of the chip are all power pins, in this design, pin 8 is not connected to the power supply, but to the voltage measurement circuit on the aging board. The power supply + supplies power to the chip through the probes 1-7 on the socket. Since the pins 1-8 inside the chip are directly connected, when the chip is reliably connected to the socket, the voltage on pin 8 is consistent with the voltage provided to the chip. The voltage on pin 8 is measured by the voltage measurement circuit on the aging board. If the measured voltage is lower than the set voltage and close to 0, it can be judged that there is a short circuit in the pins 1-8 of the chip. At the same time, at the chip power input end, a current measurement circuit is used to detect the chip current. If the chip current is lower than the normal working current and close to 0, it can be judged that the chip power supply is open.

[0059] Regarding steps S4.2-S4.3:

[0060] like Figure 4 As shown, the PC and system software control the digital signal generator board, input digital signals to the input circuit according to the test vector of the chip, and the digital signals are loaded to the probe marked as "I" on the aging board. The digital signals are transmitted to the pin marked as "I" on the chip through the probe. When there is a pin short circuit in the transmission path, no matter whether the digital signal board outputs a high level or a low level, the digital signal generator board can only detect a low level, and it can be determined that there is a short circuit in the transmission path.

[0061] When the "I" pin of the chip receives a digital signal, it will output a fixed high and low level sequence from the pin marked as "O". These high and low level sequences are determined by the characteristics of the chip itself and usually do not change. When the chip outputs a high and low level sequence, it is transmitted to the digital signal generator board through the output circuit. The digital signal generator board will compare it with the value specified in the test vector. If the comparison result does not meet the expectations, it can be judged that the chip has poor contact, and there may be an open circuit on the "I" or "O" pin, or an open circuit on the "O" pin.

[0062] As shown in Table 1 below, the present invention addresses the design defects of existing test systems and systematically solves the identification of chip connection problems from multiple dimensions, including aging boards, aging equipment, and PC system software detection methods.

[0063]

[0064]

[0065] What needs to be further explained about the detection is that after the chip design is completed, the functions of each pin such as the power pin and IO pin are determined. The PCB on the aging board is provided with corresponding metal pads, which correspond to the pins of the chip one by one. Each probe on the socket will connect the pad of the corresponding PCB on the aging board and a corresponding pin of the chip. That is, the specific pins of the corresponding chip can be detected through program settings.

[0066] After the power is input from the reliability equipment to the burn-in board, multiple chips are connected in parallel to this power supply. The current measurement circuit and the voltage measurement circuit are pre-set on the burn-in board. The purpose of current measurement is to measure the current on each chip. Through the current measurement circuit, it is connected in series to the power supply loop to measure the current. The current flow direction of a single chip is: power supply output of the power board -> current measurement circuit -> socket probe -> chip. The purpose of voltage measurement is to measure the voltage of each chip, which can be directly measured by the socket probe for the corresponding pin.

[0067] For the measurement of chip IO, a series of signals are output to the chip through a digital signal generator board. After receiving the signal, the chip will generate a specific output signal. By detecting whether the output signal is correct, it can be determined whether the corresponding input / output pins of the chip are in reliable contact.

[0068] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

[0069] 1. Compared with the existing solutions, this detection method can locate which chip among several chips connected in parallel on the aging board has a power short circuit or open circuit.

[0070] 2. Compared with the existing solutions, this detection method can detect whether other digital pins of the chip are in reliable contact except the power supply.

[0071] 3. Compared with the existing scheme, this detection method improves the connection reliability detection range in chip testing by uniformly considering the aging board, reliability equipment, and PC, and improves the utilization rate of equipment and the confidence of test data.

[0072] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A chip contact reliability detection device, characterized in that: include: A burn-in board, the burn-in board is provided with a plurality of sockets, the sockets are used for installing the chips to be tested, and the burn-in board is also used for providing peripheral circuits necessary for the chip to work; A reliability device, comprising a digital signal generating board, a power board, a backplane and an adapter board, wherein the power board is used to provide output power to the chip under test, and the digital signal generating board is used to output digital signals to the chip under test and read back the digital signal level output by the chip under test; The digital signal generating board and the power supply board are connected to the aging board through the backboard and the adapter board; A detection component, including a current measurement circuit, a voltage measurement circuit, an input circuit, and an output circuit, wherein the current measurement circuit, the voltage measurement circuit, the input circuit, and the output circuit are respectively connected to the pins of the chip to be tested through corresponding probes; The PC is connected to the power board, the digital signal generating board and the detection component for controlling the power board, the digital signal generating board and the detection component to work and obtain detection information.

2. The chip contact reliability detection device according to claim 1, characterized in that: The power board is provided with a current and voltage detection device for checking the output power and output current of the power board.

3. The chip contact reliability detection device according to claim 1, characterized in that: The power board is also provided with a protection device, which performs a shut-down or clamping action when a short circuit or open circuit occurs.

4. A chip contact reliability detection method, characterized in that: The reliability detection device according to any one of claims 1 to 3 comprises the following steps: S1: Installing a number of the chips to be tested into the sockets corresponding to the aging board, and docking the aging board with the reliability equipment; S2: The PC sets the upper and lower limits of the output voltage and current of the power board, the upper and lower limits of the working voltage and current of the aging board, sets the open circuit voltage and current detection threshold, and sets the short circuit voltage and current detection threshold; S3: The power board supplies power to the aging board, detects the output voltage and current of the power board and the working voltage and current of the aging board, and determines whether the power supply is short-circuited or open-circuited by the output voltage and current. If it is determined that the power supply is short-circuited or open-circuited, the power board starts power protection. If the working voltage and current of the aging board exceed the preset upper and lower limits of the working voltage and current, the power board starts power protection. After starting the power protection, the power board feeds back a signal to the PC, and the PC records the error and terminates the detection. S4: If the above tests are normal, the following tests are performed on each of the chips to be tested on the aging board in turn: S4.1: A group of power pins in the chip under test is used as a test group, and the other power pins are used as a normal group. The voltage of the power pins in the test group is detected and compared with the voltage of the power pins in the normal group to determine whether the voltage of the power pins in the test group is normal. If it is not normal, the power board starts power protection and feeds back a signal to the PC, and the PC records the error and terminates the detection; S4.2: The digital signal generating board is connected to the input pin of the chip under test through the input circuit, and is connected to the output pin of the chip under test through the output circuit. The digital signal generating board outputs a test signal to the input pin of the chip under test, and detects the actual level of the input pin to determine whether the actual level is consistent with the expected level. If not, it is determined that the chip under test has an open circuit or a short circuit, and a signal is fed back to the PC. The PC records the error and terminates the detection. S4.3: The digital signal generating board detects the output signal of the output pin of the chip under test, determines whether the output signal is consistent with the expectation, and if not, determines that the chip under test has an open circuit or a short circuit, and feeds back a signal to the PC, which records the error and terminates the detection; S4.4: If the above tests are all normal, the chip to be tested is determined to be normal and the test ends.

5. The chip contact reliability detection method according to claim 4, characterized in that: When the current chip to be tested is terminated due to a short circuit or an open circuit in the steps S4.1-S4.3, the next chip to be tested is tested sequentially until all chips are tested.

6. The chip contact reliability detection method according to claim 4, characterized in that: The power protection is a clamping or shutting down action.

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