Self-detection control circuit, control method thereof and chip

Abstract

The invention relates to a self-detection control circuit, a control method thereof and a chip. The self-detection control circuit comprises a selection module and a control module. The selection module is configured to receive at least two sets of configuration information and selection signals required by self-detection, select one set of configuration information as self-detection information according to the selection signals, and load the self-detection information to the control module. The control module comprises a processing unit and an analysis unit. The processing unit is connected with the selection module. The processing unit is configured to generate one-to-one corresponding self-detection vectors according to the self-detection information, and load the self-detection vectors to the detected circuit. Wherein the detected circuit responds to the self-detection vector to generate one-to-one corresponding output signals. And the analysis unit is connected with the tested circuit. The analysis unit is configured to automatically compare the output signals with the corresponding expected values one by one so as to determine the correctness of the tested circuit. According to the invention, the self-detection efficiency of the detected circuit can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a self-detection control circuit and a control method and chip thereof. Background Art

[0002] With the development of semiconductor technology, semiconductor production processes have become more and more sophisticated, and the integration of integrated circuits has also been greatly improved. Therefore, in order to ensure the quality of chips, various chip testing operations have become an indispensable part.

[0003] As a solution of Design For Test (DFT), Logic Built-in Self-Test (LBIST) can perform self-test on the logic circuit under test at any time except the production stage. It can be placed inside the chip, with a simple test process and short test time.

[0004] Therefore, how to optimize the self-detection control circuit to further improve the self-detection efficiency of the circuit under test is an urgent problem to be solved. Summary of the invention

[0005] Based on this, it is necessary to provide a self-detection control circuit and a control method and chip thereof to optimize the self-detection control circuit, thereby further improving the self-detection efficiency of the circuit under test.

[0006] According to some embodiments, the present application provides a self-detection control circuit on one hand, including: a selection module and a control module. The selection module is configured to receive at least two groups of configuration information and a selection signal required for self-detection, select a group of configuration information as self-detection information according to the selection signal, and load the self-detection information into the control module. The control module includes a processing unit and an analysis unit. The processing unit is connected to the selection module. The processing unit is configured to generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector into the circuit under test. The circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector. The analysis unit is connected to the circuit under test. The analysis unit is configured to automatically compare the output signal with the corresponding expected value one by one to determine the correctness of the circuit under test.

[0007] According to some embodiments, the self-detection control circuit further includes: a state machine. The state machine is connected to the control module.

[0008] The state machine is configured to: receive a start instruction, and when the state machine is in an idle state, send an enable signal to the control module in response to the start instruction.

[0009] The processing unit is also configured to: when the circuit under test is in a non-working state, in response to an enable signal, generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector to the circuit under test to control the circuit under test to start self-detection.

[0010] According to some embodiments, the self-detection control circuit further includes: a reset module. The reset module is connected to the state machine.

[0011] The reset module is configured to: first perform a reset operation on the circuit under test and then perform an external reset operation in response to a first reset signal; and, in response to a second reset signal, perform a reset operation on the circuit under test.

[0012] The state machine is also configured to: in the event of an abnormal external reset during the self-detection process, jump to a first response reset state and send a first reset signal to the reset module; and, after determining the correctness of the circuit under test, jump to a second response reset state and send a second reset signal to the reset module.

[0013] After the reset operation is completed, the state machine jumps back to the idle state to end the self-test of the circuit under test.

[0014] According to some embodiments, the self-detection control circuit further includes: a first register. The first register is connected to the control module. The first register is configured to store a pass flag and a fail flag.

[0015] The pass mark indicates that the output signal is consistent with the corresponding expected value, and the circuit under test functions normally. The fail mark indicates that the output signal is inconsistent with the corresponding expected value, and there is a problem in the circuit under test.

[0016] According to some embodiments, the self-detection control circuit further includes: an electronic fuse and an electronic fuse controller. The electronic fuse controller is connected to the electronic fuse and the selection module.

[0017] The electronic fuse is configured to store at least two groups of configuration information and selection signals required for self-detection.

[0018] The electronic fuse controller is configured to load at least two groups of configuration information and selection signals required for self-testing into the selection module.

[0019] According to some embodiments, the present application provides a control method of a self-detection control circuit, the self-detection control circuit comprising: a selection module and a control module. The control module comprises a processing unit and an analysis unit. The processing unit is connected to the selection module; the analysis unit is connected to the circuit under test. The control method of the self-detection control circuit comprises the following steps:

[0020] receiving at least two sets of configuration information and selection signals required for self-detection;

[0021] selecting a set of configuration information as self-detection information according to a selection signal, and loading the self-detection information into a control module;

[0022] Generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector to the circuit under test;

[0023] The circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector;

[0024] Automatically compare the output signals with the corresponding expected values ​​one by one to determine the correctness of the circuit under test.

[0025] According to some embodiments, generating a one-to-one corresponding self-detection vector according to the self-detection information and loading the self-detection vector to the circuit under test includes the following steps:

[0026] The state machine receives a start instruction, and when the state machine is in an idle state, sends an enable signal to the control module in response to the start instruction;

[0027] When the circuit under test is in a non-operating state, in response to an enable signal, a one-to-one corresponding self-detection vector is generated according to the self-detection information, and the self-detection vector is loaded to the circuit under test to control the circuit under test to start self-detection.

[0028] According to some embodiments, the control method of the self-detection control circuit further includes the following steps:

[0029] In the event of an abnormal external reset during the self-detection process, the state machine jumps to the first response reset state and sends a first reset signal to the reset module;

[0030] The reset module performs a reset operation on the circuit under test in response to the first reset signal, and then performs an external reset operation;

[0031] After determining the correctness of the circuit under test, the state machine jumps to a second response reset state and sends a second reset signal to the reset module;

[0032] The reset module performs a reset operation on the circuit under test in response to the second reset signal.

[0033] According to some embodiments, comparing the output signals with the corresponding expected values ​​one by one to determine the correctness of the circuit under test includes the following steps:

[0034] If the output signal is consistent with the corresponding expected value, the circuit under test functions normally, and a pass flag is automatically output and stored in the first register;

[0035] If there is an output signal that is inconsistent with the corresponding expected value, there is a problem with the circuit under test, and a failure flag is automatically output and stored in the first register.

[0036] According to some embodiments, the present application provides a chip on another aspect, comprising the self-detection control circuit as described in the aforementioned embodiments.

[0037] The embodiments of the present application may or at least have the following advantages:

[0038] In the embodiment of the present application, by optimizing the self-detection control circuit, a set of configuration information is selected as the self-detection information according to the selection signal by the selection module, and then the processing unit in the control module generates a one-to-one corresponding self-detection vector according to the self-detection information, and the self-detection vector is loaded to the circuit under test, and the circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector, and finally the analysis unit in the control module is used to automatically compare the output signal with the corresponding expected value one by one. In this way, the embodiment of the present application can adjust the selected configuration of the self-detection according to the selection signal, thereby adjusting the time and coverage of the self-detection. In this way, the embodiment of the present application improves the flexibility and coverage of the self-detection, and further improves the self-detection efficiency of the circuit under test.

[0039] Moreover, in the embodiment of the present application, the self-detection only needs one start instruction to automatically complete the comparison of all output signals with the corresponding expected values, thereby determining the correctness of the circuit under test. That is, the embodiment of the present application realizes the automation of hardware circuit self-detection. Compared with the self-detection solution of soft execution, the embodiment of the present application has the advantages of not occupying memory, high reliability, high execution efficiency, and can be completely implemented based on hardware.

[0040] In addition, in the embodiment of the present application, when an external reset is encountered during the self-test process and after the correctness of the circuit under test is determined, the state machine can control the state transition, and the reset module can reset the circuit under test. In this way, the circuit under test is prevented from being in a chaotic state, and it is ensured that the circuit under test can immediately start normal operation after the self-test is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 is a structural block diagram of a self-detection control circuit provided in an embodiment;

[0043] Figure 2is a structural block diagram of another self-detection control circuit provided in an embodiment;

[0044] Figure 3 is a flow chart of a control method of a self-detection control circuit provided in an embodiment;

[0045] Figure 4 The figure is a flow chart of another control method of a self-detection control circuit provided in an embodiment.

[0046] Description of reference numerals:

[0047] 1-selection module; 2-control module, 21-processing unit, 22-analysis unit; 23-compressor; 24-decompressor; 3-tested circuit; 4-electronic fuse; 5-electronic fuse controller; 6-state machine; 71-first register; 72-second register;

[0048] CFG-self-detection information, CFG1-a set of configuration information required for self-detection, CFG2-another set of configuration information required for self-detection; switch-selection signal; pattern-self-detection vector; out-output signal; EN-enable signal. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] It is understood that the terms "first", "second", "third", "fourth", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first register may be referred to as a second register, and similarly, a second register may be referred to as a first register. Both the first register and the second register are registers, but they are not the same register.

[0053] It can be understood that the “connection” in the following embodiments should be understood as “connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other.

[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0055] With the development of semiconductor technology, semiconductor production processes have become more and more sophisticated, and the integration of integrated circuits has also been greatly improved. Therefore, in order to ensure the quality of chips, various chip testing operations have become an indispensable part. Especially for Application Specific Integrated Circuit (ASIC) chips, damage to a small unit in the circuit may cause the entire chip to not work properly. Therefore, the chip testing function has always been a hot research direction in the field of integrated circuits.

[0056] For large-area complex chips, the traditional scan chain test method is too large. Inserting a scan chain into the chip will significantly increase the chip production cost and consume a lot of testing time. Therefore, Design For Test (DFT) constitutes an essential link in the chip design process, aiming to solve the problems related to chip testing and provide an important solution for chip testability.

[0057] As a DFT solution, Logic Built-in Self-Test (LBIST) can perform self-test on the logic circuit under test at any time except the production stage. It can be placed inside the chip, with a simple test process and short test time. Therefore, how to optimize the self-test control circuit to further improve the self-test efficiency of the circuit under test is an urgent problem to be solved.

[0058] Based on this, an embodiment of the present application provides a self-detection control circuit and a control method and chip thereof to optimize the self-detection control circuit, thereby further improving the self-detection efficiency of the circuit under test.

[0059] See also Figure 1 , an embodiment of the present application provides a self-detection control circuit, including: a selection module 1 and a control module 2. The selection module 1 is configured to: receive at least two groups of configuration information required for self-detection (for example: CFG1 and CFG2) and a selection signal switch, select a group of configuration information as self-detection information CFG according to the selection signal switch, and load the self-detection information CFG to the control module 2. The control module 2 includes a processing unit 21 and an analysis unit 22. The processing unit 21 is connected to the selection module 1. The processing unit 21 is configured to: generate a one-to-one corresponding self-detection vector pattern according to the self-detection information CFG, and load the self-detection vector pattern to the circuit under test 3. The circuit under test 3 generates a one-to-one corresponding output signal out in response to the self-detection vector pattern. The analysis unit 22 is connected to the circuit under test 3. The analysis unit 22 is configured to: automatically compare the output signal out with the corresponding expected value one by one to determine the correctness of the circuit under test 3.

[0060] In the embodiment of the present application, by optimizing the self-detection control circuit, a set of configuration information is selected as the self-detection information CFG according to the selection signal switch by the selection module 1, and then the processing unit 21 in the control module 2 generates a one-to-one corresponding self-detection vector pattern according to the self-detection information CFG, and loads the self-detection vector pattern to the circuit under test 3, and the circuit under test 3 generates a one-to-one corresponding output signal out in response to the self-detection vector pattern, and finally the analysis unit 22 in the control module 2 is used to automatically compare the output signal out with the corresponding expected value one by one. In this way, the embodiment of the present application can adjust the selected configuration of the self-detection according to the selection signal switch, thereby adjusting the time and coverage of the self-detection. In this way, the embodiment of the present application improves the flexibility and coverage of the self-detection, and further improves the self-detection efficiency of the circuit under test 3.

[0061] Moreover, before the end of the self-test, the embodiment of the present application automatically compares the output signal out with the corresponding expected value one by one, thereby determining the correctness of the tested circuit 3. That is, the embodiment of the present application realizes the automation of the self-test of the hardware circuit. Compared with the self-test solution executed by software, the embodiment of the present application has the advantages of not occupying memory, high reliability, high execution efficiency, and can be completely implemented based on hardware.

[0062] In some embodiments, the self-test includes a logic built-in self-test (LBIST). The selection module 1 includes: an LBIST configuration selection module. The control module 2 includes: an LBIST function control module. The circuit under test 3 includes a logic circuit under test.

[0063] Correspondingly, in some examples, the configuration information required for each group of self-detection is the configuration information that LBIST needs to use. Further, the configuration information required for each group of self-detection is determined when designing the LBIST test chain, according to the design of the tested logic circuit and the coverage rate that is expected to be achieved. Wherein, the coverage rate is related to the self-detection execution time. Generally, the more self-detection vector patterns there are, the longer the self-detection execution time is, and the higher the coverage rate is.

[0064] In some examples, the configuration information required for each set of self-tests includes: a signature, a number of self-test vectors (pattern number), an initial value (bist seed) for calculating the data of the Multiple Input Signature Register (MISR), and the number of shift calculations (length). The signature is determined according to the design of the circuit under test. The pattern number indicates the number of self-test vector patterns for a self-test run. More self-test vector patterns can achieve higher self-test coverage.

[0065] In some examples, the configuration information CFG1 required for self-detection includes: signature0, pattern number0, bist seed0, and length0. The configuration information CFG2 required for self-detection includes: signature1, pattern number1, bist seed1, and length1. The selection signal switch is regarded as a simple multi-way selection switch signal.

[0066] Further, for example, selecting a set of configuration information as the self-detection information CFG according to the selection signal switch includes: when the selection signal switch is at a low level, selecting signature0, pattern number0, bist seed0, and length0 to load into the control module 2. When the selection signal switch is at a high level, selecting signature1, pattern number1, bist seed1, and length1 to load into the control module 2.

[0067] In the embodiment of the present application, the self-detection configuration information such as signature, pattern number, bistseed and length are selected according to the selection signal switch, so that the time and coverage of the self-detection can be adjusted.

[0068] In some embodiments, see Figure 2 The self-detection control circuit further includes: an electronic fuse 4 and an electronic fuse controller 5. The electronic fuse controller 5 is connected to the electronic fuse 4 and the selection module 1.

[0069] The electronic fuse 4 is configured to store at least two sets of configuration information required for self-detection (eg, CFG1 and CFG2 ) and a selection signal switch.

[0070] The electronic fuse controller 5 is configured to load at least two groups of configuration information required for self-detection (eg, CFG1 and CFG2 ) and a selection signal switch into the selection module 1 .

[0071] For example, the electronic fuse controller 5 loads two sets of self-detection configuration information CFG1 and CFG2 stored in the electronic fuse 4 , and the selected configuration of the self-detection can be adjusted according to the selection signal switch.

[0072] In some embodiments, please refer to Figure 2 The self-detection control circuit further includes: a state machine 6. The state machine 6 is connected to the control module 2. The state machine 6 is configured to: receive a start instruction, and when the state machine 6 is in an idle state, send an enable signal EN to the control module 2 in response to the start instruction.

[0073] The processing unit 21 is also configured to: when the circuit under test 3 is in a non-working state, respond to the enable signal EN, generate a one-to-one corresponding self-detection vector pattern according to the self-detection information CFG, and load the self-detection vector pattern to the circuit under test 3 to control the circuit under test 3 to start self-detection.

[0074] In some examples, after receiving the start instruction, the state machine 6 first enters the LBIST enabled state, then resets the logic circuit under test, and performs a handshake process with its enable signal. After confirming that all the logic circuits under test are in the enabled and closed state (i.e., non-working state), it jumps to the LBIST started state to control the logic circuit under test to start self-detection.

[0075] In some examples, the self-detection vector pattern includes: a combination of performing high and low level flipping on all reg ports of the tested logic circuit.

[0076] Furthermore, for example, there are many reg ports inside the tested logic circuit, including CLK, D, Q, RN, SI, SE, and LBIST. When performing self-test, the CLK, D, SI, and SE input terminals of all reg ports of the tested logic circuit are stimulated according to the self-test vector pattern to perform flipping. If the tested logic circuit functions normally, the flipping is the expected behavior; otherwise, the flipping is inconsistent with the expectation.

[0077] In some embodiments, please refer to Figure 2 The self-detection control circuit further includes: a compressor 23 and a decompressor 24. The compressor 23 and the decompressor 24 are responsible for compressing and decompressing the self-detection vector pattern.

[0078] In some examples, the combinational logic between all reg ports will be strung together into a scan chain, and the stimulus source is provided by the decompressor 24. After the scan is completed, it is finally returned to the compressor 23, and the analysis unit 22 compares the detection results. For example, the stimulus source provided is 8'h5a, and the expected result after the logic circuit calculation of the scan chain is 8'ha5. If the result is as expected, it means that the logic circuit functions normally. If the result is inconsistent with the expectation, it means that there is a device flip in the middle of the logic circuit that does not meet expectations, and the circuit is damaged.

[0079] In some embodiments, please refer to Figure 2 The self-detection control circuit further includes: a first register 71. The first register 71 is connected to the control module 2. The first register 71 is configured to store a pass (PASS) flag and a fail (FALL) flag.

[0080] The PASS mark indicates that the output signal out is consistent with the corresponding expected value, and the circuit under test 3 functions normally. The FALL mark indicates that the output signal out is inconsistent with the corresponding expected value, and there is a problem with the circuit under test 3.

[0081] In some examples, after all self-detection vector patterns are executed, the MISR data is shifted and calculated according to the bist seed to obtain the final MISR data. If the final MISR meets the expectations, it means that the comparison is passed, otherwise the comparison fails, and the related pass (PASS) flag and fail (FALL) flag are stored in the corresponding first register 71.

[0082] In some embodiments, please refer to Figure 2 , the self-detection control circuit also includes: a second register 72.

[0083] In some examples, after the configuration information is selected, the start instruction is sent to the state machine 6 by writing into the second register 72. Here, the port to which the second register 72 is written is reserved, and the writing form is not limited as long as the register writing operation can be performed.

[0084] For example, the host computer (for example, microcontroller unit MCU) sends a command through the serial peripheral interface (Serial Peripheral Interface, referred to as SPI) bus, and then after the command is decoded, the writing operation of the second register 72 is completed. For example, the second register 72 for starting LBIST is 2 bits wide, and when it is written from 2'b01 to 2'b10 and given to the state machine 6, the state machine 6 will decode it into a start signal and perform a state jump.

[0085] In some examples, after receiving the start instruction, the state machine 6 will first confirm whether the current state machine 6 is in an idle state, and if the state machine 6 is in an idle state, the state machine 6 sends an enable signal EN to the control module 2 in response to the start instruction. If the state machine 6 is in a busy state, the state machine 6 ignores the start instruction, that is, the self-test of the circuit under test is in progress, and the state machine 6 will not respond to the start instruction.

[0086] In some embodiments, the self-detection control circuit further includes: a reset module (not shown in the figure). The reset module is connected to the state machine 6. The reset module is configured to: in response to the first reset signal, first perform a reset operation on the circuit under test 3, and then perform an external reset operation; and, in response to the second reset signal, perform a reset operation on the circuit under test 3.

[0087] Here, it should be noted that the reset domain of the external reset cannot cover the entire logic circuit under test. Therefore, if the external reset is directly executed, the circuit under test that cannot be reset will be in a chaotic state.

[0088] The state machine 6 is also configured to: jump to the first response reset state and send a first reset signal to the reset module in the event of an abnormal external reset during the self-test process, and jump to the second response reset state and send a second reset signal to the reset module after determining the correctness of the circuit under test 3. After the reset operation is completed, the state machine 6 jumps back to the idle state to end the self-test of the circuit under test 3.

[0089] In the embodiment of the present disclosure, when an external reset is encountered during the self-test process and after the correctness of the circuit under test is determined, the state machine can control the state transition, and the reset module can perform a reset operation on the circuit under test. In this way, the circuit under test is prevented from being in a chaotic state, and it is ensured that the circuit under test can immediately start normal operation after the self-test is completed.

[0090] In some examples, when the state machine 6 is in an idle state, the external reset is a normal reset and can be performed directly, and the state of the state machine 6 will not jump; when the state machine 6 is in a non-idle state, the system encounters an external reset, and the state machine 6 will first jump to the first response reset state according to the external reset signal. At this time, the state machine 6 gives the first response reset state to the reset module, and the reset module resets the reset domain of the external reset after performing a comprehensive safety reset on the logic circuit under test.

[0091] Here, system refers to the entire chip. System external reset is a pin of the chip that can input a reset signal from the outside. When the chip receives the external reset signal, this signal will be given to the reset module of the chip, and the reset module will reset the reset domain of the external reset.

[0092] Some embodiments of the present application also provide a control method for a self-detection control circuit. By adopting the self-detection control circuit described in the aforementioned embodiments, the control method for the self-detection control circuit also possesses the technical advantages of the aforementioned self-detection control circuit, which will not be repeated here.

[0093] In some embodiments, see Figure 3 , the control method of the self-detection control circuit includes steps S100~S500.

[0094] S100, receiving at least two groups of configuration information and selection signals required for self-detection.

[0095] S200, selecting a set of configuration information as self-detection information according to a selection signal, and loading the self-detection information into a control module.

[0096] S300, generating a one-to-one corresponding self-detection vector according to the self-detection information, and loading the self-detection vector to the circuit under test.

[0097] S400 , the circuit under test generates a one-to-one corresponding output signal in response to a self-detection vector.

[0098] S500 automatically compares the output signals with the corresponding expected values ​​one by one to determine the correctness of the circuit under test.

[0099] See also Figure 1 and Figure 2 The self-detection control circuit includes: a selection module 1 and a control module 2. The control module 2 includes a processing unit 21 and an analysis unit 22. The processing unit 21 is connected to the selection module 1; the analysis unit 22 is connected to the circuit under test 3.

[0100] In step S100 , at least two sets of configuration information required for self-detection (eg, CFG1 and CFG2 ) and a selection signal switch are received.

[0101] In some examples, before step S100, the control method of the self-detection control circuit further includes:

[0102] An electronic fuse is used to store at least two sets of configuration information required for self-detection (for example, CFG1 and CFG2) and a selection signal switch;

[0103] The electronic fuse controller is used to load at least two sets of configuration information required for self-test (for example, CFG1 and CFG2) and a selection signal switch into the selection module, wherein the electronic fuse controller is connected to the electronic fuse and the selection module.

[0104] For example, the electronic fuse controller loads two sets of self-detection configuration information CFG1 and CFG2 stored in the electronic fuse, and the selected configuration of the self-detection can be adjusted according to the selection signal switch.

[0105] In some examples, the configuration information required for each set of self-tests includes: a signature, a number of self-test vectors (pattern number), an initial value (bist seed) for calculating the data of the Multiple Input Signature Register (MISR), and the number of shift calculations (length). The signature is determined according to the design of the circuit under test. The pattern number indicates the number of self-test vector patterns for a self-test run. More self-test vector patterns can achieve higher self-test coverage.

[0106] In some examples, the configuration information CFG1 required for self-detection includes: signature0, pattern number0, bist seed0, and length0. The configuration information CFG2 required for self-detection includes: signature1, pattern number1, bist seed1, and length1. The selection signal switch is regarded as a simple multi-way selection switch signal.

[0107] In step S200, please continue to refer to Figure 4 , a set of configuration information is selected as self-detection information CFG according to the selection signal switch, and the self-detection information CFG is loaded into the control module.

[0108] For example, selecting a set of configuration information as the self-detection information CFG according to the selection signal switch includes: when the selection signal switch is at a low level, selecting signature0, pattern number0, bist seed0, and length0 to load into the control module. When the selection signal switch is at a high level, selecting signature1, pattern number1, bist seed1, and length1 to load into the control module.

[0109] In the embodiment of the present application, the self-detection configuration information such as signature, pattern number, bistseed and length are selected according to the selection signal switch, so that the time and coverage of the self-detection can be adjusted.

[0110] In step S300, please continue to refer to Figure 4 , generating a one-to-one corresponding self-detection vector pattern according to the self-detection information CFG, and loading the self-detection vector CFG to the circuit under test includes:

[0111] The state machine receives a start instruction, and when the state machine is in an idle state, sends an enable signal EN to the control module in response to the start instruction;

[0112] When the circuit under test is in a non-operating state, in response to the enable signal EN, a one-to-one self-detection vector pattern is generated according to the self-detection information CFG, and the self-detection vector pattern is loaded to the circuit under test to control the circuit under test to start self-detection.

[0113] In some embodiments, please refer to Figure 4 , the control method of the self-detection control circuit also includes:

[0114] In the event of an abnormal external reset during the self-detection process, the state machine jumps to the first response reset state and sends a first reset signal to the reset module;

[0115] The reset module first performs a reset operation on the circuit under test in response to the first reset signal, and then performs an external reset operation.

[0116] In step S400, please continue to refer to Figure 4 , the circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector pattern.

[0117] In step S500, please continue to refer to Figure 4 , automatically compare the output signal with the corresponding expected value one by one to determine the correctness of the circuit under test.

[0118] In some embodiments, comparing the output signals with the corresponding expected values ​​one by one to determine the correctness of the circuit under test includes the following steps:

[0119] If the output signal is consistent with the corresponding expected value, the circuit under test functions normally, and a pass (PASS) flag is automatically output and stored in the first register;

[0120] If there is an output signal that is inconsistent with the corresponding expected value, there is a problem with the circuit under test, and a fail (FALL) flag is automatically output and stored in the first register.

[0121] In some embodiments, please refer to Figure 4 , after determining the correctness of the circuit under test, that is, after the final verification result is compared, the state machine jumps to the second response reset state and sends a second reset signal to the reset module;

[0122] The reset module performs a reset operation on the circuit under test in response to the second reset signal.

[0123] Some embodiments of the present application further provide a chip, including the self-detection control circuit as described in the above embodiments. The chip also has the technical advantages of the above self-detection control circuit, which will not be repeated here.

[0124] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), floppy disk, flash memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The processor involved in the embodiments provided in this application can be a general-purpose processor, a central processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0125] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A self-detection control circuit, characterized in that: include: Selection module and control module; among them, The selection module is configured to: receive at least two sets of configuration information required for self-detection and a selection signal, select one set of the configuration information as self-detection information according to the selection signal, and load the self-detection information into the control module; The control module includes a processing unit and an analysis unit; The processing unit is connected to the selection module; the processing unit is configured to: generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector to the circuit under test; wherein the circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector; The analysis unit is connected to the circuit under test; the analysis unit is configured to automatically compare the output signals with corresponding expected values ​​one by one to determine the correctness of the circuit under test.

2. The self-detection control circuit according to claim 1, characterized in that: It also includes: a state machine; the state machine is connected to the control module; The state machine is configured to: receive a start instruction, and send an enable signal to the control module in response to the start instruction when the state machine is in an idle state; The processing unit is also configured to: when the circuit under test is in a non-working state, in response to the enable signal, generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector to the circuit under test to control the circuit under test to start self-detection.

3. The self-detection control circuit according to claim 2, characterized in that: Also includes: Reset module; the reset module is connected to the state machine; The reset module is configured to: first perform a reset operation on the circuit under test in response to a first reset signal, and then perform an external reset operation; and, in response to a second reset signal, perform a reset operation on the circuit under test; The state machine is further configured to: in case of an abnormal external reset during the self-detection process, jump to the first response reset state and send the first reset signal to the reset module; and, after determining the correctness of the circuit under test, jumping to a second response reset state, sending the second reset signal to the reset module; After the reset operation is completed, the state machine jumps back to the idle state to end the self-test of the circuit under test.

4. The self-detection control circuit according to claim 1, characterized in that: Also includes: A first register; the first register is connected to the control module; The first register is configured to: store a pass flag and a fail flag; Among them, the pass mark indicates that the output signal is consistent with the corresponding expected value, and the circuit under test functions normally; the fail mark indicates that the output signal is inconsistent with the corresponding expected value, and there is a problem with the circuit under test.

5. The self-detection control circuit according to claim 1, characterized in that: Also includes: An electronic fuse and an electronic fuse controller; the electronic fuse controller is connected to the electronic fuse and the selection module; The electronic fuse is configured to: store the configuration information required for the at least two groups of self-tests and the selection signal; The electronic fuse controller is configured to: load the at least two groups of configuration information required for self-testing and the selection signal into the selection module.

6. A control method for a self-detection control circuit, characterized in that: The self-detection control circuit comprises: a selection module and a control module; the control module comprises a processing unit and an analysis unit; the processing unit is connected to the selection module; the analysis unit is connected to the circuit under test; the control method of the self-detection control circuit comprises: receiving at least two sets of configuration information and selection signals required for self-detection; Selecting a set of the configuration information as self-detection information according to the selection signal, and loading the self-detection information into the control module; Generate a one-to-one corresponding self-detection vector according to the self-detection information, and load the self-detection vector to the circuit under test; The circuit under test generates a one-to-one corresponding output signal in response to the self-detection vector; The output signals are automatically compared with corresponding expected values ​​one by one to determine the correctness of the circuit under test.

7. The control method of the self-detection control circuit according to claim 6, characterized in that: The step of generating a one-to-one corresponding self-detection vector according to the self-detection information and loading the self-detection vector to the circuit under test comprises: The state machine receives a start instruction, and sends an enable signal to the control module in response to the start instruction when the state machine is in an idle state; When the circuit under test is in a non-working state, in response to the enable signal, a one-to-one corresponding self-detection vector is generated according to the self-detection information, and the self-detection vector is loaded to the circuit under test to control the circuit under test to start self-detection.

8. The control method of the self-detection control circuit according to claim 7, characterized in that: Also includes: In the event of an abnormal external reset during the self-detection process, the state machine jumps to a first response reset state and sends a first reset signal to the reset module; The reset module first performs a reset operation on the circuit under test in response to the first reset signal, and then performs an external reset operation; After determining the correctness of the circuit under test, the state machine jumps to a second response reset state and sends a second reset signal to the reset module; The reset module performs a reset operation on the circuit under test in response to the second reset signal.

9. The control method of the self-detection control circuit according to claim 6, characterized in that: The step of comparing the output signals with the corresponding expected values ​​one by one to determine the correctness of the circuit under test includes: If the output signal is consistent with the corresponding expected value, the circuit under test functions normally, and a pass flag is automatically output and stored in the first register; If the output signal is inconsistent with the corresponding expected value, there is a problem with the circuit under test, and a failure flag is automatically output and stored in the first register.

10. A chip, characterized in that: It comprises the self-detection control circuit as described in any one of claims 1 to 5.

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